1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // mt9v011 -Micron 1/4-Inch VGA Digital Image Sensor
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2009 Mauro Carvalho Chehab <mchehab@kernel.org>
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/i2c.h>
8*4882a593Smuzhiyun #include <linux/slab.h>
9*4882a593Smuzhiyun #include <linux/videodev2.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <asm/div64.h>
13*4882a593Smuzhiyun #include <media/v4l2-device.h>
14*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
15*4882a593Smuzhiyun #include <media/i2c/mt9v011.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun MODULE_DESCRIPTION("Micron mt9v011 sensor driver");
18*4882a593Smuzhiyun MODULE_AUTHOR("Mauro Carvalho Chehab");
19*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static int debug;
22*4882a593Smuzhiyun module_param(debug, int, 0);
23*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level (0-2)");
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define R00_MT9V011_CHIP_VERSION 0x00
26*4882a593Smuzhiyun #define R01_MT9V011_ROWSTART 0x01
27*4882a593Smuzhiyun #define R02_MT9V011_COLSTART 0x02
28*4882a593Smuzhiyun #define R03_MT9V011_HEIGHT 0x03
29*4882a593Smuzhiyun #define R04_MT9V011_WIDTH 0x04
30*4882a593Smuzhiyun #define R05_MT9V011_HBLANK 0x05
31*4882a593Smuzhiyun #define R06_MT9V011_VBLANK 0x06
32*4882a593Smuzhiyun #define R07_MT9V011_OUT_CTRL 0x07
33*4882a593Smuzhiyun #define R09_MT9V011_SHUTTER_WIDTH 0x09
34*4882a593Smuzhiyun #define R0A_MT9V011_CLK_SPEED 0x0a
35*4882a593Smuzhiyun #define R0B_MT9V011_RESTART 0x0b
36*4882a593Smuzhiyun #define R0C_MT9V011_SHUTTER_DELAY 0x0c
37*4882a593Smuzhiyun #define R0D_MT9V011_RESET 0x0d
38*4882a593Smuzhiyun #define R1E_MT9V011_DIGITAL_ZOOM 0x1e
39*4882a593Smuzhiyun #define R20_MT9V011_READ_MODE 0x20
40*4882a593Smuzhiyun #define R2B_MT9V011_GREEN_1_GAIN 0x2b
41*4882a593Smuzhiyun #define R2C_MT9V011_BLUE_GAIN 0x2c
42*4882a593Smuzhiyun #define R2D_MT9V011_RED_GAIN 0x2d
43*4882a593Smuzhiyun #define R2E_MT9V011_GREEN_2_GAIN 0x2e
44*4882a593Smuzhiyun #define R35_MT9V011_GLOBAL_GAIN 0x35
45*4882a593Smuzhiyun #define RF1_MT9V011_CHIP_ENABLE 0xf1
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define MT9V011_VERSION 0x8232
48*4882a593Smuzhiyun #define MT9V011_REV_B_VERSION 0x8243
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun struct mt9v011 {
51*4882a593Smuzhiyun struct v4l2_subdev sd;
52*4882a593Smuzhiyun #ifdef CONFIG_MEDIA_CONTROLLER
53*4882a593Smuzhiyun struct media_pad pad;
54*4882a593Smuzhiyun #endif
55*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrls;
56*4882a593Smuzhiyun unsigned width, height;
57*4882a593Smuzhiyun unsigned xtal;
58*4882a593Smuzhiyun unsigned hflip:1;
59*4882a593Smuzhiyun unsigned vflip:1;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun u16 global_gain, exposure;
62*4882a593Smuzhiyun s16 red_bal, blue_bal;
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
to_mt9v011(struct v4l2_subdev * sd)65*4882a593Smuzhiyun static inline struct mt9v011 *to_mt9v011(struct v4l2_subdev *sd)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun return container_of(sd, struct mt9v011, sd);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
mt9v011_read(struct v4l2_subdev * sd,unsigned char addr)70*4882a593Smuzhiyun static int mt9v011_read(struct v4l2_subdev *sd, unsigned char addr)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun struct i2c_client *c = v4l2_get_subdevdata(sd);
73*4882a593Smuzhiyun __be16 buffer;
74*4882a593Smuzhiyun int rc, val;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun rc = i2c_master_send(c, &addr, 1);
77*4882a593Smuzhiyun if (rc != 1)
78*4882a593Smuzhiyun v4l2_dbg(0, debug, sd,
79*4882a593Smuzhiyun "i2c i/o error: rc == %d (should be 1)\n", rc);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun msleep(10);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun rc = i2c_master_recv(c, (char *)&buffer, 2);
84*4882a593Smuzhiyun if (rc != 2)
85*4882a593Smuzhiyun v4l2_dbg(0, debug, sd,
86*4882a593Smuzhiyun "i2c i/o error: rc == %d (should be 2)\n", rc);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun val = be16_to_cpu(buffer);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun v4l2_dbg(2, debug, sd, "mt9v011: read 0x%02x = 0x%04x\n", addr, val);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return val;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
mt9v011_write(struct v4l2_subdev * sd,unsigned char addr,u16 value)95*4882a593Smuzhiyun static void mt9v011_write(struct v4l2_subdev *sd, unsigned char addr,
96*4882a593Smuzhiyun u16 value)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun struct i2c_client *c = v4l2_get_subdevdata(sd);
99*4882a593Smuzhiyun unsigned char buffer[3];
100*4882a593Smuzhiyun int rc;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun buffer[0] = addr;
103*4882a593Smuzhiyun buffer[1] = value >> 8;
104*4882a593Smuzhiyun buffer[2] = value & 0xff;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun v4l2_dbg(2, debug, sd,
107*4882a593Smuzhiyun "mt9v011: writing 0x%02x 0x%04x\n", buffer[0], value);
108*4882a593Smuzhiyun rc = i2c_master_send(c, buffer, 3);
109*4882a593Smuzhiyun if (rc != 3)
110*4882a593Smuzhiyun v4l2_dbg(0, debug, sd,
111*4882a593Smuzhiyun "i2c i/o error: rc == %d (should be 3)\n", rc);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun struct i2c_reg_value {
116*4882a593Smuzhiyun unsigned char reg;
117*4882a593Smuzhiyun u16 value;
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /*
121*4882a593Smuzhiyun * Values used at the original driver
122*4882a593Smuzhiyun * Some values are marked as Reserved at the datasheet
123*4882a593Smuzhiyun */
124*4882a593Smuzhiyun static const struct i2c_reg_value mt9v011_init_default[] = {
125*4882a593Smuzhiyun { R0D_MT9V011_RESET, 0x0001 },
126*4882a593Smuzhiyun { R0D_MT9V011_RESET, 0x0000 },
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun { R0C_MT9V011_SHUTTER_DELAY, 0x0000 },
129*4882a593Smuzhiyun { R09_MT9V011_SHUTTER_WIDTH, 0x1fc },
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun { R0A_MT9V011_CLK_SPEED, 0x0000 },
132*4882a593Smuzhiyun { R1E_MT9V011_DIGITAL_ZOOM, 0x0000 },
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun { R07_MT9V011_OUT_CTRL, 0x0002 }, /* chip enable */
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun
calc_mt9v011_gain(s16 lineargain)138*4882a593Smuzhiyun static u16 calc_mt9v011_gain(s16 lineargain)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun u16 digitalgain = 0;
142*4882a593Smuzhiyun u16 analogmult = 0;
143*4882a593Smuzhiyun u16 analoginit = 0;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun if (lineargain < 0)
146*4882a593Smuzhiyun lineargain = 0;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* recommended minimum */
149*4882a593Smuzhiyun lineargain += 0x0020;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun if (lineargain > 2047)
152*4882a593Smuzhiyun lineargain = 2047;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (lineargain > 1023) {
155*4882a593Smuzhiyun digitalgain = 3;
156*4882a593Smuzhiyun analogmult = 3;
157*4882a593Smuzhiyun analoginit = lineargain / 16;
158*4882a593Smuzhiyun } else if (lineargain > 511) {
159*4882a593Smuzhiyun digitalgain = 1;
160*4882a593Smuzhiyun analogmult = 3;
161*4882a593Smuzhiyun analoginit = lineargain / 8;
162*4882a593Smuzhiyun } else if (lineargain > 255) {
163*4882a593Smuzhiyun analogmult = 3;
164*4882a593Smuzhiyun analoginit = lineargain / 4;
165*4882a593Smuzhiyun } else if (lineargain > 127) {
166*4882a593Smuzhiyun analogmult = 1;
167*4882a593Smuzhiyun analoginit = lineargain / 2;
168*4882a593Smuzhiyun } else
169*4882a593Smuzhiyun analoginit = lineargain;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun return analoginit + (analogmult << 7) + (digitalgain << 9);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
set_balance(struct v4l2_subdev * sd)175*4882a593Smuzhiyun static void set_balance(struct v4l2_subdev *sd)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun struct mt9v011 *core = to_mt9v011(sd);
178*4882a593Smuzhiyun u16 green_gain, blue_gain, red_gain;
179*4882a593Smuzhiyun u16 exposure;
180*4882a593Smuzhiyun s16 bal;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun exposure = core->exposure;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun green_gain = calc_mt9v011_gain(core->global_gain);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun bal = core->global_gain;
187*4882a593Smuzhiyun bal += (core->blue_bal * core->global_gain / (1 << 7));
188*4882a593Smuzhiyun blue_gain = calc_mt9v011_gain(bal);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun bal = core->global_gain;
191*4882a593Smuzhiyun bal += (core->red_bal * core->global_gain / (1 << 7));
192*4882a593Smuzhiyun red_gain = calc_mt9v011_gain(bal);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun mt9v011_write(sd, R2B_MT9V011_GREEN_1_GAIN, green_gain);
195*4882a593Smuzhiyun mt9v011_write(sd, R2E_MT9V011_GREEN_2_GAIN, green_gain);
196*4882a593Smuzhiyun mt9v011_write(sd, R2C_MT9V011_BLUE_GAIN, blue_gain);
197*4882a593Smuzhiyun mt9v011_write(sd, R2D_MT9V011_RED_GAIN, red_gain);
198*4882a593Smuzhiyun mt9v011_write(sd, R09_MT9V011_SHUTTER_WIDTH, exposure);
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
calc_fps(struct v4l2_subdev * sd,u32 * numerator,u32 * denominator)201*4882a593Smuzhiyun static void calc_fps(struct v4l2_subdev *sd, u32 *numerator, u32 *denominator)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun struct mt9v011 *core = to_mt9v011(sd);
204*4882a593Smuzhiyun unsigned height, width, hblank, vblank, speed;
205*4882a593Smuzhiyun unsigned row_time, t_time;
206*4882a593Smuzhiyun u64 frames_per_ms;
207*4882a593Smuzhiyun unsigned tmp;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun height = mt9v011_read(sd, R03_MT9V011_HEIGHT);
210*4882a593Smuzhiyun width = mt9v011_read(sd, R04_MT9V011_WIDTH);
211*4882a593Smuzhiyun hblank = mt9v011_read(sd, R05_MT9V011_HBLANK);
212*4882a593Smuzhiyun vblank = mt9v011_read(sd, R06_MT9V011_VBLANK);
213*4882a593Smuzhiyun speed = mt9v011_read(sd, R0A_MT9V011_CLK_SPEED);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun row_time = (width + 113 + hblank) * (speed + 2);
216*4882a593Smuzhiyun t_time = row_time * (height + vblank + 1);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun frames_per_ms = core->xtal * 1000l;
219*4882a593Smuzhiyun do_div(frames_per_ms, t_time);
220*4882a593Smuzhiyun tmp = frames_per_ms;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "Programmed to %u.%03u fps (%d pixel clcks)\n",
223*4882a593Smuzhiyun tmp / 1000, tmp % 1000, t_time);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun if (numerator && denominator) {
226*4882a593Smuzhiyun *numerator = 1000;
227*4882a593Smuzhiyun *denominator = (u32)frames_per_ms;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
calc_speed(struct v4l2_subdev * sd,u32 numerator,u32 denominator)231*4882a593Smuzhiyun static u16 calc_speed(struct v4l2_subdev *sd, u32 numerator, u32 denominator)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun struct mt9v011 *core = to_mt9v011(sd);
234*4882a593Smuzhiyun unsigned height, width, hblank, vblank;
235*4882a593Smuzhiyun unsigned row_time, line_time;
236*4882a593Smuzhiyun u64 t_time, speed;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun /* Avoid bogus calculus */
239*4882a593Smuzhiyun if (!numerator || !denominator)
240*4882a593Smuzhiyun return 0;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun height = mt9v011_read(sd, R03_MT9V011_HEIGHT);
243*4882a593Smuzhiyun width = mt9v011_read(sd, R04_MT9V011_WIDTH);
244*4882a593Smuzhiyun hblank = mt9v011_read(sd, R05_MT9V011_HBLANK);
245*4882a593Smuzhiyun vblank = mt9v011_read(sd, R06_MT9V011_VBLANK);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun row_time = width + 113 + hblank;
248*4882a593Smuzhiyun line_time = height + vblank + 1;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun t_time = core->xtal * ((u64)numerator);
251*4882a593Smuzhiyun /* round to the closest value */
252*4882a593Smuzhiyun t_time += denominator / 2;
253*4882a593Smuzhiyun do_div(t_time, denominator);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun speed = t_time;
256*4882a593Smuzhiyun do_div(speed, row_time * line_time);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /* Avoid having a negative value for speed */
259*4882a593Smuzhiyun if (speed < 2)
260*4882a593Smuzhiyun speed = 0;
261*4882a593Smuzhiyun else
262*4882a593Smuzhiyun speed -= 2;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* Avoid speed overflow */
265*4882a593Smuzhiyun if (speed > 15)
266*4882a593Smuzhiyun return 15;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun return (u16)speed;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
set_res(struct v4l2_subdev * sd)271*4882a593Smuzhiyun static void set_res(struct v4l2_subdev *sd)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun struct mt9v011 *core = to_mt9v011(sd);
274*4882a593Smuzhiyun unsigned vstart, hstart;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun /*
277*4882a593Smuzhiyun * The mt9v011 doesn't have scaling. So, in order to select the desired
278*4882a593Smuzhiyun * resolution, we're cropping at the middle of the sensor.
279*4882a593Smuzhiyun * hblank and vblank should be adjusted, in order to warrant that
280*4882a593Smuzhiyun * we'll preserve the line timings for 30 fps, no matter what resolution
281*4882a593Smuzhiyun * is selected.
282*4882a593Smuzhiyun * NOTE: datasheet says that width (and height) should be filled with
283*4882a593Smuzhiyun * width-1. However, this doesn't work, since one pixel per line will
284*4882a593Smuzhiyun * be missing.
285*4882a593Smuzhiyun */
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun hstart = 20 + (640 - core->width) / 2;
288*4882a593Smuzhiyun mt9v011_write(sd, R02_MT9V011_COLSTART, hstart);
289*4882a593Smuzhiyun mt9v011_write(sd, R04_MT9V011_WIDTH, core->width);
290*4882a593Smuzhiyun mt9v011_write(sd, R05_MT9V011_HBLANK, 771 - core->width);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun vstart = 8 + (480 - core->height) / 2;
293*4882a593Smuzhiyun mt9v011_write(sd, R01_MT9V011_ROWSTART, vstart);
294*4882a593Smuzhiyun mt9v011_write(sd, R03_MT9V011_HEIGHT, core->height);
295*4882a593Smuzhiyun mt9v011_write(sd, R06_MT9V011_VBLANK, 508 - core->height);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun calc_fps(sd, NULL, NULL);
298*4882a593Smuzhiyun };
299*4882a593Smuzhiyun
set_read_mode(struct v4l2_subdev * sd)300*4882a593Smuzhiyun static void set_read_mode(struct v4l2_subdev *sd)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun struct mt9v011 *core = to_mt9v011(sd);
303*4882a593Smuzhiyun unsigned mode = 0x1000;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun if (core->hflip)
306*4882a593Smuzhiyun mode |= 0x4000;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun if (core->vflip)
309*4882a593Smuzhiyun mode |= 0x8000;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun mt9v011_write(sd, R20_MT9V011_READ_MODE, mode);
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
mt9v011_reset(struct v4l2_subdev * sd,u32 val)314*4882a593Smuzhiyun static int mt9v011_reset(struct v4l2_subdev *sd, u32 val)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun int i;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mt9v011_init_default); i++)
319*4882a593Smuzhiyun mt9v011_write(sd, mt9v011_init_default[i].reg,
320*4882a593Smuzhiyun mt9v011_init_default[i].value);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun set_balance(sd);
323*4882a593Smuzhiyun set_res(sd);
324*4882a593Smuzhiyun set_read_mode(sd);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun return 0;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
mt9v011_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)329*4882a593Smuzhiyun static int mt9v011_enum_mbus_code(struct v4l2_subdev *sd,
330*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
331*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun if (code->pad || code->index > 0)
334*4882a593Smuzhiyun return -EINVAL;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun code->code = MEDIA_BUS_FMT_SGRBG8_1X8;
337*4882a593Smuzhiyun return 0;
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
mt9v011_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)340*4882a593Smuzhiyun static int mt9v011_set_fmt(struct v4l2_subdev *sd,
341*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
342*4882a593Smuzhiyun struct v4l2_subdev_format *format)
343*4882a593Smuzhiyun {
344*4882a593Smuzhiyun struct v4l2_mbus_framefmt *fmt = &format->format;
345*4882a593Smuzhiyun struct mt9v011 *core = to_mt9v011(sd);
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun if (format->pad || fmt->code != MEDIA_BUS_FMT_SGRBG8_1X8)
348*4882a593Smuzhiyun return -EINVAL;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun v4l_bound_align_image(&fmt->width, 48, 639, 1,
351*4882a593Smuzhiyun &fmt->height, 32, 480, 1, 0);
352*4882a593Smuzhiyun fmt->field = V4L2_FIELD_NONE;
353*4882a593Smuzhiyun fmt->colorspace = V4L2_COLORSPACE_SRGB;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
356*4882a593Smuzhiyun core->width = fmt->width;
357*4882a593Smuzhiyun core->height = fmt->height;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun set_res(sd);
360*4882a593Smuzhiyun } else {
361*4882a593Smuzhiyun cfg->try_fmt = *fmt;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun return 0;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
mt9v011_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * ival)367*4882a593Smuzhiyun static int mt9v011_g_frame_interval(struct v4l2_subdev *sd,
368*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *ival)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun calc_fps(sd,
371*4882a593Smuzhiyun &ival->interval.numerator,
372*4882a593Smuzhiyun &ival->interval.denominator);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun return 0;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
mt9v011_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * ival)377*4882a593Smuzhiyun static int mt9v011_s_frame_interval(struct v4l2_subdev *sd,
378*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *ival)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun struct v4l2_fract *tpf = &ival->interval;
381*4882a593Smuzhiyun u16 speed;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun speed = calc_speed(sd, tpf->numerator, tpf->denominator);
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun mt9v011_write(sd, R0A_MT9V011_CLK_SPEED, speed);
386*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "Setting speed to %d\n", speed);
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun /* Recalculate and update fps info */
389*4882a593Smuzhiyun calc_fps(sd, &tpf->numerator, &tpf->denominator);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun return 0;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
mt9v011_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)395*4882a593Smuzhiyun static int mt9v011_g_register(struct v4l2_subdev *sd,
396*4882a593Smuzhiyun struct v4l2_dbg_register *reg)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun reg->val = mt9v011_read(sd, reg->reg & 0xff);
399*4882a593Smuzhiyun reg->size = 2;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun return 0;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
mt9v011_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)404*4882a593Smuzhiyun static int mt9v011_s_register(struct v4l2_subdev *sd,
405*4882a593Smuzhiyun const struct v4l2_dbg_register *reg)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun mt9v011_write(sd, reg->reg & 0xff, reg->val & 0xffff);
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun return 0;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun #endif
412*4882a593Smuzhiyun
mt9v011_s_ctrl(struct v4l2_ctrl * ctrl)413*4882a593Smuzhiyun static int mt9v011_s_ctrl(struct v4l2_ctrl *ctrl)
414*4882a593Smuzhiyun {
415*4882a593Smuzhiyun struct mt9v011 *core =
416*4882a593Smuzhiyun container_of(ctrl->handler, struct mt9v011, ctrls);
417*4882a593Smuzhiyun struct v4l2_subdev *sd = &core->sd;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun switch (ctrl->id) {
420*4882a593Smuzhiyun case V4L2_CID_GAIN:
421*4882a593Smuzhiyun core->global_gain = ctrl->val;
422*4882a593Smuzhiyun break;
423*4882a593Smuzhiyun case V4L2_CID_EXPOSURE:
424*4882a593Smuzhiyun core->exposure = ctrl->val;
425*4882a593Smuzhiyun break;
426*4882a593Smuzhiyun case V4L2_CID_RED_BALANCE:
427*4882a593Smuzhiyun core->red_bal = ctrl->val;
428*4882a593Smuzhiyun break;
429*4882a593Smuzhiyun case V4L2_CID_BLUE_BALANCE:
430*4882a593Smuzhiyun core->blue_bal = ctrl->val;
431*4882a593Smuzhiyun break;
432*4882a593Smuzhiyun case V4L2_CID_HFLIP:
433*4882a593Smuzhiyun core->hflip = ctrl->val;
434*4882a593Smuzhiyun set_read_mode(sd);
435*4882a593Smuzhiyun return 0;
436*4882a593Smuzhiyun case V4L2_CID_VFLIP:
437*4882a593Smuzhiyun core->vflip = ctrl->val;
438*4882a593Smuzhiyun set_read_mode(sd);
439*4882a593Smuzhiyun return 0;
440*4882a593Smuzhiyun default:
441*4882a593Smuzhiyun return -EINVAL;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun set_balance(sd);
445*4882a593Smuzhiyun return 0;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun static const struct v4l2_ctrl_ops mt9v011_ctrl_ops = {
449*4882a593Smuzhiyun .s_ctrl = mt9v011_s_ctrl,
450*4882a593Smuzhiyun };
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops mt9v011_core_ops = {
453*4882a593Smuzhiyun .reset = mt9v011_reset,
454*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
455*4882a593Smuzhiyun .g_register = mt9v011_g_register,
456*4882a593Smuzhiyun .s_register = mt9v011_s_register,
457*4882a593Smuzhiyun #endif
458*4882a593Smuzhiyun };
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops mt9v011_video_ops = {
461*4882a593Smuzhiyun .g_frame_interval = mt9v011_g_frame_interval,
462*4882a593Smuzhiyun .s_frame_interval = mt9v011_s_frame_interval,
463*4882a593Smuzhiyun };
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops mt9v011_pad_ops = {
466*4882a593Smuzhiyun .enum_mbus_code = mt9v011_enum_mbus_code,
467*4882a593Smuzhiyun .set_fmt = mt9v011_set_fmt,
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun static const struct v4l2_subdev_ops mt9v011_ops = {
471*4882a593Smuzhiyun .core = &mt9v011_core_ops,
472*4882a593Smuzhiyun .video = &mt9v011_video_ops,
473*4882a593Smuzhiyun .pad = &mt9v011_pad_ops,
474*4882a593Smuzhiyun };
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun /****************************************************************************
478*4882a593Smuzhiyun I2C Client & Driver
479*4882a593Smuzhiyun ****************************************************************************/
480*4882a593Smuzhiyun
mt9v011_probe(struct i2c_client * c,const struct i2c_device_id * id)481*4882a593Smuzhiyun static int mt9v011_probe(struct i2c_client *c,
482*4882a593Smuzhiyun const struct i2c_device_id *id)
483*4882a593Smuzhiyun {
484*4882a593Smuzhiyun u16 version;
485*4882a593Smuzhiyun struct mt9v011 *core;
486*4882a593Smuzhiyun struct v4l2_subdev *sd;
487*4882a593Smuzhiyun #ifdef CONFIG_MEDIA_CONTROLLER
488*4882a593Smuzhiyun int ret;
489*4882a593Smuzhiyun #endif
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun /* Check if the adapter supports the needed features */
492*4882a593Smuzhiyun if (!i2c_check_functionality(c->adapter,
493*4882a593Smuzhiyun I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
494*4882a593Smuzhiyun return -EIO;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun core = devm_kzalloc(&c->dev, sizeof(struct mt9v011), GFP_KERNEL);
497*4882a593Smuzhiyun if (!core)
498*4882a593Smuzhiyun return -ENOMEM;
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun sd = &core->sd;
501*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, c, &mt9v011_ops);
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun #ifdef CONFIG_MEDIA_CONTROLLER
504*4882a593Smuzhiyun core->pad.flags = MEDIA_PAD_FL_SOURCE;
505*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, 1, &core->pad);
508*4882a593Smuzhiyun if (ret < 0)
509*4882a593Smuzhiyun return ret;
510*4882a593Smuzhiyun #endif
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun /* Check if the sensor is really a MT9V011 */
513*4882a593Smuzhiyun version = mt9v011_read(sd, R00_MT9V011_CHIP_VERSION);
514*4882a593Smuzhiyun if ((version != MT9V011_VERSION) &&
515*4882a593Smuzhiyun (version != MT9V011_REV_B_VERSION)) {
516*4882a593Smuzhiyun v4l2_info(sd, "*** unknown micron chip detected (0x%04x).\n",
517*4882a593Smuzhiyun version);
518*4882a593Smuzhiyun return -EINVAL;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun v4l2_ctrl_handler_init(&core->ctrls, 5);
522*4882a593Smuzhiyun v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
523*4882a593Smuzhiyun V4L2_CID_GAIN, 0, (1 << 12) - 1 - 0x20, 1, 0x20);
524*4882a593Smuzhiyun v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
525*4882a593Smuzhiyun V4L2_CID_EXPOSURE, 0, 2047, 1, 0x01fc);
526*4882a593Smuzhiyun v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
527*4882a593Smuzhiyun V4L2_CID_RED_BALANCE, -(1 << 9), (1 << 9) - 1, 1, 0);
528*4882a593Smuzhiyun v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
529*4882a593Smuzhiyun V4L2_CID_BLUE_BALANCE, -(1 << 9), (1 << 9) - 1, 1, 0);
530*4882a593Smuzhiyun v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
531*4882a593Smuzhiyun V4L2_CID_HFLIP, 0, 1, 1, 0);
532*4882a593Smuzhiyun v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
533*4882a593Smuzhiyun V4L2_CID_VFLIP, 0, 1, 1, 0);
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun if (core->ctrls.error) {
536*4882a593Smuzhiyun int ret = core->ctrls.error;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun v4l2_err(sd, "control initialization error %d\n", ret);
539*4882a593Smuzhiyun v4l2_ctrl_handler_free(&core->ctrls);
540*4882a593Smuzhiyun return ret;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun core->sd.ctrl_handler = &core->ctrls;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun core->global_gain = 0x0024;
545*4882a593Smuzhiyun core->exposure = 0x01fc;
546*4882a593Smuzhiyun core->width = 640;
547*4882a593Smuzhiyun core->height = 480;
548*4882a593Smuzhiyun core->xtal = 27000000; /* Hz */
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun if (c->dev.platform_data) {
551*4882a593Smuzhiyun struct mt9v011_platform_data *pdata = c->dev.platform_data;
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun core->xtal = pdata->xtal;
554*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "xtal set to %d.%03d MHz\n",
555*4882a593Smuzhiyun core->xtal / 1000000, (core->xtal / 1000) % 1000);
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun v4l_info(c, "chip found @ 0x%02x (%s - chip version 0x%04x)\n",
559*4882a593Smuzhiyun c->addr << 1, c->adapter->name, version);
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun return 0;
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun
mt9v011_remove(struct i2c_client * c)564*4882a593Smuzhiyun static int mt9v011_remove(struct i2c_client *c)
565*4882a593Smuzhiyun {
566*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(c);
567*4882a593Smuzhiyun struct mt9v011 *core = to_mt9v011(sd);
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun v4l2_dbg(1, debug, sd,
570*4882a593Smuzhiyun "mt9v011.c: removing mt9v011 adapter on address 0x%x\n",
571*4882a593Smuzhiyun c->addr << 1);
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun v4l2_device_unregister_subdev(sd);
574*4882a593Smuzhiyun v4l2_ctrl_handler_free(&core->ctrls);
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun return 0;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun static const struct i2c_device_id mt9v011_id[] = {
582*4882a593Smuzhiyun { "mt9v011", 0 },
583*4882a593Smuzhiyun { }
584*4882a593Smuzhiyun };
585*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mt9v011_id);
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun static struct i2c_driver mt9v011_driver = {
588*4882a593Smuzhiyun .driver = {
589*4882a593Smuzhiyun .name = "mt9v011",
590*4882a593Smuzhiyun },
591*4882a593Smuzhiyun .probe = mt9v011_probe,
592*4882a593Smuzhiyun .remove = mt9v011_remove,
593*4882a593Smuzhiyun .id_table = mt9v011_id,
594*4882a593Smuzhiyun };
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun module_i2c_driver(mt9v011_driver);
597