xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/mt9m001.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Driver for MT9M001 CMOS Image Sensor from Micron
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/log2.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/pm_runtime.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/videodev2.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
19*4882a593Smuzhiyun #include <media/v4l2-device.h>
20*4882a593Smuzhiyun #include <media/v4l2-event.h>
21*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun  * mt9m001 i2c address 0x5d
25*4882a593Smuzhiyun  */
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* mt9m001 selected register addresses */
28*4882a593Smuzhiyun #define MT9M001_CHIP_VERSION		0x00
29*4882a593Smuzhiyun #define MT9M001_ROW_START		0x01
30*4882a593Smuzhiyun #define MT9M001_COLUMN_START		0x02
31*4882a593Smuzhiyun #define MT9M001_WINDOW_HEIGHT		0x03
32*4882a593Smuzhiyun #define MT9M001_WINDOW_WIDTH		0x04
33*4882a593Smuzhiyun #define MT9M001_HORIZONTAL_BLANKING	0x05
34*4882a593Smuzhiyun #define MT9M001_VERTICAL_BLANKING	0x06
35*4882a593Smuzhiyun #define MT9M001_OUTPUT_CONTROL		0x07
36*4882a593Smuzhiyun #define MT9M001_SHUTTER_WIDTH		0x09
37*4882a593Smuzhiyun #define MT9M001_FRAME_RESTART		0x0b
38*4882a593Smuzhiyun #define MT9M001_SHUTTER_DELAY		0x0c
39*4882a593Smuzhiyun #define MT9M001_RESET			0x0d
40*4882a593Smuzhiyun #define MT9M001_READ_OPTIONS1		0x1e
41*4882a593Smuzhiyun #define MT9M001_READ_OPTIONS2		0x20
42*4882a593Smuzhiyun #define MT9M001_GLOBAL_GAIN		0x35
43*4882a593Smuzhiyun #define MT9M001_CHIP_ENABLE		0xF1
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define MT9M001_MAX_WIDTH		1280
46*4882a593Smuzhiyun #define MT9M001_MAX_HEIGHT		1024
47*4882a593Smuzhiyun #define MT9M001_MIN_WIDTH		48
48*4882a593Smuzhiyun #define MT9M001_MIN_HEIGHT		32
49*4882a593Smuzhiyun #define MT9M001_COLUMN_SKIP		20
50*4882a593Smuzhiyun #define MT9M001_ROW_SKIP		12
51*4882a593Smuzhiyun #define MT9M001_DEFAULT_HBLANK		9
52*4882a593Smuzhiyun #define MT9M001_DEFAULT_VBLANK		25
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /* MT9M001 has only one fixed colorspace per pixelcode */
55*4882a593Smuzhiyun struct mt9m001_datafmt {
56*4882a593Smuzhiyun 	u32	code;
57*4882a593Smuzhiyun 	enum v4l2_colorspace		colorspace;
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /* Find a data format by a pixel code in an array */
mt9m001_find_datafmt(u32 code,const struct mt9m001_datafmt * fmt,int n)61*4882a593Smuzhiyun static const struct mt9m001_datafmt *mt9m001_find_datafmt(
62*4882a593Smuzhiyun 	u32 code, const struct mt9m001_datafmt *fmt,
63*4882a593Smuzhiyun 	int n)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	int i;
66*4882a593Smuzhiyun 	for (i = 0; i < n; i++)
67*4882a593Smuzhiyun 		if (fmt[i].code == code)
68*4882a593Smuzhiyun 			return fmt + i;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	return NULL;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun static const struct mt9m001_datafmt mt9m001_colour_fmts[] = {
74*4882a593Smuzhiyun 	/*
75*4882a593Smuzhiyun 	 * Order important: first natively supported,
76*4882a593Smuzhiyun 	 * second supported with a GPIO extender
77*4882a593Smuzhiyun 	 */
78*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB},
79*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun static const struct mt9m001_datafmt mt9m001_monochrome_fmts[] = {
83*4882a593Smuzhiyun 	/* Order important - see above */
84*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_Y10_1X10, V4L2_COLORSPACE_JPEG},
85*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_Y8_1X8, V4L2_COLORSPACE_JPEG},
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun struct mt9m001 {
89*4882a593Smuzhiyun 	struct v4l2_subdev subdev;
90*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
91*4882a593Smuzhiyun 	struct {
92*4882a593Smuzhiyun 		/* exposure/auto-exposure cluster */
93*4882a593Smuzhiyun 		struct v4l2_ctrl *autoexposure;
94*4882a593Smuzhiyun 		struct v4l2_ctrl *exposure;
95*4882a593Smuzhiyun 	};
96*4882a593Smuzhiyun 	bool streaming;
97*4882a593Smuzhiyun 	struct mutex mutex;
98*4882a593Smuzhiyun 	struct v4l2_rect rect;	/* Sensor window */
99*4882a593Smuzhiyun 	struct clk *clk;
100*4882a593Smuzhiyun 	struct gpio_desc *standby_gpio;
101*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
102*4882a593Smuzhiyun 	const struct mt9m001_datafmt *fmt;
103*4882a593Smuzhiyun 	const struct mt9m001_datafmt *fmts;
104*4882a593Smuzhiyun 	int num_fmts;
105*4882a593Smuzhiyun 	unsigned int total_h;
106*4882a593Smuzhiyun 	unsigned short y_skip_top;	/* Lines to skip at the top */
107*4882a593Smuzhiyun 	struct media_pad pad;
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun 
to_mt9m001(const struct i2c_client * client)110*4882a593Smuzhiyun static struct mt9m001 *to_mt9m001(const struct i2c_client *client)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	return container_of(i2c_get_clientdata(client), struct mt9m001, subdev);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
reg_read(struct i2c_client * client,const u8 reg)115*4882a593Smuzhiyun static int reg_read(struct i2c_client *client, const u8 reg)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	return i2c_smbus_read_word_swapped(client, reg);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
reg_write(struct i2c_client * client,const u8 reg,const u16 data)120*4882a593Smuzhiyun static int reg_write(struct i2c_client *client, const u8 reg,
121*4882a593Smuzhiyun 		     const u16 data)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun 	return i2c_smbus_write_word_swapped(client, reg, data);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
reg_set(struct i2c_client * client,const u8 reg,const u16 data)126*4882a593Smuzhiyun static int reg_set(struct i2c_client *client, const u8 reg,
127*4882a593Smuzhiyun 		   const u16 data)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	int ret;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	ret = reg_read(client, reg);
132*4882a593Smuzhiyun 	if (ret < 0)
133*4882a593Smuzhiyun 		return ret;
134*4882a593Smuzhiyun 	return reg_write(client, reg, ret | data);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
reg_clear(struct i2c_client * client,const u8 reg,const u16 data)137*4882a593Smuzhiyun static int reg_clear(struct i2c_client *client, const u8 reg,
138*4882a593Smuzhiyun 		     const u16 data)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	int ret;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	ret = reg_read(client, reg);
143*4882a593Smuzhiyun 	if (ret < 0)
144*4882a593Smuzhiyun 		return ret;
145*4882a593Smuzhiyun 	return reg_write(client, reg, ret & ~data);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun struct mt9m001_reg {
149*4882a593Smuzhiyun 	u8 reg;
150*4882a593Smuzhiyun 	u16 data;
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun 
multi_reg_write(struct i2c_client * client,const struct mt9m001_reg * regs,int num)153*4882a593Smuzhiyun static int multi_reg_write(struct i2c_client *client,
154*4882a593Smuzhiyun 			   const struct mt9m001_reg *regs, int num)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun 	int i;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	for (i = 0; i < num; i++) {
159*4882a593Smuzhiyun 		int ret = reg_write(client, regs[i].reg, regs[i].data);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 		if (ret)
162*4882a593Smuzhiyun 			return ret;
163*4882a593Smuzhiyun 	}
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	return 0;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
mt9m001_init(struct i2c_client * client)168*4882a593Smuzhiyun static int mt9m001_init(struct i2c_client *client)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun 	static const struct mt9m001_reg init_regs[] = {
171*4882a593Smuzhiyun 		/*
172*4882a593Smuzhiyun 		 * Issue a soft reset. This returns all registers to their
173*4882a593Smuzhiyun 		 * default values.
174*4882a593Smuzhiyun 		 */
175*4882a593Smuzhiyun 		{ MT9M001_RESET, 1 },
176*4882a593Smuzhiyun 		{ MT9M001_RESET, 0 },
177*4882a593Smuzhiyun 		/* Disable chip, synchronous option update */
178*4882a593Smuzhiyun 		{ MT9M001_OUTPUT_CONTROL, 0 }
179*4882a593Smuzhiyun 	};
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	dev_dbg(&client->dev, "%s\n", __func__);
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	return multi_reg_write(client, init_regs, ARRAY_SIZE(init_regs));
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
mt9m001_apply_selection(struct v4l2_subdev * sd)186*4882a593Smuzhiyun static int mt9m001_apply_selection(struct v4l2_subdev *sd)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
189*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
190*4882a593Smuzhiyun 	const struct mt9m001_reg regs[] = {
191*4882a593Smuzhiyun 		/* Blanking and start values - default... */
192*4882a593Smuzhiyun 		{ MT9M001_HORIZONTAL_BLANKING, MT9M001_DEFAULT_HBLANK },
193*4882a593Smuzhiyun 		{ MT9M001_VERTICAL_BLANKING, MT9M001_DEFAULT_VBLANK },
194*4882a593Smuzhiyun 		/*
195*4882a593Smuzhiyun 		 * The caller provides a supported format, as verified per
196*4882a593Smuzhiyun 		 * call to .set_fmt(FORMAT_TRY).
197*4882a593Smuzhiyun 		 */
198*4882a593Smuzhiyun 		{ MT9M001_COLUMN_START, mt9m001->rect.left },
199*4882a593Smuzhiyun 		{ MT9M001_ROW_START, mt9m001->rect.top },
200*4882a593Smuzhiyun 		{ MT9M001_WINDOW_WIDTH, mt9m001->rect.width - 1 },
201*4882a593Smuzhiyun 		{ MT9M001_WINDOW_HEIGHT,
202*4882a593Smuzhiyun 			mt9m001->rect.height + mt9m001->y_skip_top - 1 },
203*4882a593Smuzhiyun 	};
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	return multi_reg_write(client, regs, ARRAY_SIZE(regs));
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
mt9m001_s_stream(struct v4l2_subdev * sd,int enable)208*4882a593Smuzhiyun static int mt9m001_s_stream(struct v4l2_subdev *sd, int enable)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
211*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
212*4882a593Smuzhiyun 	int ret = 0;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	mutex_lock(&mt9m001->mutex);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	if (mt9m001->streaming == enable)
217*4882a593Smuzhiyun 		goto done;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	if (enable) {
220*4882a593Smuzhiyun 		ret = pm_runtime_get_sync(&client->dev);
221*4882a593Smuzhiyun 		if (ret < 0)
222*4882a593Smuzhiyun 			goto put_unlock;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 		ret = mt9m001_apply_selection(sd);
225*4882a593Smuzhiyun 		if (ret)
226*4882a593Smuzhiyun 			goto put_unlock;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 		ret = __v4l2_ctrl_handler_setup(&mt9m001->hdl);
229*4882a593Smuzhiyun 		if (ret)
230*4882a593Smuzhiyun 			goto put_unlock;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 		/* Switch to master "normal" mode */
233*4882a593Smuzhiyun 		ret = reg_write(client, MT9M001_OUTPUT_CONTROL, 2);
234*4882a593Smuzhiyun 		if (ret < 0)
235*4882a593Smuzhiyun 			goto put_unlock;
236*4882a593Smuzhiyun 	} else {
237*4882a593Smuzhiyun 		/* Switch to master stop sensor readout */
238*4882a593Smuzhiyun 		reg_write(client, MT9M001_OUTPUT_CONTROL, 0);
239*4882a593Smuzhiyun 		pm_runtime_put(&client->dev);
240*4882a593Smuzhiyun 	}
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	mt9m001->streaming = enable;
243*4882a593Smuzhiyun done:
244*4882a593Smuzhiyun 	mutex_unlock(&mt9m001->mutex);
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	return 0;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun put_unlock:
249*4882a593Smuzhiyun 	pm_runtime_put(&client->dev);
250*4882a593Smuzhiyun 	mutex_unlock(&mt9m001->mutex);
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	return ret;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun 
mt9m001_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)255*4882a593Smuzhiyun static int mt9m001_set_selection(struct v4l2_subdev *sd,
256*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
257*4882a593Smuzhiyun 		struct v4l2_subdev_selection *sel)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
260*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
261*4882a593Smuzhiyun 	struct v4l2_rect rect = sel->r;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
264*4882a593Smuzhiyun 	    sel->target != V4L2_SEL_TGT_CROP)
265*4882a593Smuzhiyun 		return -EINVAL;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	if (mt9m001->fmts == mt9m001_colour_fmts)
268*4882a593Smuzhiyun 		/*
269*4882a593Smuzhiyun 		 * Bayer format - even number of rows for simplicity,
270*4882a593Smuzhiyun 		 * but let the user play with the top row.
271*4882a593Smuzhiyun 		 */
272*4882a593Smuzhiyun 		rect.height = ALIGN(rect.height, 2);
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	/* Datasheet requirement: see register description */
275*4882a593Smuzhiyun 	rect.width = ALIGN(rect.width, 2);
276*4882a593Smuzhiyun 	rect.left = ALIGN(rect.left, 2);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	rect.width = clamp_t(u32, rect.width, MT9M001_MIN_WIDTH,
279*4882a593Smuzhiyun 			MT9M001_MAX_WIDTH);
280*4882a593Smuzhiyun 	rect.left = clamp_t(u32, rect.left, MT9M001_COLUMN_SKIP,
281*4882a593Smuzhiyun 			MT9M001_COLUMN_SKIP + MT9M001_MAX_WIDTH - rect.width);
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	rect.height = clamp_t(u32, rect.height, MT9M001_MIN_HEIGHT,
284*4882a593Smuzhiyun 			MT9M001_MAX_HEIGHT);
285*4882a593Smuzhiyun 	rect.top = clamp_t(u32, rect.top, MT9M001_ROW_SKIP,
286*4882a593Smuzhiyun 			MT9M001_ROW_SKIP + MT9M001_MAX_HEIGHT - rect.height);
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	mt9m001->total_h = rect.height + mt9m001->y_skip_top +
289*4882a593Smuzhiyun 			   MT9M001_DEFAULT_VBLANK;
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	mt9m001->rect = rect;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	return 0;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun 
mt9m001_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)296*4882a593Smuzhiyun static int mt9m001_get_selection(struct v4l2_subdev *sd,
297*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
298*4882a593Smuzhiyun 		struct v4l2_subdev_selection *sel)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
301*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
304*4882a593Smuzhiyun 		return -EINVAL;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	switch (sel->target) {
307*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP_BOUNDS:
308*4882a593Smuzhiyun 		sel->r.left = MT9M001_COLUMN_SKIP;
309*4882a593Smuzhiyun 		sel->r.top = MT9M001_ROW_SKIP;
310*4882a593Smuzhiyun 		sel->r.width = MT9M001_MAX_WIDTH;
311*4882a593Smuzhiyun 		sel->r.height = MT9M001_MAX_HEIGHT;
312*4882a593Smuzhiyun 		return 0;
313*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP:
314*4882a593Smuzhiyun 		sel->r = mt9m001->rect;
315*4882a593Smuzhiyun 		return 0;
316*4882a593Smuzhiyun 	default:
317*4882a593Smuzhiyun 		return -EINVAL;
318*4882a593Smuzhiyun 	}
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun 
mt9m001_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)321*4882a593Smuzhiyun static int mt9m001_get_fmt(struct v4l2_subdev *sd,
322*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
323*4882a593Smuzhiyun 		struct v4l2_subdev_format *format)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
326*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
327*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &format->format;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	if (format->pad)
330*4882a593Smuzhiyun 		return -EINVAL;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
333*4882a593Smuzhiyun 		mf = v4l2_subdev_get_try_format(sd, cfg, 0);
334*4882a593Smuzhiyun 		format->format = *mf;
335*4882a593Smuzhiyun 		return 0;
336*4882a593Smuzhiyun 	}
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	mf->width	= mt9m001->rect.width;
339*4882a593Smuzhiyun 	mf->height	= mt9m001->rect.height;
340*4882a593Smuzhiyun 	mf->code	= mt9m001->fmt->code;
341*4882a593Smuzhiyun 	mf->colorspace	= mt9m001->fmt->colorspace;
342*4882a593Smuzhiyun 	mf->field	= V4L2_FIELD_NONE;
343*4882a593Smuzhiyun 	mf->ycbcr_enc	= V4L2_YCBCR_ENC_DEFAULT;
344*4882a593Smuzhiyun 	mf->quantization = V4L2_QUANTIZATION_DEFAULT;
345*4882a593Smuzhiyun 	mf->xfer_func	= V4L2_XFER_FUNC_DEFAULT;
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	return 0;
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun 
mt9m001_s_fmt(struct v4l2_subdev * sd,const struct mt9m001_datafmt * fmt,struct v4l2_mbus_framefmt * mf)350*4882a593Smuzhiyun static int mt9m001_s_fmt(struct v4l2_subdev *sd,
351*4882a593Smuzhiyun 			 const struct mt9m001_datafmt *fmt,
352*4882a593Smuzhiyun 			 struct v4l2_mbus_framefmt *mf)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
355*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
356*4882a593Smuzhiyun 	struct v4l2_subdev_selection sel = {
357*4882a593Smuzhiyun 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
358*4882a593Smuzhiyun 		.target = V4L2_SEL_TGT_CROP,
359*4882a593Smuzhiyun 		.r.left = mt9m001->rect.left,
360*4882a593Smuzhiyun 		.r.top = mt9m001->rect.top,
361*4882a593Smuzhiyun 		.r.width = mf->width,
362*4882a593Smuzhiyun 		.r.height = mf->height,
363*4882a593Smuzhiyun 	};
364*4882a593Smuzhiyun 	int ret;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	/* No support for scaling so far, just crop. TODO: use skipping */
367*4882a593Smuzhiyun 	ret = mt9m001_set_selection(sd, NULL, &sel);
368*4882a593Smuzhiyun 	if (!ret) {
369*4882a593Smuzhiyun 		mf->width	= mt9m001->rect.width;
370*4882a593Smuzhiyun 		mf->height	= mt9m001->rect.height;
371*4882a593Smuzhiyun 		mt9m001->fmt	= fmt;
372*4882a593Smuzhiyun 		mf->colorspace	= fmt->colorspace;
373*4882a593Smuzhiyun 	}
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	return ret;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun 
mt9m001_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)378*4882a593Smuzhiyun static int mt9m001_set_fmt(struct v4l2_subdev *sd,
379*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
380*4882a593Smuzhiyun 		struct v4l2_subdev_format *format)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &format->format;
383*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
384*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
385*4882a593Smuzhiyun 	const struct mt9m001_datafmt *fmt;
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	if (format->pad)
388*4882a593Smuzhiyun 		return -EINVAL;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	v4l_bound_align_image(&mf->width, MT9M001_MIN_WIDTH,
391*4882a593Smuzhiyun 		MT9M001_MAX_WIDTH, 1,
392*4882a593Smuzhiyun 		&mf->height, MT9M001_MIN_HEIGHT + mt9m001->y_skip_top,
393*4882a593Smuzhiyun 		MT9M001_MAX_HEIGHT + mt9m001->y_skip_top, 0, 0);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	if (mt9m001->fmts == mt9m001_colour_fmts)
396*4882a593Smuzhiyun 		mf->height = ALIGN(mf->height - 1, 2);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	fmt = mt9m001_find_datafmt(mf->code, mt9m001->fmts,
399*4882a593Smuzhiyun 				   mt9m001->num_fmts);
400*4882a593Smuzhiyun 	if (!fmt) {
401*4882a593Smuzhiyun 		fmt = mt9m001->fmt;
402*4882a593Smuzhiyun 		mf->code = fmt->code;
403*4882a593Smuzhiyun 	}
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	mf->colorspace	= fmt->colorspace;
406*4882a593Smuzhiyun 	mf->field	= V4L2_FIELD_NONE;
407*4882a593Smuzhiyun 	mf->ycbcr_enc	= V4L2_YCBCR_ENC_DEFAULT;
408*4882a593Smuzhiyun 	mf->quantization = V4L2_QUANTIZATION_DEFAULT;
409*4882a593Smuzhiyun 	mf->xfer_func	= V4L2_XFER_FUNC_DEFAULT;
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
412*4882a593Smuzhiyun 		return mt9m001_s_fmt(sd, fmt, mf);
413*4882a593Smuzhiyun 	cfg->try_fmt = *mf;
414*4882a593Smuzhiyun 	return 0;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
mt9m001_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)418*4882a593Smuzhiyun static int mt9m001_g_register(struct v4l2_subdev *sd,
419*4882a593Smuzhiyun 			      struct v4l2_dbg_register *reg)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	if (reg->reg > 0xff)
424*4882a593Smuzhiyun 		return -EINVAL;
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	reg->size = 2;
427*4882a593Smuzhiyun 	reg->val = reg_read(client, reg->reg);
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	if (reg->val > 0xffff)
430*4882a593Smuzhiyun 		return -EIO;
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	return 0;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun 
mt9m001_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)435*4882a593Smuzhiyun static int mt9m001_s_register(struct v4l2_subdev *sd,
436*4882a593Smuzhiyun 			      const struct v4l2_dbg_register *reg)
437*4882a593Smuzhiyun {
438*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 	if (reg->reg > 0xff)
441*4882a593Smuzhiyun 		return -EINVAL;
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	if (reg_write(client, reg->reg, reg->val) < 0)
444*4882a593Smuzhiyun 		return -EIO;
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	return 0;
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun #endif
449*4882a593Smuzhiyun 
mt9m001_power_on(struct device * dev)450*4882a593Smuzhiyun static int mt9m001_power_on(struct device *dev)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
453*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
454*4882a593Smuzhiyun 	int ret;
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	ret = clk_prepare_enable(mt9m001->clk);
457*4882a593Smuzhiyun 	if (ret)
458*4882a593Smuzhiyun 		return ret;
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun 	if (mt9m001->standby_gpio) {
461*4882a593Smuzhiyun 		gpiod_set_value_cansleep(mt9m001->standby_gpio, 0);
462*4882a593Smuzhiyun 		usleep_range(1000, 2000);
463*4882a593Smuzhiyun 	}
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	if (mt9m001->reset_gpio) {
466*4882a593Smuzhiyun 		gpiod_set_value_cansleep(mt9m001->reset_gpio, 1);
467*4882a593Smuzhiyun 		usleep_range(1000, 2000);
468*4882a593Smuzhiyun 		gpiod_set_value_cansleep(mt9m001->reset_gpio, 0);
469*4882a593Smuzhiyun 		usleep_range(1000, 2000);
470*4882a593Smuzhiyun 	}
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	return 0;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun 
mt9m001_power_off(struct device * dev)475*4882a593Smuzhiyun static int mt9m001_power_off(struct device *dev)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
478*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	gpiod_set_value_cansleep(mt9m001->standby_gpio, 1);
481*4882a593Smuzhiyun 	clk_disable_unprepare(mt9m001->clk);
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	return 0;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun 
mt9m001_g_volatile_ctrl(struct v4l2_ctrl * ctrl)486*4882a593Smuzhiyun static int mt9m001_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
487*4882a593Smuzhiyun {
488*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = container_of(ctrl->handler,
489*4882a593Smuzhiyun 					       struct mt9m001, hdl);
490*4882a593Smuzhiyun 	s32 min, max;
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	switch (ctrl->id) {
493*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE_AUTO:
494*4882a593Smuzhiyun 		min = mt9m001->exposure->minimum;
495*4882a593Smuzhiyun 		max = mt9m001->exposure->maximum;
496*4882a593Smuzhiyun 		mt9m001->exposure->val =
497*4882a593Smuzhiyun 			(524 + (mt9m001->total_h - 1) * (max - min)) / 1048 + min;
498*4882a593Smuzhiyun 		break;
499*4882a593Smuzhiyun 	}
500*4882a593Smuzhiyun 	return 0;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun 
mt9m001_s_ctrl(struct v4l2_ctrl * ctrl)503*4882a593Smuzhiyun static int mt9m001_s_ctrl(struct v4l2_ctrl *ctrl)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = container_of(ctrl->handler,
506*4882a593Smuzhiyun 					       struct mt9m001, hdl);
507*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &mt9m001->subdev;
508*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
509*4882a593Smuzhiyun 	struct v4l2_ctrl *exp = mt9m001->exposure;
510*4882a593Smuzhiyun 	int data;
511*4882a593Smuzhiyun 	int ret;
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun 	if (!pm_runtime_get_if_in_use(&client->dev))
514*4882a593Smuzhiyun 		return 0;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	switch (ctrl->id) {
517*4882a593Smuzhiyun 	case V4L2_CID_VFLIP:
518*4882a593Smuzhiyun 		if (ctrl->val)
519*4882a593Smuzhiyun 			ret = reg_set(client, MT9M001_READ_OPTIONS2, 0x8000);
520*4882a593Smuzhiyun 		else
521*4882a593Smuzhiyun 			ret = reg_clear(client, MT9M001_READ_OPTIONS2, 0x8000);
522*4882a593Smuzhiyun 		break;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	case V4L2_CID_GAIN:
525*4882a593Smuzhiyun 		/* See Datasheet Table 7, Gain settings. */
526*4882a593Smuzhiyun 		if (ctrl->val <= ctrl->default_value) {
527*4882a593Smuzhiyun 			/* Pack it into 0..1 step 0.125, register values 0..8 */
528*4882a593Smuzhiyun 			unsigned long range = ctrl->default_value - ctrl->minimum;
529*4882a593Smuzhiyun 			data = ((ctrl->val - (s32)ctrl->minimum) * 8 + range / 2) / range;
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 			dev_dbg(&client->dev, "Setting gain %d\n", data);
532*4882a593Smuzhiyun 			ret = reg_write(client, MT9M001_GLOBAL_GAIN, data);
533*4882a593Smuzhiyun 		} else {
534*4882a593Smuzhiyun 			/* Pack it into 1.125..15 variable step, register values 9..67 */
535*4882a593Smuzhiyun 			/* We assume qctrl->maximum - qctrl->default_value - 1 > 0 */
536*4882a593Smuzhiyun 			unsigned long range = ctrl->maximum - ctrl->default_value - 1;
537*4882a593Smuzhiyun 			unsigned long gain = ((ctrl->val - (s32)ctrl->default_value - 1) *
538*4882a593Smuzhiyun 					       111 + range / 2) / range + 9;
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 			if (gain <= 32)
541*4882a593Smuzhiyun 				data = gain;
542*4882a593Smuzhiyun 			else if (gain <= 64)
543*4882a593Smuzhiyun 				data = ((gain - 32) * 16 + 16) / 32 + 80;
544*4882a593Smuzhiyun 			else
545*4882a593Smuzhiyun 				data = ((gain - 64) * 7 + 28) / 56 + 96;
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 			dev_dbg(&client->dev, "Setting gain from %d to %d\n",
548*4882a593Smuzhiyun 				 reg_read(client, MT9M001_GLOBAL_GAIN), data);
549*4882a593Smuzhiyun 			ret = reg_write(client, MT9M001_GLOBAL_GAIN, data);
550*4882a593Smuzhiyun 		}
551*4882a593Smuzhiyun 		break;
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE_AUTO:
554*4882a593Smuzhiyun 		if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
555*4882a593Smuzhiyun 			unsigned long range = exp->maximum - exp->minimum;
556*4882a593Smuzhiyun 			unsigned long shutter = ((exp->val - (s32)exp->minimum) * 1048 +
557*4882a593Smuzhiyun 						 range / 2) / range + 1;
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 			dev_dbg(&client->dev,
560*4882a593Smuzhiyun 				"Setting shutter width from %d to %lu\n",
561*4882a593Smuzhiyun 				reg_read(client, MT9M001_SHUTTER_WIDTH), shutter);
562*4882a593Smuzhiyun 			ret = reg_write(client, MT9M001_SHUTTER_WIDTH, shutter);
563*4882a593Smuzhiyun 		} else {
564*4882a593Smuzhiyun 			mt9m001->total_h = mt9m001->rect.height +
565*4882a593Smuzhiyun 				mt9m001->y_skip_top + MT9M001_DEFAULT_VBLANK;
566*4882a593Smuzhiyun 			ret = reg_write(client, MT9M001_SHUTTER_WIDTH,
567*4882a593Smuzhiyun 					mt9m001->total_h);
568*4882a593Smuzhiyun 		}
569*4882a593Smuzhiyun 		break;
570*4882a593Smuzhiyun 	default:
571*4882a593Smuzhiyun 		ret = -EINVAL;
572*4882a593Smuzhiyun 		break;
573*4882a593Smuzhiyun 	}
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	pm_runtime_put(&client->dev);
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	return ret;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun /*
581*4882a593Smuzhiyun  * Interface active, can use i2c. If it fails, it can indeed mean, that
582*4882a593Smuzhiyun  * this wasn't our capture interface, so, we wait for the right one
583*4882a593Smuzhiyun  */
mt9m001_video_probe(struct i2c_client * client)584*4882a593Smuzhiyun static int mt9m001_video_probe(struct i2c_client *client)
585*4882a593Smuzhiyun {
586*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
587*4882a593Smuzhiyun 	s32 data;
588*4882a593Smuzhiyun 	int ret;
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	/* Enable the chip */
591*4882a593Smuzhiyun 	data = reg_write(client, MT9M001_CHIP_ENABLE, 1);
592*4882a593Smuzhiyun 	dev_dbg(&client->dev, "write: %d\n", data);
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	/* Read out the chip version register */
595*4882a593Smuzhiyun 	data = reg_read(client, MT9M001_CHIP_VERSION);
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	/* must be 0x8411 or 0x8421 for colour sensor and 8431 for bw */
598*4882a593Smuzhiyun 	switch (data) {
599*4882a593Smuzhiyun 	case 0x8411:
600*4882a593Smuzhiyun 	case 0x8421:
601*4882a593Smuzhiyun 		mt9m001->fmts = mt9m001_colour_fmts;
602*4882a593Smuzhiyun 		mt9m001->num_fmts = ARRAY_SIZE(mt9m001_colour_fmts);
603*4882a593Smuzhiyun 		break;
604*4882a593Smuzhiyun 	case 0x8431:
605*4882a593Smuzhiyun 		mt9m001->fmts = mt9m001_monochrome_fmts;
606*4882a593Smuzhiyun 		mt9m001->num_fmts = ARRAY_SIZE(mt9m001_monochrome_fmts);
607*4882a593Smuzhiyun 		break;
608*4882a593Smuzhiyun 	default:
609*4882a593Smuzhiyun 		dev_err(&client->dev,
610*4882a593Smuzhiyun 			"No MT9M001 chip detected, register read %x\n", data);
611*4882a593Smuzhiyun 		ret = -ENODEV;
612*4882a593Smuzhiyun 		goto done;
613*4882a593Smuzhiyun 	}
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	mt9m001->fmt = &mt9m001->fmts[0];
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun 	dev_info(&client->dev, "Detected a MT9M001 chip ID %x (%s)\n", data,
618*4882a593Smuzhiyun 		 data == 0x8431 ? "C12STM" : "C12ST");
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun 	ret = mt9m001_init(client);
621*4882a593Smuzhiyun 	if (ret < 0) {
622*4882a593Smuzhiyun 		dev_err(&client->dev, "Failed to initialise the camera\n");
623*4882a593Smuzhiyun 		goto done;
624*4882a593Smuzhiyun 	}
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 	/* mt9m001_init() has reset the chip, returning registers to defaults */
627*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_setup(&mt9m001->hdl);
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun done:
630*4882a593Smuzhiyun 	return ret;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun 
mt9m001_g_skip_top_lines(struct v4l2_subdev * sd,u32 * lines)633*4882a593Smuzhiyun static int mt9m001_g_skip_top_lines(struct v4l2_subdev *sd, u32 *lines)
634*4882a593Smuzhiyun {
635*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
636*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 	*lines = mt9m001->y_skip_top;
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun 	return 0;
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun static const struct v4l2_ctrl_ops mt9m001_ctrl_ops = {
644*4882a593Smuzhiyun 	.g_volatile_ctrl = mt9m001_g_volatile_ctrl,
645*4882a593Smuzhiyun 	.s_ctrl = mt9m001_s_ctrl,
646*4882a593Smuzhiyun };
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops mt9m001_subdev_core_ops = {
649*4882a593Smuzhiyun 	.log_status = v4l2_ctrl_subdev_log_status,
650*4882a593Smuzhiyun 	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,
651*4882a593Smuzhiyun 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
652*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
653*4882a593Smuzhiyun 	.g_register	= mt9m001_g_register,
654*4882a593Smuzhiyun 	.s_register	= mt9m001_s_register,
655*4882a593Smuzhiyun #endif
656*4882a593Smuzhiyun };
657*4882a593Smuzhiyun 
mt9m001_init_cfg(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg)658*4882a593Smuzhiyun static int mt9m001_init_cfg(struct v4l2_subdev *sd,
659*4882a593Smuzhiyun 			    struct v4l2_subdev_pad_config *cfg)
660*4882a593Smuzhiyun {
661*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
662*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
663*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *try_fmt =
664*4882a593Smuzhiyun 		v4l2_subdev_get_try_format(sd, cfg, 0);
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	try_fmt->width		= MT9M001_MAX_WIDTH;
667*4882a593Smuzhiyun 	try_fmt->height		= MT9M001_MAX_HEIGHT;
668*4882a593Smuzhiyun 	try_fmt->code		= mt9m001->fmts[0].code;
669*4882a593Smuzhiyun 	try_fmt->colorspace	= mt9m001->fmts[0].colorspace;
670*4882a593Smuzhiyun 	try_fmt->field		= V4L2_FIELD_NONE;
671*4882a593Smuzhiyun 	try_fmt->ycbcr_enc	= V4L2_YCBCR_ENC_DEFAULT;
672*4882a593Smuzhiyun 	try_fmt->quantization	= V4L2_QUANTIZATION_DEFAULT;
673*4882a593Smuzhiyun 	try_fmt->xfer_func	= V4L2_XFER_FUNC_DEFAULT;
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	return 0;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun 
mt9m001_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)678*4882a593Smuzhiyun static int mt9m001_enum_mbus_code(struct v4l2_subdev *sd,
679*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
680*4882a593Smuzhiyun 		struct v4l2_subdev_mbus_code_enum *code)
681*4882a593Smuzhiyun {
682*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
683*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun 	if (code->pad || code->index >= mt9m001->num_fmts)
686*4882a593Smuzhiyun 		return -EINVAL;
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	code->code = mt9m001->fmts[code->index].code;
689*4882a593Smuzhiyun 	return 0;
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun 
mt9m001_get_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)692*4882a593Smuzhiyun static int mt9m001_get_mbus_config(struct v4l2_subdev *sd,
693*4882a593Smuzhiyun 				   unsigned int pad,
694*4882a593Smuzhiyun 				   struct v4l2_mbus_config *cfg)
695*4882a593Smuzhiyun {
696*4882a593Smuzhiyun 	/* MT9M001 has all capture_format parameters fixed */
697*4882a593Smuzhiyun 	cfg->flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
698*4882a593Smuzhiyun 		V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
699*4882a593Smuzhiyun 		V4L2_MBUS_DATA_ACTIVE_HIGH | V4L2_MBUS_MASTER;
700*4882a593Smuzhiyun 	cfg->type = V4L2_MBUS_PARALLEL;
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun 	return 0;
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops mt9m001_subdev_video_ops = {
706*4882a593Smuzhiyun 	.s_stream	= mt9m001_s_stream,
707*4882a593Smuzhiyun };
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun static const struct v4l2_subdev_sensor_ops mt9m001_subdev_sensor_ops = {
710*4882a593Smuzhiyun 	.g_skip_top_lines	= mt9m001_g_skip_top_lines,
711*4882a593Smuzhiyun };
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops mt9m001_subdev_pad_ops = {
714*4882a593Smuzhiyun 	.init_cfg	= mt9m001_init_cfg,
715*4882a593Smuzhiyun 	.enum_mbus_code = mt9m001_enum_mbus_code,
716*4882a593Smuzhiyun 	.get_selection	= mt9m001_get_selection,
717*4882a593Smuzhiyun 	.set_selection	= mt9m001_set_selection,
718*4882a593Smuzhiyun 	.get_fmt	= mt9m001_get_fmt,
719*4882a593Smuzhiyun 	.set_fmt	= mt9m001_set_fmt,
720*4882a593Smuzhiyun 	.get_mbus_config = mt9m001_get_mbus_config,
721*4882a593Smuzhiyun };
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun static const struct v4l2_subdev_ops mt9m001_subdev_ops = {
724*4882a593Smuzhiyun 	.core	= &mt9m001_subdev_core_ops,
725*4882a593Smuzhiyun 	.video	= &mt9m001_subdev_video_ops,
726*4882a593Smuzhiyun 	.sensor	= &mt9m001_subdev_sensor_ops,
727*4882a593Smuzhiyun 	.pad	= &mt9m001_subdev_pad_ops,
728*4882a593Smuzhiyun };
729*4882a593Smuzhiyun 
mt9m001_probe(struct i2c_client * client)730*4882a593Smuzhiyun static int mt9m001_probe(struct i2c_client *client)
731*4882a593Smuzhiyun {
732*4882a593Smuzhiyun 	struct mt9m001 *mt9m001;
733*4882a593Smuzhiyun 	struct i2c_adapter *adapter = client->adapter;
734*4882a593Smuzhiyun 	int ret;
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun 	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
737*4882a593Smuzhiyun 		dev_warn(&adapter->dev,
738*4882a593Smuzhiyun 			 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
739*4882a593Smuzhiyun 		return -EIO;
740*4882a593Smuzhiyun 	}
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun 	mt9m001 = devm_kzalloc(&client->dev, sizeof(*mt9m001), GFP_KERNEL);
743*4882a593Smuzhiyun 	if (!mt9m001)
744*4882a593Smuzhiyun 		return -ENOMEM;
745*4882a593Smuzhiyun 
746*4882a593Smuzhiyun 	mt9m001->clk = devm_clk_get(&client->dev, NULL);
747*4882a593Smuzhiyun 	if (IS_ERR(mt9m001->clk))
748*4882a593Smuzhiyun 		return PTR_ERR(mt9m001->clk);
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun 	mt9m001->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
751*4882a593Smuzhiyun 							GPIOD_OUT_LOW);
752*4882a593Smuzhiyun 	if (IS_ERR(mt9m001->standby_gpio))
753*4882a593Smuzhiyun 		return PTR_ERR(mt9m001->standby_gpio);
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 	mt9m001->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
756*4882a593Smuzhiyun 						      GPIOD_OUT_LOW);
757*4882a593Smuzhiyun 	if (IS_ERR(mt9m001->reset_gpio))
758*4882a593Smuzhiyun 		return PTR_ERR(mt9m001->reset_gpio);
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(&mt9m001->subdev, client, &mt9m001_subdev_ops);
761*4882a593Smuzhiyun 	mt9m001->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
762*4882a593Smuzhiyun 				 V4L2_SUBDEV_FL_HAS_EVENTS;
763*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(&mt9m001->hdl, 4);
764*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
765*4882a593Smuzhiyun 			V4L2_CID_VFLIP, 0, 1, 1, 0);
766*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
767*4882a593Smuzhiyun 			V4L2_CID_GAIN, 0, 127, 1, 64);
768*4882a593Smuzhiyun 	mt9m001->exposure = v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
769*4882a593Smuzhiyun 			V4L2_CID_EXPOSURE, 1, 255, 1, 255);
770*4882a593Smuzhiyun 	/*
771*4882a593Smuzhiyun 	 * Simulated autoexposure. If enabled, we calculate shutter width
772*4882a593Smuzhiyun 	 * ourselves in the driver based on vertical blanking and frame width
773*4882a593Smuzhiyun 	 */
774*4882a593Smuzhiyun 	mt9m001->autoexposure = v4l2_ctrl_new_std_menu(&mt9m001->hdl,
775*4882a593Smuzhiyun 			&mt9m001_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
776*4882a593Smuzhiyun 			V4L2_EXPOSURE_AUTO);
777*4882a593Smuzhiyun 	mt9m001->subdev.ctrl_handler = &mt9m001->hdl;
778*4882a593Smuzhiyun 	if (mt9m001->hdl.error)
779*4882a593Smuzhiyun 		return mt9m001->hdl.error;
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun 	v4l2_ctrl_auto_cluster(2, &mt9m001->autoexposure,
782*4882a593Smuzhiyun 					V4L2_EXPOSURE_MANUAL, true);
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun 	mutex_init(&mt9m001->mutex);
785*4882a593Smuzhiyun 	mt9m001->hdl.lock = &mt9m001->mutex;
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun 	/* Second stage probe - when a capture adapter is there */
788*4882a593Smuzhiyun 	mt9m001->y_skip_top	= 0;
789*4882a593Smuzhiyun 	mt9m001->rect.left	= MT9M001_COLUMN_SKIP;
790*4882a593Smuzhiyun 	mt9m001->rect.top	= MT9M001_ROW_SKIP;
791*4882a593Smuzhiyun 	mt9m001->rect.width	= MT9M001_MAX_WIDTH;
792*4882a593Smuzhiyun 	mt9m001->rect.height	= MT9M001_MAX_HEIGHT;
793*4882a593Smuzhiyun 
794*4882a593Smuzhiyun 	ret = mt9m001_power_on(&client->dev);
795*4882a593Smuzhiyun 	if (ret)
796*4882a593Smuzhiyun 		goto error_hdl_free;
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 	pm_runtime_set_active(&client->dev);
799*4882a593Smuzhiyun 	pm_runtime_enable(&client->dev);
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 	ret = mt9m001_video_probe(client);
802*4882a593Smuzhiyun 	if (ret)
803*4882a593Smuzhiyun 		goto error_power_off;
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 	mt9m001->pad.flags = MEDIA_PAD_FL_SOURCE;
806*4882a593Smuzhiyun 	mt9m001->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
807*4882a593Smuzhiyun 	ret = media_entity_pads_init(&mt9m001->subdev.entity, 1, &mt9m001->pad);
808*4882a593Smuzhiyun 	if (ret)
809*4882a593Smuzhiyun 		goto error_power_off;
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun 	ret = v4l2_async_register_subdev(&mt9m001->subdev);
812*4882a593Smuzhiyun 	if (ret)
813*4882a593Smuzhiyun 		goto error_entity_cleanup;
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun 	pm_runtime_idle(&client->dev);
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun 	return 0;
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun error_entity_cleanup:
820*4882a593Smuzhiyun 	media_entity_cleanup(&mt9m001->subdev.entity);
821*4882a593Smuzhiyun error_power_off:
822*4882a593Smuzhiyun 	pm_runtime_disable(&client->dev);
823*4882a593Smuzhiyun 	pm_runtime_set_suspended(&client->dev);
824*4882a593Smuzhiyun 	mt9m001_power_off(&client->dev);
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun error_hdl_free:
827*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&mt9m001->hdl);
828*4882a593Smuzhiyun 	mutex_destroy(&mt9m001->mutex);
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun 	return ret;
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun 
mt9m001_remove(struct i2c_client * client)833*4882a593Smuzhiyun static int mt9m001_remove(struct i2c_client *client)
834*4882a593Smuzhiyun {
835*4882a593Smuzhiyun 	struct mt9m001 *mt9m001 = to_mt9m001(client);
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun 	pm_runtime_get_sync(&client->dev);
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(&mt9m001->subdev);
840*4882a593Smuzhiyun 	media_entity_cleanup(&mt9m001->subdev.entity);
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun 	pm_runtime_disable(&client->dev);
843*4882a593Smuzhiyun 	pm_runtime_set_suspended(&client->dev);
844*4882a593Smuzhiyun 	pm_runtime_put_noidle(&client->dev);
845*4882a593Smuzhiyun 	mt9m001_power_off(&client->dev);
846*4882a593Smuzhiyun 
847*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&mt9m001->hdl);
848*4882a593Smuzhiyun 	mutex_destroy(&mt9m001->mutex);
849*4882a593Smuzhiyun 
850*4882a593Smuzhiyun 	return 0;
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun static const struct i2c_device_id mt9m001_id[] = {
854*4882a593Smuzhiyun 	{ "mt9m001", 0 },
855*4882a593Smuzhiyun 	{ }
856*4882a593Smuzhiyun };
857*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mt9m001_id);
858*4882a593Smuzhiyun 
859*4882a593Smuzhiyun static const struct dev_pm_ops mt9m001_pm_ops = {
860*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(mt9m001_power_off, mt9m001_power_on, NULL)
861*4882a593Smuzhiyun };
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun static const struct of_device_id mt9m001_of_match[] = {
864*4882a593Smuzhiyun 	{ .compatible = "onnn,mt9m001", },
865*4882a593Smuzhiyun 	{ /* sentinel */ },
866*4882a593Smuzhiyun };
867*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mt9m001_of_match);
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun static struct i2c_driver mt9m001_i2c_driver = {
870*4882a593Smuzhiyun 	.driver = {
871*4882a593Smuzhiyun 		.name = "mt9m001",
872*4882a593Smuzhiyun 		.pm = &mt9m001_pm_ops,
873*4882a593Smuzhiyun 		.of_match_table = mt9m001_of_match,
874*4882a593Smuzhiyun 	},
875*4882a593Smuzhiyun 	.probe_new	= mt9m001_probe,
876*4882a593Smuzhiyun 	.remove		= mt9m001_remove,
877*4882a593Smuzhiyun 	.id_table	= mt9m001_id,
878*4882a593Smuzhiyun };
879*4882a593Smuzhiyun 
880*4882a593Smuzhiyun module_i2c_driver(mt9m001_i2c_driver);
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun MODULE_DESCRIPTION("Micron MT9M001 Camera driver");
883*4882a593Smuzhiyun MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
884*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
885