1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * max96714 GMSL2/GMSL1 to CSI-2 Deserializer driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * V0.0X01.0X00 first version.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/clk.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/pm_runtime.h>
18*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
19*4882a593Smuzhiyun #include <linux/sysfs.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun #include <linux/version.h>
22*4882a593Smuzhiyun #include <linux/compat.h>
23*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
24*4882a593Smuzhiyun #include <media/media-entity.h>
25*4882a593Smuzhiyun #include <media/v4l2-async.h>
26*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
27*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
28*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
29*4882a593Smuzhiyun #include "max96714.h"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
34*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35*4882a593Smuzhiyun #endif
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define MAX96714_LINK_FREQ_150MHZ 150000000UL
38*4882a593Smuzhiyun /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
39*4882a593Smuzhiyun #define MAX96714_PIXEL_RATE (MAX96714_LINK_FREQ_150MHZ * 2LL * 4LL / 8LL)
40*4882a593Smuzhiyun #define MAX96714_XVCLK_FREQ 24000000
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define CHIP_ID 0xC9
43*4882a593Smuzhiyun #define MAX96714_REG_CHIP_ID 0x0D
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define MAX96714_REG_CTRL_MODE 0x0313
46*4882a593Smuzhiyun #define MAX96714_MODE_SW_STANDBY 0x0
47*4882a593Smuzhiyun #define MAX96714_MODE_STREAMING BIT(1)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define REG_NULL 0xFFFF
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define MAX96714_LANES 4
52*4882a593Smuzhiyun #define MAX96714_BITS_PER_SAMPLE 8
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
55*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define MAX96714_REG_VALUE_08BIT 1
58*4882a593Smuzhiyun #define MAX96714_REG_VALUE_16BIT 2
59*4882a593Smuzhiyun #define MAX96714_REG_VALUE_24BIT 3
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define MAX96714_NAME "max96714"
62*4882a593Smuzhiyun #define MAX96714_MEDIA_BUS_FMT MEDIA_BUS_FMT_UYVY8_2X8
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static const char * const max96714_supply_names[] = {
65*4882a593Smuzhiyun "avdd", /* Analog power */
66*4882a593Smuzhiyun "dovdd", /* Digital I/O power */
67*4882a593Smuzhiyun "dvdd", /* Digital core power */
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define MAX96714_NUM_SUPPLIES ARRAY_SIZE(max96714_supply_names)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct regval {
73*4882a593Smuzhiyun u16 i2c_addr;
74*4882a593Smuzhiyun u16 addr;
75*4882a593Smuzhiyun u8 val;
76*4882a593Smuzhiyun u16 delay;
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun struct max96714_mode {
80*4882a593Smuzhiyun u32 width;
81*4882a593Smuzhiyun u32 height;
82*4882a593Smuzhiyun struct v4l2_fract max_fps;
83*4882a593Smuzhiyun u32 hts_def;
84*4882a593Smuzhiyun u32 vts_def;
85*4882a593Smuzhiyun u32 exp_def;
86*4882a593Smuzhiyun u32 link_freq_idx;
87*4882a593Smuzhiyun u32 bpp;
88*4882a593Smuzhiyun const struct regval *reg_list;
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct max96714 {
92*4882a593Smuzhiyun struct i2c_client *client;
93*4882a593Smuzhiyun struct clk *xvclk;
94*4882a593Smuzhiyun struct gpio_desc *power_gpio;
95*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
96*4882a593Smuzhiyun struct gpio_desc *pwdn_gpio;
97*4882a593Smuzhiyun struct regulator_bulk_data supplies[MAX96714_NUM_SUPPLIES];
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun struct pinctrl *pinctrl;
100*4882a593Smuzhiyun struct pinctrl_state *pins_default;
101*4882a593Smuzhiyun struct pinctrl_state *pins_sleep;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun struct v4l2_subdev subdev;
104*4882a593Smuzhiyun struct media_pad pad;
105*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
106*4882a593Smuzhiyun struct v4l2_ctrl *exposure;
107*4882a593Smuzhiyun struct v4l2_ctrl *anal_gain;
108*4882a593Smuzhiyun struct v4l2_ctrl *digi_gain;
109*4882a593Smuzhiyun struct v4l2_ctrl *hblank;
110*4882a593Smuzhiyun struct v4l2_ctrl *vblank;
111*4882a593Smuzhiyun struct v4l2_ctrl *pixel_rate;
112*4882a593Smuzhiyun struct v4l2_ctrl *link_freq;
113*4882a593Smuzhiyun struct v4l2_ctrl *test_pattern;
114*4882a593Smuzhiyun struct mutex mutex;
115*4882a593Smuzhiyun bool streaming;
116*4882a593Smuzhiyun bool power_on;
117*4882a593Smuzhiyun bool hot_plug;
118*4882a593Smuzhiyun u8 is_reset;
119*4882a593Smuzhiyun const struct max96714_mode *cur_mode;
120*4882a593Smuzhiyun u32 module_index;
121*4882a593Smuzhiyun const char *module_facing;
122*4882a593Smuzhiyun const char *module_name;
123*4882a593Smuzhiyun const char *len_name;
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #define to_max96714(sd) container_of(sd, struct max96714, subdev)
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static const struct regval max96714_mipi_1080p_30fps[] = {
129*4882a593Smuzhiyun {0x4C, 0x0313, 0x00, 0x00},
130*4882a593Smuzhiyun {0x4C, 0x0001, 0x01, 0x00},
131*4882a593Smuzhiyun {0x4C, 0x0010, 0x21, 0x00},
132*4882a593Smuzhiyun {0x4C, 0x0320, 0x23, 0x00},
133*4882a593Smuzhiyun {0x4C, 0x0325, 0x80, 0x00},
134*4882a593Smuzhiyun {0x4C, 0x0313, 0x00, 0x00},
135*4882a593Smuzhiyun {0x4C, REG_NULL, 0x00, 0x00},
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun static const struct max96714_mode supported_modes[] = {
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun .width = 1920,
141*4882a593Smuzhiyun .height = 1080,
142*4882a593Smuzhiyun .max_fps = {
143*4882a593Smuzhiyun .numerator = 10000,
144*4882a593Smuzhiyun .denominator = 300000,
145*4882a593Smuzhiyun },
146*4882a593Smuzhiyun .reg_list = max96714_mipi_1080p_30fps,
147*4882a593Smuzhiyun .link_freq_idx = 0,
148*4882a593Smuzhiyun },
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const s64 link_freq_items[] = {
152*4882a593Smuzhiyun MAX96714_LINK_FREQ_150MHZ,
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /* Write registers up to 4 at a time */
max96714_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)156*4882a593Smuzhiyun static int max96714_write_reg(struct i2c_client *client, u16 reg,
157*4882a593Smuzhiyun u32 len, u32 val)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun u32 buf_i, val_i;
160*4882a593Smuzhiyun u8 buf[6];
161*4882a593Smuzhiyun u8 *val_p;
162*4882a593Smuzhiyun __be32 val_be;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun if (len > 4)
167*4882a593Smuzhiyun return -EINVAL;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun buf[0] = reg >> 8;
170*4882a593Smuzhiyun buf[1] = reg & 0xff;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun val_be = cpu_to_be32(val);
173*4882a593Smuzhiyun val_p = (u8 *)&val_be;
174*4882a593Smuzhiyun buf_i = 2;
175*4882a593Smuzhiyun val_i = 4 - len;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun while (val_i < 4)
178*4882a593Smuzhiyun buf[buf_i++] = val_p[val_i++];
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun if (i2c_master_send(client, buf, len + 2) != len + 2)
181*4882a593Smuzhiyun return -EIO;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun return 0;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
max96714_write_array(struct i2c_client * client,const struct regval * regs)186*4882a593Smuzhiyun static int max96714_write_array(struct i2c_client *client,
187*4882a593Smuzhiyun const struct regval *regs)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun u32 i;
190*4882a593Smuzhiyun int ret = 0;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
193*4882a593Smuzhiyun client->addr = regs[i].i2c_addr;
194*4882a593Smuzhiyun ret = max96714_write_reg(client, regs[i].addr,
195*4882a593Smuzhiyun MAX96714_REG_VALUE_08BIT,
196*4882a593Smuzhiyun regs[i].val);
197*4882a593Smuzhiyun msleep(regs[i].delay);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return ret;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun /* Read registers up to 4 at a time */
max96714_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)204*4882a593Smuzhiyun static int max96714_read_reg(struct i2c_client *client, u16 reg,
205*4882a593Smuzhiyun unsigned int len, u32 *val)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun struct i2c_msg msgs[2];
208*4882a593Smuzhiyun u8 *data_be_p;
209*4882a593Smuzhiyun __be32 data_be = 0;
210*4882a593Smuzhiyun __be16 reg_addr_be = cpu_to_be16(reg);
211*4882a593Smuzhiyun int ret;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun if (len > 4 || !len)
214*4882a593Smuzhiyun return -EINVAL;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun data_be_p = (u8 *)&data_be;
217*4882a593Smuzhiyun /* Write register address */
218*4882a593Smuzhiyun msgs[0].addr = client->addr;
219*4882a593Smuzhiyun msgs[0].flags = 0;
220*4882a593Smuzhiyun msgs[0].len = 2;
221*4882a593Smuzhiyun msgs[0].buf = (u8 *)®_addr_be;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* Read data from register */
224*4882a593Smuzhiyun msgs[1].addr = client->addr;
225*4882a593Smuzhiyun msgs[1].flags = I2C_M_RD;
226*4882a593Smuzhiyun msgs[1].len = len;
227*4882a593Smuzhiyun msgs[1].buf = &data_be_p[4 - len];
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
230*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs))
231*4882a593Smuzhiyun return -EIO;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun *val = be32_to_cpu(data_be);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun return 0;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
max96714_get_reso_dist(const struct max96714_mode * mode,struct v4l2_mbus_framefmt * framefmt)238*4882a593Smuzhiyun static int max96714_get_reso_dist(const struct max96714_mode *mode,
239*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun return abs(mode->width - framefmt->width) +
242*4882a593Smuzhiyun abs(mode->height - framefmt->height);
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun static const struct max96714_mode *
max96714_find_best_fit(struct v4l2_subdev_format * fmt)246*4882a593Smuzhiyun max96714_find_best_fit(struct v4l2_subdev_format *fmt)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt = &fmt->format;
249*4882a593Smuzhiyun int dist;
250*4882a593Smuzhiyun int cur_best_fit = 0;
251*4882a593Smuzhiyun int cur_best_fit_dist = -1;
252*4882a593Smuzhiyun unsigned int i;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
255*4882a593Smuzhiyun dist = max96714_get_reso_dist(&supported_modes[i], framefmt);
256*4882a593Smuzhiyun if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
257*4882a593Smuzhiyun cur_best_fit_dist = dist;
258*4882a593Smuzhiyun cur_best_fit = i;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun return &supported_modes[cur_best_fit];
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
max96714_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)265*4882a593Smuzhiyun static int max96714_set_fmt(struct v4l2_subdev *sd,
266*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
267*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
270*4882a593Smuzhiyun const struct max96714_mode *mode;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun mutex_lock(&max96714->mutex);
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun mode = max96714_find_best_fit(fmt);
275*4882a593Smuzhiyun fmt->format.code = MAX96714_MEDIA_BUS_FMT;
276*4882a593Smuzhiyun fmt->format.width = mode->width;
277*4882a593Smuzhiyun fmt->format.height = mode->height;
278*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
279*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
280*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
281*4882a593Smuzhiyun *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
282*4882a593Smuzhiyun #else
283*4882a593Smuzhiyun mutex_unlock(&max96714->mutex);
284*4882a593Smuzhiyun return -ENOTTY;
285*4882a593Smuzhiyun #endif
286*4882a593Smuzhiyun } else {
287*4882a593Smuzhiyun if (max96714->streaming) {
288*4882a593Smuzhiyun mutex_unlock(&max96714->mutex);
289*4882a593Smuzhiyun return -EBUSY;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun mutex_unlock(&max96714->mutex);
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun return 0;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
max96714_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)298*4882a593Smuzhiyun static int max96714_get_fmt(struct v4l2_subdev *sd,
299*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
300*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
303*4882a593Smuzhiyun const struct max96714_mode *mode = max96714->cur_mode;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun mutex_lock(&max96714->mutex);
306*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
307*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
308*4882a593Smuzhiyun fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
309*4882a593Smuzhiyun #else
310*4882a593Smuzhiyun mutex_unlock(&max96714->mutex);
311*4882a593Smuzhiyun return -ENOTTY;
312*4882a593Smuzhiyun #endif
313*4882a593Smuzhiyun } else {
314*4882a593Smuzhiyun fmt->format.width = mode->width;
315*4882a593Smuzhiyun fmt->format.height = mode->height;
316*4882a593Smuzhiyun fmt->format.code = MAX96714_MEDIA_BUS_FMT;
317*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun mutex_unlock(&max96714->mutex);
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun return 0;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
max96714_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)324*4882a593Smuzhiyun static int max96714_enum_mbus_code(struct v4l2_subdev *sd,
325*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
326*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun if (code->index != 0)
329*4882a593Smuzhiyun return -EINVAL;
330*4882a593Smuzhiyun code->code = MAX96714_MEDIA_BUS_FMT;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun return 0;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
max96714_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)335*4882a593Smuzhiyun static int max96714_enum_frame_sizes(struct v4l2_subdev *sd,
336*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
337*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
338*4882a593Smuzhiyun {
339*4882a593Smuzhiyun if (fse->index >= ARRAY_SIZE(supported_modes))
340*4882a593Smuzhiyun return -EINVAL;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun if (fse->code != MAX96714_MEDIA_BUS_FMT)
343*4882a593Smuzhiyun return -EINVAL;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun fse->min_width = supported_modes[fse->index].width;
346*4882a593Smuzhiyun fse->max_width = supported_modes[fse->index].width;
347*4882a593Smuzhiyun fse->max_height = supported_modes[fse->index].height;
348*4882a593Smuzhiyun fse->min_height = supported_modes[fse->index].height;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun return 0;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
max96714_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)353*4882a593Smuzhiyun static int max96714_g_frame_interval(struct v4l2_subdev *sd,
354*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *fi)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
357*4882a593Smuzhiyun const struct max96714_mode *mode = max96714->cur_mode;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun mutex_lock(&max96714->mutex);
360*4882a593Smuzhiyun fi->interval = mode->max_fps;
361*4882a593Smuzhiyun mutex_unlock(&max96714->mutex);
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun return 0;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
max96714_get_module_inf(struct max96714 * max96714,struct rkmodule_inf * inf)366*4882a593Smuzhiyun static void max96714_get_module_inf(struct max96714 *max96714,
367*4882a593Smuzhiyun struct rkmodule_inf *inf)
368*4882a593Smuzhiyun {
369*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
370*4882a593Smuzhiyun strscpy(inf->base.sensor, MAX96714_NAME, sizeof(inf->base.sensor));
371*4882a593Smuzhiyun strscpy(inf->base.module, max96714->module_name,
372*4882a593Smuzhiyun sizeof(inf->base.module));
373*4882a593Smuzhiyun strscpy(inf->base.lens, max96714->len_name, sizeof(inf->base.lens));
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
max96714_get_vicap_rst_inf(struct max96714 * max96714,struct rkmodule_vicap_reset_info * rst_info)376*4882a593Smuzhiyun static void max96714_get_vicap_rst_inf(struct max96714 *max96714,
377*4882a593Smuzhiyun struct rkmodule_vicap_reset_info *rst_info)
378*4882a593Smuzhiyun {
379*4882a593Smuzhiyun struct i2c_client *client = max96714->client;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun rst_info->is_reset = max96714->hot_plug;
382*4882a593Smuzhiyun max96714->hot_plug = false;
383*4882a593Smuzhiyun rst_info->src = RKCIF_RESET_SRC_ERR_HOTPLUG;
384*4882a593Smuzhiyun dev_info(&client->dev, "%s: rst_info->is_reset:%d.\n", __func__, rst_info->is_reset);
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
max96714_set_vicap_rst_inf(struct max96714 * max96714,struct rkmodule_vicap_reset_info rst_info)387*4882a593Smuzhiyun static void max96714_set_vicap_rst_inf(struct max96714 *max96714,
388*4882a593Smuzhiyun struct rkmodule_vicap_reset_info rst_info)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun max96714->is_reset = rst_info.is_reset;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
max96714_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)393*4882a593Smuzhiyun static long max96714_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
396*4882a593Smuzhiyun long ret = 0;
397*4882a593Smuzhiyun u32 stream = 0;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun switch (cmd) {
400*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
401*4882a593Smuzhiyun max96714_get_module_inf(max96714, (struct rkmodule_inf *)arg);
402*4882a593Smuzhiyun break;
403*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun stream = *((u32 *)arg);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun if (stream)
408*4882a593Smuzhiyun ret = max96714_write_reg(max96714->client,
409*4882a593Smuzhiyun MAX96714_REG_CTRL_MODE,
410*4882a593Smuzhiyun MAX96714_REG_VALUE_08BIT,
411*4882a593Smuzhiyun MAX96714_MODE_STREAMING);
412*4882a593Smuzhiyun else
413*4882a593Smuzhiyun ret = max96714_write_reg(max96714->client,
414*4882a593Smuzhiyun MAX96714_REG_CTRL_MODE,
415*4882a593Smuzhiyun MAX96714_REG_VALUE_08BIT,
416*4882a593Smuzhiyun MAX96714_MODE_SW_STANDBY);
417*4882a593Smuzhiyun break;
418*4882a593Smuzhiyun case RKMODULE_GET_VICAP_RST_INFO:
419*4882a593Smuzhiyun max96714_get_vicap_rst_inf(max96714,
420*4882a593Smuzhiyun (struct rkmodule_vicap_reset_info *)arg);
421*4882a593Smuzhiyun break;
422*4882a593Smuzhiyun case RKMODULE_SET_VICAP_RST_INFO:
423*4882a593Smuzhiyun max96714_set_vicap_rst_inf(max96714,
424*4882a593Smuzhiyun *(struct rkmodule_vicap_reset_info *)arg);
425*4882a593Smuzhiyun break;
426*4882a593Smuzhiyun case RKMODULE_GET_START_STREAM_SEQ:
427*4882a593Smuzhiyun // +*(int *)arg = RKMODULE_START_STREAM_FRONT;
428*4882a593Smuzhiyun // *(int *)arg = RKMODULE_START_STREAM_BEHIND;
429*4882a593Smuzhiyun break;
430*4882a593Smuzhiyun default:
431*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
432*4882a593Smuzhiyun break;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun return ret;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
max96714_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)439*4882a593Smuzhiyun static long max96714_compat_ioctl32(struct v4l2_subdev *sd,
440*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun void __user *up = compat_ptr(arg);
443*4882a593Smuzhiyun struct rkmodule_inf *inf;
444*4882a593Smuzhiyun struct rkmodule_awb_cfg *cfg;
445*4882a593Smuzhiyun struct rkmodule_vicap_reset_info *vicap_rst_inf;
446*4882a593Smuzhiyun long ret = 0;
447*4882a593Smuzhiyun int *seq;
448*4882a593Smuzhiyun u32 stream = 0;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun switch (cmd) {
451*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
452*4882a593Smuzhiyun inf = kzalloc(sizeof(*inf), GFP_KERNEL);
453*4882a593Smuzhiyun if (!inf) {
454*4882a593Smuzhiyun ret = -ENOMEM;
455*4882a593Smuzhiyun return ret;
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun ret = max96714_ioctl(sd, cmd, inf);
459*4882a593Smuzhiyun if (!ret) {
460*4882a593Smuzhiyun ret = copy_to_user(up, inf, sizeof(*inf));
461*4882a593Smuzhiyun if (ret)
462*4882a593Smuzhiyun ret = -EFAULT;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun kfree(inf);
465*4882a593Smuzhiyun break;
466*4882a593Smuzhiyun case RKMODULE_AWB_CFG:
467*4882a593Smuzhiyun cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
468*4882a593Smuzhiyun if (!cfg) {
469*4882a593Smuzhiyun ret = -ENOMEM;
470*4882a593Smuzhiyun return ret;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun ret = copy_from_user(cfg, up, sizeof(*cfg));
474*4882a593Smuzhiyun if (!ret)
475*4882a593Smuzhiyun ret = max96714_ioctl(sd, cmd, cfg);
476*4882a593Smuzhiyun else
477*4882a593Smuzhiyun ret = -EFAULT;
478*4882a593Smuzhiyun kfree(cfg);
479*4882a593Smuzhiyun break;
480*4882a593Smuzhiyun case RKMODULE_GET_VICAP_RST_INFO:
481*4882a593Smuzhiyun vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
482*4882a593Smuzhiyun if (!vicap_rst_inf) {
483*4882a593Smuzhiyun ret = -ENOMEM;
484*4882a593Smuzhiyun return ret;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun ret = max96714_ioctl(sd, cmd, vicap_rst_inf);
488*4882a593Smuzhiyun if (!ret) {
489*4882a593Smuzhiyun ret = copy_to_user(up, vicap_rst_inf, sizeof(*vicap_rst_inf));
490*4882a593Smuzhiyun if (ret)
491*4882a593Smuzhiyun ret = -EFAULT;
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun kfree(vicap_rst_inf);
494*4882a593Smuzhiyun break;
495*4882a593Smuzhiyun case RKMODULE_SET_VICAP_RST_INFO:
496*4882a593Smuzhiyun vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
497*4882a593Smuzhiyun if (!vicap_rst_inf) {
498*4882a593Smuzhiyun ret = -ENOMEM;
499*4882a593Smuzhiyun return ret;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun ret = copy_from_user(vicap_rst_inf, up, sizeof(*vicap_rst_inf));
503*4882a593Smuzhiyun if (!ret)
504*4882a593Smuzhiyun ret = max96714_ioctl(sd, cmd, vicap_rst_inf);
505*4882a593Smuzhiyun else
506*4882a593Smuzhiyun ret = -EFAULT;
507*4882a593Smuzhiyun kfree(vicap_rst_inf);
508*4882a593Smuzhiyun break;
509*4882a593Smuzhiyun case RKMODULE_GET_START_STREAM_SEQ:
510*4882a593Smuzhiyun seq = kzalloc(sizeof(*seq), GFP_KERNEL);
511*4882a593Smuzhiyun if (!seq) {
512*4882a593Smuzhiyun ret = -ENOMEM;
513*4882a593Smuzhiyun return ret;
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun ret = max96714_ioctl(sd, cmd, seq);
517*4882a593Smuzhiyun if (!ret) {
518*4882a593Smuzhiyun ret = copy_to_user(up, seq, sizeof(*seq));
519*4882a593Smuzhiyun if (ret)
520*4882a593Smuzhiyun ret = -EFAULT;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun kfree(seq);
523*4882a593Smuzhiyun break;
524*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
525*4882a593Smuzhiyun ret = copy_from_user(&stream, up, sizeof(u32));
526*4882a593Smuzhiyun if (!ret)
527*4882a593Smuzhiyun ret = max96714_ioctl(sd, cmd, &stream);
528*4882a593Smuzhiyun else
529*4882a593Smuzhiyun ret = -EFAULT;
530*4882a593Smuzhiyun break;
531*4882a593Smuzhiyun default:
532*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
533*4882a593Smuzhiyun break;
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun return ret;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun #endif
539*4882a593Smuzhiyun
__max96714_start_stream(struct max96714 * max96714)540*4882a593Smuzhiyun static int __max96714_start_stream(struct max96714 *max96714)
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun int ret;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun ret = max96714_write_array(max96714->client, max96714->cur_mode->reg_list);
545*4882a593Smuzhiyun if (ret)
546*4882a593Smuzhiyun return ret;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun /* In case these controls are set before streaming */
549*4882a593Smuzhiyun mutex_unlock(&max96714->mutex);
550*4882a593Smuzhiyun ret = v4l2_ctrl_handler_setup(&max96714->ctrl_handler);
551*4882a593Smuzhiyun mutex_lock(&max96714->mutex);
552*4882a593Smuzhiyun if (ret)
553*4882a593Smuzhiyun return ret;
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun return max96714_write_reg(max96714->client,
556*4882a593Smuzhiyun MAX96714_REG_CTRL_MODE,
557*4882a593Smuzhiyun MAX96714_REG_VALUE_08BIT,
558*4882a593Smuzhiyun MAX96714_MODE_STREAMING);
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun
__max96714_stop_stream(struct max96714 * max96714)561*4882a593Smuzhiyun static int __max96714_stop_stream(struct max96714 *max96714)
562*4882a593Smuzhiyun {
563*4882a593Smuzhiyun return max96714_write_reg(max96714->client,
564*4882a593Smuzhiyun MAX96714_REG_CTRL_MODE,
565*4882a593Smuzhiyun MAX96714_REG_VALUE_08BIT,
566*4882a593Smuzhiyun MAX96714_MODE_SW_STANDBY);
567*4882a593Smuzhiyun }
568*4882a593Smuzhiyun
max96714_s_stream(struct v4l2_subdev * sd,int on)569*4882a593Smuzhiyun static int max96714_s_stream(struct v4l2_subdev *sd, int on)
570*4882a593Smuzhiyun {
571*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
572*4882a593Smuzhiyun struct i2c_client *client = max96714->client;
573*4882a593Smuzhiyun int ret = 0;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
576*4882a593Smuzhiyun max96714->cur_mode->width,
577*4882a593Smuzhiyun max96714->cur_mode->height,
578*4882a593Smuzhiyun DIV_ROUND_CLOSEST(max96714->cur_mode->max_fps.denominator,
579*4882a593Smuzhiyun max96714->cur_mode->max_fps.numerator));
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun mutex_lock(&max96714->mutex);
582*4882a593Smuzhiyun on = !!on;
583*4882a593Smuzhiyun if (on == max96714->streaming)
584*4882a593Smuzhiyun goto unlock_and_return;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun if (on) {
587*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
588*4882a593Smuzhiyun if (ret < 0) {
589*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
590*4882a593Smuzhiyun goto unlock_and_return;
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun ret = __max96714_start_stream(max96714);
594*4882a593Smuzhiyun if (ret) {
595*4882a593Smuzhiyun v4l2_err(sd, "start stream failed while write regs\n");
596*4882a593Smuzhiyun pm_runtime_put(&client->dev);
597*4882a593Smuzhiyun goto unlock_and_return;
598*4882a593Smuzhiyun }
599*4882a593Smuzhiyun } else {
600*4882a593Smuzhiyun __max96714_stop_stream(max96714);
601*4882a593Smuzhiyun pm_runtime_put(&client->dev);
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun max96714->streaming = on;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun unlock_and_return:
607*4882a593Smuzhiyun mutex_unlock(&max96714->mutex);
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun return ret;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun
max96714_s_power(struct v4l2_subdev * sd,int on)612*4882a593Smuzhiyun static int max96714_s_power(struct v4l2_subdev *sd, int on)
613*4882a593Smuzhiyun {
614*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
615*4882a593Smuzhiyun struct i2c_client *client = max96714->client;
616*4882a593Smuzhiyun int ret = 0;
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun mutex_lock(&max96714->mutex);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun /* If the power state is not modified - no work to do. */
621*4882a593Smuzhiyun if (max96714->power_on == !!on)
622*4882a593Smuzhiyun goto unlock_and_return;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun if (on) {
625*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
626*4882a593Smuzhiyun if (ret < 0) {
627*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
628*4882a593Smuzhiyun goto unlock_and_return;
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun max96714->power_on = true;
632*4882a593Smuzhiyun } else {
633*4882a593Smuzhiyun pm_runtime_put(&client->dev);
634*4882a593Smuzhiyun max96714->power_on = false;
635*4882a593Smuzhiyun }
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun unlock_and_return:
638*4882a593Smuzhiyun mutex_unlock(&max96714->mutex);
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun return ret;
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun /* Calculate the delay in us by clock rate and clock cycles */
max96714_cal_delay(u32 cycles)644*4882a593Smuzhiyun static inline u32 max96714_cal_delay(u32 cycles)
645*4882a593Smuzhiyun {
646*4882a593Smuzhiyun return DIV_ROUND_UP(cycles, MAX96714_XVCLK_FREQ / 1000 / 1000);
647*4882a593Smuzhiyun }
648*4882a593Smuzhiyun
__max96714_power_on(struct max96714 * max96714)649*4882a593Smuzhiyun static int __max96714_power_on(struct max96714 *max96714)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun int ret;
652*4882a593Smuzhiyun u32 delay_us;
653*4882a593Smuzhiyun struct device *dev = &max96714->client->dev;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun if (!IS_ERR(max96714->power_gpio))
656*4882a593Smuzhiyun gpiod_set_value_cansleep(max96714->power_gpio, 1);
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun usleep_range(1000, 2000);
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(max96714->pins_default)) {
661*4882a593Smuzhiyun ret = pinctrl_select_state(max96714->pinctrl,
662*4882a593Smuzhiyun max96714->pins_default);
663*4882a593Smuzhiyun if (ret < 0)
664*4882a593Smuzhiyun dev_err(dev, "could not set pins\n");
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun if (!IS_ERR(max96714->reset_gpio))
668*4882a593Smuzhiyun gpiod_set_value_cansleep(max96714->reset_gpio, 0);
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun ret = regulator_bulk_enable(MAX96714_NUM_SUPPLIES, max96714->supplies);
671*4882a593Smuzhiyun if (ret < 0) {
672*4882a593Smuzhiyun dev_err(dev, "Failed to enable regulators\n");
673*4882a593Smuzhiyun goto disable_clk;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun if (!IS_ERR(max96714->reset_gpio))
677*4882a593Smuzhiyun gpiod_set_value_cansleep(max96714->reset_gpio, 1);
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun usleep_range(500, 1000);
680*4882a593Smuzhiyun if (!IS_ERR(max96714->pwdn_gpio))
681*4882a593Smuzhiyun gpiod_set_value_cansleep(max96714->pwdn_gpio, 1);
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun /* 8192 cycles prior to first SCCB transaction */
684*4882a593Smuzhiyun delay_us = max96714_cal_delay(8192);
685*4882a593Smuzhiyun usleep_range(delay_us, delay_us * 2);
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun return 0;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun disable_clk:
690*4882a593Smuzhiyun clk_disable_unprepare(max96714->xvclk);
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun return ret;
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun
__max96714_power_off(struct max96714 * max96714)695*4882a593Smuzhiyun static void __max96714_power_off(struct max96714 *max96714)
696*4882a593Smuzhiyun {
697*4882a593Smuzhiyun int ret;
698*4882a593Smuzhiyun struct device *dev = &max96714->client->dev;
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun if (!IS_ERR(max96714->pwdn_gpio))
701*4882a593Smuzhiyun gpiod_set_value_cansleep(max96714->pwdn_gpio, 0);
702*4882a593Smuzhiyun clk_disable_unprepare(max96714->xvclk);
703*4882a593Smuzhiyun if (!IS_ERR(max96714->reset_gpio))
704*4882a593Smuzhiyun gpiod_set_value_cansleep(max96714->reset_gpio, 0);
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(max96714->pins_sleep)) {
707*4882a593Smuzhiyun ret = pinctrl_select_state(max96714->pinctrl,
708*4882a593Smuzhiyun max96714->pins_sleep);
709*4882a593Smuzhiyun if (ret < 0)
710*4882a593Smuzhiyun dev_dbg(dev, "could not set pins\n");
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun if (!IS_ERR(max96714->power_gpio))
713*4882a593Smuzhiyun gpiod_set_value_cansleep(max96714->power_gpio, 0);
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun regulator_bulk_disable(MAX96714_NUM_SUPPLIES, max96714->supplies);
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun
max96714_runtime_resume(struct device * dev)718*4882a593Smuzhiyun static int max96714_runtime_resume(struct device *dev)
719*4882a593Smuzhiyun {
720*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
721*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
722*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun return __max96714_power_on(max96714);
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun
max96714_runtime_suspend(struct device * dev)727*4882a593Smuzhiyun static int max96714_runtime_suspend(struct device *dev)
728*4882a593Smuzhiyun {
729*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
730*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
731*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun __max96714_power_off(max96714);
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun return 0;
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
max96714_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)739*4882a593Smuzhiyun static int max96714_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
742*4882a593Smuzhiyun struct v4l2_mbus_framefmt *try_fmt =
743*4882a593Smuzhiyun v4l2_subdev_get_try_format(sd, fh->pad, 0);
744*4882a593Smuzhiyun const struct max96714_mode *def_mode = &supported_modes[0];
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun mutex_lock(&max96714->mutex);
747*4882a593Smuzhiyun /* Initialize try_fmt */
748*4882a593Smuzhiyun try_fmt->width = def_mode->width;
749*4882a593Smuzhiyun try_fmt->height = def_mode->height;
750*4882a593Smuzhiyun try_fmt->code = MAX96714_MEDIA_BUS_FMT;
751*4882a593Smuzhiyun try_fmt->field = V4L2_FIELD_NONE;
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun mutex_unlock(&max96714->mutex);
754*4882a593Smuzhiyun /* No crop or compose */
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun return 0;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun #endif
759*4882a593Smuzhiyun
max96714_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)760*4882a593Smuzhiyun static int max96714_enum_frame_interval(struct v4l2_subdev *sd,
761*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
762*4882a593Smuzhiyun struct v4l2_subdev_frame_interval_enum *fie)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun if (fie->index >= ARRAY_SIZE(supported_modes))
765*4882a593Smuzhiyun return -EINVAL;
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun fie->code = MAX96714_MEDIA_BUS_FMT;
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun fie->width = supported_modes[fie->index].width;
770*4882a593Smuzhiyun fie->height = supported_modes[fie->index].height;
771*4882a593Smuzhiyun fie->interval = supported_modes[fie->index].max_fps;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun return 0;
774*4882a593Smuzhiyun }
775*4882a593Smuzhiyun
max96714_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)776*4882a593Smuzhiyun static int max96714_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
777*4882a593Smuzhiyun struct v4l2_mbus_config *config)
778*4882a593Smuzhiyun {
779*4882a593Smuzhiyun config->type = V4L2_MBUS_CSI2_DPHY;
780*4882a593Smuzhiyun config->flags = V4L2_MBUS_CSI2_4_LANE |
781*4882a593Smuzhiyun V4L2_MBUS_CSI2_CHANNEL_0 |
782*4882a593Smuzhiyun V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun return 0;
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun
max96714_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)787*4882a593Smuzhiyun static int max96714_get_selection(struct v4l2_subdev *sd,
788*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
789*4882a593Smuzhiyun struct v4l2_subdev_selection *sel)
790*4882a593Smuzhiyun {
791*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
794*4882a593Smuzhiyun sel->r.left = 0;
795*4882a593Smuzhiyun sel->r.width = max96714->cur_mode->width;
796*4882a593Smuzhiyun sel->r.top = 0;
797*4882a593Smuzhiyun sel->r.height = max96714->cur_mode->height;
798*4882a593Smuzhiyun return 0;
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun return -EINVAL;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun static const struct dev_pm_ops max96714_pm_ops = {
805*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(max96714_runtime_suspend,
806*4882a593Smuzhiyun max96714_runtime_resume, NULL)
807*4882a593Smuzhiyun };
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
810*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops max96714_internal_ops = {
811*4882a593Smuzhiyun .open = max96714_open,
812*4882a593Smuzhiyun };
813*4882a593Smuzhiyun #endif
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops max96714_core_ops = {
816*4882a593Smuzhiyun .s_power = max96714_s_power,
817*4882a593Smuzhiyun .ioctl = max96714_ioctl,
818*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
819*4882a593Smuzhiyun .compat_ioctl32 = max96714_compat_ioctl32,
820*4882a593Smuzhiyun #endif
821*4882a593Smuzhiyun };
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops max96714_video_ops = {
824*4882a593Smuzhiyun .s_stream = max96714_s_stream,
825*4882a593Smuzhiyun .g_frame_interval = max96714_g_frame_interval,
826*4882a593Smuzhiyun };
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops max96714_pad_ops = {
829*4882a593Smuzhiyun .enum_mbus_code = max96714_enum_mbus_code,
830*4882a593Smuzhiyun .enum_frame_size = max96714_enum_frame_sizes,
831*4882a593Smuzhiyun .enum_frame_interval = max96714_enum_frame_interval,
832*4882a593Smuzhiyun .get_fmt = max96714_get_fmt,
833*4882a593Smuzhiyun .set_fmt = max96714_set_fmt,
834*4882a593Smuzhiyun .get_selection = max96714_get_selection,
835*4882a593Smuzhiyun .get_mbus_config = max96714_g_mbus_config,
836*4882a593Smuzhiyun };
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun static const struct v4l2_subdev_ops max96714_subdev_ops = {
839*4882a593Smuzhiyun .core = &max96714_core_ops,
840*4882a593Smuzhiyun .video = &max96714_video_ops,
841*4882a593Smuzhiyun .pad = &max96714_pad_ops,
842*4882a593Smuzhiyun };
843*4882a593Smuzhiyun
max96714_initialize_controls(struct max96714 * max96714)844*4882a593Smuzhiyun static int max96714_initialize_controls(struct max96714 *max96714)
845*4882a593Smuzhiyun {
846*4882a593Smuzhiyun const struct max96714_mode *mode;
847*4882a593Smuzhiyun struct v4l2_ctrl_handler *handler;
848*4882a593Smuzhiyun int ret;
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun handler = &max96714->ctrl_handler;
851*4882a593Smuzhiyun mode = max96714->cur_mode;
852*4882a593Smuzhiyun ret = v4l2_ctrl_handler_init(handler, 2);
853*4882a593Smuzhiyun if (ret)
854*4882a593Smuzhiyun return ret;
855*4882a593Smuzhiyun handler->lock = &max96714->mutex;
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun max96714->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
858*4882a593Smuzhiyun V4L2_CID_LINK_FREQ,
859*4882a593Smuzhiyun 1, 0, link_freq_items);
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun max96714->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
862*4882a593Smuzhiyun V4L2_CID_PIXEL_RATE,
863*4882a593Smuzhiyun 0, MAX96714_PIXEL_RATE,
864*4882a593Smuzhiyun 1, MAX96714_PIXEL_RATE);
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(max96714->link_freq,
867*4882a593Smuzhiyun mode->link_freq_idx);
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun if (handler->error) {
870*4882a593Smuzhiyun ret = handler->error;
871*4882a593Smuzhiyun dev_err(&max96714->client->dev,
872*4882a593Smuzhiyun "Failed to init controls(%d)\n", ret);
873*4882a593Smuzhiyun goto err_free_handler;
874*4882a593Smuzhiyun }
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun max96714->subdev.ctrl_handler = handler;
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun return 0;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun err_free_handler:
881*4882a593Smuzhiyun v4l2_ctrl_handler_free(handler);
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun return ret;
884*4882a593Smuzhiyun }
885*4882a593Smuzhiyun
max96714_check_sensor_id(struct max96714 * max96714,struct i2c_client * client)886*4882a593Smuzhiyun static int max96714_check_sensor_id(struct max96714 *max96714,
887*4882a593Smuzhiyun struct i2c_client *client)
888*4882a593Smuzhiyun {
889*4882a593Smuzhiyun struct device *dev = &max96714->client->dev;
890*4882a593Smuzhiyun u32 id = 0;
891*4882a593Smuzhiyun int ret;
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun ret = max96714_read_reg(client, MAX96714_REG_CHIP_ID,
894*4882a593Smuzhiyun MAX96714_REG_VALUE_08BIT, &id);
895*4882a593Smuzhiyun if (id != CHIP_ID) {
896*4882a593Smuzhiyun dev_err(dev, "Unexpected sensor id(%02x), ret(%d)\n", id, ret);
897*4882a593Smuzhiyun return -ENODEV;
898*4882a593Smuzhiyun }
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun dev_info(dev, "Detected %02x sensor\n", CHIP_ID);
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun return 0;
903*4882a593Smuzhiyun }
904*4882a593Smuzhiyun
max96714_configure_regulators(struct max96714 * max96714)905*4882a593Smuzhiyun static int max96714_configure_regulators(struct max96714 *max96714)
906*4882a593Smuzhiyun {
907*4882a593Smuzhiyun unsigned int i;
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun for (i = 0; i < MAX96714_NUM_SUPPLIES; i++)
910*4882a593Smuzhiyun max96714->supplies[i].supply = max96714_supply_names[i];
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun return devm_regulator_bulk_get(&max96714->client->dev,
913*4882a593Smuzhiyun MAX96714_NUM_SUPPLIES,
914*4882a593Smuzhiyun max96714->supplies);
915*4882a593Smuzhiyun }
916*4882a593Smuzhiyun
max96714_probe(struct i2c_client * client,const struct i2c_device_id * id)917*4882a593Smuzhiyun static int max96714_probe(struct i2c_client *client,
918*4882a593Smuzhiyun const struct i2c_device_id *id)
919*4882a593Smuzhiyun {
920*4882a593Smuzhiyun struct device *dev = &client->dev;
921*4882a593Smuzhiyun struct device_node *node = dev->of_node;
922*4882a593Smuzhiyun struct max96714 *max96714;
923*4882a593Smuzhiyun struct v4l2_subdev *sd;
924*4882a593Smuzhiyun char facing[2];
925*4882a593Smuzhiyun int ret;
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun dev_info(dev, "driver version: %02x.%02x.%02x",
928*4882a593Smuzhiyun DRIVER_VERSION >> 16,
929*4882a593Smuzhiyun (DRIVER_VERSION & 0xff00) >> 8,
930*4882a593Smuzhiyun DRIVER_VERSION & 0x00ff);
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun max96714 = devm_kzalloc(dev, sizeof(*max96714), GFP_KERNEL);
933*4882a593Smuzhiyun if (!max96714)
934*4882a593Smuzhiyun return -ENOMEM;
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
937*4882a593Smuzhiyun &max96714->module_index);
938*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
939*4882a593Smuzhiyun &max96714->module_facing);
940*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
941*4882a593Smuzhiyun &max96714->module_name);
942*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
943*4882a593Smuzhiyun &max96714->len_name);
944*4882a593Smuzhiyun if (ret) {
945*4882a593Smuzhiyun dev_err(dev, "could not get module information!\n");
946*4882a593Smuzhiyun return -EINVAL;
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun max96714->client = client;
950*4882a593Smuzhiyun max96714->cur_mode = &supported_modes[0];
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun max96714->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
953*4882a593Smuzhiyun if (IS_ERR(max96714->power_gpio))
954*4882a593Smuzhiyun dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun max96714->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
957*4882a593Smuzhiyun if (IS_ERR(max96714->reset_gpio))
958*4882a593Smuzhiyun dev_warn(dev, "Failed to get reset-gpios\n");
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun max96714->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
961*4882a593Smuzhiyun if (IS_ERR(max96714->pwdn_gpio))
962*4882a593Smuzhiyun dev_warn(dev, "Failed to get pwdn-gpios\n");
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun ret = max96714_configure_regulators(max96714);
965*4882a593Smuzhiyun if (ret) {
966*4882a593Smuzhiyun dev_err(dev, "Failed to get power regulators\n");
967*4882a593Smuzhiyun return ret;
968*4882a593Smuzhiyun }
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun max96714->pinctrl = devm_pinctrl_get(dev);
971*4882a593Smuzhiyun if (!IS_ERR(max96714->pinctrl)) {
972*4882a593Smuzhiyun max96714->pins_default =
973*4882a593Smuzhiyun pinctrl_lookup_state(max96714->pinctrl,
974*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_DEFAULT);
975*4882a593Smuzhiyun if (IS_ERR(max96714->pins_default))
976*4882a593Smuzhiyun dev_err(dev, "could not get default pinstate\n");
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun max96714->pins_sleep =
979*4882a593Smuzhiyun pinctrl_lookup_state(max96714->pinctrl,
980*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_SLEEP);
981*4882a593Smuzhiyun if (IS_ERR(max96714->pins_sleep))
982*4882a593Smuzhiyun dev_err(dev, "could not get sleep pinstate\n");
983*4882a593Smuzhiyun }
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun mutex_init(&max96714->mutex);
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun sd = &max96714->subdev;
988*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &max96714_subdev_ops);
989*4882a593Smuzhiyun ret = max96714_initialize_controls(max96714);
990*4882a593Smuzhiyun if (ret)
991*4882a593Smuzhiyun goto err_destroy_mutex;
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun ret = __max96714_power_on(max96714);
994*4882a593Smuzhiyun if (ret)
995*4882a593Smuzhiyun goto err_free_handler;
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun ret = max96714_check_sensor_id(max96714, client);
998*4882a593Smuzhiyun if (ret)
999*4882a593Smuzhiyun goto err_power_off;
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1002*4882a593Smuzhiyun sd->internal_ops = &max96714_internal_ops;
1003*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1004*4882a593Smuzhiyun #endif
1005*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1006*4882a593Smuzhiyun max96714->pad.flags = MEDIA_PAD_FL_SOURCE;
1007*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1008*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, 1, &max96714->pad);
1009*4882a593Smuzhiyun if (ret < 0)
1010*4882a593Smuzhiyun goto err_power_off;
1011*4882a593Smuzhiyun #endif
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun memset(facing, 0, sizeof(facing));
1014*4882a593Smuzhiyun if (strcmp(max96714->module_facing, "back") == 0)
1015*4882a593Smuzhiyun facing[0] = 'b';
1016*4882a593Smuzhiyun else
1017*4882a593Smuzhiyun facing[0] = 'f';
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1020*4882a593Smuzhiyun max96714->module_index, facing,
1021*4882a593Smuzhiyun MAX96714_NAME, dev_name(sd->dev));
1022*4882a593Smuzhiyun ret = v4l2_async_register_subdev_sensor_common(sd);
1023*4882a593Smuzhiyun if (ret) {
1024*4882a593Smuzhiyun dev_err(dev, "v4l2 async register subdev failed\n");
1025*4882a593Smuzhiyun goto err_clean_entity;
1026*4882a593Smuzhiyun }
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun pm_runtime_set_active(dev);
1029*4882a593Smuzhiyun pm_runtime_enable(dev);
1030*4882a593Smuzhiyun pm_runtime_idle(dev);
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun return 0;
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun err_clean_entity:
1035*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1036*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1037*4882a593Smuzhiyun #endif
1038*4882a593Smuzhiyun err_power_off:
1039*4882a593Smuzhiyun __max96714_power_off(max96714);
1040*4882a593Smuzhiyun err_free_handler:
1041*4882a593Smuzhiyun v4l2_ctrl_handler_free(&max96714->ctrl_handler);
1042*4882a593Smuzhiyun err_destroy_mutex:
1043*4882a593Smuzhiyun mutex_destroy(&max96714->mutex);
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun return ret;
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun
max96714_remove(struct i2c_client * client)1048*4882a593Smuzhiyun static int max96714_remove(struct i2c_client *client)
1049*4882a593Smuzhiyun {
1050*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1051*4882a593Smuzhiyun struct max96714 *max96714 = to_max96714(sd);
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
1054*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1055*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1056*4882a593Smuzhiyun #endif
1057*4882a593Smuzhiyun v4l2_ctrl_handler_free(&max96714->ctrl_handler);
1058*4882a593Smuzhiyun mutex_destroy(&max96714->mutex);
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1061*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&client->dev))
1062*4882a593Smuzhiyun __max96714_power_off(max96714);
1063*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun return 0;
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1069*4882a593Smuzhiyun static const struct of_device_id max96714_of_match[] = {
1070*4882a593Smuzhiyun { .compatible = "maxim,max96714" },
1071*4882a593Smuzhiyun {},
1072*4882a593Smuzhiyun };
1073*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max96714_of_match);
1074*4882a593Smuzhiyun #endif
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun static const struct i2c_device_id max96714_match_id[] = {
1077*4882a593Smuzhiyun { "maxim,max96714", 0 },
1078*4882a593Smuzhiyun {},
1079*4882a593Smuzhiyun };
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun static struct i2c_driver max96714_i2c_driver = {
1082*4882a593Smuzhiyun .driver = {
1083*4882a593Smuzhiyun .name = MAX96714_NAME,
1084*4882a593Smuzhiyun .pm = &max96714_pm_ops,
1085*4882a593Smuzhiyun .of_match_table = of_match_ptr(max96714_of_match),
1086*4882a593Smuzhiyun },
1087*4882a593Smuzhiyun .probe = &max96714_probe,
1088*4882a593Smuzhiyun .remove = &max96714_remove,
1089*4882a593Smuzhiyun .id_table = max96714_match_id,
1090*4882a593Smuzhiyun };
1091*4882a593Smuzhiyun
max96714_sensor_mod_init(void)1092*4882a593Smuzhiyun int max96714_sensor_mod_init(void)
1093*4882a593Smuzhiyun {
1094*4882a593Smuzhiyun return i2c_add_driver(&max96714_i2c_driver);
1095*4882a593Smuzhiyun }
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun #ifndef CONFIG_VIDEO_REVERSE_IMAGE
1098*4882a593Smuzhiyun device_initcall_sync(max96714_sensor_mod_init);
1099*4882a593Smuzhiyun #endif
1100*4882a593Smuzhiyun
sensor_mod_exit(void)1101*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1102*4882a593Smuzhiyun {
1103*4882a593Smuzhiyun i2c_del_driver(&max96714_i2c_driver);
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun MODULE_DESCRIPTION("Maxim max96714 sensor driver");
1109*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1110