1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Dingxian Wen <shawn.wen@rock-chips.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _LT8619C_H 9*4882a593Smuzhiyun #define _LT8619C_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* --------------- configuration -------------------- */ 12*4882a593Smuzhiyun #define CLK_SRC XTAL_CLK 13*4882a593Smuzhiyun #define REF_RESISTANCE EXT_RESISTANCE 14*4882a593Smuzhiyun #define CP_CONVERT_MODE HDPC 15*4882a593Smuzhiyun #define YUV_COLORDEPTH OUTPUT_16BIT_LOW 16*4882a593Smuzhiyun #define BT_TX_SYNC_POL BT_TX_SYNC_POSITIVE 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* -------------------------------------------------- */ 19*4882a593Smuzhiyun #define LT8619C_CHIPID 0x1604B0 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define EDID_NUM_BLOCKS_MAX 2 22*4882a593Smuzhiyun #define EDID_BLOCK_SIZE 128 23*4882a593Smuzhiyun #define POLL_INTERVAL_MS 1000 24*4882a593Smuzhiyun #define lt8619c_PIXEL_RATE 400000000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define BANK_REG 0xff 27*4882a593Smuzhiyun #define BANK_60 0x60 28*4882a593Smuzhiyun #define BANK_80 0x80 29*4882a593Smuzhiyun #define CHIPID_REG_H 0x00 30*4882a593Smuzhiyun #define CHIPID_REG_M 0x01 31*4882a593Smuzhiyun #define CHIPID_REG_L 0x02 32*4882a593Smuzhiyun #define LT8619C_MAX_REGISTER 0xff 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define WAIT_MAX_TIMES 10 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define BT656_OUTPUT 0x04 37*4882a593Smuzhiyun #define BT1120_OUTPUT 0x03 38*4882a593Smuzhiyun #define BT1120_8BIT_OUTPUT 0x05 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define BT_TX_SYNC_POSITIVE 0x30 41*4882a593Smuzhiyun #define BT_TX_SYNC_NEGATIVE 0x00 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define PROGRESSIVE_INDICATOR 0x00 44*4882a593Smuzhiyun #define INTERLACE_INDICATOR 0x08 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 0x08: Use xtal clk; 0x18: Use internal clk */ 47*4882a593Smuzhiyun #define XTAL_CLK 0x08 48*4882a593Smuzhiyun #define INT_CLK 0x18 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* internal resistance */ 51*4882a593Smuzhiyun #define INT_RESISTANCE 0x88 52*4882a593Smuzhiyun /* external resistance(Pin 16 - REXT, 2K resistance) */ 53*4882a593Smuzhiyun #define EXT_RESISTANCE 0x80 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CLK_SDRMODE 0 56*4882a593Smuzhiyun /* CLK divided by 2 */ 57*4882a593Smuzhiyun #define CLK_DDRMODE 1 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define SDTV 0x00 60*4882a593Smuzhiyun #define SDPC 0x10 61*4882a593Smuzhiyun #define HDTV 0x20 62*4882a593Smuzhiyun #define HDPC 0x30 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * enable 66*4882a593Smuzhiyun * D0 ~ D7 Y ; D8 ~ D15 C 67*4882a593Smuzhiyun * D8 ~ D15 Y ; D16 ~ D23 C 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun #define YC_SWAP_EN 0x08 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * disable 72*4882a593Smuzhiyun * D0 ~ D7 C ; D8 ~ D15 Y 73*4882a593Smuzhiyun * D8 ~ D15 C ; D16 ~ D23 Y 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun #define YC_SWAP_DIS 0x00 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * BT1120 24bit / BT656 12bit 79*4882a593Smuzhiyun * when YC_SWAP_EN: 80*4882a593Smuzhiyun * BT656 12bit D0 ~ D11 81*4882a593Smuzhiyun * BT1120 24bit : D0 ~ D11 Y ; D12 ~ D23 C 82*4882a593Smuzhiyun * when YC_SWAP_DIS: 83*4882a593Smuzhiyun * BT656 12bit D12 ~ D23 84*4882a593Smuzhiyun * BT1120 24bit : D0 ~ D11 C ; D12 ~ D23 Y 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun #define OUTPUT_24BIT 0x00 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * BT1120 20bit / BT656 10bit 90*4882a593Smuzhiyun * when YC_SWAP_EN: 91*4882a593Smuzhiyun * BT656 10bit D4 ~ D13 92*4882a593Smuzhiyun * BT1120 20bit : D4 ~ D13 Y ; D14 ~ D23 C 93*4882a593Smuzhiyun * when YC_SWAP_DIS: 94*4882a593Smuzhiyun * BT656 10bit D14 ~ D23 95*4882a593Smuzhiyun * BT1120 20bit : D4 ~ D13 C ; D14 ~ D23 Y 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun #define OUTPUT_20BIT_HIGH 0x04 98*4882a593Smuzhiyun /* 99*4882a593Smuzhiyun * when YC_SWAP_EN: 100*4882a593Smuzhiyun * BT656 10bit D0 ~ D9 101*4882a593Smuzhiyun * BT1120 20bit : D0 ~ D9 Y ; D10 ~ D19 C 102*4882a593Smuzhiyun * when YC_SWAP_DIS: 103*4882a593Smuzhiyun * BT656 10bit D10 ~ D19 104*4882a593Smuzhiyun * BT1120 20bit : D0 ~ D9 C ; D10 ~ D19 Y 105*4882a593Smuzhiyun */ 106*4882a593Smuzhiyun #define OUTPUT_20BIT_LOW 0x05 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* 109*4882a593Smuzhiyun * BT1120 16bit / BT656 8bit 110*4882a593Smuzhiyun * when YC_SWAP_EN: 111*4882a593Smuzhiyun * BT656 8bit D8 ~ D15 112*4882a593Smuzhiyun * BT1120 16bit : D8 ~ D15 Y ; D16 ~ D23 C 113*4882a593Smuzhiyun * when YC_SWAP_DIS: 114*4882a593Smuzhiyun * BT656 8bit D16 ~ D23 115*4882a593Smuzhiyun * BT1120 16bit : D8 ~ D15 C ; D16 ~ D23 Y 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun #define OUTPUT_16BIT_HIGH 0x06 118*4882a593Smuzhiyun /* 119*4882a593Smuzhiyun * when YC_SWAP_EN: 120*4882a593Smuzhiyun * BT656 8bit D0 ~ D7 121*4882a593Smuzhiyun * BT1120 16bit : D0 ~ D7 Y ; D8 ~ D15 C 122*4882a593Smuzhiyun * when YC_SWAP_DIS: 123*4882a593Smuzhiyun * BT656 8bit D8 ~ D15 124*4882a593Smuzhiyun * BT1120 16bit : D0 ~ D7 C ; D8 ~ D15 Y 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun #define OUTPUT_16BIT_LOW 0x07 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* ---------------- regs ----------------- */ 129*4882a593Smuzhiyun /* reg: 0x60_60 */ 130*4882a593Smuzhiyun #define SYNC_POL_MASK GENMASK(5, 4) 131*4882a593Smuzhiyun #define IP_SEL_MASK GENMASK(3, 3) 132*4882a593Smuzhiyun #define OUTPUT_MODE_MASK GENMASK(2, 0) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* reg: 0x80_05 */ 135*4882a593Smuzhiyun #define RGD_HS_POL_ADJ_MASK GENMASK(5, 5) 136*4882a593Smuzhiyun #define RGD_VS_POL_ADJ_MASK GENMASK(4, 4) 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* reg: 0x80_17 */ 139*4882a593Smuzhiyun #define RGOD_VID_HSPOL BIT(7) 140*4882a593Smuzhiyun #define RGOD_VID_VSPOL BIT(6) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #endif 143