xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/lt7911uxc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * lt7911uxc type-c/DP to MIPI CSI-2 bridge driver.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Jianwei Fan <jianwei.fan@rock-chips.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * V0.0X01.0X00 first version.
10*4882a593Smuzhiyun  * V0.0X01.0X01 support DPHY 4K60.
11*4882a593Smuzhiyun  * V0.0X01.0X02 add CPHY support.
12*4882a593Smuzhiyun  * V0.0X01.0X03 add rk3588 dcphy param.
13*4882a593Smuzhiyun  * V0.0X01.0X04 add 5K60 support for CPHY.
14*4882a593Smuzhiyun  * V0.0X01.0X05 add CSI BGR888 fmt.
15*4882a593Smuzhiyun  * V0.0X01.0X06 fix dcphy params and add more fmt.
16*4882a593Smuzhiyun  * V0.0X01.0X07
17*4882a593Smuzhiyun  *	1.fix driver probe sequence.
18*4882a593Smuzhiyun  *	2.set default timing
19*4882a593Smuzhiyun  *	3.fix dcphy params
20*4882a593Smuzhiyun  *	4.fix hotplug event report
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  */
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include <linux/clk.h>
25*4882a593Smuzhiyun #include <linux/delay.h>
26*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
27*4882a593Smuzhiyun #include <linux/hdmi.h>
28*4882a593Smuzhiyun #include <linux/i2c.h>
29*4882a593Smuzhiyun #include <linux/interrupt.h>
30*4882a593Smuzhiyun #include <linux/kernel.h>
31*4882a593Smuzhiyun #include <linux/module.h>
32*4882a593Smuzhiyun #include <linux/of_graph.h>
33*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
34*4882a593Smuzhiyun #include <linux/slab.h>
35*4882a593Smuzhiyun #include <linux/timer.h>
36*4882a593Smuzhiyun #include <linux/v4l2-dv-timings.h>
37*4882a593Smuzhiyun #include <linux/version.h>
38*4882a593Smuzhiyun #include <linux/videodev2.h>
39*4882a593Smuzhiyun #include <linux/workqueue.h>
40*4882a593Smuzhiyun #include <linux/compat.h>
41*4882a593Smuzhiyun #include <media/v4l2-controls_rockchip.h>
42*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
43*4882a593Smuzhiyun #include <media/v4l2-device.h>
44*4882a593Smuzhiyun #include <media/v4l2-dv-timings.h>
45*4882a593Smuzhiyun #include <media/v4l2-event.h>
46*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x07)
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun static int debug;
51*4882a593Smuzhiyun module_param(debug, int, 0644);
52*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "debug level (0-3)");
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define I2C_MAX_XFER_SIZE	128
55*4882a593Smuzhiyun #define POLL_INTERVAL_MS	1000
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define LT7911UXC_LINK_FREQ_1250M	1250000000
58*4882a593Smuzhiyun #define LT7911UXC_LINK_FREQ_860M	860000000
59*4882a593Smuzhiyun #define LT7911UXC_LINK_FREQ_700M	700000000
60*4882a593Smuzhiyun #define LT7911UXC_LINK_FREQ_400M	400000000
61*4882a593Smuzhiyun #define LT7911UXC_LINK_FREQ_300M	300000000
62*4882a593Smuzhiyun #define LT7911UXC_LINK_FREQ_200M	200000000
63*4882a593Smuzhiyun #define LT7911UXC_LINK_FREQ_100M	100000000
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define LT7911UXC_PIXEL_RATE		800000000
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define LT7911UXC_CHIPID	0x0119
68*4882a593Smuzhiyun #define CHIPID_REGH		0xe101
69*4882a593Smuzhiyun #define CHIPID_REGL		0xe100
70*4882a593Smuzhiyun #define I2C_EN_REG		0xe0ee
71*4882a593Smuzhiyun #define I2C_ENABLE		0x1
72*4882a593Smuzhiyun #define I2C_DISABLE		0x0
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define HTOTAL_H		0xe088
75*4882a593Smuzhiyun #define HTOTAL_L		0xe089
76*4882a593Smuzhiyun #define HACT_H			0xe08c
77*4882a593Smuzhiyun #define HACT_L			0xe08d
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #define VTOTAL_H		0xe08a
80*4882a593Smuzhiyun #define VTOTAL_L		0xe08b
81*4882a593Smuzhiyun #define VACT_H			0xe08e
82*4882a593Smuzhiyun #define VACT_L			0xe08f
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define PCLK_H			0xe085
85*4882a593Smuzhiyun #define PCLK_M			0xe086
86*4882a593Smuzhiyun #define PCLK_L			0xe087
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun #define BYTE_PCLK_H		0xe092
89*4882a593Smuzhiyun #define BYTE_PCLK_M		0xe093
90*4882a593Smuzhiyun #define BYTE_PCLK_L		0xe094
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define AUDIO_FS_VALUE_H	0xe090
93*4882a593Smuzhiyun #define AUDIO_FS_VALUE_L	0xe091
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun //CPHY timing
96*4882a593Smuzhiyun #define CLK_ZERO_REG		0xf9a7
97*4882a593Smuzhiyun #define CLK_PRE_REG		0xf9a8
98*4882a593Smuzhiyun #define CLK_POST_REG		0xf9a9
99*4882a593Smuzhiyun #define HS_LPX_REG		0xf9a4
100*4882a593Smuzhiyun #define HS_PREP_REG		0xf9a5
101*4882a593Smuzhiyun #define HS_TRAIL		0xf9a6
102*4882a593Smuzhiyun #define HS_RQST_PRE_REG		0xf98a
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun #define STREAM_CTL		0xe0b0
105*4882a593Smuzhiyun #define ENABLE_STREAM		0x01
106*4882a593Smuzhiyun #define DISABLE_STREAM		0x00
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun #ifdef LT7911UXC_OUT_RGB
109*4882a593Smuzhiyun #define LT7911UXC_MEDIA_BUS_FMT		MEDIA_BUS_FMT_BGR888_1X24
110*4882a593Smuzhiyun #else
111*4882a593Smuzhiyun #define LT7911UXC_MEDIA_BUS_FMT		MEDIA_BUS_FMT_UYVY8_2X8
112*4882a593Smuzhiyun #endif
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun #define LT7911UXC_NAME			"LT7911UXC"
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
117*4882a593Smuzhiyun 	LT7911UXC_LINK_FREQ_1250M,
118*4882a593Smuzhiyun 	LT7911UXC_LINK_FREQ_860M,
119*4882a593Smuzhiyun 	LT7911UXC_LINK_FREQ_700M,
120*4882a593Smuzhiyun 	LT7911UXC_LINK_FREQ_400M,
121*4882a593Smuzhiyun 	LT7911UXC_LINK_FREQ_300M,
122*4882a593Smuzhiyun 	LT7911UXC_LINK_FREQ_200M,
123*4882a593Smuzhiyun 	LT7911UXC_LINK_FREQ_100M,
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun struct lt7911uxc {
127*4882a593Smuzhiyun 	struct v4l2_fwnode_bus_mipi_csi2 bus;
128*4882a593Smuzhiyun 	struct v4l2_subdev sd;
129*4882a593Smuzhiyun 	struct media_pad pad;
130*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
131*4882a593Smuzhiyun 	struct i2c_client *i2c_client;
132*4882a593Smuzhiyun 	struct mutex confctl_mutex;
133*4882a593Smuzhiyun 	struct v4l2_ctrl *detect_tx_5v_ctrl;
134*4882a593Smuzhiyun 	struct v4l2_ctrl *audio_sampling_rate_ctrl;
135*4882a593Smuzhiyun 	struct v4l2_ctrl *audio_present_ctrl;
136*4882a593Smuzhiyun 	struct v4l2_ctrl *link_freq;
137*4882a593Smuzhiyun 	struct v4l2_ctrl *pixel_rate;
138*4882a593Smuzhiyun 	struct delayed_work delayed_work_hotplug;
139*4882a593Smuzhiyun 	struct delayed_work delayed_work_res_change;
140*4882a593Smuzhiyun 	struct v4l2_dv_timings timings;
141*4882a593Smuzhiyun 	struct clk *xvclk;
142*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
143*4882a593Smuzhiyun 	struct gpio_desc *plugin_det_gpio;
144*4882a593Smuzhiyun 	struct gpio_desc *power_gpio;
145*4882a593Smuzhiyun 	struct work_struct work_i2c_poll;
146*4882a593Smuzhiyun 	struct timer_list timer;
147*4882a593Smuzhiyun 	const char *module_facing;
148*4882a593Smuzhiyun 	const char *module_name;
149*4882a593Smuzhiyun 	const char *len_name;
150*4882a593Smuzhiyun 	const struct lt7911uxc_mode *cur_mode;
151*4882a593Smuzhiyun 	const struct lt7911uxc_mode *support_modes;
152*4882a593Smuzhiyun 	u32 cfg_num;
153*4882a593Smuzhiyun 	struct v4l2_fwnode_endpoint bus_cfg;
154*4882a593Smuzhiyun 	bool nosignal;
155*4882a593Smuzhiyun 	bool enable_hdcp;
156*4882a593Smuzhiyun 	bool is_audio_present;
157*4882a593Smuzhiyun 	bool power_on;
158*4882a593Smuzhiyun 	int plugin_irq;
159*4882a593Smuzhiyun 	u32 mbus_fmt_code;
160*4882a593Smuzhiyun 	u32 module_index;
161*4882a593Smuzhiyun 	u32 audio_sampling_rate;
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun static const struct v4l2_dv_timings_cap lt7911uxc_timings_cap = {
165*4882a593Smuzhiyun 	.type = V4L2_DV_BT_656_1120,
166*4882a593Smuzhiyun 	.reserved = { 0 },
167*4882a593Smuzhiyun 	V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 800000000,
168*4882a593Smuzhiyun 			V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
169*4882a593Smuzhiyun 			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
170*4882a593Smuzhiyun 			V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
171*4882a593Smuzhiyun 			V4L2_DV_BT_CAP_REDUCED_BLANKING |
172*4882a593Smuzhiyun 			V4L2_DV_BT_CAP_CUSTOM)
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun struct lt7911uxc_mode {
176*4882a593Smuzhiyun 	u32 width;
177*4882a593Smuzhiyun 	u32 height;
178*4882a593Smuzhiyun 	struct v4l2_fract max_fps;
179*4882a593Smuzhiyun 	u32 hts_def;
180*4882a593Smuzhiyun 	u32 vts_def;
181*4882a593Smuzhiyun 	u32 exp_def;
182*4882a593Smuzhiyun 	u32 mipi_freq_idx;
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
186*4882a593Smuzhiyun 	.vendor = PHY_VENDOR_SAMSUNG,
187*4882a593Smuzhiyun 	.lp_vol_ref = 3,
188*4882a593Smuzhiyun 	.lp_hys_sw = {3, 0, 3, 0},
189*4882a593Smuzhiyun 	.lp_escclk_pol_sel = {1, 1, 0, 0},
190*4882a593Smuzhiyun 	.skew_data_cal_clk = {0, 0, 0, 0},
191*4882a593Smuzhiyun 	.clk_hs_term_sel = 0,
192*4882a593Smuzhiyun 	.data_hs_term_sel = {0, 0, 0, 0},
193*4882a593Smuzhiyun 	.reserved = {0},
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun static const struct lt7911uxc_mode supported_modes_dphy[] = {
197*4882a593Smuzhiyun 	{
198*4882a593Smuzhiyun 		.width = 3840,
199*4882a593Smuzhiyun 		.height = 2160,
200*4882a593Smuzhiyun 		.max_fps = {
201*4882a593Smuzhiyun 			.numerator = 10000,
202*4882a593Smuzhiyun 			.denominator = 600000,
203*4882a593Smuzhiyun 		},
204*4882a593Smuzhiyun 		.hts_def = 4400,
205*4882a593Smuzhiyun 		.vts_def = 2250,
206*4882a593Smuzhiyun 		.mipi_freq_idx = 0,
207*4882a593Smuzhiyun 	}, {
208*4882a593Smuzhiyun 		.width = 1920,
209*4882a593Smuzhiyun 		.height = 1080,
210*4882a593Smuzhiyun 		.max_fps = {
211*4882a593Smuzhiyun 			.numerator = 10000,
212*4882a593Smuzhiyun 			.denominator = 600000,
213*4882a593Smuzhiyun 		},
214*4882a593Smuzhiyun 		.hts_def = 2200,
215*4882a593Smuzhiyun 		.vts_def = 1125,
216*4882a593Smuzhiyun 		.mipi_freq_idx = 4,
217*4882a593Smuzhiyun 	}, {
218*4882a593Smuzhiyun 		.width = 1600,
219*4882a593Smuzhiyun 		.height = 1200,
220*4882a593Smuzhiyun 		.max_fps = {
221*4882a593Smuzhiyun 			.numerator = 10000,
222*4882a593Smuzhiyun 			.denominator = 600000,
223*4882a593Smuzhiyun 		},
224*4882a593Smuzhiyun 		.hts_def = 2160,
225*4882a593Smuzhiyun 		.vts_def = 1250,
226*4882a593Smuzhiyun 		.mipi_freq_idx = 4,
227*4882a593Smuzhiyun 	}, {
228*4882a593Smuzhiyun 		.width = 1280,
229*4882a593Smuzhiyun 		.height = 960,
230*4882a593Smuzhiyun 		.max_fps = {
231*4882a593Smuzhiyun 			.numerator = 10000,
232*4882a593Smuzhiyun 			.denominator = 600000,
233*4882a593Smuzhiyun 		},
234*4882a593Smuzhiyun 		.hts_def = 1712,
235*4882a593Smuzhiyun 		.vts_def = 994,
236*4882a593Smuzhiyun 		.mipi_freq_idx = 5,
237*4882a593Smuzhiyun 	}, {
238*4882a593Smuzhiyun 		.width = 1280,
239*4882a593Smuzhiyun 		.height = 720,
240*4882a593Smuzhiyun 		.max_fps = {
241*4882a593Smuzhiyun 			.numerator = 10000,
242*4882a593Smuzhiyun 			.denominator = 600000,
243*4882a593Smuzhiyun 		},
244*4882a593Smuzhiyun 		.hts_def = 1650,
245*4882a593Smuzhiyun 		.vts_def = 750,
246*4882a593Smuzhiyun 		.mipi_freq_idx = 5,
247*4882a593Smuzhiyun 	}, {
248*4882a593Smuzhiyun 		.width = 800,
249*4882a593Smuzhiyun 		.height = 600,
250*4882a593Smuzhiyun 		.max_fps = {
251*4882a593Smuzhiyun 			.numerator = 10000,
252*4882a593Smuzhiyun 			.denominator = 600000,
253*4882a593Smuzhiyun 		},
254*4882a593Smuzhiyun 		.hts_def = 1056,
255*4882a593Smuzhiyun 		.vts_def = 628,
256*4882a593Smuzhiyun 		.mipi_freq_idx = 6,
257*4882a593Smuzhiyun 	}, {
258*4882a593Smuzhiyun 		.width = 720,
259*4882a593Smuzhiyun 		.height = 576,
260*4882a593Smuzhiyun 		.max_fps = {
261*4882a593Smuzhiyun 			.numerator = 10000,
262*4882a593Smuzhiyun 			.denominator = 500000,
263*4882a593Smuzhiyun 		},
264*4882a593Smuzhiyun 		.hts_def = 864,
265*4882a593Smuzhiyun 		.vts_def = 625,
266*4882a593Smuzhiyun 		.mipi_freq_idx = 6,
267*4882a593Smuzhiyun 	}, {
268*4882a593Smuzhiyun 		.width = 720,
269*4882a593Smuzhiyun 		.height = 480,
270*4882a593Smuzhiyun 		.max_fps = {
271*4882a593Smuzhiyun 			.numerator = 10000,
272*4882a593Smuzhiyun 			.denominator = 600000,
273*4882a593Smuzhiyun 		},
274*4882a593Smuzhiyun 		.hts_def = 858,
275*4882a593Smuzhiyun 		.vts_def = 525,
276*4882a593Smuzhiyun 		.mipi_freq_idx = 6,
277*4882a593Smuzhiyun 	},
278*4882a593Smuzhiyun };
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun static const struct lt7911uxc_mode supported_modes_cphy[] = {
281*4882a593Smuzhiyun 	{
282*4882a593Smuzhiyun 		.width = 5120,
283*4882a593Smuzhiyun 		.height = 2160,
284*4882a593Smuzhiyun 		.max_fps = {
285*4882a593Smuzhiyun 			.numerator = 10000,
286*4882a593Smuzhiyun 			.denominator = 600000,
287*4882a593Smuzhiyun 		},
288*4882a593Smuzhiyun 		.hts_def = 5500,
289*4882a593Smuzhiyun 		.vts_def = 2250,
290*4882a593Smuzhiyun 		.mipi_freq_idx = 1,
291*4882a593Smuzhiyun 	}, {
292*4882a593Smuzhiyun 		.width = 3840,
293*4882a593Smuzhiyun 		.height = 2160,
294*4882a593Smuzhiyun 		.max_fps = {
295*4882a593Smuzhiyun 			.numerator = 10000,
296*4882a593Smuzhiyun 			.denominator = 600000,
297*4882a593Smuzhiyun 		},
298*4882a593Smuzhiyun 		.hts_def = 4400,
299*4882a593Smuzhiyun 		.vts_def = 2250,
300*4882a593Smuzhiyun 		.mipi_freq_idx = 2,
301*4882a593Smuzhiyun 	}, {
302*4882a593Smuzhiyun 		.width = 1920,
303*4882a593Smuzhiyun 		.height = 1080,
304*4882a593Smuzhiyun 		.max_fps = {
305*4882a593Smuzhiyun 			.numerator = 10000,
306*4882a593Smuzhiyun 			.denominator = 600000,
307*4882a593Smuzhiyun 		},
308*4882a593Smuzhiyun 		.hts_def = 2200,
309*4882a593Smuzhiyun 		.vts_def = 1125,
310*4882a593Smuzhiyun 		.mipi_freq_idx = 5,
311*4882a593Smuzhiyun 	}, {
312*4882a593Smuzhiyun 		.width = 1280,
313*4882a593Smuzhiyun 		.height = 720,
314*4882a593Smuzhiyun 		.max_fps = {
315*4882a593Smuzhiyun 			.numerator = 10000,
316*4882a593Smuzhiyun 			.denominator = 600000,
317*4882a593Smuzhiyun 		},
318*4882a593Smuzhiyun 		.hts_def = 1650,
319*4882a593Smuzhiyun 		.vts_def = 750,
320*4882a593Smuzhiyun 		.mipi_freq_idx = 6,
321*4882a593Smuzhiyun 	}, {
322*4882a593Smuzhiyun 		.width = 720,
323*4882a593Smuzhiyun 		.height = 576,
324*4882a593Smuzhiyun 		.max_fps = {
325*4882a593Smuzhiyun 			.numerator = 10000,
326*4882a593Smuzhiyun 			.denominator = 500000,
327*4882a593Smuzhiyun 		},
328*4882a593Smuzhiyun 		.hts_def = 864,
329*4882a593Smuzhiyun 		.vts_def = 625,
330*4882a593Smuzhiyun 		.mipi_freq_idx = 6,
331*4882a593Smuzhiyun 	}, {
332*4882a593Smuzhiyun 		.width = 720,
333*4882a593Smuzhiyun 		.height = 480,
334*4882a593Smuzhiyun 		.max_fps = {
335*4882a593Smuzhiyun 			.numerator = 10000,
336*4882a593Smuzhiyun 			.denominator = 600000,
337*4882a593Smuzhiyun 		},
338*4882a593Smuzhiyun 		.hts_def = 858,
339*4882a593Smuzhiyun 		.vts_def = 525,
340*4882a593Smuzhiyun 		.mipi_freq_idx = 6,
341*4882a593Smuzhiyun 	},
342*4882a593Smuzhiyun };
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun static void lt7911uxc_format_change(struct v4l2_subdev *sd);
345*4882a593Smuzhiyun static int lt7911uxc_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
346*4882a593Smuzhiyun static int lt7911uxc_s_dv_timings(struct v4l2_subdev *sd,
347*4882a593Smuzhiyun 				struct v4l2_dv_timings *timings);
348*4882a593Smuzhiyun 
to_lt7911uxc(struct v4l2_subdev * sd)349*4882a593Smuzhiyun static inline struct lt7911uxc *to_lt7911uxc(struct v4l2_subdev *sd)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun 	return container_of(sd, struct lt7911uxc, sd);
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun 
i2c_rd(struct v4l2_subdev * sd,u16 reg,u8 * values,u32 n)354*4882a593Smuzhiyun static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
357*4882a593Smuzhiyun 	struct i2c_client *client = lt7911uxc->i2c_client;
358*4882a593Smuzhiyun 	int err;
359*4882a593Smuzhiyun 	u8 buf[2] = { 0xFF, reg >> 8};
360*4882a593Smuzhiyun 	u8 reg_addr = reg & 0xFF;
361*4882a593Smuzhiyun 	struct i2c_msg msgs[3];
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	msgs[0].addr = client->addr;
364*4882a593Smuzhiyun 	msgs[0].flags = 0;
365*4882a593Smuzhiyun 	msgs[0].len = 2;
366*4882a593Smuzhiyun 	msgs[0].buf = buf;
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	msgs[1].addr = client->addr;
369*4882a593Smuzhiyun 	msgs[1].flags = 0;
370*4882a593Smuzhiyun 	msgs[1].len = 1;
371*4882a593Smuzhiyun 	msgs[1].buf = &reg_addr;
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	msgs[2].addr = client->addr;
374*4882a593Smuzhiyun 	msgs[2].flags = I2C_M_RD;
375*4882a593Smuzhiyun 	msgs[2].len = n;
376*4882a593Smuzhiyun 	msgs[2].buf = values;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
379*4882a593Smuzhiyun 	if (err != ARRAY_SIZE(msgs)) {
380*4882a593Smuzhiyun 		v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
381*4882a593Smuzhiyun 				__func__, reg, client->addr);
382*4882a593Smuzhiyun 	}
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	if (!debug)
385*4882a593Smuzhiyun 		return;
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	switch (n) {
388*4882a593Smuzhiyun 	case 1:
389*4882a593Smuzhiyun 		v4l2_info(sd, "I2C read 0x%04x = 0x%02x\n",
390*4882a593Smuzhiyun 			reg, values[0]);
391*4882a593Smuzhiyun 		break;
392*4882a593Smuzhiyun 	case 2:
393*4882a593Smuzhiyun 		v4l2_info(sd, "I2C read 0x%04x = 0x%02x%02x\n",
394*4882a593Smuzhiyun 			reg, values[1], values[0]);
395*4882a593Smuzhiyun 		break;
396*4882a593Smuzhiyun 	case 4:
397*4882a593Smuzhiyun 		v4l2_info(sd, "I2C read 0x%04x = 0x%02x%02x%02x%02x\n",
398*4882a593Smuzhiyun 			reg, values[3], values[2], values[1], values[0]);
399*4882a593Smuzhiyun 		break;
400*4882a593Smuzhiyun 	default:
401*4882a593Smuzhiyun 		v4l2_info(sd, "I2C read %d bytes from address 0x%04x\n",
402*4882a593Smuzhiyun 			n, reg);
403*4882a593Smuzhiyun 	}
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun 
i2c_wr(struct v4l2_subdev * sd,u16 reg,u8 * values,u32 n)406*4882a593Smuzhiyun static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
407*4882a593Smuzhiyun {
408*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
409*4882a593Smuzhiyun 	struct i2c_client *client = lt7911uxc->i2c_client;
410*4882a593Smuzhiyun 	int err, i;
411*4882a593Smuzhiyun 	struct i2c_msg msgs[2];
412*4882a593Smuzhiyun 	u8 data[I2C_MAX_XFER_SIZE];
413*4882a593Smuzhiyun 	u8 buf[2] = { 0xFF, reg >> 8};
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	if ((1 + n) > I2C_MAX_XFER_SIZE) {
416*4882a593Smuzhiyun 		n = I2C_MAX_XFER_SIZE - 1;
417*4882a593Smuzhiyun 		v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
418*4882a593Smuzhiyun 			  reg, 1 + n);
419*4882a593Smuzhiyun 	}
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	msgs[0].addr = client->addr;
422*4882a593Smuzhiyun 	msgs[0].flags = 0;
423*4882a593Smuzhiyun 	msgs[0].len = 2;
424*4882a593Smuzhiyun 	msgs[0].buf = buf;
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	msgs[1].addr = client->addr;
427*4882a593Smuzhiyun 	msgs[1].flags = 0;
428*4882a593Smuzhiyun 	msgs[1].len = 1 + n;
429*4882a593Smuzhiyun 	msgs[1].buf = data;
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	data[0] = reg & 0xff;
432*4882a593Smuzhiyun 	for (i = 0; i < n; i++)
433*4882a593Smuzhiyun 		data[1 + i] = values[i];
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
436*4882a593Smuzhiyun 	if (err < 0) {
437*4882a593Smuzhiyun 		v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
438*4882a593Smuzhiyun 				__func__, reg, client->addr);
439*4882a593Smuzhiyun 		return;
440*4882a593Smuzhiyun 	}
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	if (!debug)
443*4882a593Smuzhiyun 		return;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	switch (n) {
446*4882a593Smuzhiyun 	case 1:
447*4882a593Smuzhiyun 		v4l2_info(sd, "I2C write 0x%04x = 0x%02x\n",
448*4882a593Smuzhiyun 				reg, data[1]);
449*4882a593Smuzhiyun 		break;
450*4882a593Smuzhiyun 	case 2:
451*4882a593Smuzhiyun 		v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x\n",
452*4882a593Smuzhiyun 				reg, data[2], data[1]);
453*4882a593Smuzhiyun 		break;
454*4882a593Smuzhiyun 	case 4:
455*4882a593Smuzhiyun 		v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x\n",
456*4882a593Smuzhiyun 				reg, data[4], data[3], data[2], data[1]);
457*4882a593Smuzhiyun 		break;
458*4882a593Smuzhiyun 	default:
459*4882a593Smuzhiyun 		v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
460*4882a593Smuzhiyun 				n, reg);
461*4882a593Smuzhiyun 	}
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun 
i2c_rd8(struct v4l2_subdev * sd,u16 reg)464*4882a593Smuzhiyun static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun 	u32 val;
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	i2c_rd(sd, reg, (u8 __force *)&val, 1);
469*4882a593Smuzhiyun 	return val;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun 
i2c_wr8(struct v4l2_subdev * sd,u16 reg,u8 val)472*4882a593Smuzhiyun static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun 	i2c_wr(sd, reg, &val, 1);
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun 
lt7911uxc_i2c_enable(struct v4l2_subdev * sd)477*4882a593Smuzhiyun static void lt7911uxc_i2c_enable(struct v4l2_subdev *sd)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun 	i2c_wr8(sd, I2C_EN_REG, I2C_ENABLE);
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun 
lt7911uxc_i2c_disable(struct v4l2_subdev * sd)482*4882a593Smuzhiyun static void lt7911uxc_i2c_disable(struct v4l2_subdev *sd)
483*4882a593Smuzhiyun {
484*4882a593Smuzhiyun 	i2c_wr8(sd, I2C_EN_REG, I2C_DISABLE);
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun 
tx_5v_power_present(struct v4l2_subdev * sd)487*4882a593Smuzhiyun static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun 	bool ret;
490*4882a593Smuzhiyun 	int val, i, cnt;
491*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun 	/* if not use plugin det gpio */
494*4882a593Smuzhiyun 	if (!lt7911uxc->plugin_det_gpio)
495*4882a593Smuzhiyun 		return true;
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 	cnt = 0;
498*4882a593Smuzhiyun 	for (i = 0; i < 5; i++) {
499*4882a593Smuzhiyun 		val = gpiod_get_value(lt7911uxc->plugin_det_gpio);
500*4882a593Smuzhiyun 		if (val > 0)
501*4882a593Smuzhiyun 			cnt++;
502*4882a593Smuzhiyun 		usleep_range(500, 600);
503*4882a593Smuzhiyun 	}
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	ret = (cnt >= 3) ? true : false;
506*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: %d\n", __func__, ret);
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	return ret;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun 
no_signal(struct v4l2_subdev * sd)511*4882a593Smuzhiyun static inline bool no_signal(struct v4l2_subdev *sd)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s no signal:%d\n", __func__,
516*4882a593Smuzhiyun 			lt7911uxc->nosignal);
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	return lt7911uxc->nosignal;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun 
audio_present(struct v4l2_subdev * sd)521*4882a593Smuzhiyun static inline bool audio_present(struct v4l2_subdev *sd)
522*4882a593Smuzhiyun {
523*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 	return lt7911uxc->is_audio_present;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun 
get_audio_sampling_rate(struct v4l2_subdev * sd)528*4882a593Smuzhiyun static int get_audio_sampling_rate(struct v4l2_subdev *sd)
529*4882a593Smuzhiyun {
530*4882a593Smuzhiyun 	static const int code_to_rate[] = {
531*4882a593Smuzhiyun 		44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
532*4882a593Smuzhiyun 		88200, 768000, 96000, 705600, 176400, 0, 192000, 0
533*4882a593Smuzhiyun 	};
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	if (no_signal(sd))
536*4882a593Smuzhiyun 		return 0;
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	return code_to_rate[2];
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun 
fps_calc(const struct v4l2_bt_timings * t)541*4882a593Smuzhiyun static inline unsigned int fps_calc(const struct v4l2_bt_timings *t)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun 	if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
544*4882a593Smuzhiyun 		return 0;
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	return DIV_ROUND_CLOSEST((unsigned int)t->pixelclock,
547*4882a593Smuzhiyun 			V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun 
lt7911uxc_rcv_supported_res(struct v4l2_subdev * sd,u32 width,u32 height)550*4882a593Smuzhiyun static bool lt7911uxc_rcv_supported_res(struct v4l2_subdev *sd, u32 width,
551*4882a593Smuzhiyun 		u32 height)
552*4882a593Smuzhiyun {
553*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
554*4882a593Smuzhiyun 	u32 i;
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	for (i = 0; i < lt7911uxc->cfg_num; i++) {
557*4882a593Smuzhiyun 		if ((lt7911uxc->support_modes[i].width == width) &&
558*4882a593Smuzhiyun 		    (lt7911uxc->support_modes[i].height == height)) {
559*4882a593Smuzhiyun 			break;
560*4882a593Smuzhiyun 		}
561*4882a593Smuzhiyun 	}
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 	if (i == lt7911uxc->cfg_num) {
564*4882a593Smuzhiyun 		v4l2_err(sd, "%s do not support res wxh: %dx%d\n", __func__,
565*4882a593Smuzhiyun 				width, height);
566*4882a593Smuzhiyun 		return false;
567*4882a593Smuzhiyun 	} else {
568*4882a593Smuzhiyun 		return true;
569*4882a593Smuzhiyun 	}
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun 
lt7911uxc_get_detected_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)572*4882a593Smuzhiyun static int lt7911uxc_get_detected_timings(struct v4l2_subdev *sd,
573*4882a593Smuzhiyun 				     struct v4l2_dv_timings *timings)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
576*4882a593Smuzhiyun 	struct v4l2_bt_timings *bt = &timings->bt;
577*4882a593Smuzhiyun 	u32 hact, vact, htotal, vtotal;
578*4882a593Smuzhiyun 	u32 pixel_clock, fps, halt_pix_clk;
579*4882a593Smuzhiyun 	u8 clk_h, clk_m, clk_l;
580*4882a593Smuzhiyun 	u8 val_h, val_l;
581*4882a593Smuzhiyun 	u64 byte_clk, mipi_clk, mipi_data_rate;
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 	memset(timings, 0, sizeof(struct v4l2_dv_timings));
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	clk_h = i2c_rd8(sd, PCLK_H);
586*4882a593Smuzhiyun 	clk_m = i2c_rd8(sd, PCLK_M);
587*4882a593Smuzhiyun 	clk_l = i2c_rd8(sd, PCLK_L);
588*4882a593Smuzhiyun 	halt_pix_clk = ((clk_h << 16) | (clk_m << 8) | clk_l);
589*4882a593Smuzhiyun 	pixel_clock = halt_pix_clk * 1000;
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	clk_h = i2c_rd8(sd, BYTE_PCLK_H);
592*4882a593Smuzhiyun 	clk_m = i2c_rd8(sd, BYTE_PCLK_M);
593*4882a593Smuzhiyun 	clk_l = i2c_rd8(sd, BYTE_PCLK_L);
594*4882a593Smuzhiyun 	byte_clk = ((clk_h << 16) | (clk_m << 8) | clk_l) * 1000;
595*4882a593Smuzhiyun 	mipi_clk = byte_clk * 4;
596*4882a593Smuzhiyun 	mipi_data_rate = byte_clk * 8;
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 	val_h = i2c_rd8(sd, HTOTAL_H);
599*4882a593Smuzhiyun 	val_l = i2c_rd8(sd, HTOTAL_L);
600*4882a593Smuzhiyun 	htotal = ((val_h << 8) | val_l);
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	val_h = i2c_rd8(sd, VTOTAL_H);
603*4882a593Smuzhiyun 	val_l = i2c_rd8(sd, VTOTAL_L);
604*4882a593Smuzhiyun 	vtotal = (val_h << 8) | val_l;
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	val_h = i2c_rd8(sd, HACT_H);
607*4882a593Smuzhiyun 	val_l = i2c_rd8(sd, HACT_L);
608*4882a593Smuzhiyun 	hact = ((val_h << 8) | val_l);
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	val_h = i2c_rd8(sd, VACT_H);
611*4882a593Smuzhiyun 	val_l = i2c_rd8(sd, VACT_L);
612*4882a593Smuzhiyun 	vact = (val_h << 8) | val_l;
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	lt7911uxc->nosignal = false;
615*4882a593Smuzhiyun 	lt7911uxc->is_audio_present = true;
616*4882a593Smuzhiyun 	timings->type = V4L2_DV_BT_656_1120;
617*4882a593Smuzhiyun 	bt->interlaced = V4L2_DV_PROGRESSIVE;
618*4882a593Smuzhiyun 	bt->width = hact;
619*4882a593Smuzhiyun 	bt->height = vact;
620*4882a593Smuzhiyun 	bt->pixelclock = pixel_clock;
621*4882a593Smuzhiyun 	fps = pixel_clock / (htotal * vtotal);
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	if (!lt7911uxc_rcv_supported_res(sd, hact, vact)) {
624*4882a593Smuzhiyun 		lt7911uxc->nosignal = true;
625*4882a593Smuzhiyun 		v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__);
626*4882a593Smuzhiyun 		return -EINVAL;
627*4882a593Smuzhiyun 	}
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 	v4l2_info(sd, "act:%dx%d, total:%dx%d, pixclk:%d, fps:%d\n",
630*4882a593Smuzhiyun 			hact, vact, htotal, vtotal, pixel_clock, fps);
631*4882a593Smuzhiyun 	v4l2_info(sd, "byte_clk:%llu, mipi_clk:%llu, mipi_data_rate:%llu\n",
632*4882a593Smuzhiyun 			byte_clk, mipi_clk, mipi_data_rate);
633*4882a593Smuzhiyun 	v4l2_info(sd, "inerlaced:%d\n", bt->interlaced);
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 	return 0;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun 
lt7911uxc_delayed_work_hotplug(struct work_struct * work)638*4882a593Smuzhiyun static void lt7911uxc_delayed_work_hotplug(struct work_struct *work)
639*4882a593Smuzhiyun {
640*4882a593Smuzhiyun 	struct delayed_work *dwork = to_delayed_work(work);
641*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = container_of(dwork,
642*4882a593Smuzhiyun 			struct lt7911uxc, delayed_work_hotplug);
643*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt7911uxc->sd;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	lt7911uxc_s_ctrl_detect_tx_5v(sd);
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun 
lt7911uxc_s_ctrl_detect_event(struct v4l2_subdev * sd)648*4882a593Smuzhiyun static void lt7911uxc_s_ctrl_detect_event(struct v4l2_subdev *sd)
649*4882a593Smuzhiyun {
650*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
651*4882a593Smuzhiyun 	u8 val;
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	val = i2c_rd8(sd, 0xe084);
654*4882a593Smuzhiyun 	if (val == 0x01)
655*4882a593Smuzhiyun 		v4l2_ctrl_s_ctrl(lt7911uxc->detect_tx_5v_ctrl, 1);
656*4882a593Smuzhiyun 	else if (val == 0x00)
657*4882a593Smuzhiyun 		v4l2_ctrl_s_ctrl(lt7911uxc->detect_tx_5v_ctrl, 0);
658*4882a593Smuzhiyun }
659*4882a593Smuzhiyun 
lt7911uxc_delayed_work_res_change(struct work_struct * work)660*4882a593Smuzhiyun static void lt7911uxc_delayed_work_res_change(struct work_struct *work)
661*4882a593Smuzhiyun {
662*4882a593Smuzhiyun 	struct delayed_work *dwork = to_delayed_work(work);
663*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = container_of(dwork,
664*4882a593Smuzhiyun 			struct lt7911uxc, delayed_work_res_change);
665*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt7911uxc->sd;
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	lt7911uxc_s_ctrl_detect_event(sd);
668*4882a593Smuzhiyun 	lt7911uxc_format_change(sd);
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun 
lt7911uxc_s_ctrl_detect_tx_5v(struct v4l2_subdev * sd)671*4882a593Smuzhiyun static int lt7911uxc_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
672*4882a593Smuzhiyun {
673*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	return v4l2_ctrl_s_ctrl(lt7911uxc->detect_tx_5v_ctrl,
676*4882a593Smuzhiyun 			tx_5v_power_present(sd));
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun 
lt7911uxc_s_ctrl_audio_sampling_rate(struct v4l2_subdev * sd)679*4882a593Smuzhiyun static int lt7911uxc_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	return v4l2_ctrl_s_ctrl(lt7911uxc->audio_sampling_rate_ctrl,
684*4882a593Smuzhiyun 			get_audio_sampling_rate(sd));
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun 
lt7911uxc_s_ctrl_audio_present(struct v4l2_subdev * sd)687*4882a593Smuzhiyun static int lt7911uxc_s_ctrl_audio_present(struct v4l2_subdev *sd)
688*4882a593Smuzhiyun {
689*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun 	return v4l2_ctrl_s_ctrl(lt7911uxc->audio_present_ctrl,
692*4882a593Smuzhiyun 			audio_present(sd));
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun 
lt7911uxc_update_controls(struct v4l2_subdev * sd)695*4882a593Smuzhiyun static int lt7911uxc_update_controls(struct v4l2_subdev *sd)
696*4882a593Smuzhiyun {
697*4882a593Smuzhiyun 	int ret = 0;
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 	ret |= lt7911uxc_s_ctrl_detect_tx_5v(sd);
700*4882a593Smuzhiyun 	ret |= lt7911uxc_s_ctrl_audio_sampling_rate(sd);
701*4882a593Smuzhiyun 	ret |= lt7911uxc_s_ctrl_audio_present(sd);
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	return ret;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun 
lt7911uxc_cphy_timing_config(struct v4l2_subdev * sd)706*4882a593Smuzhiyun static void lt7911uxc_cphy_timing_config(struct v4l2_subdev *sd)
707*4882a593Smuzhiyun {
708*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
709*4882a593Smuzhiyun 
710*4882a593Smuzhiyun 	if (lt7911uxc->bus_cfg.bus_type == V4L2_MBUS_CSI2_CPHY) {
711*4882a593Smuzhiyun 		lt7911uxc_i2c_enable(sd);
712*4882a593Smuzhiyun 		while (i2c_rd8(sd, HS_RQST_PRE_REG) != 0x3c) {
713*4882a593Smuzhiyun 			i2c_wr8(sd, HS_RQST_PRE_REG, 0x3c);
714*4882a593Smuzhiyun 			usleep_range(500, 600);
715*4882a593Smuzhiyun 		}
716*4882a593Smuzhiyun 		// i2c_wr8(sd, HS_TRAIL, 0x0b);
717*4882a593Smuzhiyun 		lt7911uxc_i2c_disable(sd);
718*4882a593Smuzhiyun 	}
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s config timing succeed\n", __func__);
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun 
lt7911uxc_match_timings(const struct v4l2_dv_timings * t1,const struct v4l2_dv_timings * t2)723*4882a593Smuzhiyun static bool lt7911uxc_match_timings(const struct v4l2_dv_timings *t1,
724*4882a593Smuzhiyun 					const struct v4l2_dv_timings *t2)
725*4882a593Smuzhiyun {
726*4882a593Smuzhiyun 	if (t1->type != t2->type || t1->type != V4L2_DV_BT_656_1120)
727*4882a593Smuzhiyun 		return false;
728*4882a593Smuzhiyun 	if (t1->bt.width == t2->bt.width &&
729*4882a593Smuzhiyun 		t1->bt.height == t2->bt.height &&
730*4882a593Smuzhiyun 		t1->bt.interlaced == t2->bt.interlaced)
731*4882a593Smuzhiyun 		return true;
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	return false;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun 
enable_stream(struct v4l2_subdev * sd,bool enable)736*4882a593Smuzhiyun static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
737*4882a593Smuzhiyun {
738*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	lt7911uxc_cphy_timing_config(&lt7911uxc->sd);
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun 	if (enable)
743*4882a593Smuzhiyun 		i2c_wr8(&lt7911uxc->sd, STREAM_CTL, ENABLE_STREAM);
744*4882a593Smuzhiyun 	else
745*4882a593Smuzhiyun 		i2c_wr8(&lt7911uxc->sd, STREAM_CTL, DISABLE_STREAM);
746*4882a593Smuzhiyun 	msleep(50);
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd, "%s: %sable\n",
749*4882a593Smuzhiyun 			__func__, enable ? "en" : "dis");
750*4882a593Smuzhiyun }
751*4882a593Smuzhiyun 
lt7911uxc_get_reso_dist(const struct lt7911uxc_mode * mode,struct v4l2_dv_timings * timings)752*4882a593Smuzhiyun static int lt7911uxc_get_reso_dist(const struct lt7911uxc_mode *mode,
753*4882a593Smuzhiyun 				struct v4l2_dv_timings *timings)
754*4882a593Smuzhiyun {
755*4882a593Smuzhiyun 	struct v4l2_bt_timings *bt = &timings->bt;
756*4882a593Smuzhiyun 	u32 cur_fps, dist_fps;
757*4882a593Smuzhiyun 
758*4882a593Smuzhiyun 	cur_fps = fps_calc(bt);
759*4882a593Smuzhiyun 	dist_fps = DIV_ROUND_CLOSEST(mode->max_fps.denominator, mode->max_fps.numerator);
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun 	return abs(mode->width - bt->width) +
762*4882a593Smuzhiyun 		abs(mode->height - bt->height) + abs(dist_fps - cur_fps);
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun static const struct lt7911uxc_mode *
lt7911uxc_find_best_fit(struct lt7911uxc * lt7911uxc)766*4882a593Smuzhiyun lt7911uxc_find_best_fit(struct lt7911uxc *lt7911uxc)
767*4882a593Smuzhiyun {
768*4882a593Smuzhiyun 	int dist;
769*4882a593Smuzhiyun 	int cur_best_fit = 0;
770*4882a593Smuzhiyun 	int cur_best_fit_dist = -1;
771*4882a593Smuzhiyun 	unsigned int i;
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	for (i = 0; i < lt7911uxc->cfg_num; i++) {
774*4882a593Smuzhiyun 		dist = lt7911uxc_get_reso_dist(&lt7911uxc->support_modes[i], &lt7911uxc->timings);
775*4882a593Smuzhiyun 		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
776*4882a593Smuzhiyun 			cur_best_fit_dist = dist;
777*4882a593Smuzhiyun 			cur_best_fit = i;
778*4882a593Smuzhiyun 		}
779*4882a593Smuzhiyun 	}
780*4882a593Smuzhiyun 	dev_dbg(&lt7911uxc->i2c_client->dev,
781*4882a593Smuzhiyun 		"find current mode: support_mode[%d], %dx%d@%dfps\n",
782*4882a593Smuzhiyun 		cur_best_fit, lt7911uxc->support_modes[cur_best_fit].width,
783*4882a593Smuzhiyun 		lt7911uxc->support_modes[cur_best_fit].height,
784*4882a593Smuzhiyun 		DIV_ROUND_CLOSEST(lt7911uxc->support_modes[cur_best_fit].max_fps.denominator,
785*4882a593Smuzhiyun 		lt7911uxc->support_modes[cur_best_fit].max_fps.numerator));
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun 	return &lt7911uxc->support_modes[cur_best_fit];
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun 
lt7911uxc_print_dv_timings(struct v4l2_subdev * sd,const char * prefix)790*4882a593Smuzhiyun static void lt7911uxc_print_dv_timings(struct v4l2_subdev *sd, const char *prefix)
791*4882a593Smuzhiyun {
792*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
793*4882a593Smuzhiyun 	struct device *dev = &lt7911uxc->i2c_client->dev;
794*4882a593Smuzhiyun 	const struct v4l2_bt_timings *bt = &lt7911uxc->timings.bt;
795*4882a593Smuzhiyun 	const struct lt7911uxc_mode *mode;
796*4882a593Smuzhiyun 	u32 htot, vtot;
797*4882a593Smuzhiyun 	u32 fps;
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 	mode = lt7911uxc_find_best_fit(lt7911uxc);
800*4882a593Smuzhiyun 	lt7911uxc->cur_mode = mode;
801*4882a593Smuzhiyun 	htot = lt7911uxc->cur_mode->hts_def;
802*4882a593Smuzhiyun 	vtot = lt7911uxc->cur_mode->vts_def;
803*4882a593Smuzhiyun 	if (bt->interlaced)
804*4882a593Smuzhiyun 		vtot /= 2;
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun 	fps = (htot * vtot) > 0 ? div_u64((100 * (u64)bt->pixelclock),
807*4882a593Smuzhiyun 				(htot * vtot)) : 0;
808*4882a593Smuzhiyun 
809*4882a593Smuzhiyun 	if (prefix == NULL)
810*4882a593Smuzhiyun 		prefix = "";
811*4882a593Smuzhiyun 
812*4882a593Smuzhiyun 	dev_info(dev, "%s: %s%ux%u%s%u.%02u (%ux%u)\n", sd->name, prefix,
813*4882a593Smuzhiyun 		bt->width, bt->height, bt->interlaced ? "i" : "p",
814*4882a593Smuzhiyun 		fps / 100, fps % 100, htot, vtot);
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun 
lt7911uxc_format_change(struct v4l2_subdev * sd)817*4882a593Smuzhiyun static void lt7911uxc_format_change(struct v4l2_subdev *sd)
818*4882a593Smuzhiyun {
819*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
820*4882a593Smuzhiyun 	struct v4l2_dv_timings timings;
821*4882a593Smuzhiyun 	const struct v4l2_event lt7911uxc_ev_fmt = {
822*4882a593Smuzhiyun 		.type = V4L2_EVENT_SOURCE_CHANGE,
823*4882a593Smuzhiyun 		.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
824*4882a593Smuzhiyun 	};
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun 	if (lt7911uxc_get_detected_timings(sd, &timings)) {
827*4882a593Smuzhiyun 		enable_stream(sd, false);
828*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: No signal\n", __func__);
829*4882a593Smuzhiyun 	}
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun 	if (!lt7911uxc_match_timings(&lt7911uxc->timings, &timings)) {
832*4882a593Smuzhiyun 		enable_stream(sd, false);
833*4882a593Smuzhiyun 		/* automatically set timing rather than set by user */
834*4882a593Smuzhiyun 		lt7911uxc_s_dv_timings(sd, &timings);
835*4882a593Smuzhiyun 		lt7911uxc_print_dv_timings(sd,
836*4882a593Smuzhiyun 				"Format_change: New format: ");
837*4882a593Smuzhiyun 	}
838*4882a593Smuzhiyun 	if (sd->devnode)
839*4882a593Smuzhiyun 		v4l2_subdev_notify_event(sd, &lt7911uxc_ev_fmt);
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun 
lt7911uxc_isr(struct v4l2_subdev * sd,u32 status,bool * handled)842*4882a593Smuzhiyun static int lt7911uxc_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
843*4882a593Smuzhiyun {
844*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
845*4882a593Smuzhiyun 
846*4882a593Smuzhiyun 	schedule_delayed_work(&lt7911uxc->delayed_work_res_change, HZ / 20);
847*4882a593Smuzhiyun 	*handled = true;
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun 	return 0;
850*4882a593Smuzhiyun }
851*4882a593Smuzhiyun 
lt7911uxc_res_change_irq_handler(int irq,void * dev_id)852*4882a593Smuzhiyun static irqreturn_t lt7911uxc_res_change_irq_handler(int irq, void *dev_id)
853*4882a593Smuzhiyun {
854*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = dev_id;
855*4882a593Smuzhiyun 	bool handled;
856*4882a593Smuzhiyun 
857*4882a593Smuzhiyun 	lt7911uxc_isr(&lt7911uxc->sd, 0, &handled);
858*4882a593Smuzhiyun 
859*4882a593Smuzhiyun 	return handled ? IRQ_HANDLED : IRQ_NONE;
860*4882a593Smuzhiyun }
861*4882a593Smuzhiyun 
plugin_detect_irq_handler(int irq,void * dev_id)862*4882a593Smuzhiyun static irqreturn_t plugin_detect_irq_handler(int irq, void *dev_id)
863*4882a593Smuzhiyun {
864*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = dev_id;
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun 	/* control hpd output level after 25ms */
867*4882a593Smuzhiyun 	schedule_delayed_work(&lt7911uxc->delayed_work_hotplug,
868*4882a593Smuzhiyun 			HZ / 40);
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun 	return IRQ_HANDLED;
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun 
lt7911uxc_irq_poll_timer(struct timer_list * t)873*4882a593Smuzhiyun static void lt7911uxc_irq_poll_timer(struct timer_list *t)
874*4882a593Smuzhiyun {
875*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = from_timer(lt7911uxc, t, timer);
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	schedule_work(&lt7911uxc->work_i2c_poll);
878*4882a593Smuzhiyun 	mod_timer(&lt7911uxc->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS));
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun 
lt7911uxc_work_i2c_poll(struct work_struct * work)881*4882a593Smuzhiyun static void lt7911uxc_work_i2c_poll(struct work_struct *work)
882*4882a593Smuzhiyun {
883*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = container_of(work,
884*4882a593Smuzhiyun 			struct lt7911uxc, work_i2c_poll);
885*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt7911uxc->sd;
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun 	lt7911uxc_format_change(sd);
888*4882a593Smuzhiyun }
889*4882a593Smuzhiyun 
lt7911uxc_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)890*4882a593Smuzhiyun static int lt7911uxc_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
891*4882a593Smuzhiyun 				    struct v4l2_event_subscription *sub)
892*4882a593Smuzhiyun {
893*4882a593Smuzhiyun 	switch (sub->type) {
894*4882a593Smuzhiyun 	case V4L2_EVENT_SOURCE_CHANGE:
895*4882a593Smuzhiyun 		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
896*4882a593Smuzhiyun 	case V4L2_EVENT_CTRL:
897*4882a593Smuzhiyun 		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
898*4882a593Smuzhiyun 	default:
899*4882a593Smuzhiyun 		return -EINVAL;
900*4882a593Smuzhiyun 	}
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun 
lt7911uxc_g_input_status(struct v4l2_subdev * sd,u32 * status)903*4882a593Smuzhiyun static int lt7911uxc_g_input_status(struct v4l2_subdev *sd, u32 *status)
904*4882a593Smuzhiyun {
905*4882a593Smuzhiyun 	*status = 0;
906*4882a593Smuzhiyun 	*status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
907*4882a593Smuzhiyun 
908*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun 	return 0;
911*4882a593Smuzhiyun }
912*4882a593Smuzhiyun 
lt7911uxc_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)913*4882a593Smuzhiyun static int lt7911uxc_s_dv_timings(struct v4l2_subdev *sd,
914*4882a593Smuzhiyun 				 struct v4l2_dv_timings *timings)
915*4882a593Smuzhiyun {
916*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
917*4882a593Smuzhiyun 
918*4882a593Smuzhiyun 	if (!timings)
919*4882a593Smuzhiyun 		return -EINVAL;
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun 	if (debug)
922*4882a593Smuzhiyun 		v4l2_print_dv_timings(sd->name, "s_dv_timings: ",
923*4882a593Smuzhiyun 				timings, false);
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 	if (lt7911uxc_match_timings(&lt7911uxc->timings, timings)) {
926*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
927*4882a593Smuzhiyun 		return 0;
928*4882a593Smuzhiyun 	}
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun 	if (!v4l2_valid_dv_timings(timings,
931*4882a593Smuzhiyun 				&lt7911uxc_timings_cap, NULL, NULL)) {
932*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
933*4882a593Smuzhiyun 		return -ERANGE;
934*4882a593Smuzhiyun 	}
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun 	lt7911uxc->timings = *timings;
937*4882a593Smuzhiyun 
938*4882a593Smuzhiyun 	enable_stream(sd, false);
939*4882a593Smuzhiyun 
940*4882a593Smuzhiyun 	return 0;
941*4882a593Smuzhiyun }
942*4882a593Smuzhiyun 
lt7911uxc_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)943*4882a593Smuzhiyun static int lt7911uxc_g_dv_timings(struct v4l2_subdev *sd,
944*4882a593Smuzhiyun 				struct v4l2_dv_timings *timings)
945*4882a593Smuzhiyun {
946*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun 	*timings = lt7911uxc->timings;
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun 	return 0;
951*4882a593Smuzhiyun }
952*4882a593Smuzhiyun 
lt7911uxc_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)953*4882a593Smuzhiyun static int lt7911uxc_enum_dv_timings(struct v4l2_subdev *sd,
954*4882a593Smuzhiyun 				struct v4l2_enum_dv_timings *timings)
955*4882a593Smuzhiyun {
956*4882a593Smuzhiyun 	if (timings->pad != 0)
957*4882a593Smuzhiyun 		return -EINVAL;
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun 	return v4l2_enum_dv_timings_cap(timings,
960*4882a593Smuzhiyun 			&lt7911uxc_timings_cap, NULL, NULL);
961*4882a593Smuzhiyun }
962*4882a593Smuzhiyun 
lt7911uxc_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)963*4882a593Smuzhiyun static int lt7911uxc_query_dv_timings(struct v4l2_subdev *sd,
964*4882a593Smuzhiyun 				struct v4l2_dv_timings *timings)
965*4882a593Smuzhiyun {
966*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
967*4882a593Smuzhiyun 
968*4882a593Smuzhiyun 	*timings = lt7911uxc->timings;
969*4882a593Smuzhiyun 	if (debug)
970*4882a593Smuzhiyun 		v4l2_print_dv_timings(sd->name,
971*4882a593Smuzhiyun 				"query_dv_timings: ", timings, false);
972*4882a593Smuzhiyun 
973*4882a593Smuzhiyun 	if (!v4l2_valid_dv_timings(timings, &lt7911uxc_timings_cap, NULL,
974*4882a593Smuzhiyun 				NULL)) {
975*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: timings out of range\n",
976*4882a593Smuzhiyun 				__func__);
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun 		return -ERANGE;
979*4882a593Smuzhiyun 	}
980*4882a593Smuzhiyun 
981*4882a593Smuzhiyun 	return 0;
982*4882a593Smuzhiyun }
983*4882a593Smuzhiyun 
lt7911uxc_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)984*4882a593Smuzhiyun static int lt7911uxc_dv_timings_cap(struct v4l2_subdev *sd,
985*4882a593Smuzhiyun 				struct v4l2_dv_timings_cap *cap)
986*4882a593Smuzhiyun {
987*4882a593Smuzhiyun 	if (cap->pad != 0)
988*4882a593Smuzhiyun 		return -EINVAL;
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun 	*cap = lt7911uxc_timings_cap;
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 	return 0;
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun 
lt7911uxc_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)995*4882a593Smuzhiyun static int lt7911uxc_g_mbus_config(struct v4l2_subdev *sd,
996*4882a593Smuzhiyun 			unsigned int pad, struct v4l2_mbus_config *cfg)
997*4882a593Smuzhiyun {
998*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
999*4882a593Smuzhiyun 	u32 lane_num = lt7911uxc->bus_cfg.bus.mipi_csi2.num_data_lanes;
1000*4882a593Smuzhiyun 	u32 val = 0;
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 	val = 1 << (lane_num - 1) |
1003*4882a593Smuzhiyun 		V4L2_MBUS_CSI2_CHANNEL_0 |
1004*4882a593Smuzhiyun 		V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun 	cfg->type = lt7911uxc->bus_cfg.bus_type;
1007*4882a593Smuzhiyun 	cfg->flags = val;
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun 	return 0;
1010*4882a593Smuzhiyun }
1011*4882a593Smuzhiyun 
lt7911uxc_s_stream(struct v4l2_subdev * sd,int on)1012*4882a593Smuzhiyun static int lt7911uxc_s_stream(struct v4l2_subdev *sd, int on)
1013*4882a593Smuzhiyun {
1014*4882a593Smuzhiyun 	enable_stream(sd, on);
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	return 0;
1017*4882a593Smuzhiyun }
1018*4882a593Smuzhiyun 
lt7911uxc_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1019*4882a593Smuzhiyun static int lt7911uxc_enum_mbus_code(struct v4l2_subdev *sd,
1020*4882a593Smuzhiyun 			struct v4l2_subdev_pad_config *cfg,
1021*4882a593Smuzhiyun 			struct v4l2_subdev_mbus_code_enum *code)
1022*4882a593Smuzhiyun {
1023*4882a593Smuzhiyun 	switch (code->index) {
1024*4882a593Smuzhiyun 	case 0:
1025*4882a593Smuzhiyun 		code->code = LT7911UXC_MEDIA_BUS_FMT;
1026*4882a593Smuzhiyun 		break;
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun 	default:
1029*4882a593Smuzhiyun 		return -EINVAL;
1030*4882a593Smuzhiyun 	}
1031*4882a593Smuzhiyun 
1032*4882a593Smuzhiyun 	return 0;
1033*4882a593Smuzhiyun }
1034*4882a593Smuzhiyun 
lt7911uxc_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1035*4882a593Smuzhiyun static int lt7911uxc_enum_frame_sizes(struct v4l2_subdev *sd,
1036*4882a593Smuzhiyun 				   struct v4l2_subdev_pad_config *cfg,
1037*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_size_enum *fse)
1038*4882a593Smuzhiyun {
1039*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun 	if (fse->index >= lt7911uxc->cfg_num)
1042*4882a593Smuzhiyun 		return -EINVAL;
1043*4882a593Smuzhiyun 
1044*4882a593Smuzhiyun 	if (fse->code != LT7911UXC_MEDIA_BUS_FMT)
1045*4882a593Smuzhiyun 		return -EINVAL;
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	fse->min_width  = lt7911uxc->support_modes[fse->index].width;
1048*4882a593Smuzhiyun 	fse->max_width  = lt7911uxc->support_modes[fse->index].width;
1049*4882a593Smuzhiyun 	fse->max_height = lt7911uxc->support_modes[fse->index].height;
1050*4882a593Smuzhiyun 	fse->min_height = lt7911uxc->support_modes[fse->index].height;
1051*4882a593Smuzhiyun 
1052*4882a593Smuzhiyun 	return 0;
1053*4882a593Smuzhiyun }
1054*4882a593Smuzhiyun 
lt7911uxc_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1055*4882a593Smuzhiyun static int lt7911uxc_get_fmt(struct v4l2_subdev *sd,
1056*4882a593Smuzhiyun 			struct v4l2_subdev_pad_config *cfg,
1057*4882a593Smuzhiyun 			struct v4l2_subdev_format *format)
1058*4882a593Smuzhiyun {
1059*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1060*4882a593Smuzhiyun 	const struct lt7911uxc_mode *mode;
1061*4882a593Smuzhiyun 
1062*4882a593Smuzhiyun 	mutex_lock(&lt7911uxc->confctl_mutex);
1063*4882a593Smuzhiyun 	format->format.code = lt7911uxc->mbus_fmt_code;
1064*4882a593Smuzhiyun 	format->format.width = lt7911uxc->timings.bt.width;
1065*4882a593Smuzhiyun 	format->format.height = lt7911uxc->timings.bt.height;
1066*4882a593Smuzhiyun 	format->format.field =
1067*4882a593Smuzhiyun 		lt7911uxc->timings.bt.interlaced ?
1068*4882a593Smuzhiyun 		V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
1069*4882a593Smuzhiyun 	format->format.colorspace = V4L2_COLORSPACE_SRGB;
1070*4882a593Smuzhiyun 	mutex_unlock(&lt7911uxc->confctl_mutex);
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 	mode = lt7911uxc_find_best_fit(lt7911uxc);
1073*4882a593Smuzhiyun 	lt7911uxc->cur_mode = mode;
1074*4882a593Smuzhiyun 
1075*4882a593Smuzhiyun 	__v4l2_ctrl_s_ctrl_int64(lt7911uxc->pixel_rate,
1076*4882a593Smuzhiyun 				LT7911UXC_PIXEL_RATE);
1077*4882a593Smuzhiyun 	__v4l2_ctrl_s_ctrl(lt7911uxc->link_freq,
1078*4882a593Smuzhiyun 				mode->mipi_freq_idx);
1079*4882a593Smuzhiyun 
1080*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: mode->mipi_freq_idx(%d)",
1081*4882a593Smuzhiyun 		 __func__, mode->mipi_freq_idx);
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: fmt code:%d, w:%d, h:%d, field code:%d\n",
1084*4882a593Smuzhiyun 			__func__, format->format.code, format->format.width,
1085*4882a593Smuzhiyun 			format->format.height, format->format.field);
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun 	return 0;
1088*4882a593Smuzhiyun }
1089*4882a593Smuzhiyun 
lt7911uxc_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1090*4882a593Smuzhiyun static int lt7911uxc_enum_frame_interval(struct v4l2_subdev *sd,
1091*4882a593Smuzhiyun 				struct v4l2_subdev_pad_config *cfg,
1092*4882a593Smuzhiyun 				struct v4l2_subdev_frame_interval_enum *fie)
1093*4882a593Smuzhiyun {
1094*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1095*4882a593Smuzhiyun 
1096*4882a593Smuzhiyun 	if (fie->index >= lt7911uxc->cfg_num)
1097*4882a593Smuzhiyun 		return -EINVAL;
1098*4882a593Smuzhiyun 
1099*4882a593Smuzhiyun 	fie->code = LT7911UXC_MEDIA_BUS_FMT;
1100*4882a593Smuzhiyun 
1101*4882a593Smuzhiyun 	fie->width = lt7911uxc->support_modes[fie->index].width;
1102*4882a593Smuzhiyun 	fie->height = lt7911uxc->support_modes[fie->index].height;
1103*4882a593Smuzhiyun 	fie->interval = lt7911uxc->support_modes[fie->index].max_fps;
1104*4882a593Smuzhiyun 
1105*4882a593Smuzhiyun 	return 0;
1106*4882a593Smuzhiyun }
1107*4882a593Smuzhiyun 
lt7911uxc_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1108*4882a593Smuzhiyun static int lt7911uxc_set_fmt(struct v4l2_subdev *sd,
1109*4882a593Smuzhiyun 			struct v4l2_subdev_pad_config *cfg,
1110*4882a593Smuzhiyun 			struct v4l2_subdev_format *format)
1111*4882a593Smuzhiyun {
1112*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1113*4882a593Smuzhiyun 	const struct lt7911uxc_mode *mode;
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun 	/* is overwritten by get_fmt */
1116*4882a593Smuzhiyun 	u32 code = format->format.code;
1117*4882a593Smuzhiyun 	int ret = lt7911uxc_get_fmt(sd, cfg, format);
1118*4882a593Smuzhiyun 
1119*4882a593Smuzhiyun 	format->format.code = code;
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 	if (ret)
1122*4882a593Smuzhiyun 		return ret;
1123*4882a593Smuzhiyun 
1124*4882a593Smuzhiyun 	switch (code) {
1125*4882a593Smuzhiyun 	case LT7911UXC_MEDIA_BUS_FMT:
1126*4882a593Smuzhiyun 		break;
1127*4882a593Smuzhiyun 
1128*4882a593Smuzhiyun 	default:
1129*4882a593Smuzhiyun 		return -EINVAL;
1130*4882a593Smuzhiyun 	}
1131*4882a593Smuzhiyun 
1132*4882a593Smuzhiyun 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1133*4882a593Smuzhiyun 		return 0;
1134*4882a593Smuzhiyun 
1135*4882a593Smuzhiyun 	lt7911uxc->mbus_fmt_code = format->format.code;
1136*4882a593Smuzhiyun 	mode = lt7911uxc_find_best_fit(lt7911uxc);
1137*4882a593Smuzhiyun 	lt7911uxc->cur_mode = mode;
1138*4882a593Smuzhiyun 
1139*4882a593Smuzhiyun 	enable_stream(sd, false);
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	return 0;
1142*4882a593Smuzhiyun }
1143*4882a593Smuzhiyun 
lt7911uxc_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1144*4882a593Smuzhiyun static int lt7911uxc_g_frame_interval(struct v4l2_subdev *sd,
1145*4882a593Smuzhiyun 			struct v4l2_subdev_frame_interval *fi)
1146*4882a593Smuzhiyun {
1147*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1148*4882a593Smuzhiyun 	const struct lt7911uxc_mode *mode = lt7911uxc->cur_mode;
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun 	mutex_lock(&lt7911uxc->confctl_mutex);
1151*4882a593Smuzhiyun 	fi->interval = mode->max_fps;
1152*4882a593Smuzhiyun 	mutex_unlock(&lt7911uxc->confctl_mutex);
1153*4882a593Smuzhiyun 
1154*4882a593Smuzhiyun 	return 0;
1155*4882a593Smuzhiyun }
1156*4882a593Smuzhiyun 
lt7911uxc_get_module_inf(struct lt7911uxc * lt7911uxc,struct rkmodule_inf * inf)1157*4882a593Smuzhiyun static void lt7911uxc_get_module_inf(struct lt7911uxc *lt7911uxc,
1158*4882a593Smuzhiyun 				  struct rkmodule_inf *inf)
1159*4882a593Smuzhiyun {
1160*4882a593Smuzhiyun 	memset(inf, 0, sizeof(*inf));
1161*4882a593Smuzhiyun 	strscpy(inf->base.sensor, LT7911UXC_NAME, sizeof(inf->base.sensor));
1162*4882a593Smuzhiyun 	strscpy(inf->base.module, lt7911uxc->module_name, sizeof(inf->base.module));
1163*4882a593Smuzhiyun 	strscpy(inf->base.lens, lt7911uxc->len_name, sizeof(inf->base.lens));
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun 
lt7911uxc_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1166*4882a593Smuzhiyun static long lt7911uxc_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1167*4882a593Smuzhiyun {
1168*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1169*4882a593Smuzhiyun 	long ret = 0;
1170*4882a593Smuzhiyun 	struct rkmodule_csi_dphy_param *dphy_param;
1171*4882a593Smuzhiyun 
1172*4882a593Smuzhiyun 	switch (cmd) {
1173*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
1174*4882a593Smuzhiyun 		lt7911uxc_get_module_inf(lt7911uxc, (struct rkmodule_inf *)arg);
1175*4882a593Smuzhiyun 		break;
1176*4882a593Smuzhiyun 	case RKMODULE_GET_HDMI_MODE:
1177*4882a593Smuzhiyun 		*(int *)arg = RKMODULE_HDMIIN_MODE;
1178*4882a593Smuzhiyun 		break;
1179*4882a593Smuzhiyun 	case RKMODULE_SET_CSI_DPHY_PARAM:
1180*4882a593Smuzhiyun 		dphy_param = (struct rkmodule_csi_dphy_param *)arg;
1181*4882a593Smuzhiyun 		if (dphy_param->vendor == rk3588_dcphy_param.vendor)
1182*4882a593Smuzhiyun 			rk3588_dcphy_param = *dphy_param;
1183*4882a593Smuzhiyun 		dev_dbg(&lt7911uxc->i2c_client->dev,
1184*4882a593Smuzhiyun 			"sensor set dphy param\n");
1185*4882a593Smuzhiyun 		break;
1186*4882a593Smuzhiyun 	case RKMODULE_GET_CSI_DPHY_PARAM:
1187*4882a593Smuzhiyun 		dphy_param = (struct rkmodule_csi_dphy_param *)arg;
1188*4882a593Smuzhiyun 		if (dphy_param->vendor == rk3588_dcphy_param.vendor)
1189*4882a593Smuzhiyun 			*dphy_param = rk3588_dcphy_param;
1190*4882a593Smuzhiyun 		dev_dbg(&lt7911uxc->i2c_client->dev,
1191*4882a593Smuzhiyun 			"sensor get dphy param\n");
1192*4882a593Smuzhiyun 		break;
1193*4882a593Smuzhiyun 	default:
1194*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
1195*4882a593Smuzhiyun 		break;
1196*4882a593Smuzhiyun 	}
1197*4882a593Smuzhiyun 
1198*4882a593Smuzhiyun 	return ret;
1199*4882a593Smuzhiyun }
1200*4882a593Smuzhiyun 
lt7911uxc_s_power(struct v4l2_subdev * sd,int on)1201*4882a593Smuzhiyun static int lt7911uxc_s_power(struct v4l2_subdev *sd, int on)
1202*4882a593Smuzhiyun {
1203*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1204*4882a593Smuzhiyun 	int ret = 0;
1205*4882a593Smuzhiyun 
1206*4882a593Smuzhiyun 	mutex_lock(&lt7911uxc->confctl_mutex);
1207*4882a593Smuzhiyun 
1208*4882a593Smuzhiyun 	if (lt7911uxc->power_on == !!on)
1209*4882a593Smuzhiyun 		goto unlock_and_return;
1210*4882a593Smuzhiyun 
1211*4882a593Smuzhiyun 	if (on)
1212*4882a593Smuzhiyun 		lt7911uxc->power_on = true;
1213*4882a593Smuzhiyun 	else
1214*4882a593Smuzhiyun 		lt7911uxc->power_on = false;
1215*4882a593Smuzhiyun 
1216*4882a593Smuzhiyun unlock_and_return:
1217*4882a593Smuzhiyun 	mutex_unlock(&lt7911uxc->confctl_mutex);
1218*4882a593Smuzhiyun 
1219*4882a593Smuzhiyun 	return ret;
1220*4882a593Smuzhiyun }
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
lt7911uxc_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1223*4882a593Smuzhiyun static long lt7911uxc_compat_ioctl32(struct v4l2_subdev *sd,
1224*4882a593Smuzhiyun 				  unsigned int cmd, unsigned long arg)
1225*4882a593Smuzhiyun {
1226*4882a593Smuzhiyun 	void __user *up = compat_ptr(arg);
1227*4882a593Smuzhiyun 	struct rkmodule_inf *inf;
1228*4882a593Smuzhiyun 	long ret;
1229*4882a593Smuzhiyun 	int *seq;
1230*4882a593Smuzhiyun 	struct rkmodule_csi_dphy_param *dphy_param;
1231*4882a593Smuzhiyun 
1232*4882a593Smuzhiyun 	switch (cmd) {
1233*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
1234*4882a593Smuzhiyun 		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1235*4882a593Smuzhiyun 		if (!inf) {
1236*4882a593Smuzhiyun 			ret = -ENOMEM;
1237*4882a593Smuzhiyun 			return ret;
1238*4882a593Smuzhiyun 		}
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun 		ret = lt7911uxc_ioctl(sd, cmd, inf);
1241*4882a593Smuzhiyun 		if (!ret) {
1242*4882a593Smuzhiyun 			ret = copy_to_user(up, inf, sizeof(*inf));
1243*4882a593Smuzhiyun 			if (ret)
1244*4882a593Smuzhiyun 				ret = -EFAULT;
1245*4882a593Smuzhiyun 		}
1246*4882a593Smuzhiyun 		kfree(inf);
1247*4882a593Smuzhiyun 		break;
1248*4882a593Smuzhiyun 	case RKMODULE_GET_HDMI_MODE:
1249*4882a593Smuzhiyun 		seq = kzalloc(sizeof(*seq), GFP_KERNEL);
1250*4882a593Smuzhiyun 		if (!seq) {
1251*4882a593Smuzhiyun 			ret = -ENOMEM;
1252*4882a593Smuzhiyun 			return ret;
1253*4882a593Smuzhiyun 		}
1254*4882a593Smuzhiyun 
1255*4882a593Smuzhiyun 		ret = lt7911uxc_ioctl(sd, cmd, seq);
1256*4882a593Smuzhiyun 		if (!ret) {
1257*4882a593Smuzhiyun 			ret = copy_to_user(up, seq, sizeof(*seq));
1258*4882a593Smuzhiyun 			if (ret)
1259*4882a593Smuzhiyun 				ret = -EFAULT;
1260*4882a593Smuzhiyun 		}
1261*4882a593Smuzhiyun 		kfree(seq);
1262*4882a593Smuzhiyun 		break;
1263*4882a593Smuzhiyun 	case RKMODULE_SET_CSI_DPHY_PARAM:
1264*4882a593Smuzhiyun 		dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
1265*4882a593Smuzhiyun 		if (!dphy_param) {
1266*4882a593Smuzhiyun 			ret = -ENOMEM;
1267*4882a593Smuzhiyun 			return ret;
1268*4882a593Smuzhiyun 		}
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun 		ret = copy_from_user(dphy_param, up, sizeof(*dphy_param));
1271*4882a593Smuzhiyun 		if (!ret)
1272*4882a593Smuzhiyun 			ret = lt7911uxc_ioctl(sd, cmd, dphy_param);
1273*4882a593Smuzhiyun 		else
1274*4882a593Smuzhiyun 			ret = -EFAULT;
1275*4882a593Smuzhiyun 		kfree(dphy_param);
1276*4882a593Smuzhiyun 		break;
1277*4882a593Smuzhiyun 	case RKMODULE_GET_CSI_DPHY_PARAM:
1278*4882a593Smuzhiyun 		dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
1279*4882a593Smuzhiyun 		if (!dphy_param) {
1280*4882a593Smuzhiyun 			ret = -ENOMEM;
1281*4882a593Smuzhiyun 			return ret;
1282*4882a593Smuzhiyun 		}
1283*4882a593Smuzhiyun 
1284*4882a593Smuzhiyun 		ret = lt7911uxc_ioctl(sd, cmd, dphy_param);
1285*4882a593Smuzhiyun 		if (!ret) {
1286*4882a593Smuzhiyun 			ret = copy_to_user(up, dphy_param, sizeof(*dphy_param));
1287*4882a593Smuzhiyun 			if (ret)
1288*4882a593Smuzhiyun 				ret = -EFAULT;
1289*4882a593Smuzhiyun 		}
1290*4882a593Smuzhiyun 		kfree(dphy_param);
1291*4882a593Smuzhiyun 		break;
1292*4882a593Smuzhiyun 	default:
1293*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
1294*4882a593Smuzhiyun 		break;
1295*4882a593Smuzhiyun 	}
1296*4882a593Smuzhiyun 
1297*4882a593Smuzhiyun 	return ret;
1298*4882a593Smuzhiyun }
1299*4882a593Smuzhiyun #endif
1300*4882a593Smuzhiyun 
1301*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
lt7911uxc_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1302*4882a593Smuzhiyun static int lt7911uxc_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1303*4882a593Smuzhiyun {
1304*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1305*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *try_fmt =
1306*4882a593Smuzhiyun 				v4l2_subdev_get_try_format(sd, fh->pad, 0);
1307*4882a593Smuzhiyun 	const struct lt7911uxc_mode *def_mode = &lt7911uxc->support_modes[0];
1308*4882a593Smuzhiyun 
1309*4882a593Smuzhiyun 	mutex_lock(&lt7911uxc->confctl_mutex);
1310*4882a593Smuzhiyun 	/* Initialize try_fmt */
1311*4882a593Smuzhiyun 	try_fmt->width = def_mode->width;
1312*4882a593Smuzhiyun 	try_fmt->height = def_mode->height;
1313*4882a593Smuzhiyun 	try_fmt->code = LT7911UXC_MEDIA_BUS_FMT;
1314*4882a593Smuzhiyun 	try_fmt->field = V4L2_FIELD_NONE;
1315*4882a593Smuzhiyun 	mutex_unlock(&lt7911uxc->confctl_mutex);
1316*4882a593Smuzhiyun 
1317*4882a593Smuzhiyun 	return 0;
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun #endif
1320*4882a593Smuzhiyun 
1321*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1322*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops lt7911uxc_internal_ops = {
1323*4882a593Smuzhiyun 	.open = lt7911uxc_open,
1324*4882a593Smuzhiyun };
1325*4882a593Smuzhiyun #endif
1326*4882a593Smuzhiyun 
1327*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops lt7911uxc_core_ops = {
1328*4882a593Smuzhiyun 	.s_power = lt7911uxc_s_power,
1329*4882a593Smuzhiyun 	.interrupt_service_routine = lt7911uxc_isr,
1330*4882a593Smuzhiyun 	.subscribe_event = lt7911uxc_subscribe_event,
1331*4882a593Smuzhiyun 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
1332*4882a593Smuzhiyun 	.ioctl = lt7911uxc_ioctl,
1333*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1334*4882a593Smuzhiyun 	.compat_ioctl32 = lt7911uxc_compat_ioctl32,
1335*4882a593Smuzhiyun #endif
1336*4882a593Smuzhiyun };
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops lt7911uxc_video_ops = {
1339*4882a593Smuzhiyun 	.g_input_status = lt7911uxc_g_input_status,
1340*4882a593Smuzhiyun 	.s_dv_timings = lt7911uxc_s_dv_timings,
1341*4882a593Smuzhiyun 	.g_dv_timings = lt7911uxc_g_dv_timings,
1342*4882a593Smuzhiyun 	.query_dv_timings = lt7911uxc_query_dv_timings,
1343*4882a593Smuzhiyun 	.s_stream = lt7911uxc_s_stream,
1344*4882a593Smuzhiyun 	.g_frame_interval = lt7911uxc_g_frame_interval,
1345*4882a593Smuzhiyun };
1346*4882a593Smuzhiyun 
1347*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops lt7911uxc_pad_ops = {
1348*4882a593Smuzhiyun 	.enum_mbus_code = lt7911uxc_enum_mbus_code,
1349*4882a593Smuzhiyun 	.enum_frame_size = lt7911uxc_enum_frame_sizes,
1350*4882a593Smuzhiyun 	.enum_frame_interval = lt7911uxc_enum_frame_interval,
1351*4882a593Smuzhiyun 	.set_fmt = lt7911uxc_set_fmt,
1352*4882a593Smuzhiyun 	.get_fmt = lt7911uxc_get_fmt,
1353*4882a593Smuzhiyun 	.enum_dv_timings = lt7911uxc_enum_dv_timings,
1354*4882a593Smuzhiyun 	.dv_timings_cap = lt7911uxc_dv_timings_cap,
1355*4882a593Smuzhiyun 	.get_mbus_config = lt7911uxc_g_mbus_config,
1356*4882a593Smuzhiyun };
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun static const struct v4l2_subdev_ops lt7911uxc_ops = {
1359*4882a593Smuzhiyun 	.core = &lt7911uxc_core_ops,
1360*4882a593Smuzhiyun 	.video = &lt7911uxc_video_ops,
1361*4882a593Smuzhiyun 	.pad = &lt7911uxc_pad_ops,
1362*4882a593Smuzhiyun };
1363*4882a593Smuzhiyun 
1364*4882a593Smuzhiyun static const struct v4l2_ctrl_config lt7911uxc_ctrl_audio_sampling_rate = {
1365*4882a593Smuzhiyun 	.id = RK_V4L2_CID_AUDIO_SAMPLING_RATE,
1366*4882a593Smuzhiyun 	.name = "Audio sampling rate",
1367*4882a593Smuzhiyun 	.type = V4L2_CTRL_TYPE_INTEGER,
1368*4882a593Smuzhiyun 	.min = 0,
1369*4882a593Smuzhiyun 	.max = 768000,
1370*4882a593Smuzhiyun 	.step = 1,
1371*4882a593Smuzhiyun 	.def = 0,
1372*4882a593Smuzhiyun 	.flags = V4L2_CTRL_FLAG_READ_ONLY,
1373*4882a593Smuzhiyun };
1374*4882a593Smuzhiyun 
1375*4882a593Smuzhiyun static const struct v4l2_ctrl_config lt7911uxc_ctrl_audio_present = {
1376*4882a593Smuzhiyun 	.id = RK_V4L2_CID_AUDIO_PRESENT,
1377*4882a593Smuzhiyun 	.name = "Audio present",
1378*4882a593Smuzhiyun 	.type = V4L2_CTRL_TYPE_BOOLEAN,
1379*4882a593Smuzhiyun 	.min = 0,
1380*4882a593Smuzhiyun 	.max = 1,
1381*4882a593Smuzhiyun 	.step = 1,
1382*4882a593Smuzhiyun 	.def = 0,
1383*4882a593Smuzhiyun 	.flags = V4L2_CTRL_FLAG_READ_ONLY,
1384*4882a593Smuzhiyun };
1385*4882a593Smuzhiyun 
lt7911uxc_init_v4l2_ctrls(struct lt7911uxc * lt7911uxc)1386*4882a593Smuzhiyun static int lt7911uxc_init_v4l2_ctrls(struct lt7911uxc *lt7911uxc)
1387*4882a593Smuzhiyun {
1388*4882a593Smuzhiyun 	const struct lt7911uxc_mode *mode;
1389*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
1390*4882a593Smuzhiyun 	int ret;
1391*4882a593Smuzhiyun 
1392*4882a593Smuzhiyun 	mode = lt7911uxc->cur_mode;
1393*4882a593Smuzhiyun 	sd = &lt7911uxc->sd;
1394*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_init(&lt7911uxc->hdl, 5);
1395*4882a593Smuzhiyun 	if (ret)
1396*4882a593Smuzhiyun 		return ret;
1397*4882a593Smuzhiyun 
1398*4882a593Smuzhiyun 	lt7911uxc->link_freq = v4l2_ctrl_new_int_menu(&lt7911uxc->hdl, NULL,
1399*4882a593Smuzhiyun 			V4L2_CID_LINK_FREQ,
1400*4882a593Smuzhiyun 			ARRAY_SIZE(link_freq_menu_items) - 1, 0,
1401*4882a593Smuzhiyun 			link_freq_menu_items);
1402*4882a593Smuzhiyun 	lt7911uxc->pixel_rate = v4l2_ctrl_new_std(&lt7911uxc->hdl, NULL,
1403*4882a593Smuzhiyun 			V4L2_CID_PIXEL_RATE,
1404*4882a593Smuzhiyun 			0, LT7911UXC_PIXEL_RATE, 1, LT7911UXC_PIXEL_RATE);
1405*4882a593Smuzhiyun 
1406*4882a593Smuzhiyun 	lt7911uxc->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&lt7911uxc->hdl,
1407*4882a593Smuzhiyun 			NULL, V4L2_CID_DV_RX_POWER_PRESENT,
1408*4882a593Smuzhiyun 			0, 1, 0, 0);
1409*4882a593Smuzhiyun 
1410*4882a593Smuzhiyun 	lt7911uxc->audio_sampling_rate_ctrl =
1411*4882a593Smuzhiyun 		v4l2_ctrl_new_custom(&lt7911uxc->hdl,
1412*4882a593Smuzhiyun 				&lt7911uxc_ctrl_audio_sampling_rate, NULL);
1413*4882a593Smuzhiyun 	lt7911uxc->audio_present_ctrl = v4l2_ctrl_new_custom(&lt7911uxc->hdl,
1414*4882a593Smuzhiyun 			&lt7911uxc_ctrl_audio_present, NULL);
1415*4882a593Smuzhiyun 
1416*4882a593Smuzhiyun 	sd->ctrl_handler = &lt7911uxc->hdl;
1417*4882a593Smuzhiyun 	if (lt7911uxc->hdl.error) {
1418*4882a593Smuzhiyun 		ret = lt7911uxc->hdl.error;
1419*4882a593Smuzhiyun 		v4l2_err(sd, "cfg v4l2 ctrls failed! ret:%d\n", ret);
1420*4882a593Smuzhiyun 		return ret;
1421*4882a593Smuzhiyun 	}
1422*4882a593Smuzhiyun 
1423*4882a593Smuzhiyun 	__v4l2_ctrl_s_ctrl(lt7911uxc->link_freq, mode->mipi_freq_idx);
1424*4882a593Smuzhiyun 	__v4l2_ctrl_s_ctrl_int64(lt7911uxc->pixel_rate, LT7911UXC_PIXEL_RATE);
1425*4882a593Smuzhiyun 
1426*4882a593Smuzhiyun 	if (lt7911uxc_update_controls(sd)) {
1427*4882a593Smuzhiyun 		ret = -ENODEV;
1428*4882a593Smuzhiyun 		v4l2_err(sd, "update v4l2 ctrls failed! ret:%d\n", ret);
1429*4882a593Smuzhiyun 		return ret;
1430*4882a593Smuzhiyun 	}
1431*4882a593Smuzhiyun 
1432*4882a593Smuzhiyun 	return 0;
1433*4882a593Smuzhiyun }
1434*4882a593Smuzhiyun 
1435*4882a593Smuzhiyun #ifdef CONFIG_OF
lt7911uxc_probe_of(struct lt7911uxc * lt7911uxc)1436*4882a593Smuzhiyun static int lt7911uxc_probe_of(struct lt7911uxc *lt7911uxc)
1437*4882a593Smuzhiyun {
1438*4882a593Smuzhiyun 	struct device *dev = &lt7911uxc->i2c_client->dev;
1439*4882a593Smuzhiyun 	struct device_node *node = dev->of_node;
1440*4882a593Smuzhiyun 	struct device_node *ep;
1441*4882a593Smuzhiyun 	int ret;
1442*4882a593Smuzhiyun 
1443*4882a593Smuzhiyun 	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1444*4882a593Smuzhiyun 			&lt7911uxc->module_index);
1445*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1446*4882a593Smuzhiyun 			&lt7911uxc->module_facing);
1447*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1448*4882a593Smuzhiyun 			&lt7911uxc->module_name);
1449*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1450*4882a593Smuzhiyun 			&lt7911uxc->len_name);
1451*4882a593Smuzhiyun 	if (ret) {
1452*4882a593Smuzhiyun 		dev_err(dev, "could not get module information!\n");
1453*4882a593Smuzhiyun 		return -EINVAL;
1454*4882a593Smuzhiyun 	}
1455*4882a593Smuzhiyun 
1456*4882a593Smuzhiyun 	lt7911uxc->power_gpio = devm_gpiod_get_optional(dev, "power",
1457*4882a593Smuzhiyun 			GPIOD_OUT_LOW);
1458*4882a593Smuzhiyun 	if (IS_ERR(lt7911uxc->power_gpio)) {
1459*4882a593Smuzhiyun 		dev_err(dev, "failed to get power gpio\n");
1460*4882a593Smuzhiyun 		ret = PTR_ERR(lt7911uxc->power_gpio);
1461*4882a593Smuzhiyun 		return ret;
1462*4882a593Smuzhiyun 	}
1463*4882a593Smuzhiyun 
1464*4882a593Smuzhiyun 	lt7911uxc->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1465*4882a593Smuzhiyun 			GPIOD_OUT_HIGH);
1466*4882a593Smuzhiyun 	if (IS_ERR(lt7911uxc->reset_gpio)) {
1467*4882a593Smuzhiyun 		dev_err(dev, "failed to get reset gpio\n");
1468*4882a593Smuzhiyun 		ret = PTR_ERR(lt7911uxc->reset_gpio);
1469*4882a593Smuzhiyun 		return ret;
1470*4882a593Smuzhiyun 	}
1471*4882a593Smuzhiyun 
1472*4882a593Smuzhiyun 	lt7911uxc->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det",
1473*4882a593Smuzhiyun 			GPIOD_IN);
1474*4882a593Smuzhiyun 	if (IS_ERR(lt7911uxc->plugin_det_gpio)) {
1475*4882a593Smuzhiyun 		dev_err(dev, "failed to get plugin det gpio\n");
1476*4882a593Smuzhiyun 		ret = PTR_ERR(lt7911uxc->plugin_det_gpio);
1477*4882a593Smuzhiyun 		return ret;
1478*4882a593Smuzhiyun 	}
1479*4882a593Smuzhiyun 
1480*4882a593Smuzhiyun 	ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1481*4882a593Smuzhiyun 	if (!ep) {
1482*4882a593Smuzhiyun 		dev_err(dev, "missing endpoint node\n");
1483*4882a593Smuzhiyun 		return -EINVAL;
1484*4882a593Smuzhiyun 	}
1485*4882a593Smuzhiyun 
1486*4882a593Smuzhiyun 	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep),
1487*4882a593Smuzhiyun 					&lt7911uxc->bus_cfg);
1488*4882a593Smuzhiyun 	if (ret) {
1489*4882a593Smuzhiyun 		dev_err(dev, "failed to parse endpoint\n");
1490*4882a593Smuzhiyun 		goto put_node;
1491*4882a593Smuzhiyun 	}
1492*4882a593Smuzhiyun 
1493*4882a593Smuzhiyun 	if (lt7911uxc->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY) {
1494*4882a593Smuzhiyun 		lt7911uxc->support_modes = supported_modes_dphy;
1495*4882a593Smuzhiyun 		lt7911uxc->cfg_num = ARRAY_SIZE(supported_modes_dphy);
1496*4882a593Smuzhiyun 	} else {
1497*4882a593Smuzhiyun 		lt7911uxc->support_modes = supported_modes_cphy;
1498*4882a593Smuzhiyun 		lt7911uxc->cfg_num = ARRAY_SIZE(supported_modes_cphy);
1499*4882a593Smuzhiyun 	}
1500*4882a593Smuzhiyun 
1501*4882a593Smuzhiyun 	lt7911uxc->xvclk = devm_clk_get(dev, "xvclk");
1502*4882a593Smuzhiyun 	if (IS_ERR(lt7911uxc->xvclk)) {
1503*4882a593Smuzhiyun 		dev_err(dev, "failed to get xvclk\n");
1504*4882a593Smuzhiyun 		ret = -EINVAL;
1505*4882a593Smuzhiyun 		goto put_node;
1506*4882a593Smuzhiyun 	}
1507*4882a593Smuzhiyun 
1508*4882a593Smuzhiyun 	ret = clk_prepare_enable(lt7911uxc->xvclk);
1509*4882a593Smuzhiyun 	if (ret) {
1510*4882a593Smuzhiyun 		dev_err(dev, "Failed! to enable xvclk\n");
1511*4882a593Smuzhiyun 		goto put_node;
1512*4882a593Smuzhiyun 	}
1513*4882a593Smuzhiyun 
1514*4882a593Smuzhiyun 	lt7911uxc->enable_hdcp = false;
1515*4882a593Smuzhiyun 
1516*4882a593Smuzhiyun 	ret = 0;
1517*4882a593Smuzhiyun 
1518*4882a593Smuzhiyun put_node:
1519*4882a593Smuzhiyun 	of_node_put(ep);
1520*4882a593Smuzhiyun 	return ret;
1521*4882a593Smuzhiyun }
1522*4882a593Smuzhiyun #else
lt7911uxc_probe_of(struct lt7911uxc * state)1523*4882a593Smuzhiyun static inline int lt7911uxc_probe_of(struct lt7911uxc *state)
1524*4882a593Smuzhiyun {
1525*4882a593Smuzhiyun 	return -ENODEV;
1526*4882a593Smuzhiyun }
1527*4882a593Smuzhiyun #endif
1528*4882a593Smuzhiyun 
__lt7911uxc_power_on(struct lt7911uxc * lt7911uxc)1529*4882a593Smuzhiyun static int __lt7911uxc_power_on(struct lt7911uxc *lt7911uxc)
1530*4882a593Smuzhiyun {
1531*4882a593Smuzhiyun 	struct device *dev = &lt7911uxc->i2c_client->dev;
1532*4882a593Smuzhiyun 
1533*4882a593Smuzhiyun 	dev_info(dev, "lt7911uxc power on\n");
1534*4882a593Smuzhiyun 	gpiod_set_value(lt7911uxc->reset_gpio, 1);
1535*4882a593Smuzhiyun 	usleep_range(20000, 25000);
1536*4882a593Smuzhiyun 	gpiod_set_value(lt7911uxc->power_gpio, 1);
1537*4882a593Smuzhiyun 	//delay 20ms before reset
1538*4882a593Smuzhiyun 	usleep_range(25000, 30000);
1539*4882a593Smuzhiyun 	gpiod_set_value(lt7911uxc->reset_gpio, 0);
1540*4882a593Smuzhiyun 	usleep_range(25000, 30000);
1541*4882a593Smuzhiyun 
1542*4882a593Smuzhiyun 	return 0;
1543*4882a593Smuzhiyun }
1544*4882a593Smuzhiyun 
__lt7911uxc_power_off(struct lt7911uxc * lt7911uxc)1545*4882a593Smuzhiyun static void __lt7911uxc_power_off(struct lt7911uxc *lt7911uxc)
1546*4882a593Smuzhiyun {
1547*4882a593Smuzhiyun 	struct device *dev = &lt7911uxc->i2c_client->dev;
1548*4882a593Smuzhiyun 
1549*4882a593Smuzhiyun 	dev_info(dev, "lt7911uxc power off\n");
1550*4882a593Smuzhiyun 
1551*4882a593Smuzhiyun 	if (!IS_ERR(lt7911uxc->reset_gpio))
1552*4882a593Smuzhiyun 		gpiod_set_value(lt7911uxc->reset_gpio, 1);
1553*4882a593Smuzhiyun 
1554*4882a593Smuzhiyun 	if (!IS_ERR(lt7911uxc->power_gpio))
1555*4882a593Smuzhiyun 		gpiod_set_value(lt7911uxc->power_gpio, 0);
1556*4882a593Smuzhiyun }
1557*4882a593Smuzhiyun 
lt7911uxc_resume(struct device * dev)1558*4882a593Smuzhiyun static int lt7911uxc_resume(struct device *dev)
1559*4882a593Smuzhiyun {
1560*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1561*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1562*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1563*4882a593Smuzhiyun 
1564*4882a593Smuzhiyun 	return __lt7911uxc_power_on(lt7911uxc);
1565*4882a593Smuzhiyun }
1566*4882a593Smuzhiyun 
lt7911uxc_suspend(struct device * dev)1567*4882a593Smuzhiyun static int lt7911uxc_suspend(struct device *dev)
1568*4882a593Smuzhiyun {
1569*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1570*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1571*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1572*4882a593Smuzhiyun 
1573*4882a593Smuzhiyun 	__lt7911uxc_power_off(lt7911uxc);
1574*4882a593Smuzhiyun 
1575*4882a593Smuzhiyun 	return 0;
1576*4882a593Smuzhiyun }
1577*4882a593Smuzhiyun 
1578*4882a593Smuzhiyun static const struct dev_pm_ops lt7911uxc_pm_ops = {
1579*4882a593Smuzhiyun 	.suspend = lt7911uxc_suspend,
1580*4882a593Smuzhiyun 	.resume = lt7911uxc_resume,
1581*4882a593Smuzhiyun };
1582*4882a593Smuzhiyun 
lt7911uxc_check_chip_id(struct lt7911uxc * lt7911uxc)1583*4882a593Smuzhiyun static int lt7911uxc_check_chip_id(struct lt7911uxc *lt7911uxc)
1584*4882a593Smuzhiyun {
1585*4882a593Smuzhiyun 	struct device *dev = &lt7911uxc->i2c_client->dev;
1586*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt7911uxc->sd;
1587*4882a593Smuzhiyun 	u8 id_h, id_l;
1588*4882a593Smuzhiyun 	u32 chipid;
1589*4882a593Smuzhiyun 	int ret = 0;
1590*4882a593Smuzhiyun 
1591*4882a593Smuzhiyun 	lt7911uxc_i2c_enable(sd);
1592*4882a593Smuzhiyun 	id_l  = i2c_rd8(sd, CHIPID_REGL);
1593*4882a593Smuzhiyun 	id_h  = i2c_rd8(sd, CHIPID_REGH);
1594*4882a593Smuzhiyun 	lt7911uxc_i2c_disable(sd);
1595*4882a593Smuzhiyun 
1596*4882a593Smuzhiyun 	chipid = (id_h << 8) | id_l;
1597*4882a593Smuzhiyun 	if (chipid != LT7911UXC_CHIPID) {
1598*4882a593Smuzhiyun 		dev_err(dev, "chipid err, read:%#x, expect:%#x\n",
1599*4882a593Smuzhiyun 				chipid, LT7911UXC_CHIPID);
1600*4882a593Smuzhiyun 		return -EINVAL;
1601*4882a593Smuzhiyun 	}
1602*4882a593Smuzhiyun 	dev_info(dev, "check chipid ok, id:%#x", chipid);
1603*4882a593Smuzhiyun 
1604*4882a593Smuzhiyun 	return ret;
1605*4882a593Smuzhiyun }
1606*4882a593Smuzhiyun 
lt7911uxc_probe(struct i2c_client * client,const struct i2c_device_id * id)1607*4882a593Smuzhiyun static int lt7911uxc_probe(struct i2c_client *client,
1608*4882a593Smuzhiyun 			  const struct i2c_device_id *id)
1609*4882a593Smuzhiyun {
1610*4882a593Smuzhiyun 	struct v4l2_dv_timings default_timing =
1611*4882a593Smuzhiyun 				V4L2_DV_BT_CEA_640X480P59_94;
1612*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc;
1613*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
1614*4882a593Smuzhiyun 	struct device *dev = &client->dev;
1615*4882a593Smuzhiyun 	char facing[2];
1616*4882a593Smuzhiyun 	int err;
1617*4882a593Smuzhiyun 
1618*4882a593Smuzhiyun 	dev_info(dev, "driver version: %02x.%02x.%02x",
1619*4882a593Smuzhiyun 		DRIVER_VERSION >> 16,
1620*4882a593Smuzhiyun 		(DRIVER_VERSION & 0xff00) >> 8,
1621*4882a593Smuzhiyun 		DRIVER_VERSION & 0x00ff);
1622*4882a593Smuzhiyun 
1623*4882a593Smuzhiyun 	lt7911uxc = devm_kzalloc(dev, sizeof(struct lt7911uxc), GFP_KERNEL);
1624*4882a593Smuzhiyun 	if (!lt7911uxc)
1625*4882a593Smuzhiyun 		return -ENOMEM;
1626*4882a593Smuzhiyun 
1627*4882a593Smuzhiyun 	sd = &lt7911uxc->sd;
1628*4882a593Smuzhiyun 	lt7911uxc->i2c_client = client;
1629*4882a593Smuzhiyun 	lt7911uxc->mbus_fmt_code = LT7911UXC_MEDIA_BUS_FMT;
1630*4882a593Smuzhiyun 
1631*4882a593Smuzhiyun 	err = lt7911uxc_probe_of(lt7911uxc);
1632*4882a593Smuzhiyun 	if (err) {
1633*4882a593Smuzhiyun 		v4l2_err(sd, "lt7911uxc_parse_of failed! err:%d\n", err);
1634*4882a593Smuzhiyun 		return err;
1635*4882a593Smuzhiyun 	}
1636*4882a593Smuzhiyun 
1637*4882a593Smuzhiyun 	lt7911uxc->timings = default_timing;
1638*4882a593Smuzhiyun 	lt7911uxc->cur_mode = &lt7911uxc->support_modes[0];
1639*4882a593Smuzhiyun 
1640*4882a593Smuzhiyun 	__lt7911uxc_power_on(lt7911uxc);
1641*4882a593Smuzhiyun 	err = lt7911uxc_check_chip_id(lt7911uxc);
1642*4882a593Smuzhiyun 	if (err < 0)
1643*4882a593Smuzhiyun 		return err;
1644*4882a593Smuzhiyun 
1645*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&lt7911uxc->delayed_work_hotplug,
1646*4882a593Smuzhiyun 			lt7911uxc_delayed_work_hotplug);
1647*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&lt7911uxc->delayed_work_res_change,
1648*4882a593Smuzhiyun 			lt7911uxc_delayed_work_res_change);
1649*4882a593Smuzhiyun 
1650*4882a593Smuzhiyun 	if (lt7911uxc->i2c_client->irq) {
1651*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "cfg lt7911uxc irq!\n");
1652*4882a593Smuzhiyun 		err = devm_request_threaded_irq(dev,
1653*4882a593Smuzhiyun 				lt7911uxc->i2c_client->irq,
1654*4882a593Smuzhiyun 				NULL, lt7911uxc_res_change_irq_handler,
1655*4882a593Smuzhiyun 				IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1656*4882a593Smuzhiyun 				"lt7911uxc", lt7911uxc);
1657*4882a593Smuzhiyun 		if (err) {
1658*4882a593Smuzhiyun 			v4l2_err(sd, "request irq failed! err:%d\n", err);
1659*4882a593Smuzhiyun 			goto err_work_queues;
1660*4882a593Smuzhiyun 		}
1661*4882a593Smuzhiyun 	} else {
1662*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "no irq, cfg poll!\n");
1663*4882a593Smuzhiyun 		INIT_WORK(&lt7911uxc->work_i2c_poll, lt7911uxc_work_i2c_poll);
1664*4882a593Smuzhiyun 		timer_setup(&lt7911uxc->timer, lt7911uxc_irq_poll_timer, 0);
1665*4882a593Smuzhiyun 		lt7911uxc->timer.expires = jiffies +
1666*4882a593Smuzhiyun 				       msecs_to_jiffies(POLL_INTERVAL_MS);
1667*4882a593Smuzhiyun 		add_timer(&lt7911uxc->timer);
1668*4882a593Smuzhiyun 	}
1669*4882a593Smuzhiyun 
1670*4882a593Smuzhiyun 	lt7911uxc->plugin_irq = gpiod_to_irq(lt7911uxc->plugin_det_gpio);
1671*4882a593Smuzhiyun 	if (lt7911uxc->plugin_irq < 0)
1672*4882a593Smuzhiyun 		dev_err(dev, "failed to get plugin det irq, maybe no use\n");
1673*4882a593Smuzhiyun 
1674*4882a593Smuzhiyun 	err = devm_request_threaded_irq(dev, lt7911uxc->plugin_irq, NULL,
1675*4882a593Smuzhiyun 			plugin_detect_irq_handler, IRQF_TRIGGER_FALLING |
1676*4882a593Smuzhiyun 			IRQF_TRIGGER_RISING | IRQF_ONESHOT, "lt7911uxc",
1677*4882a593Smuzhiyun 			lt7911uxc);
1678*4882a593Smuzhiyun 	if (err)
1679*4882a593Smuzhiyun 		dev_err(dev, "failed to register plugin det irq (%d), maybe no use\n", err);
1680*4882a593Smuzhiyun 
1681*4882a593Smuzhiyun 	mutex_init(&lt7911uxc->confctl_mutex);
1682*4882a593Smuzhiyun 	err = lt7911uxc_init_v4l2_ctrls(lt7911uxc);
1683*4882a593Smuzhiyun 	if (err)
1684*4882a593Smuzhiyun 		goto err_free_hdl;
1685*4882a593Smuzhiyun 
1686*4882a593Smuzhiyun 	client->flags |= I2C_CLIENT_SCCB;
1687*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1688*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &lt7911uxc_ops);
1689*4882a593Smuzhiyun 	sd->internal_ops = &lt7911uxc_internal_ops;
1690*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1691*4882a593Smuzhiyun #endif
1692*4882a593Smuzhiyun 
1693*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1694*4882a593Smuzhiyun 	lt7911uxc->pad.flags = MEDIA_PAD_FL_SOURCE;
1695*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1696*4882a593Smuzhiyun 	err = media_entity_pads_init(&sd->entity, 1, &lt7911uxc->pad);
1697*4882a593Smuzhiyun 	if (err < 0) {
1698*4882a593Smuzhiyun 		v4l2_err(sd, "media entity init failed! err:%d\n", err);
1699*4882a593Smuzhiyun 		goto err_free_hdl;
1700*4882a593Smuzhiyun 	}
1701*4882a593Smuzhiyun #endif
1702*4882a593Smuzhiyun 	memset(facing, 0, sizeof(facing));
1703*4882a593Smuzhiyun 	if (strcmp(lt7911uxc->module_facing, "back") == 0)
1704*4882a593Smuzhiyun 		facing[0] = 'b';
1705*4882a593Smuzhiyun 	else
1706*4882a593Smuzhiyun 		facing[0] = 'f';
1707*4882a593Smuzhiyun 
1708*4882a593Smuzhiyun 	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1709*4882a593Smuzhiyun 		 lt7911uxc->module_index, facing,
1710*4882a593Smuzhiyun 		 LT7911UXC_NAME, dev_name(sd->dev));
1711*4882a593Smuzhiyun 	err = v4l2_async_register_subdev_sensor_common(sd);
1712*4882a593Smuzhiyun 	if (err < 0) {
1713*4882a593Smuzhiyun 		v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
1714*4882a593Smuzhiyun 		goto err_clean_entity;
1715*4882a593Smuzhiyun 	}
1716*4882a593Smuzhiyun 
1717*4882a593Smuzhiyun 	err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1718*4882a593Smuzhiyun 	if (err) {
1719*4882a593Smuzhiyun 		v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
1720*4882a593Smuzhiyun 		goto err_clean_entity;
1721*4882a593Smuzhiyun 	}
1722*4882a593Smuzhiyun 
1723*4882a593Smuzhiyun 	schedule_delayed_work(&lt7911uxc->delayed_work_res_change, 100);
1724*4882a593Smuzhiyun 
1725*4882a593Smuzhiyun 	enable_stream(sd, false);
1726*4882a593Smuzhiyun 	v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1727*4882a593Smuzhiyun 			client->addr << 1, client->adapter->name);
1728*4882a593Smuzhiyun 
1729*4882a593Smuzhiyun 	return 0;
1730*4882a593Smuzhiyun 
1731*4882a593Smuzhiyun err_clean_entity:
1732*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1733*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1734*4882a593Smuzhiyun #endif
1735*4882a593Smuzhiyun err_free_hdl:
1736*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&lt7911uxc->hdl);
1737*4882a593Smuzhiyun 	mutex_destroy(&lt7911uxc->confctl_mutex);
1738*4882a593Smuzhiyun err_work_queues:
1739*4882a593Smuzhiyun 	if (!lt7911uxc->i2c_client->irq)
1740*4882a593Smuzhiyun 		flush_work(&lt7911uxc->work_i2c_poll);
1741*4882a593Smuzhiyun 	cancel_delayed_work(&lt7911uxc->delayed_work_hotplug);
1742*4882a593Smuzhiyun 	cancel_delayed_work(&lt7911uxc->delayed_work_res_change);
1743*4882a593Smuzhiyun 
1744*4882a593Smuzhiyun 	return err;
1745*4882a593Smuzhiyun }
1746*4882a593Smuzhiyun 
lt7911uxc_remove(struct i2c_client * client)1747*4882a593Smuzhiyun static int lt7911uxc_remove(struct i2c_client *client)
1748*4882a593Smuzhiyun {
1749*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1750*4882a593Smuzhiyun 	struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
1751*4882a593Smuzhiyun 
1752*4882a593Smuzhiyun 	if (!lt7911uxc->i2c_client->irq) {
1753*4882a593Smuzhiyun 		del_timer_sync(&lt7911uxc->timer);
1754*4882a593Smuzhiyun 		flush_work(&lt7911uxc->work_i2c_poll);
1755*4882a593Smuzhiyun 	}
1756*4882a593Smuzhiyun 	cancel_delayed_work_sync(&lt7911uxc->delayed_work_hotplug);
1757*4882a593Smuzhiyun 	cancel_delayed_work_sync(&lt7911uxc->delayed_work_res_change);
1758*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(sd);
1759*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
1760*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1761*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1762*4882a593Smuzhiyun #endif
1763*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&lt7911uxc->hdl);
1764*4882a593Smuzhiyun 	mutex_destroy(&lt7911uxc->confctl_mutex);
1765*4882a593Smuzhiyun 	clk_disable_unprepare(lt7911uxc->xvclk);
1766*4882a593Smuzhiyun 
1767*4882a593Smuzhiyun 	return 0;
1768*4882a593Smuzhiyun }
1769*4882a593Smuzhiyun 
1770*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1771*4882a593Smuzhiyun static const struct of_device_id lt7911uxc_of_match[] = {
1772*4882a593Smuzhiyun 	{ .compatible = "lontium,lt7911uxc" },
1773*4882a593Smuzhiyun 	{},
1774*4882a593Smuzhiyun };
1775*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, lt7911uxc_of_match);
1776*4882a593Smuzhiyun #endif
1777*4882a593Smuzhiyun 
1778*4882a593Smuzhiyun static struct i2c_driver lt7911uxc_driver = {
1779*4882a593Smuzhiyun 	.driver = {
1780*4882a593Smuzhiyun 		.name = LT7911UXC_NAME,
1781*4882a593Smuzhiyun 		.pm = &lt7911uxc_pm_ops,
1782*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(lt7911uxc_of_match),
1783*4882a593Smuzhiyun 	},
1784*4882a593Smuzhiyun 	.probe = lt7911uxc_probe,
1785*4882a593Smuzhiyun 	.remove = lt7911uxc_remove,
1786*4882a593Smuzhiyun };
1787*4882a593Smuzhiyun 
lt7911uxc_driver_init(void)1788*4882a593Smuzhiyun static int __init lt7911uxc_driver_init(void)
1789*4882a593Smuzhiyun {
1790*4882a593Smuzhiyun 	return i2c_add_driver(&lt7911uxc_driver);
1791*4882a593Smuzhiyun }
1792*4882a593Smuzhiyun 
lt7911uxc_driver_exit(void)1793*4882a593Smuzhiyun static void __exit lt7911uxc_driver_exit(void)
1794*4882a593Smuzhiyun {
1795*4882a593Smuzhiyun 	i2c_del_driver(&lt7911uxc_driver);
1796*4882a593Smuzhiyun }
1797*4882a593Smuzhiyun 
1798*4882a593Smuzhiyun device_initcall_sync(lt7911uxc_driver_init);
1799*4882a593Smuzhiyun module_exit(lt7911uxc_driver_exit);
1800*4882a593Smuzhiyun 
1801*4882a593Smuzhiyun MODULE_DESCRIPTION("Lontium lt7911uxc DP/type-c to CSI-2 bridge driver");
1802*4882a593Smuzhiyun MODULE_AUTHOR("Jianwei Fan <jianwei.fan@rock-chips.com>");
1803*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1804