1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Dingxian Wen <shawn.wen@rock-chips.com>
6*4882a593Smuzhiyun * V0.0X01.0X00 first version.
7*4882a593Smuzhiyun * V0.0X01.0X01 fix if plugin_gpio was not used.
8*4882a593Smuzhiyun * V0.0X01.0X02 modify driver init level to late_initcall.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/clk.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/hdmi.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/kernel.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/of_graph.h>
20*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun #include <linux/timer.h>
23*4882a593Smuzhiyun #include <linux/v4l2-dv-timings.h>
24*4882a593Smuzhiyun #include <linux/version.h>
25*4882a593Smuzhiyun #include <linux/videodev2.h>
26*4882a593Smuzhiyun #include <linux/workqueue.h>
27*4882a593Smuzhiyun #include <linux/compat.h>
28*4882a593Smuzhiyun #include <media/v4l2-controls_rockchip.h>
29*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
30*4882a593Smuzhiyun #include <media/v4l2-device.h>
31*4882a593Smuzhiyun #include <media/v4l2-dv-timings.h>
32*4882a593Smuzhiyun #include <media/v4l2-event.h>
33*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
34*4882a593Smuzhiyun #include "lt6911uxc.h"
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x2)
37*4882a593Smuzhiyun #define LT6911UXC_NAME "LT6911UXC"
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define LT6911UXC_LINK_FREQ_HIGH 400000000
40*4882a593Smuzhiyun #define LT6911UXC_LINK_FREQ_LOW 200000000
41*4882a593Smuzhiyun #define LT6911UXC_PIXEL_RATE 400000000
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define I2C_MAX_XFER_SIZE 128
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #ifdef LT6911UXC_OUT_RGB
46*4882a593Smuzhiyun #define LT6911UXC_MEDIA_BUS_FMT MEDIA_BUS_FMT_BGR888_1X24
47*4882a593Smuzhiyun #else
48*4882a593Smuzhiyun #define LT6911UXC_MEDIA_BUS_FMT MEDIA_BUS_FMT_UYVY8_2X8
49*4882a593Smuzhiyun #endif
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static int debug;
52*4882a593Smuzhiyun module_param(debug, int, 0644);
53*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "debug level (0-2)");
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
56*4882a593Smuzhiyun LT6911UXC_LINK_FREQ_HIGH,
57*4882a593Smuzhiyun LT6911UXC_LINK_FREQ_LOW,
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun struct lt6911uxc {
61*4882a593Smuzhiyun struct clk *xvclk;
62*4882a593Smuzhiyun struct delayed_work delayed_work_enable_hotplug;
63*4882a593Smuzhiyun struct delayed_work delayed_work_res_change;
64*4882a593Smuzhiyun struct gpio_desc *hpd_ctl_gpio;
65*4882a593Smuzhiyun struct gpio_desc *plugin_det_gpio;
66*4882a593Smuzhiyun struct gpio_desc *power_gpio;
67*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
68*4882a593Smuzhiyun struct i2c_client *i2c_client;
69*4882a593Smuzhiyun struct media_pad pad;
70*4882a593Smuzhiyun struct mutex confctl_mutex;
71*4882a593Smuzhiyun struct v4l2_ctrl *audio_present_ctrl;
72*4882a593Smuzhiyun struct v4l2_ctrl *audio_sampling_rate_ctrl;
73*4882a593Smuzhiyun struct v4l2_ctrl *detect_tx_5v_ctrl;
74*4882a593Smuzhiyun struct v4l2_ctrl *link_freq;
75*4882a593Smuzhiyun struct v4l2_ctrl *pixel_rate;
76*4882a593Smuzhiyun struct v4l2_ctrl_handler hdl;
77*4882a593Smuzhiyun struct v4l2_dv_timings timings;
78*4882a593Smuzhiyun struct v4l2_fwnode_bus_mipi_csi2 bus;
79*4882a593Smuzhiyun struct v4l2_subdev sd;
80*4882a593Smuzhiyun const char *len_name;
81*4882a593Smuzhiyun const char *module_facing;
82*4882a593Smuzhiyun const char *module_name;
83*4882a593Smuzhiyun const struct lt6911uxc_mode *cur_mode;
84*4882a593Smuzhiyun bool enable_hdcp;
85*4882a593Smuzhiyun bool nosignal;
86*4882a593Smuzhiyun bool is_audio_present;
87*4882a593Smuzhiyun int plugin_irq;
88*4882a593Smuzhiyun u32 mbus_fmt_code;
89*4882a593Smuzhiyun u32 module_index;
90*4882a593Smuzhiyun u32 csi_lanes_in_use;
91*4882a593Smuzhiyun u32 audio_sampling_rate;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun struct lt6911uxc_mode {
95*4882a593Smuzhiyun u32 width;
96*4882a593Smuzhiyun u32 height;
97*4882a593Smuzhiyun struct v4l2_fract max_fps;
98*4882a593Smuzhiyun u32 hts_def;
99*4882a593Smuzhiyun u32 vts_def;
100*4882a593Smuzhiyun u32 exp_def;
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const struct v4l2_dv_timings_cap lt6911uxc_timings_cap = {
104*4882a593Smuzhiyun .type = V4L2_DV_BT_656_1120,
105*4882a593Smuzhiyun /* keep this initialization for compatibility with GCC < 4.4.6 */
106*4882a593Smuzhiyun .reserved = { 0 },
107*4882a593Smuzhiyun V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 400000000,
108*4882a593Smuzhiyun V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
109*4882a593Smuzhiyun V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
110*4882a593Smuzhiyun V4L2_DV_BT_CAP_PROGRESSIVE |
111*4882a593Smuzhiyun V4L2_DV_BT_CAP_INTERLACED |
112*4882a593Smuzhiyun V4L2_DV_BT_CAP_REDUCED_BLANKING |
113*4882a593Smuzhiyun V4L2_DV_BT_CAP_CUSTOM)
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static const struct lt6911uxc_mode supported_modes[] = {
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun .width = 3840,
119*4882a593Smuzhiyun .height = 2160,
120*4882a593Smuzhiyun .max_fps = {
121*4882a593Smuzhiyun .numerator = 10000,
122*4882a593Smuzhiyun .denominator = 300000,
123*4882a593Smuzhiyun },
124*4882a593Smuzhiyun .hts_def = 4400,
125*4882a593Smuzhiyun .vts_def = 2250,
126*4882a593Smuzhiyun }, {
127*4882a593Smuzhiyun .width = 1920,
128*4882a593Smuzhiyun .height = 1080,
129*4882a593Smuzhiyun .max_fps = {
130*4882a593Smuzhiyun .numerator = 10000,
131*4882a593Smuzhiyun .denominator = 600000,
132*4882a593Smuzhiyun },
133*4882a593Smuzhiyun .hts_def = 2200,
134*4882a593Smuzhiyun .vts_def = 1125,
135*4882a593Smuzhiyun }, {
136*4882a593Smuzhiyun .width = 1920,
137*4882a593Smuzhiyun .height = 540,
138*4882a593Smuzhiyun .max_fps = {
139*4882a593Smuzhiyun .numerator = 10000,
140*4882a593Smuzhiyun .denominator = 600000,
141*4882a593Smuzhiyun },
142*4882a593Smuzhiyun }, {
143*4882a593Smuzhiyun .width = 1440,
144*4882a593Smuzhiyun .height = 240,
145*4882a593Smuzhiyun .max_fps = {
146*4882a593Smuzhiyun .numerator = 10000,
147*4882a593Smuzhiyun .denominator = 600000,
148*4882a593Smuzhiyun },
149*4882a593Smuzhiyun }, {
150*4882a593Smuzhiyun .width = 1440,
151*4882a593Smuzhiyun .height = 288,
152*4882a593Smuzhiyun .max_fps = {
153*4882a593Smuzhiyun .numerator = 10000,
154*4882a593Smuzhiyun .denominator = 500000,
155*4882a593Smuzhiyun },
156*4882a593Smuzhiyun }, {
157*4882a593Smuzhiyun .width = 1280,
158*4882a593Smuzhiyun .height = 720,
159*4882a593Smuzhiyun .max_fps = {
160*4882a593Smuzhiyun .numerator = 10000,
161*4882a593Smuzhiyun .denominator = 600000,
162*4882a593Smuzhiyun },
163*4882a593Smuzhiyun .hts_def = 1650,
164*4882a593Smuzhiyun .vts_def = 750,
165*4882a593Smuzhiyun }, {
166*4882a593Smuzhiyun .width = 720,
167*4882a593Smuzhiyun .height = 576,
168*4882a593Smuzhiyun .max_fps = {
169*4882a593Smuzhiyun .numerator = 10000,
170*4882a593Smuzhiyun .denominator = 500000,
171*4882a593Smuzhiyun },
172*4882a593Smuzhiyun .hts_def = 864,
173*4882a593Smuzhiyun .vts_def = 625,
174*4882a593Smuzhiyun }, {
175*4882a593Smuzhiyun .width = 720,
176*4882a593Smuzhiyun .height = 480,
177*4882a593Smuzhiyun .max_fps = {
178*4882a593Smuzhiyun .numerator = 10000,
179*4882a593Smuzhiyun .denominator = 600000,
180*4882a593Smuzhiyun },
181*4882a593Smuzhiyun .hts_def = 858,
182*4882a593Smuzhiyun .vts_def = 525,
183*4882a593Smuzhiyun },
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static void lt6911uxc_format_change(struct v4l2_subdev *sd);
187*4882a593Smuzhiyun static int lt6911uxc_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
188*4882a593Smuzhiyun static int lt6911uxc_s_dv_timings(struct v4l2_subdev *sd,
189*4882a593Smuzhiyun struct v4l2_dv_timings *timings);
190*4882a593Smuzhiyun
to_state(struct v4l2_subdev * sd)191*4882a593Smuzhiyun static inline struct lt6911uxc *to_state(struct v4l2_subdev *sd)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun return container_of(sd, struct lt6911uxc, sd);
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
i2c_rd(struct v4l2_subdev * sd,u16 reg,u8 * values,u32 n)196*4882a593Smuzhiyun static int i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
199*4882a593Smuzhiyun struct i2c_client *client = lt6911uxc->i2c_client;
200*4882a593Smuzhiyun struct i2c_msg msgs[3];
201*4882a593Smuzhiyun int err;
202*4882a593Smuzhiyun u8 bank = reg >> 8;
203*4882a593Smuzhiyun u8 reg_addr = reg & 0xFF;
204*4882a593Smuzhiyun u8 buf[2] = {0xFF, bank};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun /* write bank */
207*4882a593Smuzhiyun msgs[0].addr = client->addr;
208*4882a593Smuzhiyun msgs[0].flags = 0;
209*4882a593Smuzhiyun msgs[0].len = 2;
210*4882a593Smuzhiyun msgs[0].buf = buf;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /* write reg addr */
213*4882a593Smuzhiyun msgs[1].addr = client->addr;
214*4882a593Smuzhiyun msgs[1].flags = 0;
215*4882a593Smuzhiyun msgs[1].len = 1;
216*4882a593Smuzhiyun msgs[1].buf = ®_addr;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* read data */
219*4882a593Smuzhiyun msgs[2].addr = client->addr;
220*4882a593Smuzhiyun msgs[2].flags = I2C_M_RD;
221*4882a593Smuzhiyun msgs[2].len = n;
222*4882a593Smuzhiyun msgs[2].buf = values;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
225*4882a593Smuzhiyun if (err != ARRAY_SIZE(msgs)) {
226*4882a593Smuzhiyun v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
227*4882a593Smuzhiyun __func__, reg, client->addr);
228*4882a593Smuzhiyun return -EIO;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun return 0;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
i2c_wr(struct v4l2_subdev * sd,u16 reg,u8 * values,u32 n)234*4882a593Smuzhiyun static int i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
237*4882a593Smuzhiyun struct i2c_client *client = lt6911uxc->i2c_client;
238*4882a593Smuzhiyun struct i2c_msg msgs[2];
239*4882a593Smuzhiyun int err, i;
240*4882a593Smuzhiyun u8 data[I2C_MAX_XFER_SIZE];
241*4882a593Smuzhiyun u8 bank = reg >> 8;
242*4882a593Smuzhiyun u8 reg_addr = reg & 0xFF;
243*4882a593Smuzhiyun u8 buf[2] = {0xFF, bank};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if ((1 + n) > I2C_MAX_XFER_SIZE) {
246*4882a593Smuzhiyun n = I2C_MAX_XFER_SIZE - 1;
247*4882a593Smuzhiyun v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n", reg,
248*4882a593Smuzhiyun 1 + n);
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun data[0] = reg_addr;
252*4882a593Smuzhiyun for (i = 0; i < n; i++)
253*4882a593Smuzhiyun data[i + 1] = values[i];
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /* write bank */
256*4882a593Smuzhiyun msgs[0].addr = client->addr;
257*4882a593Smuzhiyun msgs[0].flags = 0;
258*4882a593Smuzhiyun msgs[0].len = 2;
259*4882a593Smuzhiyun msgs[0].buf = buf;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* write reg data */
262*4882a593Smuzhiyun msgs[1].addr = client->addr;
263*4882a593Smuzhiyun msgs[1].flags = 0;
264*4882a593Smuzhiyun msgs[1].len = 1 + n;
265*4882a593Smuzhiyun msgs[1].buf = data;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
268*4882a593Smuzhiyun if (err < 0) {
269*4882a593Smuzhiyun v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
270*4882a593Smuzhiyun __func__, reg, client->addr);
271*4882a593Smuzhiyun return -EIO;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun return 0;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
i2c_rd8(struct v4l2_subdev * sd,u16 reg,u8 * val_p)277*4882a593Smuzhiyun static int i2c_rd8(struct v4l2_subdev *sd, u16 reg, u8 *val_p)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun return i2c_rd(sd, reg, val_p, 1);
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
i2c_wr8(struct v4l2_subdev * sd,u16 reg,u8 val)282*4882a593Smuzhiyun static int i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun return i2c_wr(sd, reg, &val, 1);
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
lt6911uxc_i2c_enable(struct v4l2_subdev * sd)287*4882a593Smuzhiyun static void lt6911uxc_i2c_enable(struct v4l2_subdev *sd)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun i2c_wr8(sd, I2C_EN_REG, I2C_ENABLE);
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
lt6911uxc_i2c_disable(struct v4l2_subdev * sd)292*4882a593Smuzhiyun static void lt6911uxc_i2c_disable(struct v4l2_subdev *sd)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun i2c_wr8(sd, I2C_EN_REG, I2C_DISABLE);
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
tx_5v_power_present(struct v4l2_subdev * sd)297*4882a593Smuzhiyun static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun bool ret;
300*4882a593Smuzhiyun int val, i, cnt;
301*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /* if not use plugin det gpio */
304*4882a593Smuzhiyun if (!lt6911uxc->plugin_det_gpio)
305*4882a593Smuzhiyun return true;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun cnt = 0;
308*4882a593Smuzhiyun for (i = 0; i < 5; i++) {
309*4882a593Smuzhiyun val = gpiod_get_value(lt6911uxc->plugin_det_gpio);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun if (val > 0)
312*4882a593Smuzhiyun cnt++;
313*4882a593Smuzhiyun usleep_range(500, 600);
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun ret = (cnt >= 3) ? true : false;
317*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "%s: %d\n", __func__, ret);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun return ret;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
no_signal(struct v4l2_subdev * sd)322*4882a593Smuzhiyun static inline bool no_signal(struct v4l2_subdev *sd)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "%s no signal:%d\n", __func__,
327*4882a593Smuzhiyun lt6911uxc->nosignal);
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun return lt6911uxc->nosignal;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun
audio_present(struct v4l2_subdev * sd)332*4882a593Smuzhiyun static inline bool audio_present(struct v4l2_subdev *sd)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun return lt6911uxc->is_audio_present;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
get_audio_sampling_rate(struct v4l2_subdev * sd)339*4882a593Smuzhiyun static int get_audio_sampling_rate(struct v4l2_subdev *sd)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun if (no_signal(sd))
344*4882a593Smuzhiyun return 0;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun return lt6911uxc->audio_sampling_rate;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
fps_calc(const struct v4l2_bt_timings * t)349*4882a593Smuzhiyun static inline unsigned int fps_calc(const struct v4l2_bt_timings *t)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
352*4882a593Smuzhiyun return 0;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun return DIV_ROUND_CLOSEST((unsigned int)t->pixelclock,
355*4882a593Smuzhiyun V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun
lt6911uxc_rcv_supported_res(struct v4l2_subdev * sd,u32 width,u32 height)358*4882a593Smuzhiyun static bool lt6911uxc_rcv_supported_res(struct v4l2_subdev *sd, u32 width,
359*4882a593Smuzhiyun u32 height)
360*4882a593Smuzhiyun {
361*4882a593Smuzhiyun u32 i;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
364*4882a593Smuzhiyun if ((supported_modes[i].width == width) &&
365*4882a593Smuzhiyun (supported_modes[i].height == height)) {
366*4882a593Smuzhiyun break;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun if (i == ARRAY_SIZE(supported_modes)) {
371*4882a593Smuzhiyun v4l2_err(sd, "%s do not support res wxh: %dx%d\n", __func__,
372*4882a593Smuzhiyun width, height);
373*4882a593Smuzhiyun return false;
374*4882a593Smuzhiyun } else {
375*4882a593Smuzhiyun return true;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
lt6911uxc_get_detected_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)379*4882a593Smuzhiyun static int lt6911uxc_get_detected_timings(struct v4l2_subdev *sd,
380*4882a593Smuzhiyun struct v4l2_dv_timings *timings)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
383*4882a593Smuzhiyun struct v4l2_bt_timings *bt = &timings->bt;
384*4882a593Smuzhiyun u32 hact, vact, htotal, vtotal;
385*4882a593Smuzhiyun u32 hbp, hs, hfp, vbp, vs, vfp;
386*4882a593Smuzhiyun u32 pixel_clock, fps;
387*4882a593Smuzhiyun u8 clk_h, clk_m, clk_l;
388*4882a593Smuzhiyun u8 value, val_h, val_l;
389*4882a593Smuzhiyun u32 fw_ver, mipi_byte_clk, mipi_bitrate;
390*4882a593Smuzhiyun u8 fw_a, fw_b, fw_c, fw_d, lanes;
391*4882a593Smuzhiyun int ret;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun memset(timings, 0, sizeof(struct v4l2_dv_timings));
394*4882a593Smuzhiyun lt6911uxc_i2c_enable(sd);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun ret = i2c_rd8(sd, FW_VER_A, &fw_a);
397*4882a593Smuzhiyun ret |= i2c_rd8(sd, FW_VER_B, &fw_b);
398*4882a593Smuzhiyun ret |= i2c_rd8(sd, FW_VER_C, &fw_c);
399*4882a593Smuzhiyun ret |= i2c_rd8(sd, FW_VER_D, &fw_d);
400*4882a593Smuzhiyun if (ret) {
401*4882a593Smuzhiyun v4l2_err(sd, "%s: I2C transform err!\n", __func__);
402*4882a593Smuzhiyun return -ENOLINK;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun fw_ver = (fw_a << 24) | (fw_b << 16) | (fw_c << 8) | fw_d;
405*4882a593Smuzhiyun v4l2_info(sd, "read fw_version:%#x", fw_ver);
406*4882a593Smuzhiyun i2c_wr8(sd, INT_COMPARE_REG, RECEIVED_INT);
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun i2c_rd8(sd, INT_STATUS_86A3, &val_h);
409*4882a593Smuzhiyun i2c_rd8(sd, INT_STATUS_86A5, &val_l);
410*4882a593Smuzhiyun v4l2_info(sd, "int status REG_86A3:%#x, REG_86A5:%#x\n", val_h, val_l);
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun i2c_rd8(sd, HDMI_VERSION, &value);
413*4882a593Smuzhiyun i2c_rd8(sd, TMDS_CLK_H, &clk_h);
414*4882a593Smuzhiyun i2c_rd8(sd, TMDS_CLK_M, &clk_m);
415*4882a593Smuzhiyun i2c_rd8(sd, TMDS_CLK_L, &clk_l);
416*4882a593Smuzhiyun pixel_clock = (((clk_h & 0xf) << 16) | (clk_m << 8) | clk_l) * 1000;
417*4882a593Smuzhiyun if (value & BIT(0)) /* HDMI 2.0 */
418*4882a593Smuzhiyun pixel_clock *= 4;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun i2c_rd8(sd, MIPI_LANES, &lanes);
421*4882a593Smuzhiyun lt6911uxc->csi_lanes_in_use = lanes;
422*4882a593Smuzhiyun i2c_wr8(sd, FM1_DET_CLK_SRC_SEL, AD_LMTX_WRITE_CLK);
423*4882a593Smuzhiyun i2c_rd8(sd, FREQ_METER_H, &clk_h);
424*4882a593Smuzhiyun i2c_rd8(sd, FREQ_METER_M, &clk_m);
425*4882a593Smuzhiyun i2c_rd8(sd, FREQ_METER_L, &clk_l);
426*4882a593Smuzhiyun mipi_byte_clk = (((clk_h & 0xf) << 16) | (clk_m << 8) | clk_l);
427*4882a593Smuzhiyun mipi_bitrate = mipi_byte_clk * 8 / 1000;
428*4882a593Smuzhiyun v4l2_info(sd, "MIPI Byte clk: %dKHz, MIPI bitrate: %dMbps, lanes:%d\n",
429*4882a593Smuzhiyun mipi_byte_clk, mipi_bitrate, lanes);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun i2c_rd8(sd, HTOTAL_H, &val_h);
432*4882a593Smuzhiyun i2c_rd8(sd, HTOTAL_L, &val_l);
433*4882a593Smuzhiyun htotal = ((val_h << 8) | val_l) * 2;
434*4882a593Smuzhiyun i2c_rd8(sd, VTOTAL_H, &val_h);
435*4882a593Smuzhiyun i2c_rd8(sd, VTOTAL_L, &val_l);
436*4882a593Smuzhiyun vtotal = (val_h << 8) | val_l;
437*4882a593Smuzhiyun i2c_rd8(sd, HACT_H, &val_h);
438*4882a593Smuzhiyun i2c_rd8(sd, HACT_L, &val_l);
439*4882a593Smuzhiyun hact = ((val_h << 8) | val_l) * 2;
440*4882a593Smuzhiyun i2c_rd8(sd, VACT_H, &val_h);
441*4882a593Smuzhiyun i2c_rd8(sd, VACT_L, &val_l);
442*4882a593Smuzhiyun vact = (val_h << 8) | val_l;
443*4882a593Smuzhiyun i2c_rd8(sd, HS_H, &val_h);
444*4882a593Smuzhiyun i2c_rd8(sd, HS_L, &val_l);
445*4882a593Smuzhiyun hs = ((val_h << 8) | val_l) * 2;
446*4882a593Smuzhiyun i2c_rd8(sd, VS, &value);
447*4882a593Smuzhiyun vs = value;
448*4882a593Smuzhiyun i2c_rd8(sd, HFP_H, &val_h);
449*4882a593Smuzhiyun i2c_rd8(sd, HFP_L, &val_l);
450*4882a593Smuzhiyun hfp = ((val_h << 8) | val_l) * 2;
451*4882a593Smuzhiyun i2c_rd8(sd, VFP, &value);
452*4882a593Smuzhiyun vfp = value;
453*4882a593Smuzhiyun i2c_rd8(sd, HBP_H, &val_h);
454*4882a593Smuzhiyun i2c_rd8(sd, HBP_L, &val_l);
455*4882a593Smuzhiyun hbp = ((val_h << 8) | val_l) * 2;
456*4882a593Smuzhiyun i2c_rd8(sd, VBP, &value);
457*4882a593Smuzhiyun vbp = value;
458*4882a593Smuzhiyun lt6911uxc_i2c_disable(sd);
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun if (!lt6911uxc_rcv_supported_res(sd, hact, vact)) {
461*4882a593Smuzhiyun lt6911uxc->nosignal = true;
462*4882a593Smuzhiyun v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__);
463*4882a593Smuzhiyun return -EINVAL;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun lt6911uxc->nosignal = false;
467*4882a593Smuzhiyun i2c_rd8(sd, AUDIO_IN_STATUS, &value);
468*4882a593Smuzhiyun lt6911uxc->is_audio_present = (value & BIT(5)) ? true : false;
469*4882a593Smuzhiyun i2c_rd8(sd, AUDIO_SAMPLE_RATAE_H, &val_h);
470*4882a593Smuzhiyun i2c_rd8(sd, AUDIO_SAMPLE_RATAE_L, &val_l);
471*4882a593Smuzhiyun lt6911uxc->audio_sampling_rate = ((val_h << 8) | val_l) + 2;
472*4882a593Smuzhiyun v4l2_info(sd, "is_audio_present: %d, audio_sampling_rate: %dKhz\n",
473*4882a593Smuzhiyun lt6911uxc->is_audio_present,
474*4882a593Smuzhiyun lt6911uxc->audio_sampling_rate);
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun timings->type = V4L2_DV_BT_656_1120;
477*4882a593Smuzhiyun bt->width = hact;
478*4882a593Smuzhiyun bt->height = vact;
479*4882a593Smuzhiyun bt->vsync = vs;
480*4882a593Smuzhiyun bt->hsync = hs;
481*4882a593Smuzhiyun bt->pixelclock = pixel_clock;
482*4882a593Smuzhiyun bt->hfrontporch = hfp;
483*4882a593Smuzhiyun bt->vfrontporch = vfp;
484*4882a593Smuzhiyun bt->hbackporch = hbp;
485*4882a593Smuzhiyun bt->vbackporch = vbp;
486*4882a593Smuzhiyun fps = fps_calc(bt);
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun /* for interlaced res 1080i 576i 480i*/
489*4882a593Smuzhiyun if ((hact == 1920 && vact == 540) || (hact == 1440 && vact == 288)
490*4882a593Smuzhiyun || (hact == 1440 && vact == 240)) {
491*4882a593Smuzhiyun bt->interlaced = V4L2_DV_INTERLACED;
492*4882a593Smuzhiyun bt->height *= 2;
493*4882a593Smuzhiyun bt->il_vsync = bt->vsync + 1;
494*4882a593Smuzhiyun } else {
495*4882a593Smuzhiyun bt->interlaced = V4L2_DV_PROGRESSIVE;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun v4l2_info(sd, "act:%dx%d, total:%dx%d, pixclk:%d, fps:%d\n",
499*4882a593Smuzhiyun hact, vact, htotal, vtotal, pixel_clock, fps);
500*4882a593Smuzhiyun v4l2_info(sd, "hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d, inerlaced:%d\n",
501*4882a593Smuzhiyun bt->hfrontporch, bt->hsync, bt->hbackporch, bt->vfrontporch,
502*4882a593Smuzhiyun bt->vsync, bt->vbackporch, bt->interlaced);
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun return 0;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
lt6911uxc_config_hpd(struct v4l2_subdev * sd)507*4882a593Smuzhiyun static void lt6911uxc_config_hpd(struct v4l2_subdev *sd)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
510*4882a593Smuzhiyun bool plugin;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun plugin = tx_5v_power_present(sd);
513*4882a593Smuzhiyun v4l2_dbg(2, debug, sd, "%s: plugin: %d\n", __func__, plugin);
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun if (plugin) {
516*4882a593Smuzhiyun gpiod_set_value(lt6911uxc->hpd_ctl_gpio, 1);
517*4882a593Smuzhiyun } else {
518*4882a593Smuzhiyun lt6911uxc->nosignal = true;
519*4882a593Smuzhiyun gpiod_set_value(lt6911uxc->hpd_ctl_gpio, 0);
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
lt6911uxc_delayed_work_enable_hotplug(struct work_struct * work)523*4882a593Smuzhiyun static void lt6911uxc_delayed_work_enable_hotplug(struct work_struct *work)
524*4882a593Smuzhiyun {
525*4882a593Smuzhiyun struct delayed_work *dwork = to_delayed_work(work);
526*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = container_of(dwork,
527*4882a593Smuzhiyun struct lt6911uxc, delayed_work_enable_hotplug);
528*4882a593Smuzhiyun struct v4l2_subdev *sd = <6911uxc->sd;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun v4l2_dbg(2, debug, sd, "%s:\n", __func__);
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun v4l2_ctrl_s_ctrl(lt6911uxc->detect_tx_5v_ctrl, tx_5v_power_present(sd));
533*4882a593Smuzhiyun lt6911uxc_config_hpd(sd);
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun
lt6911uxc_delayed_work_res_change(struct work_struct * work)536*4882a593Smuzhiyun static void lt6911uxc_delayed_work_res_change(struct work_struct *work)
537*4882a593Smuzhiyun {
538*4882a593Smuzhiyun struct delayed_work *dwork = to_delayed_work(work);
539*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = container_of(dwork,
540*4882a593Smuzhiyun struct lt6911uxc, delayed_work_res_change);
541*4882a593Smuzhiyun struct v4l2_subdev *sd = <6911uxc->sd;
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun v4l2_dbg(2, debug, sd, "%s:\n", __func__);
544*4882a593Smuzhiyun lt6911uxc_format_change(sd);
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun
lt6911uxc_s_ctrl_detect_tx_5v(struct v4l2_subdev * sd)547*4882a593Smuzhiyun static int lt6911uxc_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun return v4l2_ctrl_s_ctrl(lt6911uxc->detect_tx_5v_ctrl,
552*4882a593Smuzhiyun tx_5v_power_present(sd));
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun
lt6911uxc_s_ctrl_audio_sampling_rate(struct v4l2_subdev * sd)555*4882a593Smuzhiyun static int lt6911uxc_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
556*4882a593Smuzhiyun {
557*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun return v4l2_ctrl_s_ctrl(lt6911uxc->audio_sampling_rate_ctrl,
560*4882a593Smuzhiyun get_audio_sampling_rate(sd));
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
lt6911uxc_s_ctrl_audio_present(struct v4l2_subdev * sd)563*4882a593Smuzhiyun static int lt6911uxc_s_ctrl_audio_present(struct v4l2_subdev *sd)
564*4882a593Smuzhiyun {
565*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun return v4l2_ctrl_s_ctrl(lt6911uxc->audio_present_ctrl,
568*4882a593Smuzhiyun audio_present(sd));
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun
lt6911uxc_update_controls(struct v4l2_subdev * sd)571*4882a593Smuzhiyun static int lt6911uxc_update_controls(struct v4l2_subdev *sd)
572*4882a593Smuzhiyun {
573*4882a593Smuzhiyun int ret = 0;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun ret |= lt6911uxc_s_ctrl_detect_tx_5v(sd);
576*4882a593Smuzhiyun ret |= lt6911uxc_s_ctrl_audio_sampling_rate(sd);
577*4882a593Smuzhiyun ret |= lt6911uxc_s_ctrl_audio_present(sd);
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun return ret;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
enable_stream(struct v4l2_subdev * sd,bool enable)582*4882a593Smuzhiyun static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun v4l2_dbg(2, debug, sd, "%s: %sable\n",
585*4882a593Smuzhiyun __func__, enable ? "en" : "dis");
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun
lt6911uxc_format_change(struct v4l2_subdev * sd)588*4882a593Smuzhiyun static void lt6911uxc_format_change(struct v4l2_subdev *sd)
589*4882a593Smuzhiyun {
590*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
591*4882a593Smuzhiyun struct v4l2_dv_timings timings;
592*4882a593Smuzhiyun const struct v4l2_event lt6911uxc_ev_fmt = {
593*4882a593Smuzhiyun .type = V4L2_EVENT_SOURCE_CHANGE,
594*4882a593Smuzhiyun .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
595*4882a593Smuzhiyun };
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun if (lt6911uxc_get_detected_timings(sd, &timings)) {
598*4882a593Smuzhiyun enable_stream(sd, false);
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "%s: No signal\n", __func__);
601*4882a593Smuzhiyun } else {
602*4882a593Smuzhiyun if (!v4l2_match_dv_timings(<6911uxc->timings, &timings, 0,
603*4882a593Smuzhiyun false)) {
604*4882a593Smuzhiyun enable_stream(sd, false);
605*4882a593Smuzhiyun /* automatically set timing rather than set by user */
606*4882a593Smuzhiyun lt6911uxc_s_dv_timings(sd, &timings);
607*4882a593Smuzhiyun v4l2_print_dv_timings(sd->name,
608*4882a593Smuzhiyun "Format_change: New format: ",
609*4882a593Smuzhiyun &timings, false);
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun if (sd->devnode)
614*4882a593Smuzhiyun v4l2_subdev_notify_event(sd, <6911uxc_ev_fmt);
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun
lt6911uxc_isr(struct v4l2_subdev * sd,u32 status,bool * handled)617*4882a593Smuzhiyun static int lt6911uxc_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun schedule_delayed_work(<6911uxc->delayed_work_res_change, HZ / 20);
622*4882a593Smuzhiyun *handled = true;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun return 0;
625*4882a593Smuzhiyun }
626*4882a593Smuzhiyun
lt6911uxc_res_change_irq_handler(int irq,void * dev_id)627*4882a593Smuzhiyun static irqreturn_t lt6911uxc_res_change_irq_handler(int irq, void *dev_id)
628*4882a593Smuzhiyun {
629*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = dev_id;
630*4882a593Smuzhiyun bool handled;
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun lt6911uxc_isr(<6911uxc->sd, 0, &handled);
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun return handled ? IRQ_HANDLED : IRQ_NONE;
635*4882a593Smuzhiyun }
636*4882a593Smuzhiyun
plugin_detect_irq_handler(int irq,void * dev_id)637*4882a593Smuzhiyun static irqreturn_t plugin_detect_irq_handler(int irq, void *dev_id)
638*4882a593Smuzhiyun {
639*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = dev_id;
640*4882a593Smuzhiyun struct v4l2_subdev *sd = <6911uxc->sd;
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun /* control hpd output level after 25ms */
643*4882a593Smuzhiyun schedule_delayed_work(<6911uxc->delayed_work_enable_hotplug,
644*4882a593Smuzhiyun HZ / 40);
645*4882a593Smuzhiyun tx_5v_power_present(sd);
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun return IRQ_HANDLED;
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun
lt6911uxc_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)650*4882a593Smuzhiyun static int lt6911uxc_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
651*4882a593Smuzhiyun struct v4l2_event_subscription *sub)
652*4882a593Smuzhiyun {
653*4882a593Smuzhiyun switch (sub->type) {
654*4882a593Smuzhiyun case V4L2_EVENT_SOURCE_CHANGE:
655*4882a593Smuzhiyun return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
656*4882a593Smuzhiyun case V4L2_EVENT_CTRL:
657*4882a593Smuzhiyun return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
658*4882a593Smuzhiyun default:
659*4882a593Smuzhiyun return -EINVAL;
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun
lt6911uxc_g_input_status(struct v4l2_subdev * sd,u32 * status)663*4882a593Smuzhiyun static int lt6911uxc_g_input_status(struct v4l2_subdev *sd, u32 *status)
664*4882a593Smuzhiyun {
665*4882a593Smuzhiyun *status = 0;
666*4882a593Smuzhiyun *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
667*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun return 0;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun
lt6911uxc_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)672*4882a593Smuzhiyun static int lt6911uxc_s_dv_timings(struct v4l2_subdev *sd,
673*4882a593Smuzhiyun struct v4l2_dv_timings *timings)
674*4882a593Smuzhiyun {
675*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun if (!timings)
678*4882a593Smuzhiyun return -EINVAL;
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun if (debug)
681*4882a593Smuzhiyun v4l2_print_dv_timings(sd->name, "s_dv_timings: ", timings, false);
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun if (v4l2_match_dv_timings(<6911uxc->timings, timings, 0, false)) {
684*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
685*4882a593Smuzhiyun return 0;
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun if (!v4l2_valid_dv_timings(timings,
689*4882a593Smuzhiyun <6911uxc_timings_cap, NULL, NULL)) {
690*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
691*4882a593Smuzhiyun return -ERANGE;
692*4882a593Smuzhiyun }
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun lt6911uxc->timings = *timings;
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun enable_stream(sd, false);
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun return 0;
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun
lt6911uxc_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)701*4882a593Smuzhiyun static int lt6911uxc_g_dv_timings(struct v4l2_subdev *sd,
702*4882a593Smuzhiyun struct v4l2_dv_timings *timings)
703*4882a593Smuzhiyun {
704*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun *timings = lt6911uxc->timings;
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun return 0;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun
lt6911uxc_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)711*4882a593Smuzhiyun static int lt6911uxc_enum_dv_timings(struct v4l2_subdev *sd,
712*4882a593Smuzhiyun struct v4l2_enum_dv_timings *timings)
713*4882a593Smuzhiyun {
714*4882a593Smuzhiyun if (timings->pad != 0)
715*4882a593Smuzhiyun return -EINVAL;
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun return v4l2_enum_dv_timings_cap(timings,
718*4882a593Smuzhiyun <6911uxc_timings_cap, NULL, NULL);
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun
lt6911uxc_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)721*4882a593Smuzhiyun static int lt6911uxc_query_dv_timings(struct v4l2_subdev *sd,
722*4882a593Smuzhiyun struct v4l2_dv_timings *timings)
723*4882a593Smuzhiyun {
724*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun *timings = lt6911uxc->timings;
727*4882a593Smuzhiyun if (debug)
728*4882a593Smuzhiyun v4l2_print_dv_timings(sd->name, "query_dv_timings: ", timings, false);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun if (!v4l2_valid_dv_timings(timings, <6911uxc_timings_cap, NULL,
731*4882a593Smuzhiyun NULL)) {
732*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun return -ERANGE;
735*4882a593Smuzhiyun }
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun return 0;
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun
lt6911uxc_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)740*4882a593Smuzhiyun static int lt6911uxc_dv_timings_cap(struct v4l2_subdev *sd,
741*4882a593Smuzhiyun struct v4l2_dv_timings_cap *cap)
742*4882a593Smuzhiyun {
743*4882a593Smuzhiyun if (cap->pad != 0)
744*4882a593Smuzhiyun return -EINVAL;
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun *cap = lt6911uxc_timings_cap;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun return 0;
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun
lt6911uxc_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)751*4882a593Smuzhiyun static int lt6911uxc_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
752*4882a593Smuzhiyun struct v4l2_mbus_config *cfg)
753*4882a593Smuzhiyun {
754*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun cfg->type = V4L2_MBUS_CSI2_DPHY;
757*4882a593Smuzhiyun cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK | V4L2_MBUS_CSI2_CHANNEL_0;
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun switch (lt6911uxc->csi_lanes_in_use) {
760*4882a593Smuzhiyun case 1:
761*4882a593Smuzhiyun cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
762*4882a593Smuzhiyun break;
763*4882a593Smuzhiyun case 2:
764*4882a593Smuzhiyun cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
765*4882a593Smuzhiyun break;
766*4882a593Smuzhiyun case 3:
767*4882a593Smuzhiyun cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
768*4882a593Smuzhiyun break;
769*4882a593Smuzhiyun case 4:
770*4882a593Smuzhiyun cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
771*4882a593Smuzhiyun break;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun default:
774*4882a593Smuzhiyun return -EINVAL;
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun return 0;
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun
lt6911uxc_s_stream(struct v4l2_subdev * sd,int enable)780*4882a593Smuzhiyun static int lt6911uxc_s_stream(struct v4l2_subdev *sd, int enable)
781*4882a593Smuzhiyun {
782*4882a593Smuzhiyun enable_stream(sd, enable);
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun return 0;
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun
lt6911uxc_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)787*4882a593Smuzhiyun static int lt6911uxc_enum_mbus_code(struct v4l2_subdev *sd,
788*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
789*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
790*4882a593Smuzhiyun {
791*4882a593Smuzhiyun switch (code->index) {
792*4882a593Smuzhiyun case 0:
793*4882a593Smuzhiyun code->code = LT6911UXC_MEDIA_BUS_FMT;
794*4882a593Smuzhiyun break;
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun default:
797*4882a593Smuzhiyun return -EINVAL;
798*4882a593Smuzhiyun }
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun return 0;
801*4882a593Smuzhiyun }
802*4882a593Smuzhiyun
lt6911uxc_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)803*4882a593Smuzhiyun static int lt6911uxc_enum_frame_sizes(struct v4l2_subdev *sd,
804*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
805*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
806*4882a593Smuzhiyun {
807*4882a593Smuzhiyun if (fse->index >= ARRAY_SIZE(supported_modes))
808*4882a593Smuzhiyun return -EINVAL;
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun if (fse->code != LT6911UXC_MEDIA_BUS_FMT)
811*4882a593Smuzhiyun return -EINVAL;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun fse->min_width = supported_modes[fse->index].width;
814*4882a593Smuzhiyun fse->max_width = supported_modes[fse->index].width;
815*4882a593Smuzhiyun fse->max_height = supported_modes[fse->index].height;
816*4882a593Smuzhiyun fse->min_height = supported_modes[fse->index].height;
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun return 0;
819*4882a593Smuzhiyun }
820*4882a593Smuzhiyun
lt6911uxc_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)821*4882a593Smuzhiyun static int lt6911uxc_enum_frame_interval(struct v4l2_subdev *sd,
822*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
823*4882a593Smuzhiyun struct v4l2_subdev_frame_interval_enum *fie)
824*4882a593Smuzhiyun {
825*4882a593Smuzhiyun if (fie->index >= ARRAY_SIZE(supported_modes))
826*4882a593Smuzhiyun return -EINVAL;
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun fie->code = LT6911UXC_MEDIA_BUS_FMT;
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun fie->width = supported_modes[fie->index].width;
831*4882a593Smuzhiyun fie->height = supported_modes[fie->index].height;
832*4882a593Smuzhiyun fie->interval = supported_modes[fie->index].max_fps;
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun return 0;
835*4882a593Smuzhiyun }
836*4882a593Smuzhiyun
lt6911uxc_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)837*4882a593Smuzhiyun static int lt6911uxc_get_fmt(struct v4l2_subdev *sd,
838*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
839*4882a593Smuzhiyun struct v4l2_subdev_format *format)
840*4882a593Smuzhiyun {
841*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun mutex_lock(<6911uxc->confctl_mutex);
844*4882a593Smuzhiyun format->format.code = lt6911uxc->mbus_fmt_code;
845*4882a593Smuzhiyun format->format.width = lt6911uxc->timings.bt.width;
846*4882a593Smuzhiyun format->format.height = lt6911uxc->timings.bt.height;
847*4882a593Smuzhiyun format->format.field =
848*4882a593Smuzhiyun lt6911uxc->timings.bt.interlaced ?
849*4882a593Smuzhiyun V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
850*4882a593Smuzhiyun format->format.colorspace = V4L2_COLORSPACE_SRGB;
851*4882a593Smuzhiyun mutex_unlock(<6911uxc->confctl_mutex);
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "%s: fmt code:%d, w:%d, h:%d, field mode:%s\n",
854*4882a593Smuzhiyun __func__, format->format.code, format->format.width, format->format.height,
855*4882a593Smuzhiyun (format->format.field == V4L2_FIELD_INTERLACED) ? "I" : "P");
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun return 0;
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun
lt6911uxc_get_reso_dist(const struct lt6911uxc_mode * mode,struct v4l2_mbus_framefmt * framefmt)860*4882a593Smuzhiyun static int lt6911uxc_get_reso_dist(const struct lt6911uxc_mode *mode,
861*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt)
862*4882a593Smuzhiyun {
863*4882a593Smuzhiyun return abs(mode->width - framefmt->width) +
864*4882a593Smuzhiyun abs(mode->height - framefmt->height);
865*4882a593Smuzhiyun }
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun static const struct lt6911uxc_mode *
lt6911uxc_find_best_fit(struct v4l2_subdev_format * fmt)868*4882a593Smuzhiyun lt6911uxc_find_best_fit(struct v4l2_subdev_format *fmt)
869*4882a593Smuzhiyun {
870*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt = &fmt->format;
871*4882a593Smuzhiyun int dist;
872*4882a593Smuzhiyun int cur_best_fit = 0;
873*4882a593Smuzhiyun int cur_best_fit_dist = -1;
874*4882a593Smuzhiyun unsigned int i;
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
877*4882a593Smuzhiyun dist = lt6911uxc_get_reso_dist(&supported_modes[i], framefmt);
878*4882a593Smuzhiyun if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
879*4882a593Smuzhiyun cur_best_fit_dist = dist;
880*4882a593Smuzhiyun cur_best_fit = i;
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun return &supported_modes[cur_best_fit];
885*4882a593Smuzhiyun }
886*4882a593Smuzhiyun
lt6911uxc_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)887*4882a593Smuzhiyun static int lt6911uxc_set_fmt(struct v4l2_subdev *sd,
888*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
889*4882a593Smuzhiyun struct v4l2_subdev_format *format)
890*4882a593Smuzhiyun {
891*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
892*4882a593Smuzhiyun const struct lt6911uxc_mode *mode;
893*4882a593Smuzhiyun int index;
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun /* is overwritten by get_fmt */
896*4882a593Smuzhiyun u32 code = format->format.code;
897*4882a593Smuzhiyun int ret = lt6911uxc_get_fmt(sd, cfg, format);
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun format->format.code = code;
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun if (ret)
902*4882a593Smuzhiyun return ret;
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun switch (code) {
905*4882a593Smuzhiyun case LT6911UXC_MEDIA_BUS_FMT:
906*4882a593Smuzhiyun break;
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun default:
909*4882a593Smuzhiyun return -EINVAL;
910*4882a593Smuzhiyun }
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun if (format->which == V4L2_SUBDEV_FORMAT_TRY)
913*4882a593Smuzhiyun return 0;
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun lt6911uxc->mbus_fmt_code = format->format.code;
916*4882a593Smuzhiyun mode = lt6911uxc_find_best_fit(format);
917*4882a593Smuzhiyun lt6911uxc->cur_mode = mode;
918*4882a593Smuzhiyun enable_stream(sd, false);
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun if (((mode->width == 720) && (mode->height == 576)) ||
921*4882a593Smuzhiyun ((mode->width == 720) && (mode->height == 480)))
922*4882a593Smuzhiyun index = 1;
923*4882a593Smuzhiyun else
924*4882a593Smuzhiyun index = 0;
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(lt6911uxc->link_freq, index);
927*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "%s res wxh:%dx%d, link freq:%llu", __func__,
928*4882a593Smuzhiyun mode->width, mode->height, link_freq_menu_items[index]);
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun return 0;
931*4882a593Smuzhiyun }
932*4882a593Smuzhiyun
lt6911uxc_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)933*4882a593Smuzhiyun static int lt6911uxc_g_frame_interval(struct v4l2_subdev *sd,
934*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *fi)
935*4882a593Smuzhiyun {
936*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
937*4882a593Smuzhiyun const struct lt6911uxc_mode *mode = lt6911uxc->cur_mode;
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun mutex_lock(<6911uxc->confctl_mutex);
940*4882a593Smuzhiyun fi->interval = mode->max_fps;
941*4882a593Smuzhiyun mutex_unlock(<6911uxc->confctl_mutex);
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun return 0;
944*4882a593Smuzhiyun }
945*4882a593Smuzhiyun
lt6911uxc_get_module_inf(struct lt6911uxc * lt6911uxc,struct rkmodule_inf * inf)946*4882a593Smuzhiyun static void lt6911uxc_get_module_inf(struct lt6911uxc *lt6911uxc,
947*4882a593Smuzhiyun struct rkmodule_inf *inf)
948*4882a593Smuzhiyun {
949*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
950*4882a593Smuzhiyun strscpy(inf->base.sensor, LT6911UXC_NAME, sizeof(inf->base.sensor));
951*4882a593Smuzhiyun strscpy(inf->base.module, lt6911uxc->module_name, sizeof(inf->base.module));
952*4882a593Smuzhiyun strscpy(inf->base.lens, lt6911uxc->len_name, sizeof(inf->base.lens));
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun
lt6911uxc_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)955*4882a593Smuzhiyun static long lt6911uxc_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
956*4882a593Smuzhiyun {
957*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
958*4882a593Smuzhiyun long ret = 0;
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun switch (cmd) {
961*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
962*4882a593Smuzhiyun lt6911uxc_get_module_inf(lt6911uxc, (struct rkmodule_inf *)arg);
963*4882a593Smuzhiyun break;
964*4882a593Smuzhiyun case RKMODULE_GET_HDMI_MODE:
965*4882a593Smuzhiyun *(int *)arg = RKMODULE_HDMIIN_MODE;
966*4882a593Smuzhiyun break;
967*4882a593Smuzhiyun default:
968*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
969*4882a593Smuzhiyun break;
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun return ret;
973*4882a593Smuzhiyun }
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
lt6911uxc_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)976*4882a593Smuzhiyun static long lt6911uxc_compat_ioctl32(struct v4l2_subdev *sd,
977*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
978*4882a593Smuzhiyun {
979*4882a593Smuzhiyun void __user *up = compat_ptr(arg);
980*4882a593Smuzhiyun struct rkmodule_inf *inf;
981*4882a593Smuzhiyun long ret;
982*4882a593Smuzhiyun int *seq;
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun switch (cmd) {
985*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
986*4882a593Smuzhiyun inf = kzalloc(sizeof(*inf), GFP_KERNEL);
987*4882a593Smuzhiyun if (!inf) {
988*4882a593Smuzhiyun ret = -ENOMEM;
989*4882a593Smuzhiyun return ret;
990*4882a593Smuzhiyun }
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun ret = lt6911uxc_ioctl(sd, cmd, inf);
993*4882a593Smuzhiyun if (!ret) {
994*4882a593Smuzhiyun ret = copy_to_user(up, inf, sizeof(*inf));
995*4882a593Smuzhiyun if (ret)
996*4882a593Smuzhiyun ret = -EFAULT;
997*4882a593Smuzhiyun }
998*4882a593Smuzhiyun kfree(inf);
999*4882a593Smuzhiyun break;
1000*4882a593Smuzhiyun case RKMODULE_GET_HDMI_MODE:
1001*4882a593Smuzhiyun seq = kzalloc(sizeof(*seq), GFP_KERNEL);
1002*4882a593Smuzhiyun if (!seq) {
1003*4882a593Smuzhiyun ret = -ENOMEM;
1004*4882a593Smuzhiyun return ret;
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun ret = lt6911uxc_ioctl(sd, cmd, seq);
1008*4882a593Smuzhiyun if (!ret) {
1009*4882a593Smuzhiyun ret = copy_to_user(up, seq, sizeof(*seq));
1010*4882a593Smuzhiyun if (ret)
1011*4882a593Smuzhiyun ret = -EFAULT;
1012*4882a593Smuzhiyun }
1013*4882a593Smuzhiyun kfree(seq);
1014*4882a593Smuzhiyun break;
1015*4882a593Smuzhiyun default:
1016*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
1017*4882a593Smuzhiyun break;
1018*4882a593Smuzhiyun }
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun return ret;
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun #endif
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops lt6911uxc_core_ops = {
1025*4882a593Smuzhiyun .interrupt_service_routine = lt6911uxc_isr,
1026*4882a593Smuzhiyun .subscribe_event = lt6911uxc_subscribe_event,
1027*4882a593Smuzhiyun .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1028*4882a593Smuzhiyun .ioctl = lt6911uxc_ioctl,
1029*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1030*4882a593Smuzhiyun .compat_ioctl32 = lt6911uxc_compat_ioctl32,
1031*4882a593Smuzhiyun #endif
1032*4882a593Smuzhiyun };
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops lt6911uxc_video_ops = {
1035*4882a593Smuzhiyun .g_input_status = lt6911uxc_g_input_status,
1036*4882a593Smuzhiyun .s_dv_timings = lt6911uxc_s_dv_timings,
1037*4882a593Smuzhiyun .g_dv_timings = lt6911uxc_g_dv_timings,
1038*4882a593Smuzhiyun .query_dv_timings = lt6911uxc_query_dv_timings,
1039*4882a593Smuzhiyun .s_stream = lt6911uxc_s_stream,
1040*4882a593Smuzhiyun .g_frame_interval = lt6911uxc_g_frame_interval,
1041*4882a593Smuzhiyun };
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops lt6911uxc_pad_ops = {
1044*4882a593Smuzhiyun .enum_mbus_code = lt6911uxc_enum_mbus_code,
1045*4882a593Smuzhiyun .enum_frame_size = lt6911uxc_enum_frame_sizes,
1046*4882a593Smuzhiyun .enum_frame_interval = lt6911uxc_enum_frame_interval,
1047*4882a593Smuzhiyun .set_fmt = lt6911uxc_set_fmt,
1048*4882a593Smuzhiyun .get_fmt = lt6911uxc_get_fmt,
1049*4882a593Smuzhiyun .enum_dv_timings = lt6911uxc_enum_dv_timings,
1050*4882a593Smuzhiyun .dv_timings_cap = lt6911uxc_dv_timings_cap,
1051*4882a593Smuzhiyun .get_mbus_config = lt6911uxc_g_mbus_config,
1052*4882a593Smuzhiyun };
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun static const struct v4l2_subdev_ops lt6911uxc_ops = {
1055*4882a593Smuzhiyun .core = <6911uxc_core_ops,
1056*4882a593Smuzhiyun .video = <6911uxc_video_ops,
1057*4882a593Smuzhiyun .pad = <6911uxc_pad_ops,
1058*4882a593Smuzhiyun };
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun static const struct v4l2_ctrl_config lt6911uxc_ctrl_audio_sampling_rate = {
1061*4882a593Smuzhiyun .id = RK_V4L2_CID_AUDIO_SAMPLING_RATE,
1062*4882a593Smuzhiyun .name = "Audio sampling rate",
1063*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
1064*4882a593Smuzhiyun .min = 0,
1065*4882a593Smuzhiyun .max = 768000,
1066*4882a593Smuzhiyun .step = 1,
1067*4882a593Smuzhiyun .def = 0,
1068*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_READ_ONLY,
1069*4882a593Smuzhiyun };
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun static const struct v4l2_ctrl_config lt6911uxc_ctrl_audio_present = {
1072*4882a593Smuzhiyun .id = RK_V4L2_CID_AUDIO_PRESENT,
1073*4882a593Smuzhiyun .name = "Audio present",
1074*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_BOOLEAN,
1075*4882a593Smuzhiyun .min = 0,
1076*4882a593Smuzhiyun .max = 1,
1077*4882a593Smuzhiyun .step = 1,
1078*4882a593Smuzhiyun .def = 0,
1079*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_READ_ONLY,
1080*4882a593Smuzhiyun };
1081*4882a593Smuzhiyun
lt6911uxc_reset(struct lt6911uxc * lt6911uxc)1082*4882a593Smuzhiyun static void lt6911uxc_reset(struct lt6911uxc *lt6911uxc)
1083*4882a593Smuzhiyun {
1084*4882a593Smuzhiyun gpiod_set_value(lt6911uxc->reset_gpio, 0);
1085*4882a593Smuzhiyun usleep_range(2000, 2100);
1086*4882a593Smuzhiyun gpiod_set_value(lt6911uxc->reset_gpio, 1);
1087*4882a593Smuzhiyun usleep_range(120*1000, 121*1000);
1088*4882a593Smuzhiyun gpiod_set_value(lt6911uxc->reset_gpio, 0);
1089*4882a593Smuzhiyun usleep_range(300*1000, 310*1000);
1090*4882a593Smuzhiyun }
1091*4882a593Smuzhiyun
lt6911uxc_init_v4l2_ctrls(struct lt6911uxc * lt6911uxc)1092*4882a593Smuzhiyun static int lt6911uxc_init_v4l2_ctrls(struct lt6911uxc *lt6911uxc)
1093*4882a593Smuzhiyun {
1094*4882a593Smuzhiyun struct v4l2_subdev *sd;
1095*4882a593Smuzhiyun int ret;
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun sd = <6911uxc->sd;
1098*4882a593Smuzhiyun ret = v4l2_ctrl_handler_init(<6911uxc->hdl, 5);
1099*4882a593Smuzhiyun if (ret)
1100*4882a593Smuzhiyun return ret;
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun lt6911uxc->link_freq = v4l2_ctrl_new_int_menu(<6911uxc->hdl, NULL,
1103*4882a593Smuzhiyun V4L2_CID_LINK_FREQ,
1104*4882a593Smuzhiyun ARRAY_SIZE(link_freq_menu_items) - 1, 0,
1105*4882a593Smuzhiyun link_freq_menu_items);
1106*4882a593Smuzhiyun v4l2_ctrl_new_std(<6911uxc->hdl, NULL, V4L2_CID_PIXEL_RATE,
1107*4882a593Smuzhiyun 0, LT6911UXC_PIXEL_RATE, 1, LT6911UXC_PIXEL_RATE);
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun lt6911uxc->detect_tx_5v_ctrl = v4l2_ctrl_new_std(<6911uxc->hdl,
1110*4882a593Smuzhiyun NULL, V4L2_CID_DV_RX_POWER_PRESENT,
1111*4882a593Smuzhiyun 0, 1, 0, 0);
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun lt6911uxc->audio_sampling_rate_ctrl =
1114*4882a593Smuzhiyun v4l2_ctrl_new_custom(<6911uxc->hdl,
1115*4882a593Smuzhiyun <6911uxc_ctrl_audio_sampling_rate, NULL);
1116*4882a593Smuzhiyun lt6911uxc->audio_present_ctrl = v4l2_ctrl_new_custom(<6911uxc->hdl,
1117*4882a593Smuzhiyun <6911uxc_ctrl_audio_present, NULL);
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun sd->ctrl_handler = <6911uxc->hdl;
1120*4882a593Smuzhiyun if (lt6911uxc->hdl.error) {
1121*4882a593Smuzhiyun ret = lt6911uxc->hdl.error;
1122*4882a593Smuzhiyun v4l2_err(sd, "cfg v4l2 ctrls failed! ret:%d\n", ret);
1123*4882a593Smuzhiyun return ret;
1124*4882a593Smuzhiyun }
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun if (lt6911uxc_update_controls(sd)) {
1127*4882a593Smuzhiyun ret = -ENODEV;
1128*4882a593Smuzhiyun v4l2_err(sd, "update v4l2 ctrls failed! ret:%d\n", ret);
1129*4882a593Smuzhiyun return ret;
1130*4882a593Smuzhiyun }
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun return 0;
1133*4882a593Smuzhiyun }
1134*4882a593Smuzhiyun
lt6911uxc_check_chip_id(struct lt6911uxc * lt6911uxc)1135*4882a593Smuzhiyun static int lt6911uxc_check_chip_id(struct lt6911uxc *lt6911uxc)
1136*4882a593Smuzhiyun {
1137*4882a593Smuzhiyun struct device *dev = <6911uxc->i2c_client->dev;
1138*4882a593Smuzhiyun struct v4l2_subdev *sd = <6911uxc->sd;
1139*4882a593Smuzhiyun u8 fw_a, fw_b, fw_c, fw_d;
1140*4882a593Smuzhiyun u8 id_h, id_l;
1141*4882a593Smuzhiyun u32 chipid, fw_ver;
1142*4882a593Smuzhiyun int ret;
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun lt6911uxc_i2c_enable(sd);
1145*4882a593Smuzhiyun ret = i2c_rd8(sd, CHIPID_L, &id_l);
1146*4882a593Smuzhiyun ret |= i2c_rd8(sd, CHIPID_H, &id_h);
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun ret |= i2c_rd8(sd, FW_VER_A, &fw_a);
1149*4882a593Smuzhiyun ret |= i2c_rd8(sd, FW_VER_B, &fw_b);
1150*4882a593Smuzhiyun ret |= i2c_rd8(sd, FW_VER_C, &fw_c);
1151*4882a593Smuzhiyun ret |= i2c_rd8(sd, FW_VER_D, &fw_d);
1152*4882a593Smuzhiyun lt6911uxc_i2c_disable(sd);
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun if (!ret) {
1155*4882a593Smuzhiyun chipid = (id_h << 8) | id_l;
1156*4882a593Smuzhiyun if (chipid != LT6911UXC_CHIPID) {
1157*4882a593Smuzhiyun dev_err(dev, "chipid err, read:%#x, expect:%#x\n",
1158*4882a593Smuzhiyun chipid, LT6911UXC_CHIPID);
1159*4882a593Smuzhiyun return -EINVAL;
1160*4882a593Smuzhiyun }
1161*4882a593Smuzhiyun
1162*4882a593Smuzhiyun fw_ver = (fw_a << 24) | (fw_b << 16) | (fw_c << 8) | fw_d;
1163*4882a593Smuzhiyun dev_info(dev, "chipid ok, id:%#x, fw_ver:%#x", chipid, fw_ver);
1164*4882a593Smuzhiyun ret = 0;
1165*4882a593Smuzhiyun } else {
1166*4882a593Smuzhiyun dev_err(dev, "%s i2c trans failed!\n", __func__);
1167*4882a593Smuzhiyun }
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun return ret;
1170*4882a593Smuzhiyun }
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun #ifdef CONFIG_OF
lt6911uxc_parse_of(struct lt6911uxc * lt6911uxc)1173*4882a593Smuzhiyun static int lt6911uxc_parse_of(struct lt6911uxc *lt6911uxc)
1174*4882a593Smuzhiyun {
1175*4882a593Smuzhiyun struct device *dev = <6911uxc->i2c_client->dev;
1176*4882a593Smuzhiyun struct device_node *node = dev->of_node;
1177*4882a593Smuzhiyun struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
1178*4882a593Smuzhiyun struct device_node *ep;
1179*4882a593Smuzhiyun int ret;
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1182*4882a593Smuzhiyun <6911uxc->module_index);
1183*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1184*4882a593Smuzhiyun <6911uxc->module_facing);
1185*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1186*4882a593Smuzhiyun <6911uxc->module_name);
1187*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1188*4882a593Smuzhiyun <6911uxc->len_name);
1189*4882a593Smuzhiyun if (ret) {
1190*4882a593Smuzhiyun dev_err(dev, "could not get module information!\n");
1191*4882a593Smuzhiyun return -EINVAL;
1192*4882a593Smuzhiyun }
1193*4882a593Smuzhiyun
1194*4882a593Smuzhiyun lt6911uxc->power_gpio = devm_gpiod_get_optional(dev, "power",
1195*4882a593Smuzhiyun GPIOD_OUT_LOW);
1196*4882a593Smuzhiyun if (IS_ERR(lt6911uxc->power_gpio)) {
1197*4882a593Smuzhiyun dev_err(dev, "failed to get power gpio\n");
1198*4882a593Smuzhiyun ret = PTR_ERR(lt6911uxc->power_gpio);
1199*4882a593Smuzhiyun return ret;
1200*4882a593Smuzhiyun }
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun lt6911uxc->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1203*4882a593Smuzhiyun GPIOD_OUT_LOW);
1204*4882a593Smuzhiyun if (IS_ERR(lt6911uxc->reset_gpio)) {
1205*4882a593Smuzhiyun dev_err(dev, "failed to get reset gpio\n");
1206*4882a593Smuzhiyun ret = PTR_ERR(lt6911uxc->reset_gpio);
1207*4882a593Smuzhiyun return ret;
1208*4882a593Smuzhiyun }
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun lt6911uxc->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det",
1211*4882a593Smuzhiyun GPIOD_IN);
1212*4882a593Smuzhiyun if (IS_ERR(lt6911uxc->plugin_det_gpio)) {
1213*4882a593Smuzhiyun dev_err(dev, "failed to get plugin det gpio\n");
1214*4882a593Smuzhiyun ret = PTR_ERR(lt6911uxc->plugin_det_gpio);
1215*4882a593Smuzhiyun return ret;
1216*4882a593Smuzhiyun }
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun lt6911uxc->hpd_ctl_gpio = devm_gpiod_get_optional(dev, "hpd-ctl",
1219*4882a593Smuzhiyun GPIOD_OUT_HIGH);
1220*4882a593Smuzhiyun if (IS_ERR(lt6911uxc->hpd_ctl_gpio)) {
1221*4882a593Smuzhiyun dev_err(dev, "failed to get hpd ctl gpio\n");
1222*4882a593Smuzhiyun ret = PTR_ERR(lt6911uxc->hpd_ctl_gpio);
1223*4882a593Smuzhiyun return ret;
1224*4882a593Smuzhiyun }
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1227*4882a593Smuzhiyun if (!ep) {
1228*4882a593Smuzhiyun dev_err(dev, "missing endpoint node\n");
1229*4882a593Smuzhiyun ret = -EINVAL;
1230*4882a593Smuzhiyun return ret;
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
1234*4882a593Smuzhiyun if (ret) {
1235*4882a593Smuzhiyun dev_err(dev, "failed to parse endpoint\n");
1236*4882a593Smuzhiyun goto put_node;
1237*4882a593Smuzhiyun }
1238*4882a593Smuzhiyun
1239*4882a593Smuzhiyun if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY ||
1240*4882a593Smuzhiyun endpoint.bus.mipi_csi2.num_data_lanes == 0) {
1241*4882a593Smuzhiyun dev_err(dev, "missing CSI-2 properties in endpoint\n");
1242*4882a593Smuzhiyun ret = -EINVAL;
1243*4882a593Smuzhiyun goto free_endpoint;
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun lt6911uxc->xvclk = devm_clk_get(dev, "xvclk");
1247*4882a593Smuzhiyun if (IS_ERR(lt6911uxc->xvclk)) {
1248*4882a593Smuzhiyun dev_err(dev, "failed to get xvclk\n");
1249*4882a593Smuzhiyun ret = -EINVAL;
1250*4882a593Smuzhiyun goto free_endpoint;
1251*4882a593Smuzhiyun }
1252*4882a593Smuzhiyun
1253*4882a593Smuzhiyun ret = clk_prepare_enable(lt6911uxc->xvclk);
1254*4882a593Smuzhiyun if (ret) {
1255*4882a593Smuzhiyun dev_err(dev, "Failed! to enable xvclk\n");
1256*4882a593Smuzhiyun goto free_endpoint;
1257*4882a593Smuzhiyun }
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun lt6911uxc->csi_lanes_in_use = endpoint.bus.mipi_csi2.num_data_lanes;
1260*4882a593Smuzhiyun lt6911uxc->bus = endpoint.bus.mipi_csi2;
1261*4882a593Smuzhiyun lt6911uxc->enable_hdcp = false;
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun gpiod_set_value(lt6911uxc->hpd_ctl_gpio, 0);
1264*4882a593Smuzhiyun gpiod_set_value(lt6911uxc->power_gpio, 1);
1265*4882a593Smuzhiyun lt6911uxc_reset(lt6911uxc);
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun ret = 0;
1268*4882a593Smuzhiyun
1269*4882a593Smuzhiyun free_endpoint:
1270*4882a593Smuzhiyun v4l2_fwnode_endpoint_free(&endpoint);
1271*4882a593Smuzhiyun put_node:
1272*4882a593Smuzhiyun of_node_put(ep);
1273*4882a593Smuzhiyun return ret;
1274*4882a593Smuzhiyun }
1275*4882a593Smuzhiyun #else
lt6911uxc_parse_of(struct lt6911uxc * lt6911uxc)1276*4882a593Smuzhiyun static inline int lt6911uxc_parse_of(struct lt6911uxc *lt6911uxc)
1277*4882a593Smuzhiyun {
1278*4882a593Smuzhiyun return -ENODEV;
1279*4882a593Smuzhiyun }
1280*4882a593Smuzhiyun #endif
1281*4882a593Smuzhiyun
lt6911uxc_probe(struct i2c_client * client,const struct i2c_device_id * id)1282*4882a593Smuzhiyun static int lt6911uxc_probe(struct i2c_client *client,
1283*4882a593Smuzhiyun const struct i2c_device_id *id)
1284*4882a593Smuzhiyun {
1285*4882a593Smuzhiyun struct v4l2_dv_timings default_timing =
1286*4882a593Smuzhiyun V4L2_DV_BT_CEA_640X480P59_94;
1287*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc;
1288*4882a593Smuzhiyun struct v4l2_subdev *sd;
1289*4882a593Smuzhiyun struct device *dev = &client->dev;
1290*4882a593Smuzhiyun char facing[2];
1291*4882a593Smuzhiyun int err;
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun dev_info(dev, "driver version: %02x.%02x.%02x",
1294*4882a593Smuzhiyun DRIVER_VERSION >> 16,
1295*4882a593Smuzhiyun (DRIVER_VERSION & 0xff00) >> 8,
1296*4882a593Smuzhiyun DRIVER_VERSION & 0x00ff);
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun lt6911uxc = devm_kzalloc(dev, sizeof(struct lt6911uxc), GFP_KERNEL);
1299*4882a593Smuzhiyun if (!lt6911uxc)
1300*4882a593Smuzhiyun return -ENOMEM;
1301*4882a593Smuzhiyun
1302*4882a593Smuzhiyun sd = <6911uxc->sd;
1303*4882a593Smuzhiyun lt6911uxc->i2c_client = client;
1304*4882a593Smuzhiyun lt6911uxc->timings = default_timing;
1305*4882a593Smuzhiyun lt6911uxc->cur_mode = &supported_modes[0];
1306*4882a593Smuzhiyun lt6911uxc->mbus_fmt_code = LT6911UXC_MEDIA_BUS_FMT;
1307*4882a593Smuzhiyun
1308*4882a593Smuzhiyun err = lt6911uxc_parse_of(lt6911uxc);
1309*4882a593Smuzhiyun if (err) {
1310*4882a593Smuzhiyun v4l2_err(sd, "lt6911uxc_parse_of failed! err:%d\n", err);
1311*4882a593Smuzhiyun return err;
1312*4882a593Smuzhiyun }
1313*4882a593Smuzhiyun
1314*4882a593Smuzhiyun err = lt6911uxc_check_chip_id(lt6911uxc);
1315*4882a593Smuzhiyun if (err < 0)
1316*4882a593Smuzhiyun return err;
1317*4882a593Smuzhiyun
1318*4882a593Smuzhiyun /* after the CPU actively accesses the lt6911uxc through I2C,
1319*4882a593Smuzhiyun * a reset operation is required.
1320*4882a593Smuzhiyun */
1321*4882a593Smuzhiyun lt6911uxc_reset(lt6911uxc);
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun mutex_init(<6911uxc->confctl_mutex);
1324*4882a593Smuzhiyun err = lt6911uxc_init_v4l2_ctrls(lt6911uxc);
1325*4882a593Smuzhiyun if (err)
1326*4882a593Smuzhiyun goto err_free_hdl;
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun client->flags |= I2C_CLIENT_SCCB;
1329*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1330*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, <6911uxc_ops);
1331*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1332*4882a593Smuzhiyun #endif
1333*4882a593Smuzhiyun
1334*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1335*4882a593Smuzhiyun lt6911uxc->pad.flags = MEDIA_PAD_FL_SOURCE;
1336*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1337*4882a593Smuzhiyun err = media_entity_pads_init(&sd->entity, 1, <6911uxc->pad);
1338*4882a593Smuzhiyun if (err < 0) {
1339*4882a593Smuzhiyun v4l2_err(sd, "media entity init failed! err: %d\n", err);
1340*4882a593Smuzhiyun goto err_free_hdl;
1341*4882a593Smuzhiyun }
1342*4882a593Smuzhiyun #endif
1343*4882a593Smuzhiyun memset(facing, 0, sizeof(facing));
1344*4882a593Smuzhiyun if (strcmp(lt6911uxc->module_facing, "back") == 0)
1345*4882a593Smuzhiyun facing[0] = 'b';
1346*4882a593Smuzhiyun else
1347*4882a593Smuzhiyun facing[0] = 'f';
1348*4882a593Smuzhiyun
1349*4882a593Smuzhiyun snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1350*4882a593Smuzhiyun lt6911uxc->module_index, facing,
1351*4882a593Smuzhiyun LT6911UXC_NAME, dev_name(sd->dev));
1352*4882a593Smuzhiyun err = v4l2_async_register_subdev_sensor_common(sd);
1353*4882a593Smuzhiyun if (err < 0) {
1354*4882a593Smuzhiyun v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
1355*4882a593Smuzhiyun goto err_clean_entity;
1356*4882a593Smuzhiyun }
1357*4882a593Smuzhiyun
1358*4882a593Smuzhiyun INIT_DELAYED_WORK(<6911uxc->delayed_work_enable_hotplug,
1359*4882a593Smuzhiyun lt6911uxc_delayed_work_enable_hotplug);
1360*4882a593Smuzhiyun INIT_DELAYED_WORK(<6911uxc->delayed_work_res_change,
1361*4882a593Smuzhiyun lt6911uxc_delayed_work_res_change);
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun if (lt6911uxc->i2c_client->irq) {
1364*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "cfg lt6911uxc irq!\n");
1365*4882a593Smuzhiyun err = devm_request_threaded_irq(dev,
1366*4882a593Smuzhiyun lt6911uxc->i2c_client->irq,
1367*4882a593Smuzhiyun NULL, lt6911uxc_res_change_irq_handler,
1368*4882a593Smuzhiyun IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1369*4882a593Smuzhiyun "lt6911uxc", lt6911uxc);
1370*4882a593Smuzhiyun if (err) {
1371*4882a593Smuzhiyun v4l2_err(sd, "request irq failed! err:%d\n", err);
1372*4882a593Smuzhiyun goto err_work_queues;
1373*4882a593Smuzhiyun }
1374*4882a593Smuzhiyun } else {
1375*4882a593Smuzhiyun err = -EINVAL;
1376*4882a593Smuzhiyun v4l2_err(sd, "no irq cfg failed!\n");
1377*4882a593Smuzhiyun goto err_work_queues;
1378*4882a593Smuzhiyun }
1379*4882a593Smuzhiyun
1380*4882a593Smuzhiyun lt6911uxc->plugin_irq = gpiod_to_irq(lt6911uxc->plugin_det_gpio);
1381*4882a593Smuzhiyun if (lt6911uxc->plugin_irq < 0)
1382*4882a593Smuzhiyun dev_err(dev, "failed to get plugin det irq, maybe no use\n");
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun err = devm_request_threaded_irq(dev, lt6911uxc->plugin_irq, NULL,
1385*4882a593Smuzhiyun plugin_detect_irq_handler, IRQF_TRIGGER_FALLING |
1386*4882a593Smuzhiyun IRQF_TRIGGER_RISING | IRQF_ONESHOT, "lt6911uxc",
1387*4882a593Smuzhiyun lt6911uxc);
1388*4882a593Smuzhiyun if (err)
1389*4882a593Smuzhiyun dev_err(dev, "failed to register plugin det irq (%d), maybe no use\n", err);
1390*4882a593Smuzhiyun
1391*4882a593Smuzhiyun err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1392*4882a593Smuzhiyun if (err) {
1393*4882a593Smuzhiyun v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
1394*4882a593Smuzhiyun goto err_work_queues;
1395*4882a593Smuzhiyun }
1396*4882a593Smuzhiyun
1397*4882a593Smuzhiyun lt6911uxc_config_hpd(sd);
1398*4882a593Smuzhiyun v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1399*4882a593Smuzhiyun client->addr << 1, client->adapter->name);
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun return 0;
1402*4882a593Smuzhiyun
1403*4882a593Smuzhiyun err_work_queues:
1404*4882a593Smuzhiyun cancel_delayed_work(<6911uxc->delayed_work_enable_hotplug);
1405*4882a593Smuzhiyun cancel_delayed_work(<6911uxc->delayed_work_res_change);
1406*4882a593Smuzhiyun err_clean_entity:
1407*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1408*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1409*4882a593Smuzhiyun #endif
1410*4882a593Smuzhiyun err_free_hdl:
1411*4882a593Smuzhiyun v4l2_ctrl_handler_free(<6911uxc->hdl);
1412*4882a593Smuzhiyun mutex_destroy(<6911uxc->confctl_mutex);
1413*4882a593Smuzhiyun return err;
1414*4882a593Smuzhiyun }
1415*4882a593Smuzhiyun
lt6911uxc_remove(struct i2c_client * client)1416*4882a593Smuzhiyun static int lt6911uxc_remove(struct i2c_client *client)
1417*4882a593Smuzhiyun {
1418*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1419*4882a593Smuzhiyun struct lt6911uxc *lt6911uxc = to_state(sd);
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun cancel_delayed_work_sync(<6911uxc->delayed_work_enable_hotplug);
1422*4882a593Smuzhiyun cancel_delayed_work_sync(<6911uxc->delayed_work_res_change);
1423*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
1424*4882a593Smuzhiyun v4l2_device_unregister_subdev(sd);
1425*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1426*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1427*4882a593Smuzhiyun #endif
1428*4882a593Smuzhiyun v4l2_ctrl_handler_free(<6911uxc->hdl);
1429*4882a593Smuzhiyun mutex_destroy(<6911uxc->confctl_mutex);
1430*4882a593Smuzhiyun clk_disable_unprepare(lt6911uxc->xvclk);
1431*4882a593Smuzhiyun
1432*4882a593Smuzhiyun return 0;
1433*4882a593Smuzhiyun }
1434*4882a593Smuzhiyun
1435*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1436*4882a593Smuzhiyun static const struct of_device_id lt6911uxc_of_match[] = {
1437*4882a593Smuzhiyun { .compatible = "lontium,lt6911uxc" },
1438*4882a593Smuzhiyun {},
1439*4882a593Smuzhiyun };
1440*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, lt6911uxc_of_match);
1441*4882a593Smuzhiyun #endif
1442*4882a593Smuzhiyun
1443*4882a593Smuzhiyun static struct i2c_driver lt6911uxc_driver = {
1444*4882a593Smuzhiyun .driver = {
1445*4882a593Smuzhiyun .name = LT6911UXC_NAME,
1446*4882a593Smuzhiyun .of_match_table = of_match_ptr(lt6911uxc_of_match),
1447*4882a593Smuzhiyun },
1448*4882a593Smuzhiyun .probe = lt6911uxc_probe,
1449*4882a593Smuzhiyun .remove = lt6911uxc_remove,
1450*4882a593Smuzhiyun };
1451*4882a593Smuzhiyun
lt6911uxc_driver_init(void)1452*4882a593Smuzhiyun static int __init lt6911uxc_driver_init(void)
1453*4882a593Smuzhiyun {
1454*4882a593Smuzhiyun return i2c_add_driver(<6911uxc_driver);
1455*4882a593Smuzhiyun }
1456*4882a593Smuzhiyun
lt6911uxc_driver_exit(void)1457*4882a593Smuzhiyun static void __exit lt6911uxc_driver_exit(void)
1458*4882a593Smuzhiyun {
1459*4882a593Smuzhiyun i2c_del_driver(<6911uxc_driver);
1460*4882a593Smuzhiyun }
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun late_initcall(lt6911uxc_driver_init);
1463*4882a593Smuzhiyun module_exit(lt6911uxc_driver_exit);
1464*4882a593Smuzhiyun
1465*4882a593Smuzhiyun MODULE_DESCRIPTION("Lontium LT6911UXC HDMI to MIPI CSI-2 bridge driver");
1466*4882a593Smuzhiyun MODULE_AUTHOR("Dingxian Wen <shawn.wen@rock-chips.com>");
1467*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1468