1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * jx_h65 driver
4 *
5 * Copyright (C) 2019 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 add enum_frame_interval function.
9 * V0.0X01.0X03 add quick stream on/off
10 * V0.0X01.0X04 add function g_mbus_config
11 */
12
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/rk-camera-module.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/sysfs.h>
23 #include <media/media-entity.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-subdev.h>
27 #include <linux/version.h>
28
29 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
30
31 #ifndef V4L2_CID_DIGITAL_GAIN
32 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
33 #endif
34
35 #define JX_H65_XVCLK_FREQ 24000000
36
37 #define CHIP_ID_H 0x0A
38 #define CHIP_ID_L 0x65
39 #define JX_H65_PIDH_ADDR 0x0a
40 #define JX_H65_PIDL_ADDR 0x0b
41
42 #define JX_H65_REG_CTRL_MODE 0x12
43 #define JX_H65_MODE_SW_STANDBY 0x40
44 #define JX_H65_MODE_STREAMING 0x00
45
46 #define JX_H65_AEC_PK_LONG_EXPO_HIGH_REG 0x02 /* Exposure Bits 8-15 */
47 #define JX_H65_AEC_PK_LONG_EXPO_LOW_REG 0x01 /* Exposure Bits 0-7 */
48 #define JX_H65_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
49 #define JX_H65_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
50 #define JX_H65_EXPOSURE_MIN 4
51 #define JX_H65_EXPOSURE_STEP 1
52 #define JX_H65_VTS_MAX 0xffff
53
54 #define JX_H65_AEC_PK_LONG_GAIN_REG 0x00 /* Bits 0 -7 */
55 #define ANALOG_GAIN_MIN 0x00
56 #define ANALOG_GAIN_MAX 0x7f
57 #define ANALOG_GAIN_STEP 1
58 #define ANALOG_GAIN_DEFAULT 0x0
59
60 #define JX_H65_DIGI_GAIN_L_MASK 0x3f
61 #define JX_H65_DIGI_GAIN_H_SHIFT 6
62 #define JX_H65_DIGI_GAIN_MIN 0
63 #define JX_H65_DIGI_GAIN_MAX (0x4000 - 1)
64 #define JX_H65_DIGI_GAIN_STEP 1
65 #define JX_H65_DIGI_GAIN_DEFAULT 1024
66
67 #define JX_H65_REG_TEST_PATTERN 0x0c
68 #define JX_H65_TEST_PATTERN_ENABLE 0x80
69 #define JX_H65_TEST_PATTERN_DISABLE 0x0
70
71 #define JX_H65_REG_HIGH_VTS 0x23
72 #define JX_H65_REG_LOW_VTS 0X22
73 #define JX_H65_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
74 #define JX_H65_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
75
76 #define REG_NULL 0xFF
77 #define REG_DELAY 0xFE
78
79 #define JX_H65_NAME "jx_h65"
80
81 #define JX_H65_LANES 1
82
83 static const char * const jx_h65_supply_names[] = {
84 "vcc2v8_dvp", /* Analog power */
85 "vcc1v8_dvp", /* Digital I/O power */
86 "vdd1v5_dvp", /* Digital core power */
87 };
88
89 #define JX_H65_NUM_SUPPLIES ARRAY_SIZE(jx_h65_supply_names)
90
91 struct regval {
92 u16 addr;
93 u8 val;
94 };
95
96 struct jx_h65_mode {
97 u32 width;
98 u32 height;
99 struct v4l2_fract max_fps;
100 u32 hts_def;
101 u32 vts_def;
102 u32 exp_def;
103 const struct regval *reg_list;
104 };
105
106 struct jx_h65 {
107 struct i2c_client *client;
108 struct clk *xvclk;
109 struct gpio_desc *reset_gpio;
110 struct gpio_desc *pwdn_gpio;
111 struct regulator_bulk_data supplies[JX_H65_NUM_SUPPLIES];
112 struct v4l2_subdev subdev;
113 struct media_pad pad;
114 struct v4l2_ctrl_handler ctrl_handler;
115 struct v4l2_ctrl *exposure;
116 struct v4l2_ctrl *anal_gain;
117 struct v4l2_ctrl *digi_gain;
118 struct v4l2_ctrl *hblank;
119 struct v4l2_ctrl *vblank;
120 struct v4l2_ctrl *test_pattern;
121 struct mutex mutex;
122 bool streaming;
123 bool power_on;
124 const struct jx_h65_mode *cur_mode;
125 u32 module_index;
126 const char *module_facing;
127 const char *module_name;
128 const char *len_name;
129 };
130
131 #define to_jx_h65(sd) container_of(sd, struct jx_h65, subdev)
132
133 /*
134 * Xclk 24Mhz
135 * Pclk 45Mhz
136 * linelength 672(0x2a0)
137 * framelength 2232(0x8b8)
138 * grabwindow_width 1280
139 * grabwindow_height 720
140 * max_framerate 30fps
141 * mipi_datarate per lane 216Mbps
142 */
143
144 static const struct regval jx_h65_1280x720_regs[] = {
145 {0x12, 0x40},
146 {0x0E, 0x11},
147 {0x0F, 0x04},
148 {0x10, 0x24},
149 {0x11, 0x80},
150 {0x5F, 0x01},
151 {0x60, 0x10},
152 {0x19, 0x64},
153 {0x48, 0x25},
154 {0x20, 0xD0},
155 {0x21, 0x02},
156 {0x22, 0xE8},
157 {0x23, 0x03},
158 {0x24, 0x80},
159 {0x25, 0xD0},
160 {0x26, 0x22},
161 {0x27, 0x5C},
162 {0x28, 0x1A},
163 {0x29, 0x01},
164 {0x2A, 0x48},
165 {0x2B, 0x25},
166 {0x2C, 0x00},
167 {0x2D, 0x1F},
168 {0x2E, 0xF9},
169 {0x2F, 0x40},
170 {0x41, 0x90},
171 {0x42, 0x12},
172 {0x39, 0x90},
173 {0x1D, 0x00},
174 {0x1E, 0x04},
175 {0x6C, 0x40},
176 {0x70, 0x89},
177 {0x71, 0x8A},
178 {0x72, 0x68},
179 {0x73, 0x33},
180 {0x74, 0x52},
181 {0x75, 0x2B},
182 {0x76, 0x40},
183 {0x77, 0x06},
184 {0x78, 0x0E},
185 {0x6E, 0x2C},
186 {0x1F, 0x10},
187 {0x31, 0x0C},
188 {0x32, 0x20},
189 {0x33, 0x0C},
190 {0x34, 0x4F},
191 {0x36, 0x06},
192 {0x38, 0x39},
193 {0x3A, 0x08},
194 {0x3B, 0x50},
195 {0x3C, 0xA0},
196 {0x3D, 0x00},
197 {0x3E, 0x01},
198 {0x3F, 0x00},
199 {0x40, 0x00},
200 {0x0D, 0x50},
201 {0x5A, 0x43},
202 {0x5B, 0xB3},
203 {0x5C, 0x0C},
204 {0x5D, 0x7E},
205 {0x5E, 0x24},
206 {0x62, 0x40},
207 {0x67, 0x48},
208 {0x6A, 0x11},
209 {0x68, 0x00},
210 {0x8F, 0x9F},
211 {0x0C, 0x00},
212 {0x59, 0x97},
213 {0x4A, 0x05},
214 {0x50, 0x03},
215 {0x47, 0x62},
216 {0x7E, 0xCD},
217 {0x8D, 0x87},
218 {0x49, 0x10},
219 {0x7F, 0x52},
220 {0x8E, 0x00},
221 {0x8C, 0xFF},
222 {0x8B, 0x01},
223 {0x57, 0x02},
224 {0x94, 0x00},
225 {0x95, 0x00},
226 {0x63, 0x80},
227 {0x7B, 0x46},
228 {0x7C, 0x2D},
229 {0x90, 0x00},
230 {0x79, 0x00},
231 {0x13, 0x81},
232 {0x45, 0x89},
233 {0x93, 0x68},
234 {REG_DELAY, 0x00},
235 {0x45, 0x19},
236 {0x1F, 0x11},
237 {0x17, 0x00},
238 {0x16, 0x77},
239 {REG_NULL, 0x00}
240 };
241
242 static const struct regval jx_h65_1280x960_regs[] = {
243 {0x12, 0x40},
244 {0x0E, 0x11},
245 {0x0F, 0x04},
246 {0x10, 0x24},
247 {0x11, 0x80},
248 {0x5F, 0x01},
249 {0x60, 0x10},
250 {0x19, 0x64},
251 {0x48, 0x25},
252 {0x20, 0xD0},
253 {0x21, 0x02},
254 {0x22, 0xE8},
255 {0x23, 0x03},
256 {0x24, 0x80},
257 {0x25, 0xC0},
258 {0x26, 0x32},
259 {0x27, 0x5C},
260 {0x28, 0x1C},
261 {0x29, 0x01},
262 {0x2A, 0x48},
263 {0x2B, 0x25},
264 {0x2C, 0x00},
265 {0x2D, 0x00},
266 {0x2E, 0xF9},
267 {0x2F, 0x40},
268 {0x41, 0x90},
269 {0x42, 0x12},
270 {0x39, 0x90},
271 {0x1D, 0x00},
272 {0x1E, 0x04},
273 {0x6C, 0x40},
274 {0x70, 0x89},
275 {0x71, 0x8A},
276 {0x72, 0x68},
277 {0x73, 0x53},
278 {0x74, 0x52},
279 {0x75, 0x2B},
280 {0x76, 0x40},
281 {0x77, 0x06},
282 {0x78, 0x0E},
283 {0x6E, 0x2C},
284 {0x1F, 0x10},
285 {0x31, 0x0C},
286 {0x32, 0x20},
287 {0x33, 0x0C},
288 {0x34, 0x4F},
289 {0x36, 0x06},
290 {0x38, 0x39},
291 {0x3A, 0x08},
292 {0x3B, 0x50},
293 {0x3C, 0xA0},
294 {0x3D, 0x00},
295 {0x3E, 0x01},
296 {0x3F, 0x00},
297 {0x40, 0x00},
298 {0x0D, 0x50},
299 {0x5A, 0x43},
300 {0x5B, 0xB3},
301 {0x5C, 0x0C},
302 {0x5D, 0x7E},
303 {0x5E, 0x24},
304 {0x62, 0x40},
305 {0x67, 0x48},
306 {0x6A, 0x11},
307 {0x68, 0x00},
308 {0x8F, 0x9F},
309 {0x0C, 0x00},
310 {0x59, 0x97},
311 {0x4A, 0x05},
312 {0x50, 0x03},
313 {0x47, 0x62},
314 {0x7E, 0xCD},
315 {0x8D, 0x87},
316 {0x49, 0x10},
317 {0x7F, 0x52},
318 {0x8E, 0x00},
319 {0x8C, 0xFF},
320 {0x8B, 0x01},
321 {0x57, 0x02},
322 {0x94, 0x00},
323 {0x95, 0x00},
324 {0x63, 0x80},
325 {0x7B, 0x46},
326 {0x7C, 0x2D},
327 {0x90, 0x00},
328 {0x79, 0x00},
329 {0x13, 0x81},
330 {0x12, 0x00},
331 {0x45, 0x89},
332 {0x93, 0x68},
333 {REG_DELAY, 0x00},
334 {0x45, 0x19},
335 {0x1F, 0x01},
336 {REG_NULL, 0x00}
337 };
338
339 static const struct jx_h65_mode supported_modes[] = {
340 {
341 .width = 1280,
342 .height = 960,
343 .max_fps = {
344 .numerator = 10000,
345 .denominator = 300000,
346 },
347 .exp_def = 0x0384,
348 .hts_def = 0x02d0,
349 .vts_def = 0x03e8,
350 .reg_list = jx_h65_1280x960_regs,
351 },
352 {
353 .width = 1280,
354 .height = 720,
355 .max_fps = {
356 .numerator = 10000,
357 .denominator = 300000,
358 },
359 .exp_def = 0x0384,
360 .hts_def = 0x02d0,
361 .vts_def = 0x03e8,
362 .reg_list = jx_h65_1280x720_regs,
363 }
364 };
365
366 #define JX_H65_LINK_FREQ_420MHZ 216000000
367 #define JX_H65_PIXEL_RATE (JX_H65_LINK_FREQ_420MHZ * 2 * 1 / 10)
368 static const s64 link_freq_menu_items[] = {
369 JX_H65_LINK_FREQ_420MHZ
370 };
371
372 static const char * const jx_h65_test_pattern_menu[] = {
373 "Disabled",
374 "Vertical Color Bar Type 1",
375 "Vertical Color Bar Type 2",
376 "Vertical Color Bar Type 3",
377 "Vertical Color Bar Type 4"
378 };
379
380 /* Calculate the delay in us by clock rate and clock cycles */
jx_h65_cal_delay(u32 cycles)381 static inline u32 jx_h65_cal_delay(u32 cycles)
382 {
383 return DIV_ROUND_UP(cycles, JX_H65_XVCLK_FREQ / 1000 / 1000);
384 }
385
jx_h65_write_reg(struct i2c_client * client,u8 reg,u8 val)386 static int jx_h65_write_reg(struct i2c_client *client, u8 reg, u8 val)
387 {
388 struct i2c_msg msg;
389 u8 buf[2];
390 int ret;
391
392 buf[0] = reg & 0xFF;
393 buf[1] = val;
394
395 msg.addr = client->addr;
396 msg.flags = client->flags;
397 msg.buf = buf;
398 msg.len = sizeof(buf);
399
400 ret = i2c_transfer(client->adapter, &msg, 1);
401 if (ret >= 0)
402 return 0;
403
404 dev_err(&client->dev,
405 "jx_h65 write reg(0x%x val:0x%x) failed !\n", reg, val);
406
407 return ret;
408 }
409
jx_h65_write_array(struct i2c_client * client,const struct regval * regs)410 static int jx_h65_write_array(struct i2c_client *client,
411 const struct regval *regs)
412 {
413 u32 i, delay_us;
414 int ret = 0;
415
416 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
417 if (regs[i].addr == REG_DELAY) {
418 delay_us = jx_h65_cal_delay(500 * 1000);
419 usleep_range(delay_us, delay_us * 2);
420 } else {
421 ret = jx_h65_write_reg(client,
422 regs[i].addr, regs[i].val);
423 }
424 }
425
426 return ret;
427 }
428
jx_h65_read_reg(struct i2c_client * client,u8 reg,u8 * val)429 static int jx_h65_read_reg(struct i2c_client *client, u8 reg, u8 *val)
430 {
431 struct i2c_msg msg[2];
432 u8 buf[1];
433 int ret;
434
435 buf[0] = reg & 0xFF;
436
437 msg[0].addr = client->addr;
438 msg[0].flags = client->flags;
439 msg[0].buf = buf;
440 msg[0].len = sizeof(buf);
441
442 msg[1].addr = client->addr;
443 msg[1].flags = client->flags | I2C_M_RD;
444 msg[1].buf = buf;
445 msg[1].len = 1;
446
447 ret = i2c_transfer(client->adapter, msg, 2);
448 if (ret >= 0) {
449 *val = buf[0];
450 return 0;
451 }
452
453 dev_err(&client->dev,
454 "jx_h65 read reg:0x%x failed !\n", reg);
455
456 return ret;
457 }
458
jx_h65_get_reso_dist(const struct jx_h65_mode * mode,struct v4l2_mbus_framefmt * framefmt)459 static int jx_h65_get_reso_dist(const struct jx_h65_mode *mode,
460 struct v4l2_mbus_framefmt *framefmt)
461 {
462 return abs(mode->width - framefmt->width) +
463 abs(mode->height - framefmt->height);
464 }
465
466 static const struct jx_h65_mode *
jx_h65_find_best_fit(struct v4l2_subdev_format * fmt)467 jx_h65_find_best_fit(struct v4l2_subdev_format *fmt)
468 {
469 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
470 int dist;
471 int cur_best_fit = 0;
472 int cur_best_fit_dist = -1;
473 unsigned int i;
474
475 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
476 dist = jx_h65_get_reso_dist(&supported_modes[i], framefmt);
477 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
478 cur_best_fit_dist = dist;
479 cur_best_fit = i;
480 }
481 }
482
483 return &supported_modes[cur_best_fit];
484 }
485
jx_h65_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)486 static int jx_h65_set_fmt(struct v4l2_subdev *sd,
487 struct v4l2_subdev_pad_config *cfg,
488 struct v4l2_subdev_format *fmt)
489 {
490 struct jx_h65 *jx_h65 = to_jx_h65(sd);
491 const struct jx_h65_mode *mode;
492 s64 h_blank, vblank_def;
493
494 mutex_lock(&jx_h65->mutex);
495
496 mode = jx_h65_find_best_fit(fmt);
497 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
498 fmt->format.width = mode->width;
499 fmt->format.height = mode->height;
500 fmt->format.field = V4L2_FIELD_NONE;
501 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
502 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
503 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
504 #else
505 mutex_unlock(&jx_h65->mutex);
506 return -ENOTTY;
507 #endif
508 } else {
509 jx_h65->cur_mode = mode;
510 h_blank = mode->hts_def - mode->width;
511 __v4l2_ctrl_modify_range(jx_h65->hblank, h_blank,
512 h_blank, 1, h_blank);
513 vblank_def = mode->vts_def - mode->height;
514 __v4l2_ctrl_modify_range(jx_h65->vblank, vblank_def,
515 JX_H65_VTS_MAX - mode->height,
516 1, vblank_def);
517 }
518
519 mutex_unlock(&jx_h65->mutex);
520
521 return 0;
522 }
523
jx_h65_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)524 static int jx_h65_get_fmt(struct v4l2_subdev *sd,
525 struct v4l2_subdev_pad_config *cfg,
526 struct v4l2_subdev_format *fmt)
527 {
528 struct jx_h65 *jx_h65 = to_jx_h65(sd);
529 const struct jx_h65_mode *mode = jx_h65->cur_mode;
530
531 mutex_lock(&jx_h65->mutex);
532 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
533 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
534 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
535 #else
536 mutex_unlock(&jx_h65->mutex);
537 return -ENOTTY;
538 #endif
539 } else {
540 fmt->format.width = mode->width;
541 fmt->format.height = mode->height;
542 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
543 fmt->format.field = V4L2_FIELD_NONE;
544 }
545 mutex_unlock(&jx_h65->mutex);
546
547 return 0;
548 }
549
jx_h65_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)550 static int jx_h65_enum_mbus_code(struct v4l2_subdev *sd,
551 struct v4l2_subdev_pad_config *cfg,
552 struct v4l2_subdev_mbus_code_enum *code)
553 {
554 if (code->index != 0)
555 return -EINVAL;
556 code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
557
558 return 0;
559 }
560
jx_h65_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)561 static int jx_h65_enum_frame_sizes(struct v4l2_subdev *sd,
562 struct v4l2_subdev_pad_config *cfg,
563 struct v4l2_subdev_frame_size_enum *fse)
564 {
565 if (fse->index >= ARRAY_SIZE(supported_modes))
566 return -EINVAL;
567
568 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
569 return -EINVAL;
570
571 fse->min_width = supported_modes[fse->index].width;
572 fse->max_width = supported_modes[fse->index].width;
573 fse->max_height = supported_modes[fse->index].height;
574 fse->min_height = supported_modes[fse->index].height;
575
576 return 0;
577 }
578
jx_h65_enable_test_pattern(struct jx_h65 * jx_h65,u32 pattern)579 static int jx_h65_enable_test_pattern(struct jx_h65 *jx_h65, u32 pattern)
580 {
581 u32 val;
582
583 if (pattern)
584 val = (pattern - 1) | JX_H65_TEST_PATTERN_ENABLE;
585 else
586 val = JX_H65_TEST_PATTERN_DISABLE;
587
588 return jx_h65_write_reg(jx_h65->client, JX_H65_REG_TEST_PATTERN, val);
589 }
590
jx_h65_get_module_inf(struct jx_h65 * jx_h65,struct rkmodule_inf * inf)591 static void jx_h65_get_module_inf(struct jx_h65 *jx_h65,
592 struct rkmodule_inf *inf)
593 {
594 memset(inf, 0, sizeof(*inf));
595 strlcpy(inf->base.sensor, JX_H65_NAME, sizeof(inf->base.sensor));
596 strlcpy(inf->base.module, jx_h65->module_name,
597 sizeof(inf->base.module));
598 strlcpy(inf->base.lens, jx_h65->len_name, sizeof(inf->base.lens));
599 }
600
jx_h65_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)601 static long jx_h65_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
602 {
603 struct jx_h65 *jx_h65 = to_jx_h65(sd);
604 long ret = 0;
605 u32 stream = 0;
606
607 switch (cmd) {
608 case RKMODULE_GET_MODULE_INFO:
609 jx_h65_get_module_inf(jx_h65, (struct rkmodule_inf *)arg);
610 break;
611 case RKMODULE_SET_QUICK_STREAM:
612
613 stream = *((u32 *)arg);
614
615 if (stream)
616 ret = jx_h65_write_reg(jx_h65->client, JX_H65_REG_CTRL_MODE,
617 JX_H65_MODE_STREAMING);
618 else
619 ret = jx_h65_write_reg(jx_h65->client, JX_H65_REG_CTRL_MODE,
620 JX_H65_MODE_SW_STANDBY);
621 break;
622 default:
623 ret = -ENOIOCTLCMD;
624 break;
625 }
626
627 return ret;
628 }
629
630 #ifdef CONFIG_COMPAT
jx_h65_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)631 static long jx_h65_compat_ioctl32(struct v4l2_subdev *sd,
632 unsigned int cmd, unsigned long arg)
633 {
634 void __user *up = compat_ptr(arg);
635 struct rkmodule_inf *inf;
636 struct rkmodule_awb_cfg *cfg;
637 long ret;
638 u32 stream = 0;
639
640 switch (cmd) {
641 case RKMODULE_GET_MODULE_INFO:
642 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
643 if (!inf) {
644 ret = -ENOMEM;
645 return ret;
646 }
647
648 ret = jx_h65_ioctl(sd, cmd, inf);
649 if (!ret)
650 ret = copy_to_user(up, inf, sizeof(*inf));
651 kfree(inf);
652 break;
653 case RKMODULE_AWB_CFG:
654 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
655 if (!cfg) {
656 ret = -ENOMEM;
657 return ret;
658 }
659
660 ret = copy_from_user(cfg, up, sizeof(*cfg));
661 if (!ret)
662 ret = jx_h65_ioctl(sd, cmd, cfg);
663 kfree(cfg);
664 break;
665 case RKMODULE_SET_QUICK_STREAM:
666 ret = copy_from_user(&stream, up, sizeof(u32));
667 if (!ret)
668 ret = jx_h65_ioctl(sd, cmd, &stream);
669 break;
670 default:
671 ret = -ENOIOCTLCMD;
672 break;
673 }
674
675 return ret;
676 }
677 #endif
678
jx_h65_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)679 static int jx_h65_g_frame_interval(struct v4l2_subdev *sd,
680 struct v4l2_subdev_frame_interval *fi)
681 {
682 struct jx_h65 *jx_h65 = to_jx_h65(sd);
683 const struct jx_h65_mode *mode = jx_h65->cur_mode;
684
685 mutex_lock(&jx_h65->mutex);
686 fi->interval = mode->max_fps;
687 mutex_unlock(&jx_h65->mutex);
688
689 return 0;
690 }
691
__jx_h65_start_stream(struct jx_h65 * jx_h65)692 static int __jx_h65_start_stream(struct jx_h65 *jx_h65)
693 {
694 return jx_h65_write_reg(jx_h65->client, JX_H65_REG_CTRL_MODE,
695 JX_H65_MODE_STREAMING);
696 }
697
__jx_h65_stop_stream(struct jx_h65 * jx_h65)698 static int __jx_h65_stop_stream(struct jx_h65 *jx_h65)
699 {
700 return jx_h65_write_reg(jx_h65->client, JX_H65_REG_CTRL_MODE,
701 JX_H65_MODE_SW_STANDBY);
702 }
703
jx_h65_s_stream(struct v4l2_subdev * sd,int on)704 static int jx_h65_s_stream(struct v4l2_subdev *sd, int on)
705 {
706 struct jx_h65 *jx_h65 = to_jx_h65(sd);
707 struct i2c_client *client = jx_h65->client;
708 int ret = 0;
709
710 mutex_lock(&jx_h65->mutex);
711 on = !!on;
712 if (on == jx_h65->streaming)
713 goto unlock_and_return;
714
715 if (on) {
716 ret = pm_runtime_get_sync(&client->dev);
717 if (ret < 0) {
718 pm_runtime_put_noidle(&client->dev);
719 goto unlock_and_return;
720 }
721
722 ret = __jx_h65_start_stream(jx_h65);
723 if (ret) {
724 v4l2_err(sd, "start stream failed while write regs\n");
725 pm_runtime_put(&client->dev);
726 goto unlock_and_return;
727 }
728 } else {
729 __jx_h65_stop_stream(jx_h65);
730 pm_runtime_put(&client->dev);
731 }
732
733 jx_h65->streaming = on;
734
735 unlock_and_return:
736 mutex_unlock(&jx_h65->mutex);
737
738 return ret;
739 }
740
jx_h65_s_power(struct v4l2_subdev * sd,int on)741 static int jx_h65_s_power(struct v4l2_subdev *sd, int on)
742 {
743 struct jx_h65 *jx_h65 = to_jx_h65(sd);
744 struct i2c_client *client = jx_h65->client;
745 int ret = 0;
746
747 mutex_lock(&jx_h65->mutex);
748
749 /* If the power state is not modified - no work to do. */
750 if (jx_h65->power_on == !!on)
751 goto unlock_and_return;
752
753 if (on) {
754 ret = pm_runtime_get_sync(&client->dev);
755 if (ret < 0) {
756 pm_runtime_put_noidle(&client->dev);
757 goto unlock_and_return;
758 }
759
760 ret = jx_h65_write_array(jx_h65->client,
761 jx_h65->cur_mode->reg_list);
762 if (ret)
763 goto unlock_and_return;
764
765 /*
766 * Enter sleep state to make sure not mipi output
767 * during rkisp init.
768 */
769 __jx_h65_stop_stream(jx_h65);
770
771 mutex_unlock(&jx_h65->mutex);
772 /* In case these controls are set before streaming */
773 ret = v4l2_ctrl_handler_setup(&jx_h65->ctrl_handler);
774 if (ret)
775 return ret;
776 mutex_lock(&jx_h65->mutex);
777
778 jx_h65->power_on = true;
779 } else {
780 pm_runtime_put(&client->dev);
781 jx_h65->power_on = false;
782 }
783
784 unlock_and_return:
785 mutex_unlock(&jx_h65->mutex);
786
787 return ret;
788 }
789
__jx_h65_power_on(struct jx_h65 * jx_h65)790 static int __jx_h65_power_on(struct jx_h65 *jx_h65)
791 {
792 int ret;
793 u32 delay_us;
794 struct device *dev = &jx_h65->client->dev;
795
796 ret = clk_set_rate(jx_h65->xvclk, JX_H65_XVCLK_FREQ);
797 if (ret < 0) {
798 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
799 return ret;
800 }
801 if (clk_get_rate(jx_h65->xvclk) != JX_H65_XVCLK_FREQ)
802 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
803 ret = clk_prepare_enable(jx_h65->xvclk);
804 if (ret < 0) {
805 dev_err(dev, "Failed to enable xvclk\n");
806 return ret;
807 }
808
809 if (!IS_ERR(jx_h65->reset_gpio))
810 gpiod_set_value_cansleep(jx_h65->reset_gpio, 1);
811
812 ret = regulator_bulk_enable(JX_H65_NUM_SUPPLIES, jx_h65->supplies);
813 if (ret < 0) {
814 dev_err(dev, "Failed to enable regulators\n");
815 goto disable_clk;
816 }
817
818 /* According to datasheet, at least 10ms for reset duration */
819 usleep_range(10 * 1000, 15 * 1000);
820
821 if (!IS_ERR(jx_h65->reset_gpio))
822 gpiod_set_value_cansleep(jx_h65->reset_gpio, 0);
823
824 if (!IS_ERR(jx_h65->pwdn_gpio))
825 gpiod_set_value_cansleep(jx_h65->pwdn_gpio, 0);
826
827 /* 8192 cycles prior to first SCCB transaction */
828 delay_us = jx_h65_cal_delay(8192);
829 usleep_range(delay_us, delay_us * 2);
830
831 return 0;
832
833 disable_clk:
834 clk_disable_unprepare(jx_h65->xvclk);
835
836 return ret;
837 }
838
__jx_h65_power_off(struct jx_h65 * jx_h65)839 static void __jx_h65_power_off(struct jx_h65 *jx_h65)
840 {
841 if (!IS_ERR(jx_h65->pwdn_gpio))
842 gpiod_set_value_cansleep(jx_h65->pwdn_gpio, 1);
843 clk_disable_unprepare(jx_h65->xvclk);
844 if (!IS_ERR(jx_h65->reset_gpio))
845 gpiod_set_value_cansleep(jx_h65->reset_gpio, 1);
846 regulator_bulk_disable(JX_H65_NUM_SUPPLIES, jx_h65->supplies);
847 }
848
jx_h65_runtime_resume(struct device * dev)849 static int jx_h65_runtime_resume(struct device *dev)
850 {
851 struct i2c_client *client = to_i2c_client(dev);
852 struct v4l2_subdev *sd = i2c_get_clientdata(client);
853 struct jx_h65 *jx_h65 = to_jx_h65(sd);
854
855 return __jx_h65_power_on(jx_h65);
856 }
857
jx_h65_runtime_suspend(struct device * dev)858 static int jx_h65_runtime_suspend(struct device *dev)
859 {
860 struct i2c_client *client = to_i2c_client(dev);
861 struct v4l2_subdev *sd = i2c_get_clientdata(client);
862 struct jx_h65 *jx_h65 = to_jx_h65(sd);
863
864 __jx_h65_power_off(jx_h65);
865
866 return 0;
867 }
868
869 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
jx_h65_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)870 static int jx_h65_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
871 {
872 struct jx_h65 *jx_h65 = to_jx_h65(sd);
873 struct v4l2_mbus_framefmt *try_fmt =
874 v4l2_subdev_get_try_format(sd, fh->pad, 0);
875 const struct jx_h65_mode *def_mode = &supported_modes[0];
876
877 mutex_lock(&jx_h65->mutex);
878 /* Initialize try_fmt */
879 try_fmt->width = def_mode->width;
880 try_fmt->height = def_mode->height;
881 try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
882 try_fmt->field = V4L2_FIELD_NONE;
883
884 mutex_unlock(&jx_h65->mutex);
885 /* No crop or compose */
886
887 return 0;
888 }
889 #endif
890
jx_h65_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)891 static int jx_h65_enum_frame_interval(struct v4l2_subdev *sd,
892 struct v4l2_subdev_pad_config *cfg,
893 struct v4l2_subdev_frame_interval_enum *fie)
894 {
895 if (fie->index >= ARRAY_SIZE(supported_modes))
896 return -EINVAL;
897
898 fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
899
900 fie->width = supported_modes[fie->index].width;
901 fie->height = supported_modes[fie->index].height;
902 fie->interval = supported_modes[fie->index].max_fps;
903 return 0;
904 }
905
jx_h65_g_mbus_config(struct v4l2_subdev * sd,struct v4l2_mbus_config * config)906 static int jx_h65_g_mbus_config(struct v4l2_subdev *sd,
907 struct v4l2_mbus_config *config)
908 {
909 u32 val = 0;
910
911 val = 1 << (JX_H65_LANES - 1) |
912 V4L2_MBUS_CSI2_CHANNEL_0 |
913 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
914 config->type = V4L2_MBUS_CSI2;
915 config->flags = val;
916
917 return 0;
918 }
919
920 static const struct dev_pm_ops jx_h65_pm_ops = {
921 SET_RUNTIME_PM_OPS(jx_h65_runtime_suspend,
922 jx_h65_runtime_resume, NULL)
923 };
924
925 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
926 static const struct v4l2_subdev_internal_ops jx_h65_internal_ops = {
927 .open = jx_h65_open,
928 };
929 #endif
930
931 static const struct v4l2_subdev_core_ops jx_h65_core_ops = {
932 .s_power = jx_h65_s_power,
933 .ioctl = jx_h65_ioctl,
934 #ifdef CONFIG_COMPAT
935 .compat_ioctl32 = jx_h65_compat_ioctl32,
936 #endif
937 };
938
939 static const struct v4l2_subdev_video_ops jx_h65_video_ops = {
940 .s_stream = jx_h65_s_stream,
941 .g_frame_interval = jx_h65_g_frame_interval,
942 .g_mbus_config = jx_h65_g_mbus_config,
943 };
944
945 static const struct v4l2_subdev_pad_ops jx_h65_pad_ops = {
946 .enum_mbus_code = jx_h65_enum_mbus_code,
947 .enum_frame_size = jx_h65_enum_frame_sizes,
948 .enum_frame_interval = jx_h65_enum_frame_interval,
949 .get_fmt = jx_h65_get_fmt,
950 .set_fmt = jx_h65_set_fmt,
951 };
952
953 static const struct v4l2_subdev_ops jx_h65_subdev_ops = {
954 .core = &jx_h65_core_ops,
955 .video = &jx_h65_video_ops,
956 .pad = &jx_h65_pad_ops,
957 };
958
jx_h65_set_ctrl(struct v4l2_ctrl * ctrl)959 static int jx_h65_set_ctrl(struct v4l2_ctrl *ctrl)
960 {
961 struct jx_h65 *jx_h65 = container_of(ctrl->handler,
962 struct jx_h65, ctrl_handler);
963 struct i2c_client *client = jx_h65->client;
964 s64 max;
965 int ret = 0;
966
967 /* Propagate change of current control to all related controls */
968 switch (ctrl->id) {
969 case V4L2_CID_VBLANK:
970 /* Update max exposure while meeting expected vblanking */
971 max = jx_h65->cur_mode->height + ctrl->val;
972 __v4l2_ctrl_modify_range(jx_h65->exposure,
973 jx_h65->exposure->minimum, max,
974 jx_h65->exposure->step,
975 jx_h65->exposure->default_value);
976 break;
977 }
978
979 if (!pm_runtime_get_if_in_use(&client->dev))
980 return 0;
981
982 switch (ctrl->id) {
983 case V4L2_CID_EXPOSURE:
984 dev_dbg(&client->dev, "set expo: val: %d\n", ctrl->val);
985 /* 4 least significant bits of expsoure are fractional part */
986 ret = jx_h65_write_reg(jx_h65->client,
987 JX_H65_AEC_PK_LONG_EXPO_HIGH_REG,
988 JX_H65_FETCH_HIGH_BYTE_EXP(ctrl->val));
989 ret |= jx_h65_write_reg(jx_h65->client,
990 JX_H65_AEC_PK_LONG_EXPO_LOW_REG,
991 JX_H65_FETCH_LOW_BYTE_EXP(ctrl->val));
992 break;
993 case V4L2_CID_ANALOGUE_GAIN:
994 dev_dbg(&client->dev, "set a-gain: val: %d\n", ctrl->val);
995 ret |= jx_h65_write_reg(jx_h65->client,
996 JX_H65_AEC_PK_LONG_GAIN_REG, ctrl->val);
997 break;
998 case V4L2_CID_DIGITAL_GAIN:
999 break;
1000 case V4L2_CID_VBLANK:
1001 dev_dbg(&client->dev, "set vblank: val: %d\n", ctrl->val);
1002 ret |= jx_h65_write_reg(jx_h65->client, JX_H65_REG_HIGH_VTS,
1003 JX_H65_FETCH_HIGH_BYTE_VTS((ctrl->val + jx_h65->cur_mode->height)));
1004 ret |= jx_h65_write_reg(jx_h65->client, JX_H65_REG_LOW_VTS,
1005 JX_H65_FETCH_LOW_BYTE_VTS((ctrl->val + jx_h65->cur_mode->height)));
1006 break;
1007 case V4L2_CID_TEST_PATTERN:
1008 ret = jx_h65_enable_test_pattern(jx_h65, ctrl->val);
1009 break;
1010 default:
1011 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1012 __func__, ctrl->id, ctrl->val);
1013 break;
1014 }
1015
1016 pm_runtime_put(&client->dev);
1017
1018 return ret;
1019 }
1020
1021 static const struct v4l2_ctrl_ops jx_h65_ctrl_ops = {
1022 .s_ctrl = jx_h65_set_ctrl,
1023 };
1024
jx_h65_initialize_controls(struct jx_h65 * jx_h65)1025 static int jx_h65_initialize_controls(struct jx_h65 *jx_h65)
1026 {
1027 const struct jx_h65_mode *mode;
1028 struct v4l2_ctrl_handler *handler;
1029 struct v4l2_ctrl *ctrl;
1030 s64 exposure_max, vblank_def;
1031 u32 h_blank;
1032 int ret;
1033
1034 handler = &jx_h65->ctrl_handler;
1035 mode = jx_h65->cur_mode;
1036 ret = v4l2_ctrl_handler_init(handler, 8);
1037 if (ret)
1038 return ret;
1039 handler->lock = &jx_h65->mutex;
1040
1041 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1042 0, 0, link_freq_menu_items);
1043 if (ctrl)
1044 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1045
1046 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1047 0, JX_H65_PIXEL_RATE, 1, JX_H65_PIXEL_RATE);
1048
1049 h_blank = mode->hts_def - mode->width;
1050 jx_h65->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1051 h_blank, h_blank, 1, h_blank);
1052 if (jx_h65->hblank)
1053 jx_h65->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1054
1055 vblank_def = mode->vts_def - mode->height;
1056 jx_h65->vblank = v4l2_ctrl_new_std(handler, &jx_h65_ctrl_ops,
1057 V4L2_CID_VBLANK, vblank_def,
1058 JX_H65_VTS_MAX - mode->height,
1059 1, vblank_def);
1060
1061 exposure_max = mode->vts_def;
1062 jx_h65->exposure = v4l2_ctrl_new_std(handler, &jx_h65_ctrl_ops,
1063 V4L2_CID_EXPOSURE, JX_H65_EXPOSURE_MIN,
1064 exposure_max, JX_H65_EXPOSURE_STEP,
1065 mode->exp_def);
1066
1067 jx_h65->anal_gain = v4l2_ctrl_new_std(handler, &jx_h65_ctrl_ops,
1068 V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1069 ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1070 ANALOG_GAIN_DEFAULT);
1071
1072 /* Digital gain */
1073 jx_h65->digi_gain = v4l2_ctrl_new_std(handler, &jx_h65_ctrl_ops,
1074 V4L2_CID_DIGITAL_GAIN, JX_H65_DIGI_GAIN_MIN,
1075 JX_H65_DIGI_GAIN_MAX, JX_H65_DIGI_GAIN_STEP,
1076 JX_H65_DIGI_GAIN_DEFAULT);
1077
1078 jx_h65->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1079 &jx_h65_ctrl_ops, V4L2_CID_TEST_PATTERN,
1080 ARRAY_SIZE(jx_h65_test_pattern_menu) - 1,
1081 0, 0, jx_h65_test_pattern_menu);
1082
1083 if (handler->error) {
1084 ret = handler->error;
1085 dev_err(&jx_h65->client->dev,
1086 "Failed to init controls(%d)\n", ret);
1087 goto err_free_handler;
1088 }
1089
1090 jx_h65->subdev.ctrl_handler = handler;
1091
1092 return 0;
1093
1094 err_free_handler:
1095 v4l2_ctrl_handler_free(handler);
1096
1097 return ret;
1098 }
1099
jx_h65_check_sensor_id(struct jx_h65 * jx_h65,struct i2c_client * client)1100 static int jx_h65_check_sensor_id(struct jx_h65 *jx_h65,
1101 struct i2c_client *client)
1102 {
1103 struct device *dev = &jx_h65->client->dev;
1104 u8 id_h = 0;
1105 u8 id_l = 0;
1106 int ret;
1107
1108 ret = jx_h65_read_reg(client, JX_H65_PIDH_ADDR, &id_h);
1109 ret |= jx_h65_read_reg(client, JX_H65_PIDL_ADDR, &id_l);
1110 if (id_h != CHIP_ID_H && id_l != CHIP_ID_L) {
1111 dev_err(dev, "Wrong camera sensor id(0x%02x%02x)\n",
1112 id_h, id_l);
1113 return -EINVAL;
1114 }
1115
1116 dev_info(dev, "Detected jx_h65 (0x%02x%02x) sensor\n",
1117 id_h, id_l);
1118
1119 return ret;
1120 }
1121
jx_h65_configure_regulators(struct jx_h65 * jx_h65)1122 static int jx_h65_configure_regulators(struct jx_h65 *jx_h65)
1123 {
1124 unsigned int i;
1125
1126 for (i = 0; i < JX_H65_NUM_SUPPLIES; i++)
1127 jx_h65->supplies[i].supply = jx_h65_supply_names[i];
1128
1129 return devm_regulator_bulk_get(&jx_h65->client->dev,
1130 JX_H65_NUM_SUPPLIES,
1131 jx_h65->supplies);
1132 }
1133
jx_h65_probe(struct i2c_client * client,const struct i2c_device_id * id)1134 static int jx_h65_probe(struct i2c_client *client,
1135 const struct i2c_device_id *id)
1136 {
1137 struct device *dev = &client->dev;
1138 struct device_node *node = dev->of_node;
1139 struct jx_h65 *jx_h65;
1140 struct v4l2_subdev *sd;
1141 char facing[2];
1142 int ret;
1143
1144 dev_info(dev, "driver version: %02x.%02x.%02x",
1145 DRIVER_VERSION >> 16,
1146 (DRIVER_VERSION & 0xff00) >> 8,
1147 DRIVER_VERSION & 0x00ff);
1148
1149 jx_h65 = devm_kzalloc(dev, sizeof(*jx_h65), GFP_KERNEL);
1150 if (!jx_h65)
1151 return -ENOMEM;
1152
1153 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1154 &jx_h65->module_index);
1155 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1156 &jx_h65->module_facing);
1157 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1158 &jx_h65->module_name);
1159 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1160 &jx_h65->len_name);
1161 if (ret) {
1162 dev_err(dev, "could not get module information!\n");
1163 return -EINVAL;
1164 }
1165
1166 jx_h65->client = client;
1167 jx_h65->cur_mode = &supported_modes[0];
1168
1169 jx_h65->xvclk = devm_clk_get(dev, "xvclk");
1170 if (IS_ERR(jx_h65->xvclk)) {
1171 dev_err(dev, "Failed to get xvclk\n");
1172 return -EINVAL;
1173 }
1174
1175 jx_h65->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1176 if (IS_ERR(jx_h65->reset_gpio))
1177 dev_warn(dev, "Failed to get reset-gpios\n");
1178
1179 jx_h65->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1180 if (IS_ERR(jx_h65->pwdn_gpio))
1181 dev_warn(dev, "Failed to get pwdn-gpios\n");
1182
1183 ret = jx_h65_configure_regulators(jx_h65);
1184 if (ret) {
1185 dev_err(dev, "Failed to get power regulators\n");
1186 return ret;
1187 }
1188
1189 mutex_init(&jx_h65->mutex);
1190
1191 sd = &jx_h65->subdev;
1192 v4l2_i2c_subdev_init(sd, client, &jx_h65_subdev_ops);
1193 ret = jx_h65_initialize_controls(jx_h65);
1194 if (ret)
1195 goto err_destroy_mutex;
1196
1197 ret = __jx_h65_power_on(jx_h65);
1198 if (ret)
1199 goto err_free_handler;
1200
1201 ret = jx_h65_check_sensor_id(jx_h65, client);
1202 if (ret)
1203 goto err_power_off;
1204
1205 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1206 sd->internal_ops = &jx_h65_internal_ops;
1207 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1208 V4L2_SUBDEV_FL_HAS_EVENTS;
1209 #endif
1210 #if defined(CONFIG_MEDIA_CONTROLLER)
1211 jx_h65->pad.flags = MEDIA_PAD_FL_SOURCE;
1212 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1213 ret = media_entity_pads_init(&sd->entity, 1, &jx_h65->pad);
1214 if (ret < 0)
1215 goto err_power_off;
1216 #endif
1217
1218 memset(facing, 0, sizeof(facing));
1219 if (strcmp(jx_h65->module_facing, "back") == 0)
1220 facing[0] = 'b';
1221 else
1222 facing[0] = 'f';
1223
1224 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1225 jx_h65->module_index, facing,
1226 JX_H65_NAME, dev_name(sd->dev));
1227
1228 ret = v4l2_async_register_subdev(sd);
1229 if (ret) {
1230 dev_err(dev, "v4l2 async register subdev failed\n");
1231 goto err_clean_entity;
1232 }
1233
1234 pm_runtime_set_active(dev);
1235 pm_runtime_enable(dev);
1236 pm_runtime_idle(dev);
1237
1238 return 0;
1239
1240 err_clean_entity:
1241 #if defined(CONFIG_MEDIA_CONTROLLER)
1242 media_entity_cleanup(&sd->entity);
1243 #endif
1244 err_power_off:
1245 __jx_h65_power_off(jx_h65);
1246 err_free_handler:
1247 v4l2_ctrl_handler_free(&jx_h65->ctrl_handler);
1248 err_destroy_mutex:
1249 mutex_destroy(&jx_h65->mutex);
1250
1251 return ret;
1252 }
1253
jx_h65_remove(struct i2c_client * client)1254 static int jx_h65_remove(struct i2c_client *client)
1255 {
1256 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1257 struct jx_h65 *jx_h65 = to_jx_h65(sd);
1258
1259 v4l2_async_unregister_subdev(sd);
1260 #if defined(CONFIG_MEDIA_CONTROLLER)
1261 media_entity_cleanup(&sd->entity);
1262 #endif
1263 v4l2_ctrl_handler_free(&jx_h65->ctrl_handler);
1264 mutex_destroy(&jx_h65->mutex);
1265
1266 pm_runtime_disable(&client->dev);
1267 if (!pm_runtime_status_suspended(&client->dev))
1268 __jx_h65_power_off(jx_h65);
1269 pm_runtime_set_suspended(&client->dev);
1270
1271 return 0;
1272 }
1273
1274 #if IS_ENABLED(CONFIG_OF)
1275 static const struct of_device_id jx_h65_of_match[] = {
1276 { .compatible = "soi,jx_h65" },
1277 {},
1278 };
1279 MODULE_DEVICE_TABLE(of, jx_h65_of_match);
1280 #endif
1281
1282 static const struct i2c_device_id jx_h65_match_id[] = {
1283 { "soi,jx_h65", 0 },
1284 { },
1285 };
1286
1287 static struct i2c_driver jx_h65_i2c_driver = {
1288 .driver = {
1289 .name = JX_H65_NAME,
1290 .pm = &jx_h65_pm_ops,
1291 .of_match_table = of_match_ptr(jx_h65_of_match),
1292 },
1293 .probe = &jx_h65_probe,
1294 .remove = &jx_h65_remove,
1295 .id_table = jx_h65_match_id,
1296 };
1297
sensor_mod_init(void)1298 static int __init sensor_mod_init(void)
1299 {
1300 return i2c_add_driver(&jx_h65_i2c_driver);
1301 }
1302
sensor_mod_exit(void)1303 static void __exit sensor_mod_exit(void)
1304 {
1305 i2c_del_driver(&jx_h65_i2c_driver);
1306 }
1307
1308 device_initcall_sync(sensor_mod_init);
1309 module_exit(sensor_mod_exit);
1310
1311 MODULE_DESCRIPTION("SOI jx_h65 sensor driver");
1312 MODULE_LICENSE("GPL v2");
1313