1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * jx_f37 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 * v0.0x01.0x04 support mirror/flip
7 */
8
9 #define DEBUG
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/rk-camera-module.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/sysfs.h>
21 #include <media/media-entity.h>
22 #include <media/v4l2-async.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-subdev.h>
25 #include <linux/version.h>
26 #include <linux/rk-preisp.h>
27
28 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
29
30 #ifndef V4L2_CID_DIGITAL_GAIN
31 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
32 #endif
33
34 #define JX_F37_XVCLK_FREQ 24000000
35
36 #define JX_F37_LANES 1
37
38 #define CHIP_ID_H 0x0F
39 #define CHIP_ID_L 0x37
40 #define JX_F37_PIDH_ADDR 0x0a
41 #define JX_F37_PIDL_ADDR 0x0b
42
43 #define JX_F37_REG_CTRL_MODE 0x12
44 #define JX_F37_MODE_SLEEP_MODE BIT(6)
45
46
47 #define JX_F37_MAX_SMPL_START 0x8f
48
49 #define JX_F37_SHORT_EXPO_REG 0x05 /* Exposure Bits 8-15 */
50
51 #define JX_F37_LONG_EXPO_HIGH_REG 0x02 /* Exposure Bits 8-15 */
52 #define JX_F37_LONG_EXPO_LOW_REG 0x01 /* Exposure Bits 0-7 */
53 #define JX_F37_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
54 #define JX_F37_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
55 #define JX_F37_EXPOSURE_MIN 4
56 #define JX_F37_EXPOSURE_STEP 1
57 #define JX_F37_VTS_MAX 0xffff
58
59 #define JX_F37_SMPL_START_S_REG 0x06
60 #define JX_F37_SMPL_START_S_VAL 0x23
61
62 #define JX_F37_LONG_GAIN_REG 0x00 /* Bits 0 -7 */
63 #define ANALOG_GAIN_MIN 0x00
64 #define ANALOG_GAIN_MAX 0x3f
65 #define ANALOG_GAIN_STEP 1
66 #define ANALOG_GAIN_DEFAULT 0x0
67
68 #define JX_F37_REG_HIGH_VTS 0x23
69 #define JX_F37_REG_LOW_VTS 0X22
70 #define JX_F37_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
71 #define JX_F37_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
72
73 #define JX_F37_FLIP_MIRROR_REG 0x12
74
75 #define REG_NULL 0xFF
76 #define REG_DELAY 0xFE
77
78 #define JX_F37_NAME "jx_f37"
79
80 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
81
82 #define USED_SYS_DEBUG
83
84 static const char * const jx_f37_supply_names[] = {
85 "vcc2v8_dvp", /* Analog power */
86 "vcc1v8_dvp", /* Digital I/O power */
87 };
88
89 #define JX_F37_NUM_SUPPLIES ARRAY_SIZE(jx_f37_supply_names)
90
91 struct regval {
92 u8 addr;
93 u8 val;
94 };
95
96 struct jx_f37_mode {
97 u32 width;
98 u32 height;
99 struct v4l2_fract max_fps;
100 u32 hts_def;
101 u32 vts_def;
102 u32 exp_def;
103 const struct regval *reg_list;
104 u32 hdr_mode;
105 u32 vc[PAD_MAX];
106 };
107
108 struct jx_f37 {
109 struct i2c_client *client;
110 struct clk *xvclk;
111 struct gpio_desc *reset_gpio;
112 struct gpio_desc *pwdn_gpio;
113 struct regulator_bulk_data supplies[JX_F37_NUM_SUPPLIES];
114 struct v4l2_subdev subdev;
115 struct media_pad pad;
116 struct v4l2_ctrl_handler ctrl_handler;
117 struct v4l2_ctrl *exposure;
118 struct v4l2_ctrl *anal_gain;
119 struct v4l2_ctrl *digi_gain;
120 struct v4l2_ctrl *hblank;
121 struct v4l2_ctrl *vblank;
122 struct mutex mutex;
123 bool streaming;
124 bool power_on;
125 const struct jx_f37_mode *cur_mode;
126 u32 module_index;
127 const char *module_facing;
128 const char *module_name;
129 const char *len_name;
130
131 bool has_init_exp;
132 struct preisp_hdrae_exp_s init_hdrae_exp;
133 };
134
135 #define to_jx_f37(sd) container_of(sd, struct jx_f37, subdev)
136
137 static const struct regval jx_f37_1080p_linear_1lane_30fps[] = {
138 {0x12, 0x60},
139 {0x48, 0x85},
140 {0x48, 0x05},
141 {0x0E, 0x11},
142 {0x0F, 0x14},
143 {0x10, 0x48},
144 {0x11, 0x80},
145 {0x0D, 0xF0},
146 {0x5F, 0x41},
147 {0x60, 0x20},
148 {0x58, 0x12},
149 {0x57, 0x60},
150 {0x9D, 0x00},
151 {0x20, 0x00},
152 {0x21, 0x05},
153 {0x22, 0x65},
154 {0x23, 0x04},
155 {0x24, 0xC0},
156 {0x25, 0x38},
157 {0x26, 0x43},
158 {0x27, 0x9A},
159 {0x28, 0x15},
160 {0x29, 0x04},
161 {0x2A, 0x8A},
162 {0x2B, 0x14},
163 {0x2C, 0x00},
164 {0x2D, 0x00},
165 {0x2E, 0x14},
166 {0x2F, 0x44},
167 {0x41, 0xC8},
168 {0x42, 0x3B},
169 {0x47, 0x42},
170 {0x76, 0x60},
171 {0x77, 0x09},
172 {0x1D, 0x00},
173 {0x1E, 0x04},
174 {0x6C, 0x50},
175 {0x6E, 0x2C},
176 {0x70, 0xD0},
177 {0x71, 0xD3},
178 {0x72, 0xD4},
179 {0x73, 0x58},
180 {0x74, 0x02},
181 {0x78, 0x96},
182 {0x89, 0x01},
183 {0x6B, 0x20},
184 {0x86, 0x40},
185 {0x31, 0x08},
186 {0x32, 0x27},
187 {0x33, 0x60},
188 {0x34, 0x5E},
189 {0x35, 0x5E},
190 {0x3A, 0xAF},
191 {0x3B, 0x00},
192 {0x3C, 0x48},
193 {0x3D, 0x5B},
194 {0x3E, 0xFF},
195 {0x3F, 0xA8},
196 {0x40, 0xFF},
197 {0x56, 0xB2},
198 {0x59, 0x9E},
199 {0x5A, 0x04},
200 {0x85, 0x4D},
201 {0x8A, 0x04},
202 {0x91, 0x13},
203 {0x9B, 0x03},
204 {0x9C, 0xE1},
205 {0xA9, 0x78},
206 {0x5B, 0xB0},
207 {0x5C, 0x71},
208 {0x5D, 0x46},
209 {0x5E, 0x14},
210 {0x62, 0x01},
211 {0x63, 0x0F},
212 {0x64, 0xC0},
213 {0x65, 0x02},
214 {0x67, 0x65},
215 {0x66, 0x04},
216 {0x68, 0x00},
217 {0x69, 0x7C},
218 {0x6A, 0x12},
219 {0x7A, 0x80},
220 {0x82, 0x21},
221 {0x8F, 0x91},
222 {0xAE, 0x30},
223 {0x13, 0x81},
224 {0x96, 0x04},
225 {0x4A, 0x05},
226 {0x7E, 0xCD},
227 {0x50, 0x02},
228 {0x49, 0x10},
229 {0xAF, 0x12},
230 {0x80, 0x41},
231 {0x7B, 0x4A},
232 {0x7C, 0x08},
233 {0x7F, 0x57},
234 {0x90, 0x00},
235 {0x8C, 0xFF},
236 {0x8D, 0xC7},
237 {0x8E, 0x00},
238 {0x8B, 0x01},
239 {0x0C, 0x00},
240 {0x81, 0x74},
241 {0x19, 0x20},
242 {0x46, 0x00},
243 {0x12, 0x20},
244 {0x48, 0x85},
245 {0x48, 0x05},
246 {REG_NULL, 0x0},
247 };
248
249 static const struct regval jx_f37_1080p_hdr_1lane_15fps[] = {
250 {0x12, 0x68},
251 {0x48, 0x85},
252 {0x48, 0x05},
253 {0x0E, 0x11},
254 {0x0F, 0x14},
255 {0x10, 0x48},
256 {0x11, 0x80},
257 {0x0D, 0xF0},
258 {0x5F, 0x41},
259 {0x60, 0x20},
260 {0x58, 0x12},
261 {0x57, 0x60},
262 {0x9D, 0x00},
263 {0x20, 0x00},
264 {0x21, 0x05},
265 {0x22, 0xCA},
266 {0x23, 0x08},
267 {0x24, 0xC0},
268 {0x25, 0x38},
269 {0x26, 0x43},
270 {0x27, 0x98},
271 {0x28, 0x29},
272 {0x29, 0x04},
273 {0x2A, 0x8A},
274 {0x2B, 0x14},
275 {0x2C, 0x02},
276 {0x2D, 0x00},
277 {0x2E, 0x14},
278 {0x2F, 0x44},
279 {0x41, 0xC5},
280 {0x42, 0x3B},
281 {0x47, 0x42},
282 {0x76, 0x60},
283 {0x77, 0x09},
284 {0x80, 0x41},
285 {0xAF, 0x22},
286 {0xAB, 0x00},
287 {0x46, 0x14}, /* Short frame use the same gain as long frame */
288 {0x1D, 0x00},
289 {0x1E, 0x04},
290 {0x6C, 0x50},
291 {0x6E, 0x2C},
292 {0x70, 0xD0},
293 {0x71, 0xD3},
294 {0x72, 0xD4},
295 {0x73, 0x58},
296 {0x74, 0x02},
297 {0x78, 0x96},
298 {0x89, 0x81},
299 {0x6B, 0x20},
300 {0x86, 0x40},
301 {0x31, 0x08},
302 {0x32, 0x27},
303 {0x33, 0x60},
304 {0x34, 0x5E},
305 {0x35, 0x5E},
306 {0x3A, 0xAF},
307 {0x3B, 0x00},
308 {0x3C, 0x48},
309 {0x3D, 0x5B},
310 {0x3E, 0xFF},
311 {0x3F, 0xA8},
312 {0x40, 0xFF},
313 {0x56, 0xB2},
314 {0x59, 0x9E},
315 {0x5A, 0x04},
316 {0x85, 0x4D},
317 {0x8A, 0x04},
318 {0x91, 0x13},
319 {0x9B, 0x43},
320 {0x9C, 0xE1},
321 {0xA9, 0x78},
322 {0x5B, 0xB0},
323 {0x5C, 0x71},
324 {0x5D, 0xF6},
325 {0x5E, 0x14},
326 {0x62, 0x01},
327 {0x63, 0x0F},
328 {0x64, 0xC0},
329 {0x65, 0x02},
330 {0x67, 0x65},
331 {0x66, 0x04},
332 {0x68, 0x00},
333 {0x69, 0x7C},
334 {0x6A, 0x12},
335 {0x7A, 0x80},
336 {0x82, 0x21},
337 {0x8F, 0x91},
338 {0xAE, 0x30},
339 {0x13, 0x81},
340 {0x96, 0x04},
341 {0x4A, 0x05},
342 {0x7E, 0xCD},
343 {0x50, 0x02},
344 {0x49, 0x10},
345 {0xAF, 0x12},
346 {0x7B, 0x4A},
347 {0x7C, 0x08},
348 {0x7F, 0x57},
349 {0x90, 0x00},
350 {0x8C, 0xFF},
351 {0x8D, 0xC7},
352 {0x8E, 0x00},
353 {0x8B, 0x01},
354 {0x0C, 0x00},
355 {0x81, 0x74},
356 {0x19, 0x20},
357 {0x07, 0x03},
358 {0x1B, 0x4F},
359 {0x06, JX_F37_MAX_SMPL_START},
360 {0x03, 0xFF},
361 {0x04, 0xFF},
362 {0x12, 0x28},
363 {0x48, 0x85},
364 {0x48, 0x05},
365 {REG_NULL, 0x0},
366 };
367
368 static const struct jx_f37_mode supported_modes[] = {
369 {
370 .width = 1920,
371 .height = 1080,
372 .max_fps = {
373 .numerator = 10000,
374 .denominator = 300000,
375 },
376 .exp_def = 0x00ff,
377 .hts_def = 0x0500 * 2,
378 .vts_def = 0x0465,
379 .reg_list = jx_f37_1080p_linear_1lane_30fps,
380 .hdr_mode = NO_HDR,
381 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
382 },
383 {
384 .width = 1920,
385 .height = 1080,
386 .max_fps = {
387 .numerator = 10000,
388 .denominator = 150000,
389 },
390 .exp_def = 0x00ff,
391 .hts_def = 0x0500 * 2,
392 .vts_def = 0x08ca,
393 .reg_list = jx_f37_1080p_hdr_1lane_15fps,
394 .hdr_mode = HDR_X2,
395 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
396 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
397 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
398 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
399 },
400 };
401
402 #define JX_F37_LINK_FREQ_432MHZ (432000000)
403 #define JX_F37_PIXEL_RATE (JX_F37_LINK_FREQ_432MHZ * 2 * JX_F37_LANES / 10)
404 static const s64 link_freq_menu_items[] = {
405 JX_F37_LINK_FREQ_432MHZ
406 };
407
408 /* Calculate the delay in us by clock rate and clock cycles */
jx_f37_cal_delay(u32 cycles)409 static inline u32 jx_f37_cal_delay(u32 cycles)
410 {
411 return DIV_ROUND_UP(cycles, JX_F37_XVCLK_FREQ / 1000 / 1000);
412 }
413
jx_f37_write_reg(struct i2c_client * client,u8 reg,u8 val)414 static int jx_f37_write_reg(struct i2c_client *client, u8 reg, u8 val)
415 {
416 struct i2c_msg msg;
417 u8 buf[2];
418 int ret;
419
420 buf[0] = reg & 0xFF;
421 buf[1] = val;
422
423 msg.addr = client->addr;
424 msg.flags = client->flags;
425 msg.buf = buf;
426 msg.len = sizeof(buf);
427
428 ret = i2c_transfer(client->adapter, &msg, 1);
429 if (ret >= 0) {
430 //dev_dbg(&client->dev,
431 // "jx_f37 write reg(0x%x val:0x%x)\n", reg, val);
432 return 0;
433 }
434
435 dev_err(&client->dev,
436 "jx_f37 write reg(0x%x val:0x%x) failed !\n", reg, val);
437
438 return ret;
439 }
440
jx_f37_write_array(struct i2c_client * client,const struct regval * regs)441 static int jx_f37_write_array(struct i2c_client *client,
442 const struct regval *regs)
443 {
444 u32 i, delay_us;
445 int ret = 0;
446
447 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
448 if (regs[i].addr == REG_DELAY) {
449 delay_us = jx_f37_cal_delay(500 * 1000);
450 usleep_range(delay_us, delay_us * 2);
451 } else {
452 ret = jx_f37_write_reg(client,
453 regs[i].addr, regs[i].val);
454 }
455 }
456
457 return ret;
458 }
459
jx_f37_read_reg(struct i2c_client * client,u8 reg,u8 * val)460 static int jx_f37_read_reg(struct i2c_client *client, u8 reg, u8 *val)
461 {
462 struct i2c_msg msg[2];
463 u8 buf[1];
464 int ret;
465
466 buf[0] = reg & 0xFF;
467
468 msg[0].addr = client->addr;
469 msg[0].flags = client->flags;
470 msg[0].buf = buf;
471 msg[0].len = sizeof(buf);
472
473 msg[1].addr = client->addr;
474 msg[1].flags = client->flags | I2C_M_RD;
475 msg[1].buf = buf;
476 msg[1].len = 1;
477
478 ret = i2c_transfer(client->adapter, msg, 2);
479 if (ret >= 0) {
480 *val = buf[0];
481 return 0;
482 }
483
484 dev_err(&client->dev,
485 "jx_f37 read reg:0x%x failed !\n", reg);
486
487 return ret;
488 }
489
jx_f37_update_cur_mode_locked(struct jx_f37 * jx_f37,const struct jx_f37_mode * mode)490 static void jx_f37_update_cur_mode_locked(struct jx_f37 *jx_f37,
491 const struct jx_f37_mode *mode)
492 {
493 s64 h_blank, vblank_def;
494
495 jx_f37->cur_mode = mode;
496 h_blank = mode->hts_def - mode->width;
497 __v4l2_ctrl_modify_range(jx_f37->hblank, h_blank,
498 h_blank, 1, h_blank);
499 vblank_def = mode->vts_def - mode->height;
500 __v4l2_ctrl_modify_range(jx_f37->vblank, vblank_def,
501 JX_F37_VTS_MAX - mode->height,
502 1, vblank_def);
503 }
504
jx_f37_set_hdr_mode_locked(struct jx_f37 * jx_f37,u32 hdr_mode)505 static int jx_f37_set_hdr_mode_locked(struct jx_f37 *jx_f37, u32 hdr_mode)
506 {
507 int i;
508
509 /*
510 * found the first one that match hdr_mode,
511 * the fmt size shall hand over to .set_fmt.
512 */
513 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
514 if (supported_modes[i].hdr_mode != hdr_mode)
515 continue;
516 jx_f37_update_cur_mode_locked(jx_f37, &supported_modes[i]);
517 return 0;
518 }
519
520 return -EINVAL;
521 }
522
523 #ifdef USED_SYS_DEBUG
set_hdr_mode(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)524 static ssize_t set_hdr_mode(struct device *dev, struct device_attribute *attr,
525 const char *buf, size_t count)
526 {
527 struct i2c_client *client = to_i2c_client(dev);
528 struct v4l2_subdev *sd = i2c_get_clientdata(client);
529 struct jx_f37 *jx_f37 = to_jx_f37(sd);
530 int status = 0;
531 int ret;
532
533 mutex_lock(&jx_f37->mutex);
534
535 ret = kstrtoint(buf, 0, &status);
536 if (!ret) {
537 ret = jx_f37_set_hdr_mode_locked(jx_f37, status);
538 if (ret)
539 dev_err(dev, "hdr_mode(%d) is not supported\n", status);
540 else
541 dev_info(dev, "Set hdr mode to: %d\n", status);
542 }
543
544 mutex_unlock(&jx_f37->mutex);
545
546 return count;
547 }
548
show_hdr_mode(struct device * dev,struct device_attribute * attr,char * buf)549 static ssize_t show_hdr_mode(struct device *dev,
550 struct device_attribute *attr, char *buf)
551 {
552 struct i2c_client *client = to_i2c_client(dev);
553 struct v4l2_subdev *sd = i2c_get_clientdata(client);
554 struct jx_f37 *jx_f37 = to_jx_f37(sd);
555
556 return sprintf(buf, "%u\n", jx_f37->cur_mode->hdr_mode);
557 }
558
559 static struct device_attribute attributes[] = {
560 __ATTR(cam_hdr_mode, 0600, show_hdr_mode, set_hdr_mode),
561 };
562
add_sysfs_interfaces(struct device * dev)563 static int add_sysfs_interfaces(struct device *dev)
564 {
565 int i;
566
567 for (i = 0; i < ARRAY_SIZE(attributes); i++)
568 if (device_create_file(dev, attributes + i))
569 goto undo;
570 return 0;
571 undo:
572 for (i--; i >= 0 ; i--)
573 device_remove_file(dev, attributes + i);
574 dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
575 return -ENODEV;
576 }
577 #endif
578
579
jx_f37_get_reso_dist(const struct jx_f37_mode * mode,struct v4l2_mbus_framefmt * framefmt)580 static int jx_f37_get_reso_dist(const struct jx_f37_mode *mode,
581 struct v4l2_mbus_framefmt *framefmt)
582 {
583 return abs(mode->width - framefmt->width) +
584 abs(mode->height - framefmt->height);
585 }
586
587 static const struct jx_f37_mode *
jx_f37_find_best_fit(struct jx_f37 * jx_f37,struct v4l2_subdev_format * fmt)588 jx_f37_find_best_fit(struct jx_f37 *jx_f37, struct v4l2_subdev_format *fmt)
589 {
590 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
591 u32 cur_hdr_mode = jx_f37->cur_mode->hdr_mode;
592 int dist;
593 int cur_best_fit = 0;
594 int cur_best_fit_dist = -1;
595 unsigned int i;
596
597 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
598 /* Do not change the hdr_mode setting */
599 if (supported_modes[i].hdr_mode != cur_hdr_mode)
600 continue;
601 dist = jx_f37_get_reso_dist(&supported_modes[i], framefmt);
602 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
603 cur_best_fit_dist = dist;
604 cur_best_fit = i;
605 }
606 }
607
608 return &supported_modes[cur_best_fit];
609 }
610
jx_f37_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)611 static int jx_f37_set_fmt(struct v4l2_subdev *sd,
612 struct v4l2_subdev_pad_config *cfg,
613 struct v4l2_subdev_format *fmt)
614 {
615 struct jx_f37 *jx_f37 = to_jx_f37(sd);
616 const struct jx_f37_mode *mode;
617
618 mutex_lock(&jx_f37->mutex);
619
620 mode = jx_f37_find_best_fit(jx_f37, fmt);
621 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
622 fmt->format.width = mode->width;
623 fmt->format.height = mode->height;
624 fmt->format.field = V4L2_FIELD_NONE;
625 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
626 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
627 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
628 #else
629 mutex_unlock(&jx_f37->mutex);
630 return -ENOTTY;
631 #endif
632 } else {
633 jx_f37_update_cur_mode_locked(jx_f37, mode);
634 }
635
636 mutex_unlock(&jx_f37->mutex);
637
638 return 0;
639 }
640
jx_f37_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)641 static int jx_f37_get_fmt(struct v4l2_subdev *sd,
642 struct v4l2_subdev_pad_config *cfg,
643 struct v4l2_subdev_format *fmt)
644 {
645 struct jx_f37 *jx_f37 = to_jx_f37(sd);
646 const struct jx_f37_mode *mode = jx_f37->cur_mode;
647
648 mutex_lock(&jx_f37->mutex);
649 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
650 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
651 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
652 #else
653 mutex_unlock(&jx_f37->mutex);
654 return -ENOTTY;
655 #endif
656 } else {
657 fmt->format.width = mode->width;
658 fmt->format.height = mode->height;
659 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
660 fmt->format.field = V4L2_FIELD_NONE;
661 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
662 fmt->reserved[0] = mode->vc[fmt->pad];
663 else
664 fmt->reserved[0] = mode->vc[PAD0];
665 }
666 mutex_unlock(&jx_f37->mutex);
667
668 return 0;
669 }
670
jx_f37_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)671 static int jx_f37_enum_mbus_code(struct v4l2_subdev *sd,
672 struct v4l2_subdev_pad_config *cfg,
673 struct v4l2_subdev_mbus_code_enum *code)
674 {
675 if (code->index != 0)
676 return -EINVAL;
677 code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
678
679 return 0;
680 }
681
jx_f37_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)682 static int jx_f37_enum_frame_sizes(struct v4l2_subdev *sd,
683 struct v4l2_subdev_pad_config *cfg,
684 struct v4l2_subdev_frame_size_enum *fse)
685 {
686 if (fse->index >= ARRAY_SIZE(supported_modes))
687 return -EINVAL;
688
689 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
690 return -EINVAL;
691
692 fse->min_width = supported_modes[fse->index].width;
693 fse->max_width = supported_modes[fse->index].width;
694 fse->max_height = supported_modes[fse->index].height;
695 fse->min_height = supported_modes[fse->index].height;
696
697 return 0;
698 }
699
jx_f37_get_module_inf(struct jx_f37 * jx_f37,struct rkmodule_inf * inf)700 static void jx_f37_get_module_inf(struct jx_f37 *jx_f37,
701 struct rkmodule_inf *inf)
702 {
703 memset(inf, 0, sizeof(*inf));
704 strlcpy(inf->base.sensor, JX_F37_NAME, sizeof(inf->base.sensor));
705 strlcpy(inf->base.module, jx_f37->module_name,
706 sizeof(inf->base.module));
707 strlcpy(inf->base.lens, jx_f37->len_name, sizeof(inf->base.lens));
708 }
709
jx_f37_set_hdrae(struct jx_f37 * jx_f37,struct preisp_hdrae_exp_s * ae)710 static int jx_f37_set_hdrae(struct jx_f37 *jx_f37,
711 struct preisp_hdrae_exp_s *ae)
712 {
713 struct i2c_client *client = jx_f37->client;
714 u32 fh, l_exp_max, l_exp_min, s_exp_max, s_exp_min;
715 u32 l_exp_time, m_exp_time, s_exp_time;
716 u32 l_a_gain, m_a_gain, s_a_gain;
717 int ret = 0;
718
719 if (!jx_f37->has_init_exp && !jx_f37->streaming) {
720 jx_f37->init_hdrae_exp = *ae;
721 jx_f37->has_init_exp = true;
722 dev_dbg(&client->dev, "jx_f37 don't stream, record exp for hdr!\n");
723 return ret;
724 }
725
726 /* The frame height, vts, default value is: 0x08ca */
727 fh = jx_f37->vblank->cur.val + jx_f37->cur_mode->height;
728 /*
729 * Restriction:
730 * Short / Long exp line shall be odd value.
731 *
732 * 0x00 <= Reg_saec1 * 2 < Smpl_Start_S * 2 - 3
733 * 0x00 <= Reg_saec1 <= Smpl_Start_S - 3
734 *
735 * 0x01 <= short_exp = Reg_saec1 * 2 + 1 <= Smpl_Start_S * 2 - 5
736 *
737 * 0x01 <= long_exp < fh - Smpl_Start_S * 2 - 6
738 *
739 * short_exp + long_exp < fh - 11
740 */
741
742 l_exp_time = ae->long_exp_reg;
743 m_exp_time = ae->middle_exp_reg;
744 s_exp_time = ae->short_exp_reg;
745 l_a_gain = ae->long_gain_reg;
746 m_a_gain = ae->middle_gain_reg;
747 s_a_gain = ae->short_gain_reg;
748 dev_dbg(&client->dev,
749 "hdrae req: exp (0x%x, 0x%x, 0x%x), gain(0x%x: 0x%x, 0x%x)\n",
750 l_exp_time, m_exp_time, s_exp_time,
751 l_a_gain, m_a_gain, s_a_gain);
752
753 if (jx_f37->cur_mode->hdr_mode == HDR_X2) {
754 //2 stagger
755 l_a_gain = m_a_gain;
756 l_exp_time = m_exp_time;
757 }
758
759 //s_exp_time = clamp_val(s_exp_time, 1, MAX_SMPL_START * 2 - 3);
760 //smpl_start = (s_exp_time + 3) / 2;
761 //jx_f37_write_reg(client, 0xc0, JX_F37_SMPL_START_S_REG);
762 //jx_f37_write_reg(client, 0xc1, smpl_start);
763
764 s_exp_min = 1;
765 s_exp_max = JX_F37_MAX_SMPL_START * 2 - 5;
766 s_exp_time = clamp_val(s_exp_time, s_exp_min, s_exp_max);
767 s_exp_time |= 0x1;
768
769 jx_f37_write_reg(client, 0xc0, JX_F37_SHORT_EXPO_REG);
770 jx_f37_write_reg(client, 0xc1, (s_exp_time - 1) / 2);
771
772 l_exp_min = 1;
773 l_exp_max = fh - JX_F37_MAX_SMPL_START * 2 - 6 - 1; /* Make it odd */
774 l_exp_time = clamp_val(l_exp_time, l_exp_min, l_exp_max);
775 l_exp_time |= 0x1;
776
777 jx_f37_write_reg(client, 0xc2, JX_F37_LONG_EXPO_HIGH_REG);
778 jx_f37_write_reg(client, 0xc3, JX_F37_FETCH_HIGH_BYTE_EXP(l_exp_time));
779 jx_f37_write_reg(client, 0xc4, JX_F37_LONG_EXPO_LOW_REG);
780 jx_f37_write_reg(client, 0xc5, JX_F37_FETCH_LOW_BYTE_EXP(l_exp_time));
781
782 /* Short frame gain is ignored */
783 jx_f37_write_reg(client, 0xc6, JX_F37_LONG_GAIN_REG);
784 jx_f37_write_reg(client, 0xc7, l_a_gain);
785
786 /* Trigger group write function */
787 jx_f37_write_reg(client, 0x1f, 0x80);
788
789 dev_dbg(&client->dev,
790 "hdrae final: smpl_start: %d, exp (0x%x, 0x%x), gain(0x%x: 0x%x)\n"
791 " l_exp[%d, %d], s_exp[%d, %d], fh = %d\n",
792 JX_F37_MAX_SMPL_START, l_exp_time, s_exp_time, l_a_gain, s_a_gain,
793 l_exp_min, l_exp_max, s_exp_min, s_exp_max, fh);
794
795 return ret;
796 }
797
jx_f37_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)798 static long jx_f37_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
799 {
800 struct jx_f37 *jx_f37 = to_jx_f37(sd);
801 struct rkmodule_hdr_cfg *hdr;
802 u32 i, h, w;
803 long ret = 0;
804
805 switch (cmd) {
806 case PREISP_CMD_SET_HDRAE_EXP:
807 ret = jx_f37_set_hdrae(jx_f37, arg);
808 break;
809 case RKMODULE_GET_MODULE_INFO:
810 jx_f37_get_module_inf(jx_f37, (struct rkmodule_inf *)arg);
811 break;
812 case RKMODULE_GET_HDR_CFG:
813 hdr = (struct rkmodule_hdr_cfg *)arg;
814 hdr->esp.mode = HDR_NORMAL_VC;
815 hdr->hdr_mode = jx_f37->cur_mode->hdr_mode;
816 break;
817 case RKMODULE_SET_HDR_CFG:
818 hdr = (struct rkmodule_hdr_cfg *)arg;
819 w = jx_f37->cur_mode->width;
820 h = jx_f37->cur_mode->height;
821 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
822 if (w == supported_modes[i].width &&
823 h == supported_modes[i].height &&
824 supported_modes[i].hdr_mode == hdr->hdr_mode) {
825 jx_f37_update_cur_mode_locked(jx_f37, &supported_modes[i]);
826 break;
827 }
828 }
829 if (i == ARRAY_SIZE(supported_modes)) {
830 dev_err(&jx_f37->client->dev,
831 "not find hdr mode:%d %dx%d config\n",
832 hdr->hdr_mode, w, h);
833 ret = -EINVAL;
834 }
835 break;
836 default:
837 ret = -ENOIOCTLCMD;
838 break;
839 }
840
841 return ret;
842 }
843
844 #ifdef CONFIG_COMPAT
jx_f37_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)845 static long jx_f37_compat_ioctl32(struct v4l2_subdev *sd,
846 unsigned int cmd, unsigned long arg)
847 {
848 void __user *up = compat_ptr(arg);
849 struct preisp_hdrae_exp_s *hdrae;
850 struct rkmodule_hdr_cfg *hdr;
851 struct rkmodule_inf *inf;
852 long ret;
853
854 switch (cmd) {
855 case RKMODULE_GET_MODULE_INFO:
856 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
857 if (!inf) {
858 ret = -ENOMEM;
859 return ret;
860 }
861
862 ret = jx_f37_ioctl(sd, cmd, inf);
863 if (!ret) {
864 ret = copy_to_user(up, inf, sizeof(*inf));
865 if (ret)
866 ret = -EFAULT;
867 }
868 kfree(inf);
869 break;
870 case RKMODULE_GET_HDR_CFG:
871 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
872 if (!hdr) {
873 ret = -ENOMEM;
874 return ret;
875 }
876
877 ret = jx_f37_ioctl(sd, cmd, hdr);
878 if (!ret) {
879 ret = copy_to_user(up, hdr, sizeof(*hdr));
880 if (ret)
881 ret = -EFAULT;
882 }
883 kfree(hdr);
884 break;
885 case RKMODULE_SET_HDR_CFG:
886 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
887 if (!hdr) {
888 ret = -ENOMEM;
889 return ret;
890 }
891
892 ret = copy_from_user(hdr, up, sizeof(*hdr));
893 if (!ret)
894 ret = jx_f37_ioctl(sd, cmd, hdr);
895 else
896 ret = -EFAULT;
897 kfree(hdr);
898 break;
899 case PREISP_CMD_SET_HDRAE_EXP:
900 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
901 if (!hdrae) {
902 ret = -ENOMEM;
903 return ret;
904 }
905
906 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
907 if (!ret)
908 ret = jx_f37_ioctl(sd, cmd, hdrae);
909 else
910 ret = -EFAULT;
911 kfree(hdrae);
912 break;
913 default:
914 ret = -ENOIOCTLCMD;
915 break;
916 }
917
918 return ret;
919 }
920 #endif
921
jx_f37_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)922 static int jx_f37_g_frame_interval(struct v4l2_subdev *sd,
923 struct v4l2_subdev_frame_interval *fi)
924 {
925 struct jx_f37 *jx_f37 = to_jx_f37(sd);
926 const struct jx_f37_mode *mode = jx_f37->cur_mode;
927
928 mutex_lock(&jx_f37->mutex);
929 fi->interval = mode->max_fps;
930 mutex_unlock(&jx_f37->mutex);
931
932 return 0;
933 }
934
jx_f37_g_mbus_config(struct v4l2_subdev * sd,struct v4l2_mbus_config * config)935 static int jx_f37_g_mbus_config(struct v4l2_subdev *sd,
936 struct v4l2_mbus_config *config)
937 {
938 struct jx_f37 *jx_f37 = to_jx_f37(sd);
939 const struct jx_f37_mode *mode = jx_f37->cur_mode;
940 u32 val = 0;
941
942 if (mode->hdr_mode == NO_HDR)
943 val = 1 << (JX_F37_LANES - 1) |
944 V4L2_MBUS_CSI2_CHANNEL_0 |
945 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
946 else if (mode->hdr_mode == HDR_X2)
947 val = 1 << (JX_F37_LANES - 1) |
948 V4L2_MBUS_CSI2_CHANNEL_0 |
949 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
950 V4L2_MBUS_CSI2_CHANNEL_1;
951
952 config->type = V4L2_MBUS_CSI2;
953 config->flags = val;
954
955 return 0;
956 }
957
__jx_f37_start_stream(struct jx_f37 * jx_f37)958 static int __jx_f37_start_stream(struct jx_f37 *jx_f37)
959 {
960 int ret;
961
962 ret = jx_f37_write_array(jx_f37->client, jx_f37->cur_mode->reg_list);
963 if (ret)
964 return ret;
965
966 /* In case these controls are set before streaming */
967
968 mutex_unlock(&jx_f37->mutex);
969 ret = v4l2_ctrl_handler_setup(&jx_f37->ctrl_handler);
970 mutex_lock(&jx_f37->mutex);
971 if (ret)
972 return ret;
973
974 if (jx_f37->has_init_exp && jx_f37->cur_mode->hdr_mode != NO_HDR) {
975 ret = jx_f37_ioctl(&jx_f37->subdev, PREISP_CMD_SET_HDRAE_EXP,
976 &jx_f37->init_hdrae_exp);
977 if (ret) {
978 dev_err(&jx_f37->client->dev,
979 "init exp fail in hdr mode\n");
980 return ret;
981 }
982 jx_f37->has_init_exp = false;
983 }
984
985 return 0;
986 }
987
__jx_f37_stop_stream(struct jx_f37 * jx_f37)988 static int __jx_f37_stop_stream(struct jx_f37 *jx_f37)
989 {
990 int ret;
991 u8 val;
992
993 ret = jx_f37_read_reg(jx_f37->client, JX_F37_REG_CTRL_MODE, &val);
994 if (ret) {
995 dev_err(&jx_f37->client->dev, "%s: read reg failed, %d\n",
996 __func__, ret);
997 return ret;
998 }
999 return jx_f37_write_reg(jx_f37->client, JX_F37_REG_CTRL_MODE,
1000 val | JX_F37_MODE_SLEEP_MODE);
1001 }
1002
jx_f37_s_stream(struct v4l2_subdev * sd,int on)1003 static int jx_f37_s_stream(struct v4l2_subdev *sd, int on)
1004 {
1005 struct jx_f37 *jx_f37 = to_jx_f37(sd);
1006 struct i2c_client *client = jx_f37->client;
1007 int ret = 0;
1008
1009 mutex_lock(&jx_f37->mutex);
1010 on = !!on;
1011 if (on == jx_f37->streaming)
1012 goto unlock_and_return;
1013
1014 if (on) {
1015 ret = pm_runtime_get_sync(&client->dev);
1016 if (ret < 0) {
1017 pm_runtime_put_noidle(&client->dev);
1018 goto unlock_and_return;
1019 }
1020
1021 ret = __jx_f37_start_stream(jx_f37);
1022 if (ret) {
1023 v4l2_err(sd, "start stream failed while write regs\n");
1024 pm_runtime_put(&client->dev);
1025 goto unlock_and_return;
1026 }
1027 dev_info(&client->dev, "hdr_mode %d\n", jx_f37->cur_mode->hdr_mode);
1028 } else {
1029 __jx_f37_stop_stream(jx_f37);
1030 pm_runtime_put(&client->dev);
1031 }
1032
1033 jx_f37->streaming = on;
1034
1035 unlock_and_return:
1036 mutex_unlock(&jx_f37->mutex);
1037
1038 return ret;
1039 }
1040
jx_f37_s_power(struct v4l2_subdev * sd,int on)1041 static int jx_f37_s_power(struct v4l2_subdev *sd, int on)
1042 {
1043 struct jx_f37 *jx_f37 = to_jx_f37(sd);
1044 struct i2c_client *client = jx_f37->client;
1045 int ret = 0;
1046
1047 mutex_lock(&jx_f37->mutex);
1048
1049 /* If the power state is not modified - no work to do. */
1050 if (jx_f37->power_on == !!on)
1051 goto unlock_and_return;
1052
1053 if (on) {
1054 ret = pm_runtime_get_sync(&client->dev);
1055 if (ret < 0) {
1056 pm_runtime_put_noidle(&client->dev);
1057 goto unlock_and_return;
1058 }
1059
1060 /*
1061 * Enter sleep state to make sure not mipi output
1062 * during rkisp init.
1063 */
1064 __jx_f37_stop_stream(jx_f37);
1065 jx_f37->power_on = true;
1066 } else {
1067 pm_runtime_put(&client->dev);
1068 jx_f37->power_on = false;
1069 }
1070
1071 unlock_and_return:
1072 mutex_unlock(&jx_f37->mutex);
1073
1074 return ret;
1075 }
1076
__jx_f37_power_on(struct jx_f37 * jx_f37)1077 static int __jx_f37_power_on(struct jx_f37 *jx_f37)
1078 {
1079 int ret;
1080 u32 delay_us;
1081 struct device *dev = &jx_f37->client->dev;
1082
1083 ret = clk_set_rate(jx_f37->xvclk, JX_F37_XVCLK_FREQ);
1084 if (ret < 0) {
1085 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
1086 return ret;
1087 }
1088 if (clk_get_rate(jx_f37->xvclk) != JX_F37_XVCLK_FREQ)
1089 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1090 ret = clk_prepare_enable(jx_f37->xvclk);
1091 if (ret < 0) {
1092 dev_err(dev, "Failed to enable xvclk\n");
1093 return ret;
1094 }
1095
1096 if (!IS_ERR(jx_f37->reset_gpio))
1097 gpiod_set_value_cansleep(jx_f37->reset_gpio, 1);
1098
1099 ret = regulator_bulk_enable(JX_F37_NUM_SUPPLIES, jx_f37->supplies);
1100 if (ret < 0) {
1101 dev_err(dev, "Failed to enable regulators\n");
1102 goto disable_clk;
1103 }
1104
1105 /* According to datasheet, at least 10ms for reset duration */
1106 usleep_range(10 * 1000, 15 * 1000);
1107
1108 if (!IS_ERR(jx_f37->reset_gpio))
1109 gpiod_set_value_cansleep(jx_f37->reset_gpio, 0);
1110
1111 if (!IS_ERR(jx_f37->pwdn_gpio))
1112 gpiod_set_value_cansleep(jx_f37->pwdn_gpio, 0);
1113
1114 /* 8192 cycles prior to first SCCB transaction */
1115 delay_us = jx_f37_cal_delay(8192);
1116 usleep_range(delay_us, delay_us * 2);
1117
1118 return 0;
1119
1120 disable_clk:
1121 clk_disable_unprepare(jx_f37->xvclk);
1122
1123 return ret;
1124 }
1125
__jx_f37_power_off(struct jx_f37 * jx_f37)1126 static void __jx_f37_power_off(struct jx_f37 *jx_f37)
1127 {
1128 if (!IS_ERR(jx_f37->pwdn_gpio))
1129 gpiod_set_value_cansleep(jx_f37->pwdn_gpio, 1);
1130 clk_disable_unprepare(jx_f37->xvclk);
1131 if (!IS_ERR(jx_f37->reset_gpio))
1132 gpiod_set_value_cansleep(jx_f37->reset_gpio, 1);
1133 regulator_bulk_disable(JX_F37_NUM_SUPPLIES, jx_f37->supplies);
1134 }
1135
jx_f37_runtime_resume(struct device * dev)1136 static int jx_f37_runtime_resume(struct device *dev)
1137 {
1138 struct i2c_client *client = to_i2c_client(dev);
1139 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1140 struct jx_f37 *jx_f37 = to_jx_f37(sd);
1141
1142 return __jx_f37_power_on(jx_f37);
1143 }
1144
jx_f37_runtime_suspend(struct device * dev)1145 static int jx_f37_runtime_suspend(struct device *dev)
1146 {
1147 struct i2c_client *client = to_i2c_client(dev);
1148 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1149 struct jx_f37 *jx_f37 = to_jx_f37(sd);
1150
1151 __jx_f37_power_off(jx_f37);
1152
1153 return 0;
1154 }
1155
1156 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
jx_f37_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1157 static int jx_f37_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1158 {
1159 struct jx_f37 *jx_f37 = to_jx_f37(sd);
1160 struct v4l2_mbus_framefmt *try_fmt =
1161 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1162 const struct jx_f37_mode *def_mode = &supported_modes[0];
1163
1164 mutex_lock(&jx_f37->mutex);
1165 /* Initialize try_fmt */
1166 try_fmt->width = def_mode->width;
1167 try_fmt->height = def_mode->height;
1168 try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1169 try_fmt->field = V4L2_FIELD_NONE;
1170
1171 mutex_unlock(&jx_f37->mutex);
1172 /* No crop or compose */
1173
1174 return 0;
1175 }
1176 #endif
1177
jx_f37_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1178 static int jx_f37_enum_frame_interval(struct v4l2_subdev *sd,
1179 struct v4l2_subdev_pad_config *cfg,
1180 struct v4l2_subdev_frame_interval_enum *fie)
1181 {
1182 if (fie->index >= ARRAY_SIZE(supported_modes))
1183 return -EINVAL;
1184
1185 fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1186 fie->width = supported_modes[fie->index].width;
1187 fie->height = supported_modes[fie->index].height;
1188 fie->interval = supported_modes[fie->index].max_fps;
1189 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1190
1191 return 0;
1192 }
1193
1194 static const struct dev_pm_ops jx_f37_pm_ops = {
1195 SET_RUNTIME_PM_OPS(jx_f37_runtime_suspend,
1196 jx_f37_runtime_resume, NULL)
1197 };
1198
1199 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1200 static const struct v4l2_subdev_internal_ops jx_f37_internal_ops = {
1201 .open = jx_f37_open,
1202 };
1203 #endif
1204
1205 static const struct v4l2_subdev_core_ops jx_f37_core_ops = {
1206 .s_power = jx_f37_s_power,
1207 .ioctl = jx_f37_ioctl,
1208 #ifdef CONFIG_COMPAT
1209 .compat_ioctl32 = jx_f37_compat_ioctl32,
1210 #endif
1211 };
1212
1213 static const struct v4l2_subdev_video_ops jx_f37_video_ops = {
1214 .s_stream = jx_f37_s_stream,
1215 .g_frame_interval = jx_f37_g_frame_interval,
1216 .g_mbus_config = jx_f37_g_mbus_config,
1217 };
1218
1219 static const struct v4l2_subdev_pad_ops jx_f37_pad_ops = {
1220 .enum_mbus_code = jx_f37_enum_mbus_code,
1221 .enum_frame_size = jx_f37_enum_frame_sizes,
1222 .enum_frame_interval = jx_f37_enum_frame_interval,
1223 .get_fmt = jx_f37_get_fmt,
1224 .set_fmt = jx_f37_set_fmt,
1225 };
1226
1227 static const struct v4l2_subdev_ops jx_f37_subdev_ops = {
1228 .core = &jx_f37_core_ops,
1229 .video = &jx_f37_video_ops,
1230 .pad = &jx_f37_pad_ops,
1231 };
1232
jx_f37_set_ctrl(struct v4l2_ctrl * ctrl)1233 static int jx_f37_set_ctrl(struct v4l2_ctrl *ctrl)
1234 {
1235 struct jx_f37 *jx_f37 = container_of(ctrl->handler,
1236 struct jx_f37, ctrl_handler);
1237 struct i2c_client *client = jx_f37->client;
1238 s64 max;
1239 u8 val = 0;
1240 int ret = 0;
1241
1242 /* Propagate change of current control to all related controls */
1243 switch (ctrl->id) {
1244 case V4L2_CID_VBLANK:
1245 /* Update max exposure while meeting expected vblanking */
1246 max = jx_f37->cur_mode->height + ctrl->val;
1247 __v4l2_ctrl_modify_range(jx_f37->exposure,
1248 jx_f37->exposure->minimum, max,
1249 jx_f37->exposure->step,
1250 jx_f37->exposure->default_value);
1251 break;
1252 }
1253
1254 if (!pm_runtime_get_if_in_use(&client->dev))
1255 return 0;
1256
1257 switch (ctrl->id) {
1258 case V4L2_CID_EXPOSURE:
1259 dev_dbg(&client->dev, "set expo: val: %d\n", ctrl->val);
1260 /* 4 least significant bits of expsoure are fractional part */
1261 ret = jx_f37_write_reg(jx_f37->client,
1262 JX_F37_LONG_EXPO_HIGH_REG,
1263 JX_F37_FETCH_HIGH_BYTE_EXP(ctrl->val));
1264 ret |= jx_f37_write_reg(jx_f37->client,
1265 JX_F37_LONG_EXPO_LOW_REG,
1266 JX_F37_FETCH_LOW_BYTE_EXP(ctrl->val));
1267 break;
1268 case V4L2_CID_ANALOGUE_GAIN:
1269 dev_dbg(&client->dev, "set a-gain: val: %d\n", ctrl->val);
1270 ret |= jx_f37_write_reg(jx_f37->client,
1271 JX_F37_LONG_GAIN_REG, ctrl->val);
1272 break;
1273 case V4L2_CID_DIGITAL_GAIN:
1274 break;
1275 case V4L2_CID_HFLIP:
1276 ret = jx_f37_read_reg(jx_f37->client, JX_F37_FLIP_MIRROR_REG,
1277 &val);
1278 if (ctrl->val)
1279 val |= BIT(5);
1280 else
1281 val &= ~BIT(5);
1282 ret |= jx_f37_write_reg(jx_f37->client, JX_F37_FLIP_MIRROR_REG,
1283 val);
1284 break;
1285 case V4L2_CID_VFLIP:
1286 ret = jx_f37_read_reg(jx_f37->client, JX_F37_FLIP_MIRROR_REG,
1287 &val);
1288 if (ctrl->val)
1289 val |= BIT(4);
1290 else
1291 val &= ~BIT(4);
1292 ret |= jx_f37_write_reg(jx_f37->client, JX_F37_FLIP_MIRROR_REG,
1293 val);
1294 break;
1295 case V4L2_CID_VBLANK:
1296 dev_dbg(&client->dev, "set vblank: val: %d\n", ctrl->val);
1297 ret |= jx_f37_write_reg(jx_f37->client, JX_F37_REG_HIGH_VTS,
1298 JX_F37_FETCH_HIGH_BYTE_VTS((ctrl->val + jx_f37->cur_mode->height)));
1299 ret |= jx_f37_write_reg(jx_f37->client, JX_F37_REG_LOW_VTS,
1300 JX_F37_FETCH_LOW_BYTE_VTS((ctrl->val + jx_f37->cur_mode->height)));
1301 break;
1302 default:
1303 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1304 __func__, ctrl->id, ctrl->val);
1305 break;
1306 }
1307
1308 pm_runtime_put(&client->dev);
1309
1310 return ret;
1311 }
1312
1313 static const struct v4l2_ctrl_ops jx_f37_ctrl_ops = {
1314 .s_ctrl = jx_f37_set_ctrl,
1315 };
1316
jx_f37_initialize_controls(struct jx_f37 * jx_f37)1317 static int jx_f37_initialize_controls(struct jx_f37 *jx_f37)
1318 {
1319 const struct jx_f37_mode *mode;
1320 struct v4l2_ctrl_handler *handler;
1321 struct v4l2_ctrl *ctrl;
1322 s64 exposure_max, vblank_def;
1323 u32 h_blank;
1324 int ret;
1325
1326 handler = &jx_f37->ctrl_handler;
1327 mode = jx_f37->cur_mode;
1328 ret = v4l2_ctrl_handler_init(handler, 8);
1329 if (ret)
1330 return ret;
1331 handler->lock = &jx_f37->mutex;
1332
1333 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1334 0, 0, link_freq_menu_items);
1335 if (ctrl)
1336 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1337
1338 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1339 0, JX_F37_PIXEL_RATE, 1, JX_F37_PIXEL_RATE);
1340
1341 h_blank = mode->hts_def - mode->width;
1342 jx_f37->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1343 h_blank, h_blank, 1, h_blank);
1344 if (jx_f37->hblank)
1345 jx_f37->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1346
1347 vblank_def = mode->vts_def - mode->height;
1348 jx_f37->vblank = v4l2_ctrl_new_std(handler, &jx_f37_ctrl_ops,
1349 V4L2_CID_VBLANK, vblank_def,
1350 JX_F37_VTS_MAX - mode->height,
1351 1, vblank_def);
1352
1353 exposure_max = mode->vts_def;
1354 jx_f37->exposure = v4l2_ctrl_new_std(handler, &jx_f37_ctrl_ops,
1355 V4L2_CID_EXPOSURE, JX_F37_EXPOSURE_MIN,
1356 exposure_max, JX_F37_EXPOSURE_STEP,
1357 mode->exp_def);
1358
1359 jx_f37->anal_gain = v4l2_ctrl_new_std(handler, &jx_f37_ctrl_ops,
1360 V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1361 ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1362 ANALOG_GAIN_DEFAULT);
1363
1364 v4l2_ctrl_new_std(handler, &jx_f37_ctrl_ops,
1365 V4L2_CID_HFLIP, 0, 1, 1, 0);
1366
1367 v4l2_ctrl_new_std(handler, &jx_f37_ctrl_ops,
1368 V4L2_CID_VFLIP, 0, 1, 1, 0);
1369
1370 if (handler->error) {
1371 ret = handler->error;
1372 dev_err(&jx_f37->client->dev,
1373 "Failed to init controls(%d)\n", ret);
1374 goto err_free_handler;
1375 }
1376
1377 jx_f37->subdev.ctrl_handler = handler;
1378
1379 return 0;
1380
1381 err_free_handler:
1382 v4l2_ctrl_handler_free(handler);
1383
1384 return ret;
1385 }
1386
jx_f37_check_sensor_id(struct jx_f37 * jx_f37,struct i2c_client * client)1387 static int jx_f37_check_sensor_id(struct jx_f37 *jx_f37,
1388 struct i2c_client *client)
1389 {
1390 struct device *dev = &jx_f37->client->dev;
1391 u8 id_h = 0;
1392 u8 id_l = 0;
1393 int ret;
1394
1395 ret = jx_f37_read_reg(client, JX_F37_PIDH_ADDR, &id_h);
1396 ret |= jx_f37_read_reg(client, JX_F37_PIDL_ADDR, &id_l);
1397 if (id_h != CHIP_ID_H && id_l != CHIP_ID_L) {
1398 dev_err(dev, "Wrong camera sensor id(0x%02x%02x)\n",
1399 id_h, id_l);
1400 return -EINVAL;
1401 }
1402
1403 dev_info(dev, "Detected jx_f37 (0x%02x%02x) sensor\n",
1404 id_h, id_l);
1405
1406 return ret;
1407 }
1408
jx_f37_configure_regulators(struct jx_f37 * jx_f37)1409 static int jx_f37_configure_regulators(struct jx_f37 *jx_f37)
1410 {
1411 unsigned int i;
1412
1413 for (i = 0; i < JX_F37_NUM_SUPPLIES; i++)
1414 jx_f37->supplies[i].supply = jx_f37_supply_names[i];
1415
1416 return devm_regulator_bulk_get(&jx_f37->client->dev,
1417 JX_F37_NUM_SUPPLIES,
1418 jx_f37->supplies);
1419 }
1420
jx_f37_probe(struct i2c_client * client,const struct i2c_device_id * id)1421 static int jx_f37_probe(struct i2c_client *client,
1422 const struct i2c_device_id *id)
1423 {
1424 struct device *dev = &client->dev;
1425 struct device_node *node = dev->of_node;
1426 struct jx_f37 *jx_f37;
1427 struct v4l2_subdev *sd;
1428 char facing[2];
1429 u32 hdr_mode;
1430 int ret;
1431
1432 dev_info(dev, "driver version: %02x.%02x.%02x",
1433 DRIVER_VERSION >> 16,
1434 (DRIVER_VERSION & 0xff00) >> 8,
1435 DRIVER_VERSION & 0x00ff);
1436
1437 jx_f37 = devm_kzalloc(dev, sizeof(*jx_f37), GFP_KERNEL);
1438 if (!jx_f37)
1439 return -ENOMEM;
1440
1441 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1442 &jx_f37->module_index);
1443 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1444 &jx_f37->module_facing);
1445 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1446 &jx_f37->module_name);
1447 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1448 &jx_f37->len_name);
1449 if (ret) {
1450 dev_err(dev, "could not get module information!\n");
1451 return -EINVAL;
1452 }
1453
1454 jx_f37->client = client;
1455
1456 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1457 if (ret || (jx_f37_set_hdr_mode_locked(jx_f37, hdr_mode))) {
1458 jx_f37->cur_mode = &supported_modes[0];
1459 dev_warn(dev, "Bad dts hdr_mode value! Use default mode\n");
1460 }
1461
1462 jx_f37->xvclk = devm_clk_get(dev, "xvclk");
1463 if (IS_ERR(jx_f37->xvclk)) {
1464 dev_err(dev, "Failed to get xvclk\n");
1465 return -EINVAL;
1466 }
1467
1468 jx_f37->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1469 if (IS_ERR(jx_f37->reset_gpio))
1470 dev_warn(dev, "Failed to get reset-gpios\n");
1471
1472 jx_f37->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1473 if (IS_ERR(jx_f37->pwdn_gpio))
1474 dev_warn(dev, "Failed to get pwdn-gpios\n");
1475
1476 ret = jx_f37_configure_regulators(jx_f37);
1477 if (ret) {
1478 dev_err(dev, "Failed to get power regulators\n");
1479 return ret;
1480 }
1481
1482 mutex_init(&jx_f37->mutex);
1483
1484 sd = &jx_f37->subdev;
1485 v4l2_i2c_subdev_init(sd, client, &jx_f37_subdev_ops);
1486 ret = jx_f37_initialize_controls(jx_f37);
1487 if (ret)
1488 goto err_destroy_mutex;
1489
1490 ret = __jx_f37_power_on(jx_f37);
1491 if (ret)
1492 goto err_free_handler;
1493
1494 ret = jx_f37_check_sensor_id(jx_f37, client);
1495 if (ret)
1496 goto err_power_off;
1497
1498 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1499 sd->internal_ops = &jx_f37_internal_ops;
1500 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1501 V4L2_SUBDEV_FL_HAS_EVENTS;
1502 #endif
1503 #if defined(CONFIG_MEDIA_CONTROLLER)
1504 jx_f37->pad.flags = MEDIA_PAD_FL_SOURCE;
1505 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1506 ret = media_entity_pads_init(&sd->entity, 1, &jx_f37->pad);
1507 if (ret < 0)
1508 goto err_power_off;
1509 #endif
1510
1511 memset(facing, 0, sizeof(facing));
1512 if (strcmp(jx_f37->module_facing, "back") == 0)
1513 facing[0] = 'b';
1514 else
1515 facing[0] = 'f';
1516
1517 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1518 jx_f37->module_index, facing,
1519 JX_F37_NAME, dev_name(sd->dev));
1520
1521 ret = v4l2_async_register_subdev_sensor_common(sd);
1522 if (ret) {
1523 dev_err(dev, "v4l2 async register subdev failed\n");
1524 goto err_clean_entity;
1525 }
1526
1527 pm_runtime_set_active(dev);
1528 pm_runtime_enable(dev);
1529 pm_runtime_idle(dev);
1530
1531 #ifdef USED_SYS_DEBUG
1532 add_sysfs_interfaces(dev);
1533 #endif
1534 dev_info(dev, "probe successful\n");
1535
1536 return 0;
1537
1538 err_clean_entity:
1539 #if defined(CONFIG_MEDIA_CONTROLLER)
1540 media_entity_cleanup(&sd->entity);
1541 #endif
1542 err_power_off:
1543 __jx_f37_power_off(jx_f37);
1544 err_free_handler:
1545 v4l2_ctrl_handler_free(&jx_f37->ctrl_handler);
1546 err_destroy_mutex:
1547 mutex_destroy(&jx_f37->mutex);
1548
1549 dev_err(dev, "probe failed\n");
1550
1551 return ret;
1552 }
1553
jx_f37_remove(struct i2c_client * client)1554 static int jx_f37_remove(struct i2c_client *client)
1555 {
1556 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1557 struct jx_f37 *jx_f37 = to_jx_f37(sd);
1558
1559 v4l2_async_unregister_subdev(sd);
1560 #if defined(CONFIG_MEDIA_CONTROLLER)
1561 media_entity_cleanup(&sd->entity);
1562 #endif
1563 v4l2_ctrl_handler_free(&jx_f37->ctrl_handler);
1564 mutex_destroy(&jx_f37->mutex);
1565
1566 pm_runtime_disable(&client->dev);
1567 if (!pm_runtime_status_suspended(&client->dev))
1568 __jx_f37_power_off(jx_f37);
1569 pm_runtime_set_suspended(&client->dev);
1570
1571 return 0;
1572 }
1573
1574 #if IS_ENABLED(CONFIG_OF)
1575 static const struct of_device_id jx_f37_of_match[] = {
1576 { .compatible = "soi,jx_f37" },
1577 {},
1578 };
1579 MODULE_DEVICE_TABLE(of, jx_f37_of_match);
1580 #endif
1581
1582 static const struct i2c_device_id jx_f37_match_id[] = {
1583 { "soi,jx_f37", 0 },
1584 { },
1585 };
1586
1587 static struct i2c_driver jx_f37_i2c_driver = {
1588 .driver = {
1589 .name = JX_F37_NAME,
1590 .pm = &jx_f37_pm_ops,
1591 .of_match_table = of_match_ptr(jx_f37_of_match),
1592 },
1593 .probe = &jx_f37_probe,
1594 .remove = &jx_f37_remove,
1595 .id_table = jx_f37_match_id,
1596 };
1597
sensor_mod_init(void)1598 static int __init sensor_mod_init(void)
1599 {
1600 return i2c_add_driver(&jx_f37_i2c_driver);
1601 }
1602
sensor_mod_exit(void)1603 static void __exit sensor_mod_exit(void)
1604 {
1605 i2c_del_driver(&jx_f37_i2c_driver);
1606 }
1607
1608 device_initcall_sync(sensor_mod_init);
1609 module_exit(sensor_mod_exit);
1610
1611 MODULE_DESCRIPTION("SOI jx_f37 sensor driver");
1612 MODULE_LICENSE("GPL v2");
1613