xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/jaguar1_drv/jaguar1_ioctl.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __JAGUAR1_IOCTL_H__
3*4882a593Smuzhiyun #define __JAGUAR1_IOCTL_H__
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun /*----------------------- Set All - for MIPI interface  ---------------------*/
6*4882a593Smuzhiyun #define IOC_VDEC_INIT_ALL                     0xF0
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun /*----------------------- VIDEO Initialize  ---------------------*/
9*4882a593Smuzhiyun #define IOC_VDEC_INPUT_INIT			 		  0x10
10*4882a593Smuzhiyun #define IOC_VDEC_OUTPUT_SEQ_SET		  		  0x11
11*4882a593Smuzhiyun #define IOC_VDEC_VIDEO_EQ_SET		  	  	  0x13
12*4882a593Smuzhiyun #define IOC_VDEC_VIDEO_SW_RESET				  0x14
13*4882a593Smuzhiyun #define IOC_VDEC_SINGLE_DIFFERNTIAL_SET		  0x15
14*4882a593Smuzhiyun #define IOC_VDEC_VIDEO_EQ_CABLE_SET		  	  0x16
15*4882a593Smuzhiyun #define IOC_VDEC_VIDEO_EQ_ANALOG_INPUT_SET	  0x17
16*4882a593Smuzhiyun #define IOC_VDEC_VIDEO_GET_VIDEO_LOSS         0x18
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /*----------------------- Coaxial protocol  ---------------------*/
19*4882a593Smuzhiyun // Coax UP Stream - 8bit
20*4882a593Smuzhiyun #define IOC_VDEC_COAX_TX_INIT			  0xA0
21*4882a593Smuzhiyun #define IOC_VDEC_COAX_TX_CMD_SEND	  0xA1
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun // Coax UP Stream - 16bit only ACP 720P Support
24*4882a593Smuzhiyun #define IOC_VDEC_COAX_TX_16BIT_INIT		  0xB4
25*4882a593Smuzhiyun #define IOC_VDEC_COAX_TX_16BIT_CMD_SEND	  0xB5
26*4882a593Smuzhiyun #define IOC_VDEC_COAX_TX_CVI_NEW_CMD_SEND 0xB6
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun // Coax Down Stream
29*4882a593Smuzhiyun #define IOC_VDEC_COAX_RX_INIT      0xA2
30*4882a593Smuzhiyun #define IOC_VDEC_COAX_RX_DATA_READ 0xA3
31*4882a593Smuzhiyun #define IOC_VDEC_COAX_RX_BUF_CLEAR 0xA4
32*4882a593Smuzhiyun #define IOC_VDEC_COAX_RX_DEINIT    0xA5
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun // Coax Test
35*4882a593Smuzhiyun #define IOC_VDEC_COAX_TEST_TX_INIT_DATA_READ  0xA6
36*4882a593Smuzhiyun #define IOC_VDEC_COAX_TEST_DATA_SET           0xA7
37*4882a593Smuzhiyun #define IOC_VDEC_COAX_TEST_DATA_READ          0xA8
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun // Coax FW Update
41*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_ACP_HEADER_GET     0xA9
42*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_READY_CMD_SET  0xAA
43*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_READY_ACK_GET  0xAB
44*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_START_CMD_SET  0xAC
45*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_START_ACK_GET  0xAD
46*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_SEND_DATA_SET  0xAE
47*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_SEND_ACK_GET   0xAF
48*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_END_CMD_SET    0xB0
49*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_END_ACK_GET    0xB1
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun // Bank Dump Test
52*4882a593Smuzhiyun #define IOC_VDEC_COAX_BANK_DUMP_GET    0xB2
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun // ACP Option
55*4882a593Smuzhiyun #define IOC_VDEC_COAX_RT_NRT_MODE_CHANGE_SET 0xB3
56*4882a593Smuzhiyun #define IOC_VDEC_COAX_RX_DETECTION_READ      0x12
57*4882a593Smuzhiyun #define IOC_VDEC_ACP_WRITE                   0xB7
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /*----------------------- MOTION -----------------*/
61*4882a593Smuzhiyun #define IOC_VDEC_MOTION_SET			0x70
62*4882a593Smuzhiyun #define IOC_VDEC_MOTION_PIXEL_SET     0x71
63*4882a593Smuzhiyun #define IOC_VDEC_MOTION_PIXEL_GET     0x72
64*4882a593Smuzhiyun #define IOC_VDEC_MOTION_TSEN_SET      0x73
65*4882a593Smuzhiyun #define IOC_VDEC_MOTION_PSEN_SET      0x74
66*4882a593Smuzhiyun #define IOC_VDEC_MOTION_ALL_PIXEL_SET 0x75
67*4882a593Smuzhiyun #define IOC_VDEC_MOTION_DETECTION_GET 0x76
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /*----------------------  GET CHIP ID FUNCTION ---------------------*/
70*4882a593Smuzhiyun #define IOC_VDEC_GET_CHIP_ID		0x90
71*4882a593Smuzhiyun #define IOC_VDEC_CH_SW_RESET		0x91
72*4882a593Smuzhiyun #define IOC_VDEC_HAFC_GAIN12_CTRL	0x92
73*4882a593Smuzhiyun #define IOC_VDEC_AFE_RESET			0x93
74*4882a593Smuzhiyun #define IOC_VDEC_GET_DRIVERVER      0x94
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define IOC_VDEC_MANUAL_AGC_STABLE_ENABLE	0x82
77*4882a593Smuzhiyun #define IOC_VDEC_MANUAL_AGC_STABLE_DISABLE	0x83
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #endif
80