1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * it66353 HDMI 3 in 1 out driver. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Kenneth.Hung@ite.com.tw 8*4882a593Smuzhiyun * Wangqiang Guo <kay.guo@rock-chips.com> 9*4882a593Smuzhiyun * Version: IT66353_SAMPLE_1.08 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #ifndef _IT66353_H_ 13*4882a593Smuzhiyun #define _IT66353_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun typedef struct { 16*4882a593Smuzhiyun u8 EnRxDDCBypass; 17*4882a593Smuzhiyun u8 EnableAutoEQ; 18*4882a593Smuzhiyun } IT6635_DEVICE_OPTION; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #ifdef __cplusplus 21*4882a593Smuzhiyun extern "C" { 22*4882a593Smuzhiyun #endif 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun // ------------------------------ 25*4882a593Smuzhiyun // APIs: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun char *it66353_get_lib_version(void); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun void it66353_setup_edid_ram_phyaddr(u8 *edid, u8 block); 30*4882a593Smuzhiyun void it66353_set_internal_EDID(u8 block, u8 *edid, u8 target_port); 31*4882a593Smuzhiyun void it66353_get_internal_EDID(u8 block, u8 *edid, u8 target_port); 32*4882a593Smuzhiyun void it66353_parse_edid_for_phyaddr(u8 *edid); 33*4882a593Smuzhiyun bool it66353_read_one_block_edid(u8 block, u8 *edid_buffer); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define SW_HPD_LOW 0 36*4882a593Smuzhiyun #define SW_HPD_AUTO 1 37*4882a593Smuzhiyun void it66353_force_rx_hpd(u8 hpd_state); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun void it66353_set_option(IT6635_DEVICE_OPTION *Opts); 40*4882a593Smuzhiyun void it66353_get_option(IT6635_DEVICE_OPTION *Opts); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun u8 it66353_get_RS(void); 43*4882a593Smuzhiyun void it66353_set_RS(u8 rs_idx0, u8 rs_idx1, u8 rs_idx2); 44*4882a593Smuzhiyun void it66353_set_ch_RS(u8 ch, u8 rs_index); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun void it66353_dump_register_all(void); 47*4882a593Smuzhiyun void it66353_dump_opts(void); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun u8 it66353_get_active_port(void); 50*4882a593Smuzhiyun bool it66353_set_active_port(u8 port); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun void it66353_change_default_RS(u8 port, u8 new_rs_idx0, 53*4882a593Smuzhiyun u8 new_rs_idx1, u8 new_rs_idx2, u8 update_hw); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun void it66353_set_rx_hpd(u8 hpd_value); 56*4882a593Smuzhiyun void it66353_set_tx_5v(u8 output_value); 57*4882a593Smuzhiyun bool it66353_toggle_hpd(u16 ms_duration); 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun bool it66353_auto_eq_adjust(void); 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun void it66353_dev_restart(void); 62*4882a593Smuzhiyun void it66353_vars_init(void); 63*4882a593Smuzhiyun void it66353_options_init(void); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * it6635 event handler: 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun // static void it66353_dev_loop(void); 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * platform dependent functions: (needs implementation) 72*4882a593Smuzhiyun * u8 it66353_i2c_write(u8 addr, u8 offset, u8 length, u8 *buffer); 73*4882a593Smuzhiyun * u8 it66353_i2c_read(u8 addr, u8 offset, u8 length, u8 *buffer); 74*4882a593Smuzhiyun * static void it66353_i2c_read(u8 i2c_addr, u16 reg, u8 n, u8 *val); 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun void delay1ms(u16 ms); 77*4882a593Smuzhiyun __tick get_tick_count(void); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #ifdef __cplusplus 80*4882a593Smuzhiyun } 81*4882a593Smuzhiyun #endif 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif 84