1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * it66353 HDMI 3 in 1 out driver. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Kenneth.Hung@ite.com.tw 8*4882a593Smuzhiyun * Wangqiang Guo <kay.guo@rock-chips.com> 9*4882a593Smuzhiyun * Version: IT66353_SAMPLE_1.08 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #ifndef _66353_CONFIG_H_ 13*4882a593Smuzhiyun #define _66353_CONFIG_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _SHOW_PRAGMA_MSG 16*4882a593Smuzhiyun #define message(ignore) 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * Switch register i2c address: 0x94(PCADR=0) or 0x96(PCADR=1) 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #define SWAddr 0xAC 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * RX register i2c address ( programmable ) 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define RXAddr 0xB2 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * CEC register i2c address ( programmable ) 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #define CECAddr 0xC0 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun * EDID RAM i2c address ( programmable ) 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define RXEDIDAddr 0xa8 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * Internal compile options: 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun #define DEBUG_FSM_CHANGE 1 43*4882a593Smuzhiyun #define USING_WDOG 0 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * 66353 and 66354 don't need this: 47*4882a593Smuzhiyun * set to 0 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define CHECK_INT_BEFORE_TXOE 0 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * EN_AUTO_RS: ( compile option ) 53*4882a593Smuzhiyun * 1: Enable Auto EQ code 54*4882a593Smuzhiyun * 0: Disable Auto EQ code 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun #define EN_H14_SKEW 0 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * EN_AUTO_RS: ( compile option ) 60*4882a593Smuzhiyun * 1: Enable Auto EQ code 61*4882a593Smuzhiyun * 0: Disable Auto EQ code 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun #define EN_AUTO_RS 1 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * EN_CEC: 67*4882a593Smuzhiyun * 1: Enable CEC function 68*4882a593Smuzhiyun * 0: Disable CEC function 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun #define EN_CEC 0 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * FIX_EDID_FOR_ATC_4BLOCK_CTS: 74*4882a593Smuzhiyun * 1: For ATC 4 blocks EDID test 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define FIX_EDID_FOR_ATC_4BLOCK_CTS 1 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #endif // _66353_CONFIG_H_ 79*4882a593Smuzhiyun 80