1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4 *
5 * it6616 HDMI to MIPI CSI-2 bridge driver.
6 *
7 * Author: Jau-Chih.Tseng@ite.com.tw
8 * Jianwei Fan <jianwei.fan@rock-chips.com>
9 * V0.0X01.0X00 first version.
10 *
11 */
12 // #define DEBUG
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/hdmi.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of_graph.h>
22 #include <linux/rk-camera-module.h>
23 #include <linux/slab.h>
24 #include <linux/timer.h>
25 #include <linux/v4l2-dv-timings.h>
26 #include <linux/version.h>
27 #include <linux/videodev2.h>
28 #include <linux/workqueue.h>
29 #include <linux/compat.h>
30 #include <linux/regmap.h>
31 #include <media/v4l2-controls_rockchip.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-device.h>
34 #include <media/v4l2-dv-timings.h>
35 #include <media/v4l2-event.h>
36 #include <media/v4l2-fwnode.h>
37 #include <media/cec.h>
38
39 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
40
41 static int debug;
42 module_param(debug, int, 0644);
43 MODULE_PARM_DESC(debug, "debug level (0-3)");
44
45 #define IT6616_NAME "IT6616"
46 #define POLL_INTERVAL_MS 100
47 #define TIMER_100MS 105
48 #define IT6616_XVCLK_FREQ 27000000
49
50 #define IT6616_LINK_FREQ 400000000
51 #define IT6616_PIXEL_RATE 400000000
52 #define IT6616_MEDIA_BUS_FMT MEDIA_BUS_FMT_UYVY8_2X8
53
54 #define I2C_ADR_HDMI 0x90
55 #define I2C_ADR_MIPI 0xAC
56 #define I2C_ADR_EDID 0xA8
57
58 //define in HDMI SPEC 2.0 PAGE 84
59 #define AUDIO_SAMPLING_1024K 0x35
60 #define AUDIO_SAMPLING_768K 0x09
61 #define AUDIO_SAMPLING_512K 0x3B
62 #define AUDIO_SAMPLING_384K 0x05
63 #define AUDIO_SAMPLING_256K 0x1B
64 #define AUDIO_SAMPLING_192K 0x0E
65 #define AUDIO_SAMPLING_176P4K 0x0C
66 #define AUDIO_SAMPLING_128K 0x2B
67 #define AUDIO_SAMPLING_96K 0x0A
68 #define AUDIO_SAMPLING_88P2K 0x08
69 #define AUDIO_SAMPLING_64K 0x0B
70 #define AUDIO_SAMPLING_48K 0x02
71 #define AUDIO_SAMPLING_44P1K 0x00
72 #define AUDIO_SAMPLING_32K 0x03
73
74 #define REG_RX_AVI_HB1 0x13
75 #define REG_RX_AVI_HB2 0x12
76 #define REG_RX_AVI_DB0 0x14
77 #define REG_RX_AVI_DB1 0x15
78 #define REG_RX_AVI_DB2 0x16
79 #define REG_RX_AVI_DB3 0x17
80 #define REG_RX_AVI_DB4 0x18
81 #define REG_RX_AVI_DB5 0x19
82 #define REG_RX_AVI_DB6 0x1A
83 #define REG_RX_AVI_DB7 0x1B
84 #define REG_RX_AVI_DB8 0x1C
85 #define REG_RX_AVI_DB9 0x1D
86 #define REG_RX_AVI_DB10 0x1E
87 #define REG_RX_AVI_DB11 0x1F
88 #define REG_RX_AVI_DB12 0x20
89 #define REG_RX_AVI_DB13 0x21
90 #define REG_RX_AVI_DB14 0x22
91 #define REG_RX_AVI_DB15 0x23
92
93 #define DP_REG_INT_STS_07 0x07
94 #define DP_REG_INT_STS_08 0x08
95 #define DP_REG_INT_STS_09 0x09
96 #define DP_REG_INT_STS_0A 0x0A
97 #define DP_REG_INT_STS_0B 0x0B
98 #define DP_REG_INT_STS_0C 0x0C
99 #define DP_REG_INT_STS_0D 0x0D
100 #define DP_REG_INT_STS_0E 0x0E
101 #define DP_REG_INT_STS_0F 0x0F
102 #define DP_REG_INT_STS_2B 0x2B
103 #define DP_REG_INT_STS_2C 0x2C
104 #define DP_REG_INT_STS_2D 0x2D
105
106 #define DP_REG_INT_MASK_07 0xD1
107 #define DP_REG_INT_MASK_08 0xD2
108 #define DP_REG_INT_MASK_09 0xD3
109 #define DP_REG_INT_MASK_0A 0xD4
110 #define DP_REG_INT_MASK_0B 0xD5
111 #define DP_REG_INT_MASK_0C 0xD6
112 #define DP_REG_INT_MASK_0D 0xD7
113 #define DP_REG_INT_MASK_0E 0xD8
114 #define DP_REG_INT_MASK_0F 0xD9
115 #define DP_REG_INT_MASK_10 0xDA
116 #define DP_REG_INT_MASK_11 0xDB
117 #define DP_REG_INT_MASK_2D 0xDC
118 #define DP_REG_INT_MASK_2C 0xDD
119 #define DP_REG_INT_MASK_2B 0xDE
120
121 #define BANK 0x0F
122 #define BANKM 0x07
123 #define FROM_CONFIG 0xFF
124
125 #define AUDIO_I2S_JUSTIFIED AUDIO_I2S_MODE
126 // #define MIPI_TX_INTERFACE MIPI_DSI
127 #define MIPI_TX_INTERFACE MIPI_CSI
128 #define MIPI_TX_LANE_SWAP false
129 #define MIPI_TX_PN_SWAP false
130 // #define MIPI_TX_DATA_TYPE DSI_RGB_24b
131 #define MIPI_TX_DATA_TYPE CSI_YCbCr4228b
132 #define MIPI_TX_ENABLE_AUTO_ADJUST_LANE_COUNT false
133 /* HDMI_RX_VIDEO_STABLE_CONDITION_V_FRAME,
134 * HDMI_RX_VIDEO_STABLE_CONDITION_CLOCK,
135 * HDMI_RX_VIDEO_STABLE_CONDITION_H_LINE
136 */
137 #define HDMI_RX_VIDEO_STABLE_CONDITION HDMI_RX_VIDEO_STABLE_CONDITION_V_FRAME
138 /* MIPI_TX_NON_CONTINUOUS_CLOCK, MIPI_TX_CONTINUOUS_CLOCK */
139 #define MIPI_TX_ENABLE_CONTINUOUS_CLOCK MIPI_TX_CONTINUOUS_CLOCK
140 #define MIPI_TX_ENABLE_DSI_SYNC_EVENT false
141 #define MIPI_TX_ENABLE_DSI_EOTP_PACKET false
142 #define MIPI_TX_ENABLE_INITIAL_FIRE_LP_CMD true
143 #define DEFAULT_RS_LEVEL 0x9F
144 #define MIPI_TX_ENABLE_MANUAL_ADJUSTED_D_PHY false
145 #define MIPI_TX_LPX 2
146 #define MIPI_TX_HS_PREPARE 0x02
147 #define MIPI_TX_HS_PREPARE_ZERO 0x04
148 #define MIPI_TX_HS_TRAIL 0x07
149
150 #define MAX_AUDIO_SAMPLING_FREQ_ERROR_COUNT 15
151 #define HDMI_RX_DISABLE_PIXEL_REPEAT true
152 #define MIPI_TX_LANE_ADJUST_THRESHOLD 30
153 #define MIPI_TX_V_LPM_LENGTH 0x200
154 #define MIPI_TX_H_LPM_LENGTH 0x80
155 #define MIPI_TX_ENABLE_H_ENTER_LPM false
156 #define MIPI_TX_ENABLE_HS_PRE_1T true
157 #define MIPI_TX_ENABLE_PCLK_INV false
158 #define MIPI_TX_ENABLE_MCLK_INV true
159 #define MIPI_TX_ENABLE_BY_PASS true
160 #define MIPI_TX_ENABLE_H_FIRE_PACKET false
161 #define HDMI_RX_ENABLE_COLOR_UP_DN_FILTER true
162 #define HDMI_RX_ENABLE_DITHER_FUNCTION false
163 #define HDMI_RX_ENABLE_DITHER_FCNT_FUNCTION false
164 #define HDMI_RX_COLOR_CLIP true
165 #define HDMI_RX_CRCB_LIMIT false
166 #define HDMI_RX_QUANT_4LB true
167 #define HDMI_RX_AUTO_CSC_SELECT false
168 #define LP_CMD_FIFO_SIZE 128
169
170 enum csc_matrix_type {
171 CSCMtx_RGB2YUV_ITU601_16_235,
172 CSCMtx_RGB2YUV_ITU601_00_255,
173 CSCMtx_RGB2YUV_ITU709_16_235,
174 CSCMtx_RGB2YUV_ITU709_00_255,
175 CSCMtx_YUV2RGB_ITU601_16_235,
176 CSCMtx_YUV2RGB_ITU601_00_255,
177 CSCMtx_YUV2RGB_ITU709_16_235,
178 CSCMtx_YUV2RGB_ITU709_00_255,
179 CSCMtx_YUV2RGB_BT2020_00_255,
180 CSCMtx_RGB_00_255_RGB_16_235,
181 CSCMtx_RGB_16_235_RGB_00_255,
182 CSCMtx_Unknown,
183 };
184
185 enum {
186 MIPI_CSI,
187 MIPI_DSI,
188 };
189
190 enum {
191 VSC_COLOR_RGB = 0x00,
192 VSC_COLOR_YUV444 = 0x01,
193 VSC_COLOR_YUV422 = 0x02,
194 VSC_COLOR_YUV420 = 0x03,
195 VSC_COLOR_YONLY,
196 VSC_COLOR_RAW,
197 VSC_COLOR_RESERVE
198 };
199
200 enum {
201 COLOR_RGB = 0x00,
202 COLOR_YUV422 = 0x01,
203 COLOR_YUV444 = 0x02,
204 COLOR_YUV420 = 0x03,
205 COLOR_RESERVE
206 };
207
208 enum {
209 COLORIMETRY_BT601 = 0x00,
210 COLORIMETRY_BT709 = 0x01,
211 COLORIMETRY_xvYCC601 = 0x02,
212 COLORIMETRY_xvYCC709 = 0x03,
213 COLORIMETRY_sYCC601 = 0x04,
214 COLORIMETRY_aYCC601 = 0x05,
215 COLORIMETRY_BT2020YcCbcCrc = 0x06,
216 COLORIMETRY_BT2020YCbCr = 0x07,
217 COLORIMETRY_RESERVE
218 };
219
220 enum {
221 COLORIMETRY_sRGB = 0x00,
222 COLORIMETRY_fixRGB = 0x01,
223 COLORIMETRY_scRGB = 0x02,
224 COLORIMETRY_aRGB = 0x03,
225 COLORIMETRY_DCIP3 = 0x04,
226 COLORIMETRY_CUSTOM = 0x05,
227 COLORIMETRY_BT2020RGB = 0x06
228
229 };
230
231 enum mipi_csi_data {
232 CSI_RGB10b = 0x25,
233 CSI_RGB888 = 0x24,
234 CSI_RGB666 = 0x23,
235 CSI_RGB565 = 0x22,
236 CSI_RGB555 = 0x21,
237 CSI_RGB444 = 0x20,
238 CSI_YCbCr4208b = 0x1A,
239 CSI_YCbCr4228b = 0x1E,
240 CSI_YCbCr42210b = 0x1F,
241 CSI_YCbCr42212b = 0x30
242 };
243
244 enum mipi_dsi_data {
245 DSI_RGB_24b = 0x3E,
246 DSI_RGB_30b = 0x0D,
247 DSI_RGB_36b = 0x1D,
248 DSI_RGB_18b = 0x1E,
249 DSI_RGB_18b_L = 0x2E,
250 DSI_YCbCr_16b = 0x2C,
251 DSI_YCbCr_20b = 0x0C,
252 DSI_YCbCr_24b = 0x1C
253 };
254
255 enum csc_select {
256 CSC_BYPASS = 0x00,
257 CSC_RGB2YUV = 0x02,
258 CSC_YUV2RGB = 0x03,
259 };
260
261 enum av_mute_state {
262 AV_MUTE_OFF,
263 AV_MUTE_ON,
264 };
265
266 enum {
267 AUDIO_OFF = 0x00,
268 AUDIO_I2S = 0x01,
269 AUDIO_SPDIF = 0x02,
270 };
271
272 enum {
273 AUDIO_I2S_MODE,
274 AUDIO_RIGHT_JUSTIFIED,
275 AUDIO_LEFT_JUSTIFIED,
276 };
277
278 enum {
279 MIPI_TX_NON_CONTINUOUS_CLOCK,
280 MIPI_TX_CONTINUOUS_CLOCK,
281 };
282
283 enum {
284 HDMI_RX_VIDEO_STABLE_CONDITION_V_FRAME,
285 HDMI_RX_VIDEO_STABLE_CONDITION_CLOCK,
286 HDMI_RX_VIDEO_STABLE_CONDITION_H_LINE,
287 };
288
289 enum dcs_cmd_name {
290 ENTER_SLEEP_MODE,
291 SET_DISPLAY_OFF,
292 EXIT_SLEEP_MODE,
293 SET_DISPLAY_ON,
294 GET_DISPLAY_MODE,
295 LONG_WRITE_CMD,
296 LONG_WRITE_CMD1,
297 DELAY,
298 };
299
300 enum mipi_lp_cmd_type {
301 LP_CMD_LPDT = 0x87,
302 LP_CMD_BTA = 0xFF,
303 };
304
305 enum mipi_packet_size {
306 SHORT_PACKET,
307 LONG_PACKET,
308 UNKNOWN_PACKET,
309 };
310
311 enum mipi_tx_lp_cmd_header {
312 NO_HEADER,
313 CALC_HEADER,
314 };
315
316 static const s64 link_freq_menu_items[] = {
317 IT6616_LINK_FREQ,
318 };
319
320 struct it6616_reg_set {
321 u8 ucAddr;
322 u8 andmask;
323 u8 ucValue;
324 };
325
326 struct bus_config {
327 u8 lane;
328 u8 type;
329 u8 reg23_p2m;
330 u8 regb0_div[3];
331 };
332
333 union tx_p2m_delay {
334 u8 tx_dsi_vsync_delay;
335 u8 tx_csi_p2m_delay;
336 };
337
338 struct bus_para {
339 struct bus_config cfg;
340 u8 swap_pn;
341 u8 swap_lan;
342 u8 pclk_inv;
343 u8 mclk_inv;
344 u8 lpx_num;
345 u8 mipi_tx_hs_prepare;
346 u8 tx_sel_line_start;
347 u8 tx_bypass;
348 u8 tx_enable_hs_pre_1T;
349 u8 tx_enable_h_enter_lpm;
350 u8 tx_vsync_delay;
351 union tx_p2m_delay p2m_delay;
352 u16 tx_vlpm_length;
353 u16 tx_hlpm_length;
354 };
355
356 struct mipi_bus {
357 u8 lane_cnt;
358 u8 data_type;
359 u8 bus_type;
360 u32 mbus_fmt_code;
361 struct bus_para bus_para_config;
362 };
363
364 struct mipi_packet_size_data_id_map {
365 u8 data_id;
366 enum mipi_packet_size packet_size;
367 };
368
369 struct mipi_packet_size_data_id_map packet_size_data_id_map[] = {
370 {0x05, SHORT_PACKET},/* dcs short write without parameter */
371 {0x15, SHORT_PACKET},/* dcs short write with one parameter */
372 {0x23, SHORT_PACKET},/* generic short write, 2 parameters */
373 {0x29, LONG_PACKET},/* generic long write */
374 {0x39, LONG_PACKET},/* dcs long write */
375 {0x06, SHORT_PACKET},
376 {0x16, SHORT_PACKET},
377 {0x37, SHORT_PACKET},
378 {0x03, SHORT_PACKET},
379 {0x13, SHORT_PACKET},
380 {0x04, SHORT_PACKET},
381 {0x14, SHORT_PACKET},
382 {0x24, SHORT_PACKET}
383 };
384
385 struct mipi_packet {
386 u8 data_id;
387 u8 word_count_l;
388 u8 word_count_h;
389 u8 ecc;
390 };
391
392 struct dcs_setting_entry {
393 enum dcs_cmd_name cmd_name;
394 enum mipi_lp_cmd_type cmd;
395 u8 data_id;
396 u8 count;
397 u8 para_list[LP_CMD_FIFO_SIZE];
398 };
399
400 static const struct dcs_setting_entry dcs_table[] = {
401 { /* command 0x10 with no parameter, checksum: 0x2C */
402 ENTER_SLEEP_MODE, LP_CMD_LPDT, 0x05, 2, {0x10, 0x00}
403 }, { /* command 0x28 with no parameter, checksum: 0x06 */
404 SET_DISPLAY_OFF, LP_CMD_LPDT, 0x05, 2, {0x28, 0x00}
405 }, { /* command 0x11 with no parameter, checksum: 0x36 */
406 EXIT_SLEEP_MODE, LP_CMD_LPDT, 0x05, 2, {0x11, 0x00}
407 }, { /* command 0x29 with no parameter, checksum: 0x1C */
408 SET_DISPLAY_ON, LP_CMD_LPDT, 0x05, 2, {0x29, 0x00}
409 }, { /* checksum: 0x1A */
410 GET_DISPLAY_MODE, LP_CMD_LPDT, 0x06, 2, {0x0D, 0x00}
411 }, { /* command 0x50 with 2 parameters */
412 LONG_WRITE_CMD, LP_CMD_LPDT, 0x39, 3, {0x50, 0x5A, 0x09}
413 }, { /* command 0x80 with 16 parameters */
414 LONG_WRITE_CMD1, LP_CMD_LPDT, 0x29, 17,
415 {0x80, 0x5A, 0x51, 0xB5, 0x2A, 0x6C, 0x35,
416 0x4B, 0x01, 0x40, 0xE1, 0x0D, 0x82, 0x20, 0x08, 0x30, 0x03}
417 }
418 };
419
420 static const int code_to_rate_table[] = {
421 44100, 0, 48000, 32000, 0, 384000, 0, 0, 88200,
422 768000, 96000, 64000, 176400, 0, 192000, 0, 0, 0,
423 0, 0, 0, 0, 0, 0, 0, 0, 0, 256000, 0, 0, 0, 0, 0,
424 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 128000, 0, 0, 0, 0,
425 0, 0, 0, 0, 0, 1024000, 0, 0, 0, 0, 0, 512000
426 };
427
428 struct color_format {
429 unsigned char color_mode;
430 unsigned char color_depth;
431 unsigned char color_cea_range;
432 unsigned char color_colorietry;
433 unsigned char color_ex_colorietry;
434 unsigned char content_type;
435 };
436
437 struct video_info {
438 u16 h_active;
439 u16 v_active;
440 u16 h_total;
441 u16 v_total;
442 u32 pclk;
443 u32 TMDSCLK;
444 u32 frame_rate;
445 u16 h_front_porch;
446 u16 h_sync_w;
447 u16 h_back_porch;
448 u16 v_front_porch;
449 u16 v_sync_w;
450 u16 v_back_porch;
451 u16 interlaced;
452 u16 v_sync_pol;
453 u16 h_sync_pol;
454 u16 ColorDepth;
455 u16 VIC;
456 };
457
458 struct audio_info {
459 u32 n;
460 u32 cts;
461 u8 channel_status;
462 u32 sample_freq;
463 u32 force_sample_freq;
464 };
465
466 struct it6616 {
467 struct i2c_client *hdmi_i2c;
468 struct i2c_client *mipi_i2c;
469 struct i2c_client *edid_i2c;
470 struct regmap *hdmi_regmap;
471 struct regmap *mipi_regmap;
472 struct regmap *edid_regmap;
473 u8 attr_hdmi_reg_bank;
474 struct class *hdmirx_class;
475 struct device *dev;
476 struct device *classdev;
477 struct v4l2_fwnode_bus_mipi_csi2 bus;
478 struct v4l2_subdev sd;
479 struct media_pad pad;
480 struct v4l2_ctrl_handler hdl;
481 struct i2c_client *i2c_client;
482 struct mutex confctl_mutex;
483 struct v4l2_ctrl *detect_tx_5v_ctrl;
484 struct v4l2_ctrl *audio_sampling_rate_ctrl;
485 struct v4l2_ctrl *audio_present_ctrl;
486 struct v4l2_ctrl *link_freq;
487 struct v4l2_ctrl *pixel_rate;
488 struct v4l2_dv_timings timings;
489 struct clk *xvclk;
490 struct gpio_desc *reset_gpio;
491 struct gpio_desc *power_gpio;
492 struct delayed_work work_i2c_poll;
493 const char *module_facing;
494 const char *module_name;
495 const char *len_name;
496 const struct it6616_mode *cur_mode;
497 bool nosignal;
498 bool is_audio_present;
499 u32 mbus_fmt_code;
500 u8 csi_lanes_in_use;
501 u32 module_index;
502 u32 audio_sampling_rate;
503 bool hdmi_rx_video_stable;
504 bool hdmi_rx_hdcp_state;
505 bool mipi_tx_video_stable;
506 bool mipi_tx_enable_manual_adjusted_d_phy;
507 u8 audio_stable;
508 u8 audio_interface;
509 u8 rs_level;
510 struct mipi_bus mipi;
511 struct color_format color_fmt;
512 struct video_info vinfo;
513 struct audio_info ainfo;
514 u8 edid_data[256];
515 u16 edid_len;
516 u8 audio_sampling_freq_error_count;
517 u8 audio_i2s_justified;
518 u8 mipi_tx_enable_auto_adjust_lane_count;
519 u8 mipi_tx_enable_h_fire_packet;
520 u8 mipi_tx_enable_initial_fire_lp_cmd;
521 u8 hdmi_rx_disable_pixel_repeat;
522 bool mipi_tx_enable_continuous_clock;
523 u8 mipi_tx_enable_mipi_output;
524 u8 hdmi_rx_video_stable_condition;
525 bool power_on;
526 u32 rclk;
527 u32 tx_mclk;
528 u32 tx_rclk;
529 u32 tx_pclk;
530 u32 tx_mclk_ps;
531 struct hdmi_avi_infoframe avi_if;
532 struct hdmi_avi_infoframe avi_if_prev;
533 enum hdmi_colorspace output_colorspace;
534 };
535
536 static const struct v4l2_dv_timings_cap it6616_timings_cap = {
537 .type = V4L2_DV_BT_656_1120,
538 .reserved = { 0 },
539 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 400000000,
540 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
541 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
542 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
543 V4L2_DV_BT_CAP_REDUCED_BLANKING |
544 V4L2_DV_BT_CAP_CUSTOM)
545 };
546
547 struct it6616_mode {
548 u32 width;
549 u32 height;
550 struct v4l2_fract max_fps;
551 u32 hts_def;
552 u32 vts_def;
553 u32 exp_def;
554 };
555
556 static const struct it6616_mode supported_modes[] = {
557 {
558 .width = 3840,
559 .height = 2160,
560 .max_fps = {
561 .numerator = 10000,
562 .denominator = 300000,
563 },
564 .hts_def = 4400,
565 .vts_def = 2250,
566 }, {
567 .width = 1920,
568 .height = 1080,
569 .max_fps = {
570 .numerator = 10000,
571 .denominator = 600000,
572 },
573 .hts_def = 2200,
574 .vts_def = 1125,
575 }, {
576 .width = 1920,
577 .height = 540,
578 .max_fps = {
579 .numerator = 10000,
580 .denominator = 600000,
581 },
582 .hts_def = 2200,
583 .vts_def = 562,
584 }, {
585 .width = 1280,
586 .height = 720,
587 .max_fps = {
588 .numerator = 10000,
589 .denominator = 600000,
590 },
591 .hts_def = 1650,
592 .vts_def = 750,
593 }, {
594 .width = 720,
595 .height = 576,
596 .max_fps = {
597 .numerator = 10000,
598 .denominator = 500000,
599 },
600 .hts_def = 864,
601 .vts_def = 625,
602 }, {
603 .width = 720,
604 .height = 480,
605 .max_fps = {
606 .numerator = 10000,
607 .denominator = 600000,
608 },
609 .hts_def = 858,
610 .vts_def = 525,
611 }, {
612 .width = 720,
613 .height = 288,
614 .max_fps = {
615 .numerator = 10000,
616 .denominator = 500000,
617 },
618 .hts_def = 864,
619 .vts_def = 312,
620 }, {
621 .width = 720,
622 .height = 240,
623 .max_fps = {
624 .numerator = 10000,
625 .denominator = 600000,
626 },
627 .hts_def = 858,
628 .vts_def = 262,
629 },
630 };
631
632 static const u8 default_edid[] = {
633 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
634 0x49, 0x78, 0x01, 0x88, 0x00, 0x88, 0x88, 0x88,
635 0x1C, 0x1F, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
636 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
637 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
638 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
639 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
640 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
641 0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
642 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
643 0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00,
644 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
645 0x37, 0x34, 0x39, 0x2D, 0x66, 0x48, 0x44, 0x37,
646 0x32, 0x30, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
647 0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
648 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x64,
649
650 0x02, 0x03, 0x1C, 0x71, 0x49, 0x90, 0x04, 0x02,
651 0x5F, 0x11, 0x07, 0x05, 0x16, 0x22, 0x23, 0x09,
652 0x07, 0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03,
653 0x0C, 0x00, 0x10, 0x00, 0x8C, 0x0A, 0xD0, 0x8A,
654 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00,
655 0x13, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0xD8, 0x09,
656 0x80, 0xA0, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x60,
657 0xA2, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x18,
658 0x8C, 0x0A, 0xD0, 0x90, 0x20, 0x40, 0x31, 0x20,
659 0x0C, 0x40, 0x55, 0x00, 0x48, 0x39, 0x00, 0x00,
660 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38,
661 0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0xC0, 0x6C,
662 0x00, 0x00, 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18,
663 0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00,
664 0xC0, 0x6C, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB3,
666 };
667
668 static const struct bus_config it6616_csi_bus_cfg[] = {
669 {4, CSI_RGB10b, 0x8F, {0xEE, 0xEE, 0xEE}},
670 {4, CSI_RGB888, 0x23, {0x65, 0x22, 0x22}},
671 {4, CSI_RGB666, 0x89, {0xE8, 0xE8, 0xE8}},
672 {4, CSI_RGB565, 0x22, {0x63, 0x21, 0x00}},
673 {4, CSI_RGB555, 0x22, {0x63, 0x21, 0x00}},
674 {4, CSI_RGB444, 0x22, {0x63, 0x21, 0x00}},
675 {4, CSI_YCbCr4208b, 0x23, {0x65, 0x22, 0x22}},
676 {4, CSI_YCbCr4228b, 0x22, {0x63, 0x21, 0x00}},
677 {4, CSI_YCbCr42210b, 0x45, {0x64, 0x64, 0x64}},
678 {4, CSI_YCbCr42212b, 0x23, {0x65, 0x22, 0x22}},
679
680 {2, CSI_RGB10b, 0x4F, {0x6E, 0x6E, 0x6E}},
681 {2, CSI_RGB888, 0x13, {0x6B, 0x25, 0x25}},
682 {2, CSI_RGB666, 0x49, {0x68, 0x68, 0x68}},
683 {2, CSI_RGB565, 0x12, {0x67, 0x23, 0x01}},
684 {2, CSI_RGB555, 0x12, {0x67, 0x23, 0x01}},
685 {2, CSI_RGB444, 0x12, {0x67, 0x23, 0x01}},
686 {2, CSI_YCbCr4208b, 0x13, {0x6B, 0x25, 0x25}},
687 {2, CSI_YCbCr4228b, 0x12, {0x67, 0x23, 0x01}},
688 {2, CSI_YCbCr42210b, 0x25, {0x69, 0x24, 0x24}},
689 {2, CSI_YCbCr42212b, 0x13, {0x6B, 0x25, 0x25}},
690
691 {1, CSI_RGB10b, 0x2F, {0x7D, 0x2E, 0x2E}},
692 {1, CSI_RGB888, 0x03, {0x77, 0x2B, 0x05}},
693 {1, CSI_RGB666, 0x29, {0x71, 0x28, 0x28}},
694 {1, CSI_RGB565, 0x02, {0x6F, 0x27, 0x03}},
695 {1, CSI_RGB555, 0x02, {0x6F, 0x27, 0x03}},
696 {1, CSI_RGB444, 0x02, {0x6F, 0x27, 0x03}},
697 {1, CSI_YCbCr4208b, 0x03, {0x77, 0x2B, 0x05}},
698 {1, CSI_YCbCr4228b, 0x02, {0x6F, 0x27, 0x03}},
699 {1, CSI_YCbCr42210b, 0x15, {0x73, 0x29, 0x04}},
700 {1, CSI_YCbCr42212b, 0x03, {0x77, 0x2B, 0x05}},
701 {0, 0, 0, {0, 0, 0}},
702 };
703
704 static const struct bus_config it6616_dsi_bus_cfg[] = {
705 {4, DSI_RGB_36b, 0x19, {0x68, 0x68, 0x68}},
706 {4, DSI_RGB_30b, 0x2F, {0xEE, 0xEE, 0xEE}},
707 {4, DSI_RGB_24b, 0x03, {0x65, 0x22, 0x22}},
708 {4, DSI_RGB_18b_L, 0x03, {0x65, 0x22, 0x22}},
709 {4, DSI_RGB_18b, 0x29, {0xE8, 0xE8, 0xE8}},
710
711 {2, DSI_RGB_36b, 0x19, {0x71, 0x28, 0x28}},
712 {2, DSI_RGB_30b, 0x2F, {0x6E, 0x6E, 0x6E}},
713 {2, DSI_RGB_24b, 0x03, {0x6B, 0x25, 0x25}},
714 {2, DSI_RGB_18b_L, 0x03, {0x6B, 0x25, 0x25}},
715 {2, DSI_RGB_18b, 0x29, {0x68, 0x68, 0x68}},
716
717 {1, DSI_RGB_36b, 0x19, {0x31, 0x31, 0x08}},
718 {1, DSI_RGB_30b, 0x2F, {0x7D, 0x2E, 0x2E}},
719 {1, DSI_RGB_24b, 0x03, {0x77, 0x2B, 0x05}},
720 {1, DSI_RGB_18b_L, 0x03, {0x77, 0x2B, 0x05}},
721 {1, DSI_RGB_18b, 0x29, {0x71, 0x28, 0x28}},
722
723 //add in D0 yuv422
724 {4, DSI_YCbCr_16b, 0x02, {0x63, 0x21, 0x00}},
725 {4, DSI_YCbCr_20b, 0x03, {0x65, 0x22, 0x22}},
726 {4, DSI_YCbCr_24b, 0x03, {0x65, 0x22, 0x22}},
727
728 {2, DSI_YCbCr_16b, 0x02, {0x67, 0x23, 0x01}},
729 {2, DSI_YCbCr_20b, 0x03, {0x6B, 0x25, 0x25}},
730 {2, DSI_YCbCr_24b, 0x03, {0x6B, 0x25, 0x25}},
731
732 {1, DSI_YCbCr_16b, 0x02, {0x6F, 0x27, 0x03}},
733 {1, DSI_YCbCr_20b, 0x03, {0x77, 0x2B, 0x05}},
734 {1, DSI_YCbCr_24b, 0x03, {0x77, 0x2B, 0x05}},
735 {0, 0, 0, {0, 0, 0}},
736 };
737
738 static const u8 mipi_color_space[][10] = {
739 {
740 CSI_RGB10b,
741 CSI_RGB888,
742 CSI_RGB666,
743 CSI_RGB565,
744 CSI_RGB555,
745 CSI_RGB444,
746 CSI_YCbCr4208b,
747 CSI_YCbCr4228b,
748 CSI_YCbCr42210b,
749 CSI_YCbCr42212b
750 }, {
751 DSI_RGB_36b,
752 DSI_RGB_30b,
753 DSI_RGB_24b,
754 DSI_RGB_18b_L,
755 DSI_RGB_18b,
756 DSI_YCbCr_16b,
757 DSI_YCbCr_20b,
758 DSI_YCbCr_24b,
759 0xFF,
760 0xFF
761 }
762 };
763
764 static char *mipi_color_space_name[][10] = {
765 {
766 "CSI_RGB10b",
767 "CSI_RGB888",
768 "CSI_RGB666",
769 "CSI_RGB565",
770 "CSI_RGB555",
771 "CSI_RGB444",
772 "CSI_YCbCr4208b",
773 "CSI_YCbCr4228b",
774 "CSI_YCbCr42210b",
775 "CSI_YCbCr42212b"
776 }, {
777 "DSI_RGB_36b",
778 "DSI_RGB_30b",
779 "DSI_RGB_24b",
780 "DSI_RGB_18b_L",
781 "DSI_RGB_18b",
782 "DSI_YCbCr_16b",
783 "DSI_YCbCr_20b",
784 "DSI_YCbCr_24b",
785 "can not find color space",
786 "can not find color space"
787 }
788 };
789
790 static const u8 csc_matrix[][22] = {
791 {
792 0x00, 0x80, 0x10, 0xB2, 0x04, 0x65, 0x02, 0xE9, 0x00, 0x93, 0x3C,
793 0x18, 0x04, 0x55, 0x3F, 0x49, 0x3D, 0x9F, 0x3E, 0x18, 0x04, 0x00
794 }, {
795 0x10, 0x80, 0x10, 0x09, 0x04, 0x0E, 0x02, 0xC9, 0x00, 0x0F, 0x3D,
796 0x84, 0x03, 0x6D, 0x3F, 0xAB, 0x3D, 0xD1, 0x3E, 0x84, 0x03, 0x00
797 }, {
798 0x00, 0x80, 0x10, 0xB8, 0x05, 0xB4, 0x01, 0x94, 0x00, 0x4A, 0x3C,
799 0x17, 0x04, 0x9F, 0x3F, 0xD9, 0x3C, 0x10, 0x3F, 0x17, 0x04, 0x00
800 }, {
801 0x10, 0x80, 0x10, 0xEA, 0x04, 0x77, 0x01, 0x7F, 0x00, 0xD0, 0x3C,
802 0x83, 0x03, 0xAD, 0x3F, 0x4B, 0x3D, 0x32, 0x3F, 0x83, 0x03, 0x00
803 }, {
804 0x00, 0x00, 0x00, 0x00, 0x08, 0x6B, 0x3A, 0x50, 0x3D, 0x00, 0x08,
805 0xF5, 0x0A, 0x02, 0x00, 0x00, 0x08, 0xFD, 0x3F, 0xDA, 0x0D, 0x00
806 }, {
807 0x04, 0x00, 0xA7, 0x4F, 0x09, 0x81, 0x39, 0xDD, 0x3C, 0x4F, 0x09,
808 0xC4, 0x0C, 0x01, 0x00, 0x4F, 0x09, 0xFD, 0x3F, 0x1F, 0x10, 0x00
809 }, {
810 0x00, 0x00, 0x00, 0x00, 0x08, 0x55, 0x3C, 0x88, 0x3E, 0x00, 0x08,
811 0x51, 0x0C, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x84, 0x0E, 0x00
812 }, {
813 0x04, 0x00, 0xA7, 0x4F, 0x09, 0xBA, 0x3B, 0x4B, 0x3E, 0x4F, 0x09,
814 0x57, 0x0E, 0x02, 0x00, 0x4F, 0x09, 0xFE, 0x3F, 0xE8, 0x10, 0x00
815 }, {
816 0x04, 0x00, 0xA7, 0x4F, 0x09, 0xCC, 0x3A, 0x7E, 0x3E, 0x4F, 0x09,
817 0x69, 0x0D, 0x0B, 0x00, 0x4F, 0x09, 0xFE, 0x3F, 0x1D, 0x11, 0x00
818 }, {
819 0x10, 0x10, 0x00, 0xe0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
820 0xe0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x06, 0x10
821 }, {
822 0xED, 0xED, 0x00, 0x50, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
823 0x50, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x09, 0xED
824 }
825 };
826
827 struct it6616_reg_set it6616_hdmi_init_table[] = {
828 {0x0F, 0xFF, 0x00},
829 {0x22, 0xFF, 0x08},
830 {0x22, 0xFF, 0x17},
831 {0x23, 0xFF, 0x1F},
832 {0x2B, 0xFF, 0x1F},
833 {0x24, 0xFF, 0xF8},
834 {0x22, 0xFF, 0x10},
835 {0x23, 0xFF, 0xA0},
836 {0x2B, 0xFF, 0xA0},
837 {0x24, 0xFF, 0x00},
838 {0x2F, 0xFF, 0xAD},
839 {0x34, 0xFF, 0x00},
840 {0x0F, 0xFF, 0x03},
841 {0xAA, 0xFF, 0xEC},
842 {0x0F, 0xFF, 0x00},
843 {0x0F, 0xFF, 0x03},
844 {0xAC, 0xFF, 0x40},
845 {0x0F, 0xFF, 0x00},
846 {0x3A, 0xFF, 0x89},
847 {0x43, 0xFF, 0x01},
848 {0x0F, 0xFF, 0x04},
849 {0x43, 0xFF, 0x01},
850 {0x3A, 0xFF, 0x89},
851 {0x0F, 0xFF, 0x03},
852 {0xA8, 0xFF, 0x0B},
853 {0x0F, 0xFF, 0x00},
854 {0x4F, 0xFF, 0x84},
855 {0x44, 0xFF, 0x19},
856 {0x46, 0xFF, 0x15},
857 {0x47, 0xFF, 0x88},
858 {0xD9, 0xFF, 0x00},
859 {0xF0, 0xFF, 0x78},
860 {0xF1, 0xFF, 0x10},
861 {0x0F, 0xFF, 0x03},
862 {0x3A, 0xFF, 0x02},
863 {0x0F, 0xFF, 0x00},
864 {0x28, 0xFF, 0x88},
865 {0x6E, 0xFF, 0x00},
866 {0x77, 0xFF, 0x87},
867 {0x7B, 0xFF, 0x00},
868 {0x86, 0xFF, 0x00},
869 {0x0F, 0xFF, 0x00},
870 {0x36, 0xFF, 0x06},
871 {0x8F, 0xFF, 0x41},
872 {0x0F, 0xFF, 0x01},
873 {0xC0, 0xFF, 0x42},
874 {0xC4, 0x70, 3<<4},
875 {0xC4, BIT(7), 0<<7},
876 {0xC7, 0xFF, 0x7F},
877 {0xC8, 0xFF, 0x1F},
878 {0xC9, 0xFF, 0x90},
879 {0xCA, 0xFF, 0x99},
880 {0x0F, 0xFF, 0x00},
881 {0x86, 0x0C, 0x08},
882 {0x81, BIT(7), BIT(7)},
883 {BANK, BANKM, 0x01},
884 {0x10, 0xFF, 0x00},
885 {0x11, 0xFF, 0x00},
886 {0x12, 0xFF, 0x00},
887 {0x13, 0xFF, 0x00},
888 {0x28, 0xFF, 0x00},
889 {0x29, 0xFF, 0x00},
890 {0x2A, 0xFF, 0x00},
891 {0x2B, 0xFF, 0x00},
892 {0x2C, 0xFF, 0x00},
893 {0xC0, 0xC0, 0x40},
894 {BANK, BANKM, 0x03},
895 {0xE3, 0xFF, 0x07},
896 {0x27, 0xFF, DEFAULT_RS_LEVEL},
897 {0x28, 0xFF, DEFAULT_RS_LEVEL},
898 {0x29, 0xFF, DEFAULT_RS_LEVEL},
899 {0xA7, BIT(6), BIT(6)},
900 {0x21, BIT(2), BIT(2)},
901 {0xF8, 0xFF, 0xC3},
902 {0xF8, 0xFF, 0xA5},
903 {BANK, BANKM, 0x01},
904 {0x5F, 0xFF, 0x04},
905 {0x58, 0xFF, 0x12},
906 {0x58, 0xFF, 0x02},
907 {0x5F, 0xFF, 0x00},
908 {BANK, BANKM, 0x00},
909 {0xF8, 0xFF, 0xFF},
910 {BANK, BANKM, 0x04},
911 {0x3C, BIT(5), 0x000},
912 {BANK, BANKM, 0x00},
913 {0x91, BIT(6), BIT(6)},
914 {BANK, BANKM, 0x03},
915 {0xF0, 0xFF, 0xC0},
916 {BANK, BANKM, 0x00},
917 {0x21, BIT(6), BIT(6)},
918 {0xCE, 0x30, 0x00},
919 {BANK, BANKM, 0x04},
920 {0xCE, 0x30, 0x00},
921 {0x42, 0xE0, 0xC0},
922 {BANK, BANKM, 0x00},
923 {0x42, 0xE0, 0xC0},
924 {0x7B, BIT(4), BIT(4)},
925 {0x3C, 0x21, 0x00},
926 {0x3B, 0xFF, 0x23},
927 {0xF6, 0xFF, 0x08},
928 {BANK, BANKM, 0x04},
929 {0x3C, 0x21, 0x00},
930 {0x3B, 0xFF, 0x23},
931 {BANK, BANKM, 0x00},
932 {0x59, 0xFF, 0x00},
933 {0xFF, 0xFF, 0xFF},
934 };
935
936 static struct it6616 *g_it6616;
937 static void it6616_format_change(struct v4l2_subdev *sd);
938 static int it6616_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
939 static int it6616_s_dv_timings(struct v4l2_subdev *sd,
940 struct v4l2_dv_timings *timings);
941
to_it6616(struct v4l2_subdev * sd)942 static inline struct it6616 *to_it6616(struct v4l2_subdev *sd)
943 {
944 return container_of(sd, struct it6616, sd);
945 }
946
it6616_hdmi_read(struct regmap * regmap,u8 reg)947 static u8 it6616_hdmi_read(struct regmap *regmap, u8 reg)
948 {
949 unsigned int val;
950
951 regmap_read(regmap, reg, &val);
952
953 return (u8)val;
954 }
955
it6616_hdmi_write(struct regmap * regmap,u8 reg,u8 value)956 static int it6616_hdmi_write(struct regmap *regmap, u8 reg, u8 value)
957 {
958 return regmap_write(regmap, reg, value);
959 }
960
it6616_hdmi_set(struct regmap * regmap,u8 reg,u8 mask,u8 value)961 static int it6616_hdmi_set(struct regmap *regmap, u8 reg, u8 mask, u8 value)
962 {
963 return regmap_update_bits(regmap, reg, mask, value);
964 }
965
it6616_mipi_tx_read(struct regmap * regmap,u8 reg)966 static u8 it6616_mipi_tx_read(struct regmap *regmap, u8 reg)
967 {
968 unsigned int val;
969
970 regmap_read(regmap, reg, &val);
971
972 return (u8)val;
973 }
974
it6616_mipi_tx_write(struct regmap * regmap,u8 reg,u8 value)975 static int it6616_mipi_tx_write(struct regmap *regmap, u8 reg, u8 value)
976 {
977 return regmap_write(regmap, reg, value);
978 }
979
it6616_mipi_tx_set_bits(struct regmap * regmap,u8 reg,u8 mask,u8 value)980 static int it6616_mipi_tx_set_bits(struct regmap *regmap, u8 reg, u8 mask, u8 value)
981 {
982 return regmap_update_bits(regmap, reg, mask, value);
983 }
984
it6616_hdmi_edid_read(struct regmap * regmap,u8 * edid,int start,int length)985 static int it6616_hdmi_edid_read(struct regmap *regmap, u8 *edid, int start, int length)
986 {
987 return regmap_bulk_read(regmap, start, edid, length);
988 }
989
it6616_hdmi_edid_write(struct regmap * regmap,u8 * edid,int start,int length)990 static int it6616_hdmi_edid_write(struct regmap *regmap, u8 *edid, int start, int length)
991 {
992 return regmap_bulk_write(regmap, start, edid, length);
993 }
994
it6616_hdmi_chgbank(struct regmap * regmap,u8 bank)995 static void it6616_hdmi_chgbank(struct regmap *regmap, u8 bank)
996 {
997 it6616_hdmi_set(regmap, 0x0F, 0x07, (u8)(bank & 0x07));
998 }
999
it6616_hdim_write_table(struct regmap * regmap,struct it6616_reg_set * tdata)1000 static void it6616_hdim_write_table(struct regmap *regmap, struct it6616_reg_set *tdata)
1001 {
1002 while (tdata->ucAddr != 0xff) {
1003 if (tdata->andmask == 0xff)
1004 it6616_hdmi_write(regmap, tdata->ucAddr, tdata->ucValue);
1005 else
1006 it6616_hdmi_set(regmap, tdata->ucAddr, tdata->andmask, tdata->ucValue);
1007 tdata++;
1008 }
1009 }
1010
it6616_mipi_tx_get_video_stable(struct it6616 * it6616)1011 static bool it6616_mipi_tx_get_video_stable(struct it6616 *it6616)
1012 {
1013 struct regmap *mipi = it6616->mipi_regmap;
1014 u8 reg09h;
1015
1016 reg09h = it6616_mipi_tx_read(mipi, 0x09);
1017
1018 return !!(reg09h & 0x40);
1019 }
1020
it6616_mipitx_init_bus_para(struct it6616 * it6616)1021 static void it6616_mipitx_init_bus_para(struct it6616 *it6616)
1022 {
1023 struct bus_para *bus_para = &it6616->mipi.bus_para_config;
1024 u8 lpx = 0x03, mipi_tx_hs_prepare = 0x01;
1025
1026 bus_para->swap_pn = MIPI_TX_PN_SWAP;
1027 bus_para->swap_lan = MIPI_TX_LANE_SWAP;
1028 bus_para->pclk_inv = MIPI_TX_ENABLE_PCLK_INV;
1029 bus_para->mclk_inv = MIPI_TX_ENABLE_MCLK_INV;
1030 bus_para->lpx_num =
1031 it6616->mipi_tx_enable_manual_adjusted_d_phy ? MIPI_TX_LPX : lpx;
1032 bus_para->mipi_tx_hs_prepare =
1033 it6616->mipi_tx_enable_manual_adjusted_d_phy ?
1034 MIPI_TX_HS_PREPARE : mipi_tx_hs_prepare;
1035 bus_para->tx_sel_line_start = true;
1036 bus_para->tx_bypass = MIPI_TX_ENABLE_BY_PASS;
1037 bus_para->tx_enable_hs_pre_1T = MIPI_TX_ENABLE_HS_PRE_1T;
1038 bus_para->tx_vlpm_length = MIPI_TX_V_LPM_LENGTH;
1039 bus_para->tx_hlpm_length = MIPI_TX_H_LPM_LENGTH;
1040 bus_para->tx_enable_h_enter_lpm = MIPI_TX_ENABLE_H_ENTER_LPM;
1041 }
1042
it6616_get_dcs_ecc(int dcshead)1043 static int it6616_get_dcs_ecc(int dcshead)
1044 {
1045 int q0, q1, q2, q3, q4, q5;
1046
1047 q0 = ((dcshead >> 0) & (0x01)) ^ ((dcshead >> 1) & (0x01)) ^
1048 ((dcshead >> 2) & (0x01)) ^ ((dcshead >> 4) & (0x01)) ^
1049 ((dcshead >> 5) & (0x01)) ^ ((dcshead >> 7) & (0x01)) ^
1050 ((dcshead >> 10) & (0x01)) ^ ((dcshead >> 11) & (0x01)) ^
1051 ((dcshead >> 13) & (0x01)) ^ ((dcshead >> 16) & (0x01)) ^
1052 ((dcshead >> 20) & (0x01)) ^ ((dcshead >> 21) & (0x01)) ^
1053 ((dcshead >> 22) & (0x01)) ^ ((dcshead >> 23) & (0x01));
1054 q1 = ((dcshead >> 0) & (0x01)) ^ ((dcshead >> 1) & (0x01)) ^
1055 ((dcshead >> 3) & (0x01)) ^ ((dcshead >> 4) & (0x01)) ^
1056 ((dcshead >> 6) & (0x01)) ^ ((dcshead >> 8) & (0x01)) ^
1057 ((dcshead >> 10) & (0x01)) ^ ((dcshead >> 12) & (0x01)) ^
1058 ((dcshead >> 14) & (0x01)) ^ ((dcshead >> 17) & (0x01)) ^
1059 ((dcshead >> 20) & (0x01)) ^ ((dcshead >> 21) & (0x01)) ^
1060 ((dcshead >> 22) & (0x01)) ^ ((dcshead >> 23) & (0x01));
1061 q2 = ((dcshead >> 0) & (0x01)) ^ ((dcshead >> 2) & (0x01)) ^
1062 ((dcshead >> 3) & (0x01)) ^ ((dcshead >> 5) & (0x01)) ^
1063 ((dcshead >> 6) & (0x01)) ^ ((dcshead >> 9) & (0x01)) ^
1064 ((dcshead >> 11) & (0x01)) ^ ((dcshead >> 12) & (0x01)) ^
1065 ((dcshead >> 15) & (0x01)) ^ ((dcshead >> 18) & (0x01)) ^
1066 ((dcshead >> 20) & (0x01)) ^ ((dcshead >> 21) & (0x01)) ^
1067 ((dcshead >> 22) & (0x01));
1068 q3 = ((dcshead >> 1) & (0x01)) ^ ((dcshead >> 2) & (0x01)) ^
1069 ((dcshead >> 3) & (0x01)) ^ ((dcshead >> 7) & (0x01)) ^
1070 ((dcshead >> 8) & (0x01)) ^ ((dcshead >> 9) & (0x01)) ^
1071 ((dcshead >> 13) & (0x01)) ^ ((dcshead >> 14) & (0x01)) ^
1072 ((dcshead >> 15) & (0x01)) ^ ((dcshead >> 19) & (0x01)) ^
1073 ((dcshead >> 20) & (0x01)) ^ ((dcshead >> 21) & (0x01)) ^
1074 ((dcshead >> 23) & (0x01));
1075 q4 = ((dcshead >> 4) & (0x01)) ^ ((dcshead >> 5) & (0x01)) ^
1076 ((dcshead >> 6) & (0x01)) ^ ((dcshead >> 7) & (0x01)) ^
1077 ((dcshead >> 8) & (0x01)) ^ ((dcshead >> 9) & (0x01)) ^
1078 ((dcshead >> 16) & (0x01)) ^ ((dcshead >> 17) & (0x01)) ^
1079 ((dcshead >> 18) & (0x01)) ^ ((dcshead >> 19) & (0x01)) ^
1080 ((dcshead >> 20) & (0x01)) ^ ((dcshead >> 22) & (0x01)) ^
1081 ((dcshead >> 23) & (0x01));
1082 q5 = ((dcshead >> 10) & (0x01)) ^ ((dcshead >> 11) & (0x01)) ^
1083 ((dcshead >> 12) & (0x01)) ^ ((dcshead >> 13) & (0x01)) ^
1084 ((dcshead >> 14) & (0x01)) ^ ((dcshead >> 15) & (0x01)) ^
1085 ((dcshead >> 16) & (0x01)) ^ ((dcshead >> 17) & (0x01)) ^
1086 ((dcshead >> 18) & (0x01)) ^ ((dcshead >> 19) & (0x01)) ^
1087 ((dcshead >> 21) & (0x01)) ^ ((dcshead >> 22) & (0x01)) ^
1088 ((dcshead >> 23) & (0x01));
1089
1090 return (q0 + (q1 << 1) + (q2 << 2) + (q3 << 3) + (q4 << 4) + (q5 << 5));
1091 }
1092
it6616_dcs_crc8t(int crcq16b,const u8 crc8bin)1093 static int it6616_dcs_crc8t(int crcq16b, const u8 crc8bin)
1094 {
1095 int lfsrout = 0, lfsr[16], i;
1096
1097 lfsr[15] = ((crc8bin >> 7) & 0x01) ^ ((crc8bin >> 3) & 0x01) ^
1098 ((crcq16b >> 7) & 0x01) ^ ((crcq16b >> 3) & 0x01);
1099 lfsr[14] = ((crc8bin >> 6) & 0x01) ^ ((crc8bin >> 2) & 0x01) ^
1100 ((crcq16b >> 6) & 0x01) ^ ((crcq16b >> 2) & 0x01);
1101 lfsr[13] = ((crc8bin >> 5) & 0x01) ^ ((crc8bin >> 1) & 0x01) ^
1102 ((crcq16b >> 5) & 0x01) ^ ((crcq16b >> 1) & 0x01);
1103 lfsr[12] = ((crc8bin >> 4) & 0x01) ^ ((crc8bin >> 0) & 0x01) ^
1104 ((crcq16b >> 4) & 0x01) ^ ((crcq16b >> 0) & 0x01);
1105 lfsr[11] = ((crc8bin >> 3) & 0x01) ^ ((crcq16b >> 3) & 0x01);
1106 lfsr[10] = ((crc8bin >> 7) & 0x01) ^ ((crc8bin >> 3) & 0x01) ^
1107 ((crc8bin >> 2) & 0x01) ^ ((crcq16b >> 7) & 0x01) ^
1108 ((crcq16b >> 3) & 0x01) ^ ((crcq16b >> 2) & 0x01);
1109 lfsr[9] = ((crc8bin >> 6) & 0x01) ^ ((crc8bin >> 2) & 0x01) ^
1110 ((crc8bin >> 1) & 0x01) ^ ((crcq16b >> 6) & 0x01) ^
1111 ((crcq16b >> 2) & 0x01) ^ ((crcq16b >> 1) & 0x01);
1112 lfsr[8] = ((crc8bin >> 5) & 0x01) ^ ((crc8bin >> 1) & 0x01) ^
1113 ((crc8bin >> 0) & 0x01) ^ ((crcq16b >> 5) & 0x01) ^
1114 ((crcq16b >> 1) & 0x01) ^ ((crcq16b >> 0) & 0x01);
1115 lfsr[7] = ((crc8bin >> 4) & 0x01) ^ ((crc8bin >> 0) & 0x01) ^
1116 ((crcq16b >> 15) & 0x01) ^ ((crcq16b >> 4) & 0x01) ^
1117 ((crcq16b >> 0) & 0x01);
1118 lfsr[6] = ((crc8bin >> 3) & 0x01) ^
1119 ((crcq16b >> 14) & 0x01) ^ ((crcq16b >> 3) & 0x01);
1120 lfsr[5] = ((crc8bin >> 2) & 0x01) ^
1121 ((crcq16b >> 13) & 0x01) ^ ((crcq16b >> 2) & 0x01);
1122 lfsr[4] = ((crc8bin >> 1) & 0x01) ^
1123 ((crcq16b >> 12) & 0x01) ^ ((crcq16b >> 1) & 0x01);
1124 lfsr[3] = ((crc8bin >> 7) & 0x01) ^ ((crc8bin >> 3) & 0x01) ^
1125 ((crc8bin >> 0) & 0x01) ^ ((crcq16b >> 11) & 0x01) ^
1126 ((crcq16b >> 7) & 0x01) ^ ((crcq16b >> 3) & 0x01) ^
1127 ((crcq16b >> 0) & 0x01);
1128 lfsr[2] = ((crc8bin >> 6) & 0x01) ^ ((crc8bin >> 2) & 0x01) ^
1129 ((crcq16b >> 10) & 0x01) ^ ((crcq16b >> 6) & 0x01) ^
1130 ((crcq16b >> 2) & 0x01);
1131 lfsr[1] = ((crc8bin >> 5) & 0x01) ^ ((crc8bin >> 1) & 0x01) ^
1132 ((crcq16b >> 9) & 0x01) ^ ((crcq16b >> 5) & 0x01) ^
1133 ((crcq16b >> 1) & 0x01);
1134 lfsr[0] = ((crc8bin >> 4) & 0x01) ^ ((crc8bin >> 0) & 0x01) ^
1135 ((crcq16b >> 8) & 0x01) ^ ((crcq16b >> 4) & 0x01) ^
1136 ((crcq16b >> 0) & 0x01);
1137
1138 for (i = 0; i < ARRAY_SIZE(lfsr); i++)
1139 lfsrout = lfsrout + (lfsr[i] << i);
1140
1141 return lfsrout;
1142 }
1143
it6616_get_dcs_crc(int bytenum,const u8 * crcbyte)1144 static int it6616_get_dcs_crc(int bytenum, const u8 *crcbyte)
1145 {
1146 int i, crctemp = 0xFFFF;
1147
1148 for (i = 0; i <= bytenum - 1; i++)
1149 crctemp = it6616_dcs_crc8t(crctemp, crcbyte[i]);
1150
1151 return crctemp;
1152 }
1153
it6616_mipi_tx_setup_long_packet_header(struct mipi_packet * pheader,u32 word_count)1154 static void it6616_mipi_tx_setup_long_packet_header(struct mipi_packet *pheader,
1155 u32 word_count)
1156 {
1157 int header;
1158
1159 pheader->word_count_h = word_count >> 8;
1160 pheader->word_count_l = (u8)word_count;
1161 header = pheader->data_id | pheader->word_count_h << 16 | pheader->word_count_l << 8;
1162 pheader->ecc = it6616_get_dcs_ecc(header);
1163 }
1164
it6616_mipi_tx_get_packet_size(struct it6616 * it6616,const struct dcs_setting_entry * dcs_setting_table,enum dcs_cmd_name cmd_name)1165 static enum mipi_packet_size it6616_mipi_tx_get_packet_size(struct it6616 *it6616,
1166 const struct dcs_setting_entry *dcs_setting_table,
1167 enum dcs_cmd_name cmd_name)
1168 {
1169 struct device *dev = &it6616->mipi_i2c->dev;
1170 u8 i, size = ARRAY_SIZE(packet_size_data_id_map);
1171
1172 for (i = 0; i < size; i++) {
1173 if (dcs_setting_table[cmd_name].data_id == packet_size_data_id_map[i].data_id)
1174 break;
1175 }
1176
1177 if (i == size) {
1178 if (dcs_setting_table[cmd_name].count == 0) {
1179 dev_err(dev, "error! cmd index: %d count = 0", cmd_name);
1180 return UNKNOWN_PACKET;
1181 } else if (dcs_setting_table[cmd_name].count < 3) {
1182 return SHORT_PACKET;
1183 } else {
1184 return LONG_PACKET;
1185 }
1186 }
1187
1188 return packet_size_data_id_map[i].packet_size;
1189 }
1190
it6616_mipi_tx_get_packet_fire_state(struct it6616 * it6616)1191 static void it6616_mipi_tx_get_packet_fire_state(struct it6616 *it6616)
1192 {
1193 struct regmap *mipi = it6616->mipi_regmap;
1194 struct device *dev = &it6616->mipi_i2c->dev;
1195 int lp_cmd_fifo, link_data_fifo;
1196
1197 lp_cmd_fifo = it6616_mipi_tx_read(mipi, 0x71) & 0x0F;
1198 link_data_fifo = it6616_mipi_tx_read(mipi, 0x72);
1199
1200 if (lp_cmd_fifo != 0)
1201 dev_err(dev,
1202 "error! fire low power cmd fail, remain bytes not fire, reg0x71:0x%02x",
1203 lp_cmd_fifo);
1204 if (link_data_fifo != 0)
1205 dev_err(dev,
1206 "error! fire link0 low power data fail, remain %d bytes not fire, reg0x72:0x%02x",
1207 link_data_fifo, link_data_fifo);
1208 }
1209
it6616_mipi_tx_setup_packet(struct it6616 * it6616,struct mipi_packet * pheader,const struct dcs_setting_entry * dcs_setting_table,enum dcs_cmd_name cmd_name)1210 static void it6616_mipi_tx_setup_packet(struct it6616 *it6616, struct mipi_packet *pheader,
1211 const struct dcs_setting_entry *dcs_setting_table,
1212 enum dcs_cmd_name cmd_name)
1213 {
1214 struct device *dev = &it6616->mipi_i2c->dev;
1215 int short_cmd;
1216 enum mipi_packet_size packet_size;
1217
1218 pheader->data_id = dcs_setting_table[cmd_name].data_id;
1219 packet_size = it6616_mipi_tx_get_packet_size(it6616, dcs_setting_table, cmd_name);
1220
1221 if (packet_size == UNKNOWN_PACKET) {
1222 dev_err(dev, "error! unknown packet size and check dcs table parameter");
1223 return;
1224 }
1225
1226 if (packet_size == SHORT_PACKET) {
1227 pheader->word_count_l = dcs_setting_table[cmd_name].para_list[0];
1228 pheader->word_count_h = dcs_setting_table[cmd_name].para_list[1];
1229 short_cmd = pheader->data_id | pheader->word_count_l << 8 |
1230 pheader->word_count_h << 16;
1231 pheader->ecc = it6616_get_dcs_ecc(short_cmd);
1232 }
1233
1234 if (packet_size == LONG_PACKET)
1235 it6616_mipi_tx_setup_long_packet_header(pheader, dcs_setting_table[cmd_name].count);
1236 }
1237
it6616_mipi_tx_fire_packet(struct it6616 * it6616,const struct dcs_setting_entry * dcs_setting_table,enum dcs_cmd_name cmd_name)1238 static inline void it6616_mipi_tx_fire_packet(struct it6616 *it6616,
1239 const struct dcs_setting_entry *dcs_setting_table,
1240 enum dcs_cmd_name cmd_name)
1241 {
1242 struct regmap *mipi = it6616->mipi_regmap;
1243
1244 it6616_mipi_tx_write(mipi, 0x75, dcs_setting_table[cmd_name].cmd);
1245 }
1246
it6616_mipi_tx_setup_packet_process(struct it6616 * it6616,const struct dcs_setting_entry * dcs_setting_table,enum dcs_cmd_name cmd_name,enum mipi_tx_lp_cmd_header header_select)1247 static void it6616_mipi_tx_setup_packet_process(struct it6616 *it6616,
1248 const struct dcs_setting_entry *dcs_setting_table,
1249 enum dcs_cmd_name cmd_name,
1250 enum mipi_tx_lp_cmd_header header_select)
1251 {
1252 struct regmap *mipi = it6616->mipi_regmap;
1253 struct device *dev = &it6616->mipi_i2c->dev;
1254 struct v4l2_subdev *sd = &it6616->sd;
1255 struct mipi_packet packet;
1256 enum mipi_packet_size packet_size;
1257 u32 long_packet_checksum;
1258 int i, header_crc, data_count;
1259
1260 if (!header_select) {
1261 dev_err(dev, "no header packet");
1262
1263 for (i = 0; i < dcs_setting_table[cmd_name].count; i++) {
1264 it6616_mipi_tx_write(mipi, 0x73, dcs_setting_table[cmd_name].para_list[i]);
1265 v4l2_dbg(1, debug, sd, "data[%d]: 0x%02x ", i,
1266 dcs_setting_table[cmd_name].para_list[i]);
1267 }
1268
1269 header_crc = 0;
1270 goto short_packet;
1271 }
1272 it6616_mipi_tx_setup_packet(it6616, &packet, dcs_setting_table, cmd_name);
1273 packet_size = it6616_mipi_tx_get_packet_size(it6616, dcs_setting_table, cmd_name);
1274 v4l2_dbg(1, debug, sd, "%s packet\n\r", packet_size == LONG_PACKET ? "long" : "short");
1275
1276 for (i = 0; i < sizeof(packet); i++) {
1277 it6616_mipi_tx_write(mipi, 0x73, ((u8 *)(&packet))[i]);
1278 v4l2_dbg(1, debug, sd, "data[%d]: 0x%02x ", i, ((u8 *)(&packet))[i]);
1279 msleep(20);
1280 }
1281
1282 if (packet_size == SHORT_PACKET) {
1283 header_crc = 2;
1284 goto short_packet;
1285 }
1286
1287 header_crc = sizeof(packet) + 2;
1288
1289 long_packet_checksum = it6616_get_dcs_crc(dcs_setting_table[cmd_name].count,
1290 dcs_setting_table[cmd_name].para_list);
1291 for (i = 0; i < dcs_setting_table[cmd_name].count; i++) {
1292 it6616_mipi_tx_write(mipi, 0x73, dcs_setting_table[cmd_name].para_list[i]);
1293 v4l2_dbg(1, debug, sd,
1294 "cmd para: 0x%02x", dcs_setting_table[cmd_name].para_list[i]);
1295 }
1296
1297 it6616_mipi_tx_write(mipi, 0x73, (u8)long_packet_checksum);
1298 it6616_mipi_tx_write(mipi, 0x73, (u8)(long_packet_checksum >> 8));
1299 v4l2_dbg(1, debug, sd,
1300 "long_packet_checksum_l: 0x%02x long_packet_checksum_h: 0x%02x",
1301 (u8)long_packet_checksum, (u8)(long_packet_checksum >> 8));
1302
1303 short_packet:
1304 data_count = dcs_setting_table[cmd_name].count + header_crc;
1305
1306 if (data_count == LP_CMD_FIFO_SIZE)
1307 data_count = 1;
1308
1309 it6616_mipi_tx_write(mipi, 0x74, (it6616->mipi_tx_enable_h_fire_packet << 7) | data_count);
1310 }
1311
it6616_mipi_tx_write_lp_cmds(struct it6616 * it6616,const struct dcs_setting_entry * dcs_setting_table,int dcs_table_size,enum dcs_cmd_name start,int count,enum mipi_tx_lp_cmd_header header_select)1312 static void it6616_mipi_tx_write_lp_cmds(struct it6616 *it6616,
1313 const struct dcs_setting_entry *dcs_setting_table,
1314 int dcs_table_size, enum dcs_cmd_name start,
1315 int count, enum mipi_tx_lp_cmd_header header_select)
1316 {
1317 struct regmap *mipi = it6616->mipi_regmap;
1318 struct device *dev = &it6616->mipi_i2c->dev;
1319 u8 header_size, i, data_count;
1320 u8 enable_force_lp_mode = !it6616_mipi_tx_get_video_stable(it6616);
1321 u8 lp_cmd_fifo_size[] = { LP_CMD_FIFO_SIZE };
1322
1323 it6616_mipi_tx_set_bits(mipi, 0x70, 0x03, 0x03);
1324 it6616_mipi_tx_set_bits(mipi, 0x70, 0x03, 0x00);
1325
1326 if (enable_force_lp_mode) {
1327 it6616_mipi_tx_set_bits(mipi, 0x05, 0x16, 0x16);
1328 it6616_mipi_tx_set_bits(mipi, 0x05, 0x16, 0x10);
1329 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x04);
1330 }
1331
1332 it6616_mipi_tx_write(mipi, 0x3D, 0x00);
1333 it6616_mipi_tx_write(mipi, 0x3E, enable_force_lp_mode ? 0x00 : 0x10);
1334 it6616_mipi_tx_write(mipi, 0x3F, enable_force_lp_mode ? 0x30 : 0x90);
1335
1336 for (i = start; i < start + count; i++) {
1337 dev_dbg(dev, "cmd:%d tx reg09:0x%02x", i, it6616_mipi_tx_read(mipi, 0x09));
1338 if (i >= dcs_table_size)
1339 goto complete_write_dcs;
1340 if (dcs_setting_table[i].cmd_name == DELAY) {
1341 msleep(dcs_setting_table[i].cmd);
1342 continue;
1343 }
1344
1345 header_size = header_select ?
1346 ((it6616_mipi_tx_get_packet_size(it6616, dcs_setting_table, i) ==
1347 SHORT_PACKET) ? 2 : 6) : 0;
1348 data_count = dcs_setting_table[i].count + header_size;
1349
1350 if (data_count > lp_cmd_fifo_size[0]) {
1351 dev_err(dev, "error! lp cmd: %d, exceed cmd fifo", i);
1352 continue;
1353 }
1354
1355 it6616_mipi_tx_setup_packet_process(it6616, dcs_setting_table, i, header_select);
1356 it6616_mipi_tx_fire_packet(it6616, dcs_setting_table, i);
1357
1358 if (enable_force_lp_mode)
1359 it6616_mipi_tx_get_packet_fire_state(it6616);
1360 }
1361 msleep(20);
1362
1363 complete_write_dcs:
1364 if (i >= dcs_table_size && (start + count > dcs_table_size))
1365 dev_err(dev, "error! exceed maximum dcs setting table index");
1366
1367 if (enable_force_lp_mode) {
1368 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x00);
1369 it6616_mipi_tx_set_bits(mipi, 0x05, 0x16, 0x00);
1370 }
1371
1372 msleep(20);
1373
1374 if (!enable_force_lp_mode)
1375 it6616_mipi_tx_get_packet_fire_state(it6616);
1376 }
1377
it6616_enter_bus_turn_around(struct it6616 * it6616)1378 static void it6616_enter_bus_turn_around(struct it6616 *it6616)
1379 {
1380 struct regmap *mipi = it6616->mipi_regmap;
1381 u8 enable_force_lp_mode = !it6616_mipi_tx_get_video_stable(it6616);
1382
1383 if (enable_force_lp_mode)
1384 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x04);
1385
1386 it6616_mipi_tx_write(mipi, 0x3E, 0x10);
1387 it6616_mipi_tx_write(mipi, 0x3F, 0x90);
1388
1389 it6616_mipi_tx_write(mipi, 0x74, it6616->mipi_tx_enable_h_fire_packet << 7);
1390 it6616_mipi_tx_write(mipi, 0x75, LP_CMD_BTA);
1391
1392 if (enable_force_lp_mode)
1393 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x00);
1394 }
1395
it6616_mipi_read_panel(struct it6616 * it6616,const struct dcs_setting_entry * dcs_setting_table,int dcs_table_size,enum dcs_cmd_name cmd_name,u8 * buffer)1396 static __maybe_unused void it6616_mipi_read_panel(struct it6616 *it6616,
1397 const struct dcs_setting_entry *dcs_setting_table,
1398 int dcs_table_size, enum dcs_cmd_name cmd_name, u8 *buffer)
1399 {
1400 struct regmap *mipi = it6616->mipi_regmap;
1401 int link0_data_count, i;
1402
1403 it6616_mipi_tx_write_lp_cmds(it6616, dcs_setting_table,
1404 dcs_table_size, cmd_name, 1, CALC_HEADER);
1405 it6616_enter_bus_turn_around(it6616);
1406 msleep(20);
1407 link0_data_count = it6616_mipi_tx_read(mipi, 0x7A);
1408
1409 for (i = 0; i < link0_data_count; i++)
1410 buffer[i] = it6616_mipi_tx_read(mipi, 0x79);
1411 }
1412
it6616_mipitx_get_bus_config(struct it6616 * it6616)1413 static int it6616_mipitx_get_bus_config(struct it6616 *it6616)
1414 {
1415 struct mipi_bus *bus = &it6616->mipi;
1416 const struct bus_config *bus_config_table;
1417 struct bus_config *cfg = &bus->bus_para_config.cfg;
1418 struct device *dev = &it6616->mipi_i2c->dev;
1419 int i;
1420
1421 bus_config_table = (bus->bus_type == MIPI_CSI) ?
1422 it6616_csi_bus_cfg : it6616_dsi_bus_cfg;
1423
1424 for (i = 0; bus_config_table[i].lane; i++) {
1425 if (bus_config_table[i].lane == bus->lane_cnt &&
1426 bus_config_table[i].type == bus->data_type) {
1427
1428 bus->bus_para_config.cfg = bus_config_table[i];
1429 dev_dbg(dev, "mipi_get_bus_config = %d (%s)",
1430 i, (bus->bus_type == MIPI_CSI) ? "MIPI_CSI" : "MIPI_DSI");
1431 dev_dbg(dev, "{%X, %X, %X, %X, %X ,%X}",
1432 cfg->lane,
1433 cfg->type,
1434 cfg->reg23_p2m,
1435 cfg->regb0_div[0],
1436 cfg->regb0_div[1],
1437 cfg->regb0_div[2]);
1438
1439 return 0;
1440 }
1441 }
1442
1443 dev_err(dev, "mipi_get_bus_config error");
1444 return -EINVAL;
1445 }
1446
it6616_mipitx_setup_dsi(struct it6616 * it6616)1447 static void it6616_mipitx_setup_dsi(struct it6616 *it6616)
1448 {
1449 struct regmap *mipi = it6616->mipi_regmap;
1450 struct bus_para *bus = &it6616->mipi.bus_para_config;
1451 struct bus_config *cfg = &bus->cfg;
1452 struct device *dev = &it6616->mipi_i2c->dev;
1453 u8 mp_lane_num = cfg->lane - 1;
1454 u8 p2m_time_mul = 0x03;
1455 u8 p2m_time_div = 0x02;
1456 u32 mp_hs_pretime = 0x4a;
1457 u32 mp_hs_endtime = 0x09;
1458 u8 mp_vid_type = cfg->type;
1459 u32 mclk_ps = it6616->tx_mclk_ps, tx_mclk_mhz = it6616->tx_mclk / 1000;
1460 u32 mipi_tx_calc_hs_end_time = (6 * mclk_ps - 20 * 1000) / mclk_ps;
1461 u8 reg23;
1462
1463 reg23 = cfg->reg23_p2m;
1464
1465 p2m_time_mul = reg23 & 0x0F;
1466 p2m_time_div = (reg23 & 0xF0) >> 4;
1467
1468 it6616_mipi_tx_set_bits(mipi, 0x28, 0x20, bus->tx_sel_line_start << 5);
1469
1470 if (!it6616->mipi_tx_enable_manual_adjusted_d_phy) {
1471 if (mp_lane_num == 3) {
1472 mp_hs_pretime = (((145 + ((4 + bus->lpx_num) * 20)) * 1000 -
1473 ((3 * mclk_ps) >> 1)) / mclk_ps);
1474 mp_hs_endtime = mipi_tx_calc_hs_end_time + 9;
1475 } else if (mp_lane_num == 1) {
1476 mp_hs_pretime = ((((145 + ((4 + bus->lpx_num) * 20)) * 1000 -
1477 ((3 * mclk_ps) >> 1)) / mclk_ps) >> 1);
1478 mp_hs_endtime = (mipi_tx_calc_hs_end_time >> 1) + 9;
1479 } else {
1480 mp_hs_pretime = ((((145 + ((4 + bus->lpx_num) * 20)) * 1000 -
1481 ((3 * mclk_ps) >> 1)) / mclk_ps) >> 2);
1482 mp_hs_endtime = (mipi_tx_calc_hs_end_time >> 2) + 9;
1483 }
1484
1485 if (mipi_tx_calc_hs_end_time <= 0)
1486 mp_hs_endtime = 3;
1487
1488 if (tx_mclk_mhz >= 300)
1489 mp_hs_pretime += 20;
1490 else if (tx_mclk_mhz >= 250)
1491 mp_hs_pretime += 18;
1492 else if (tx_mclk_mhz >= 200)
1493 mp_hs_pretime += 15;
1494 else if (tx_mclk_mhz >= 150)
1495 mp_hs_pretime += 12;
1496 else
1497 mp_hs_pretime += 9;
1498 } else {
1499 mp_hs_pretime = MIPI_TX_HS_PREPARE_ZERO;
1500 mp_hs_endtime = MIPI_TX_HS_TRAIL;
1501 }
1502
1503 //dsi setting
1504 it6616_mipi_tx_set_bits(mipi, 0x5e, 0x03, (bus->tx_vlpm_length >> 8) & 0x03);
1505 it6616_mipi_tx_set_bits(mipi, 0x5d, 0xff, bus->tx_vlpm_length & 0xFF);
1506 it6616_mipi_tx_set_bits(mipi, 0x5e, 0x0c, (bus->tx_hlpm_length & 0x300) >> 6);
1507 it6616_mipi_tx_set_bits(mipi, 0x5f, 0xff, bus->tx_hlpm_length & 0xFF);
1508 it6616_mipi_tx_set_bits(mipi, 0x5e, 0x10, bus->tx_enable_h_enter_lpm << 4);
1509 it6616_mipi_tx_set_bits(mipi, 0x6a, 0xff, bus->p2m_delay.tx_dsi_vsync_delay);
1510 it6616_mipi_tx_set_bits(mipi, 0x6c, 0xff, mp_hs_pretime);
1511 it6616_mipi_tx_set_bits(mipi, 0x6d, 0xff, mp_hs_endtime);
1512 it6616_mipi_tx_set_bits(mipi, 0x5c, 0x03, (MIPI_TX_ENABLE_DSI_EOTP_PACKET << 1) |
1513 MIPI_TX_ENABLE_DSI_SYNC_EVENT);
1514 it6616_mipi_tx_set_bits(mipi, 0x5c, 0xf0, ((mp_vid_type & 0x30) << 2) |
1515 ((mp_vid_type & 0x3) << 4));
1516 it6616_mipi_tx_set_bits(mipi, 0x60, 0x0f, p2m_time_mul);
1517 it6616_mipi_tx_set_bits(mipi, 0x61, 0x03, p2m_time_div);
1518
1519 msleep(100);
1520 dev_info(dev,
1521 "hs_prepare_zero num: 0x%02x, hs_trail num: 0x%02x, dsi_vsync_delay: 0x%02x, mipi DSI TX setting done !!!",
1522 mp_hs_pretime, mp_hs_endtime, bus->p2m_delay.tx_dsi_vsync_delay);
1523 }
1524
it6616_mipitx_setup_csi(struct it6616 * it6616)1525 static void it6616_mipitx_setup_csi(struct it6616 *it6616)//set_mptx
1526 {
1527 struct regmap *hdmi = it6616->hdmi_regmap;
1528 struct regmap *mipi = it6616->mipi_regmap;
1529 struct bus_para *bus = &it6616->mipi.bus_para_config;
1530 struct bus_config *cfg = &bus->cfg;
1531 struct device *dev = &it6616->mipi_i2c->dev;
1532 u32 mp_hs_pretime = 0x4a;// int MPHSPreTime = 0x4a;//ori:11
1533 u32 mp_hs_endtime = 0x09;// int MPHSEndTime = 0x09;//ori:06
1534 u8 mp_vid_type = cfg->type;
1535 u32 mclk_ps = it6616->tx_mclk_ps, tx_mclk_mhz = it6616->tx_mclk / 1000;
1536 u32 mipi_tx_calc_hs_end_time = (6 * mclk_ps - 20 * 1000) / mclk_ps;
1537 u8 reg23, interlace, en_fs_fr_num = false;
1538
1539 reg23 = cfg->reg23_p2m;
1540
1541 interlace = (it6616_hdmi_read(hdmi, 0x98) & 0x02) >> 1;
1542
1543 if (interlace)
1544 en_fs_fr_num = true;
1545
1546 if (!it6616->mipi_tx_enable_manual_adjusted_d_phy) {
1547 mp_hs_pretime = (((145 + ((4 + bus->lpx_num) * 20)) * 1000 -
1548 ((3 * mclk_ps) >> 1)) / mclk_ps);
1549 mp_hs_endtime = mipi_tx_calc_hs_end_time + 9;
1550
1551 if (mipi_tx_calc_hs_end_time <= 0)
1552 mp_hs_endtime = 3;
1553
1554 if (tx_mclk_mhz >= 300)
1555 mp_hs_pretime += 20;
1556 else if (tx_mclk_mhz >= 250)
1557 mp_hs_pretime += 18;
1558 else if (tx_mclk_mhz >= 200)
1559 mp_hs_pretime += 15;
1560 else if (tx_mclk_mhz >= 150)
1561 mp_hs_pretime += 12;
1562 else
1563 mp_hs_pretime += 9;
1564 } else {
1565 mp_hs_pretime = MIPI_TX_HS_PREPARE_ZERO;
1566 mp_hs_endtime = MIPI_TX_HS_TRAIL;
1567 }
1568
1569 it6616_mipi_tx_write(mipi, 0x1F, mp_hs_endtime);
1570 it6616_mipi_tx_write(mipi, 0x22, mp_hs_pretime);
1571 it6616_mipi_tx_write(mipi, 0x24, 0x20);
1572 it6616_mipi_tx_write(mipi, 0x25, bus->p2m_delay.tx_csi_p2m_delay);
1573 it6616_mipi_tx_set_bits(mipi, 0x26, 0x20, (en_fs_fr_num << 5));
1574 it6616_mipi_tx_write(mipi, 0x27, 0x02);
1575 it6616_mipi_tx_write(mipi, 0x20, mp_vid_type);
1576 it6616_mipi_tx_write(mipi, 0x23, reg23);
1577
1578 msleep(100);
1579 dev_info(dev,
1580 "hs_prepare_zero num: 0x%02x, hs_trail num: 0x%02x, tx_csi_p2m_delay: 0x%02x, mipi CSI TX setting done !!!",
1581 mp_hs_pretime, mp_hs_endtime, bus->p2m_delay.tx_csi_p2m_delay);
1582 }
1583
it6616_mipi_tx_find_color_space_name_index(struct it6616 * it6616)1584 static u8 it6616_mipi_tx_find_color_space_name_index(struct it6616 *it6616)
1585 {
1586 u8 i, csi_dsi_index = (it6616->mipi.bus_type == MIPI_CSI) ? 0 : 1;
1587
1588 for (i = 0; i < ARRAY_SIZE(mipi_color_space[0]); i++) {
1589 if (it6616->mipi.data_type == mipi_color_space[csi_dsi_index][i])
1590 return i;
1591 }
1592
1593 return 0xFF;
1594 }
1595
it6616_mipitx_output_disable(struct it6616 * it6616)1596 static void it6616_mipitx_output_disable(struct it6616 *it6616)
1597 {
1598 struct regmap *mipi = it6616->mipi_regmap;
1599
1600 it6616_mipi_tx_write(mipi, 0x05, 0x36);
1601 }
1602
it6616_mipi_tx_output_enable(struct it6616 * it6616)1603 static void it6616_mipi_tx_output_enable(struct it6616 *it6616)
1604 {
1605 struct regmap *mipi = it6616->mipi_regmap;
1606
1607 /* release reset */
1608 it6616_mipi_tx_write(mipi, 0x05, 0x00);
1609 }
1610
it6616_mipi_tx_non_continuous_clock_setup(struct it6616 * it6616)1611 static void it6616_mipi_tx_non_continuous_clock_setup(struct it6616 *it6616)
1612 {
1613 struct regmap *mipi = it6616->mipi_regmap;
1614 struct device *dev = &it6616->mipi_i2c->dev;
1615
1616 /* enable non continuous clock */
1617 it6616_mipi_tx_set_bits(mipi, 0x44, 0x01, 0x00);
1618
1619 dev_info(dev, "set mipi tx non continuous clock");
1620 }
1621
it6616_mipitx_output_setup(struct it6616 * it6616)1622 static void it6616_mipitx_output_setup(struct it6616 *it6616)
1623 {
1624 struct regmap *mipi = it6616->mipi_regmap;
1625 struct bus_para *bus = &it6616->mipi.bus_para_config;
1626 struct bus_config *cfg = &bus->cfg;
1627 struct device *dev = &it6616->mipi_i2c->dev;
1628 u8 color_space_name_index = it6616_mipi_tx_find_color_space_name_index(it6616);
1629 u8 bus_type_index = ((it6616->mipi.bus_type == MIPI_CSI) ? 0 : 1);
1630 u8 regb0, mplldiv, mprediv;
1631 u32 mclk_MHz;
1632 u32 pclk = it6616->vinfo.pclk / 1000;
1633
1634 if (it6616->mipi_tx_enable_auto_adjust_lane_count)
1635 it6616->mipi.lane_cnt = it6616->csi_lanes_in_use;
1636
1637 adjust_lane_count:
1638 dev_info(dev, "%s", bus_type_index ? "MIPI_DSI" : "MIPI_CSI");
1639 dev_info(dev, "color space: %s", (color_space_name_index != 0xFF) ?
1640 mipi_color_space_name[bus_type_index][color_space_name_index] : "not find match");
1641 dev_info(dev, "lan_num: %d, swap_pn: %d", it6616->mipi.lane_cnt, bus->swap_pn);
1642 dev_info(dev, "swap_lan: %d, pclk_inv: %d", bus->swap_lan, bus->pclk_inv);
1643 dev_info(dev, "mclk_inv: %d, lpx_num: %d", bus->mclk_inv, bus->lpx_num);
1644
1645 it6616_mipitx_get_bus_config(it6616);
1646
1647 if (pclk > 200)
1648 regb0 = cfg->regb0_div[0];
1649 else if (pclk > 100)
1650 regb0 = cfg->regb0_div[1];
1651 else
1652 regb0 = cfg->regb0_div[2];
1653
1654 mprediv = regb0 >> 5;
1655 mplldiv = regb0 & 0x1F;
1656
1657 dev_dbg(dev, "prediv: 0x%02x, plldiv: 0x%02x", mprediv, mplldiv);
1658
1659 mclk_MHz = ((pclk) * (mplldiv + 1)) >> 1;
1660 mclk_MHz = mclk_MHz / (mprediv + 1);
1661 it6616->tx_mclk = mclk_MHz * 1000;
1662 it6616->tx_mclk_ps = (2000 * (mprediv + 1) * 1000) / ((pclk) * (mplldiv + 1));
1663 dev_info(dev,
1664 "mclk_ns: %d.%d ns, mclk: %d MHz, pclk: %d MHz",
1665 it6616->tx_mclk_ps / 1000, it6616->tx_mclk_ps % 1000,
1666 it6616->tx_mclk / 1000, pclk);
1667
1668 if (it6616->mipi_tx_enable_auto_adjust_lane_count) {
1669 if (mclk_MHz < MIPI_TX_LANE_ADJUST_THRESHOLD) {
1670 it6616->mipi.lane_cnt = (it6616->mipi.lane_cnt == 4) ? 2 : 1;
1671 dev_info(dev, "mclk < %d MHz, adjust to lan_num: %d",
1672 MIPI_TX_LANE_ADJUST_THRESHOLD, it6616->mipi.lane_cnt);
1673 goto adjust_lane_count;
1674 }
1675 }
1676
1677 if (it6616->tx_mclk > 310000)
1678 bus->mclk_inv = 0;
1679
1680 it6616_mipi_tx_set_bits(mipi, 0x28, 0x0c, (bus->swap_pn << 3) | (bus->swap_lan << 2));
1681 it6616_mipi_tx_set_bits(mipi, 0x10, BIT(2), bus->pclk_inv << 2);
1682
1683 switch (it6616_mipi_tx_read(mipi, 0x04)) {
1684 case 0xC0:
1685 it6616_mipi_tx_set_bits(mipi, 0x10, BIT(1), bus->mclk_inv << 1);
1686 break;
1687 default:
1688 it6616_mipi_tx_set_bits(mipi, 0x11, BIT(3), bus->mclk_inv << 3);
1689 }
1690
1691 it6616_mipi_tx_set_bits(mipi, 0x8c, 0x40, 0x00);
1692 it6616_mipi_tx_set_bits(mipi, 0x47, 0xf0, bus->mipi_tx_hs_prepare << 4);
1693 it6616_mipi_tx_set_bits(mipi, 0x44, 0x04, bus->tx_enable_hs_pre_1T << 2);
1694 it6616_mipi_tx_set_bits(mipi, 0x21, 0x30, (it6616->mipi.lane_cnt - 1) << 4);
1695
1696 dev_dbg(dev, "set hs_prepare num: 0x%02x, hs_lpx num: 0x%02x",
1697 bus->mipi_tx_hs_prepare, bus->lpx_num);
1698
1699 if ((pclk < (10 * (mprediv + 1))) || (pclk > (100 * (mprediv + 1))))
1700 dev_err(dev,
1701 "MPTX PHY setting wrong, need to reset parameter for TXPHY!!!");
1702
1703 if (it6616->mipi.bus_type == MIPI_CSI) {
1704 if (pclk >= (mclk_MHz * 2))
1705 bus->p2m_delay.tx_csi_p2m_delay = 0x02;
1706 else if (pclk >= mclk_MHz)
1707 bus->p2m_delay.tx_csi_p2m_delay = 0x04;
1708 else if (mclk_MHz >= (pclk * 2))
1709 bus->p2m_delay.tx_csi_p2m_delay = 0x0a;
1710 else if ((mclk_MHz * 2) >= (pclk * 3))
1711 bus->p2m_delay.tx_csi_p2m_delay = 0x08;
1712 else
1713 bus->p2m_delay.tx_csi_p2m_delay = 0x04;
1714 it6616_mipitx_setup_csi(it6616);
1715 } else {
1716 if (pclk >= (mclk_MHz * 2))
1717 bus->p2m_delay.tx_dsi_vsync_delay = 0x02;
1718 else if (pclk >= mclk_MHz)
1719 bus->p2m_delay.tx_dsi_vsync_delay = 0x04;
1720 else if (mclk_MHz >= (pclk * 2))
1721 bus->p2m_delay.tx_dsi_vsync_delay = 0x0a;
1722 else if ((mclk_MHz * 2) >= (pclk * 3))
1723 bus->p2m_delay.tx_dsi_vsync_delay = 0x08;
1724 else
1725 bus->p2m_delay.tx_dsi_vsync_delay = 0x04;
1726 it6616_mipitx_setup_dsi(it6616);
1727 }
1728
1729 if (!it6616->mipi_tx_enable_continuous_clock)
1730 it6616_mipi_tx_non_continuous_clock_setup(it6616);
1731
1732 /* setup mipi-tx-afe */
1733 it6616_mipi_tx_write(mipi, 0xb0, regb0);
1734
1735 msleep(100);
1736 }
1737
it6616_enable_mipi(struct it6616 * it6616)1738 static void it6616_enable_mipi(struct it6616 *it6616)
1739 {
1740 it6616_mipitx_output_setup(it6616);
1741 it6616_mipi_tx_output_enable(it6616);
1742 it6616->mipi_tx_enable_mipi_output = 1;
1743 }
1744
it6616_disable_mipi(struct it6616 * it6616)1745 static void it6616_disable_mipi(struct it6616 *it6616)
1746 {
1747 it6616_mipitx_output_disable(it6616);
1748 it6616->mipi_tx_enable_mipi_output = 0;
1749 }
1750
it6616_mipi_tx_get_support_format(struct it6616 * it6616)1751 static void it6616_mipi_tx_get_support_format(struct it6616 *it6616)
1752 {
1753 struct regmap *mipi = it6616->mipi_regmap;
1754 struct device *dev = &it6616->mipi_i2c->dev;
1755 u8 mipi_intput_color = it6616->mipi.data_type;
1756 u8 color_space_name_index;
1757 u8 bus_type_index = ((it6616->mipi.bus_type == MIPI_CSI) ? 0 : 1);
1758
1759 if (it6616->mipi.bus_type == MIPI_CSI) {
1760 switch (mipi_intput_color) {
1761 case CSI_RGB10b:
1762 dev_dbg(dev, "csi not support CSI_RGB10b");
1763 it6616->mipi.data_type = CSI_RGB888;
1764 break;
1765
1766 case CSI_YCbCr42212b:
1767 dev_dbg(dev, "csi not support CSI_YCbCr42212b");
1768 it6616->mipi.data_type = CSI_YCbCr4228b;
1769 break;
1770
1771 default:
1772 return;
1773 }
1774
1775 color_space_name_index = it6616_mipi_tx_find_color_space_name_index(it6616);
1776
1777 if (color_space_name_index != 0xFF)
1778 dev_dbg(dev,
1779 "will set %s",
1780 mipi_color_space_name[bus_type_index][color_space_name_index]);
1781 else
1782 dev_err(dev, "error not find match color space");
1783 } else {
1784 if (it6616_mipi_tx_read(mipi, 0x04) == 0xC0) {
1785 if ((mipi_intput_color == DSI_YCbCr_16b) ||
1786 (mipi_intput_color == DSI_YCbCr_20b) ||
1787 (mipi_intput_color == DSI_YCbCr_24b)) {
1788 mipi_intput_color = it6616->mipi.data_type = DSI_RGB_24b;
1789 dev_dbg(dev, "0xC0 MIPI DSI only support RGB, using: DSI_RGB_24b(%d)",
1790 mipi_intput_color);
1791 }
1792 }
1793 }
1794 }
1795
1796 /*
1797 * mipi rx need pn swap and let first bit data(after SOT) will be rising edge
1798 * can use in it6616_mipitx_initial function before it6616_mipi_tx_write_lp_cmds
1799 */
it6616_mipi_tx_rk_fix_first_bit_issue(struct it6616 * it6616)1800 static __maybe_unused void it6616_mipi_tx_rk_fix_first_bit_issue(struct it6616 *it6616)
1801 {
1802 struct regmap *mipi = it6616->mipi_regmap;
1803
1804 it6616_mipi_tx_write(mipi, 0x05, 0x00);
1805 it6616_mipi_tx_set_bits(mipi, 0x28, 0x08, 0x08);
1806 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x04);
1807 it6616_mipi_tx_set_bits(mipi, 0x28, 0x08, 0x00);
1808 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x00);
1809 it6616_mipi_tx_write(mipi, 0x05, 0x36);
1810 }
1811
it6616_mipitx_initial(struct it6616 * it6616)1812 static void it6616_mipitx_initial(struct it6616 *it6616)
1813 {
1814 struct regmap *mipi = it6616->mipi_regmap;
1815 struct device *dev = &it6616->mipi_i2c->dev;
1816 struct bus_para *bus = &it6616->mipi.bus_para_config;
1817
1818 it6616_mipi_tx_set_bits(mipi, 0x05, 0x09, 0x09);
1819 it6616_mipi_tx_write(mipi, 0x05, 0x36);
1820
1821 it6616_mipi_tx_set_bits(mipi, 0x2A, 0x3c, 0x00);
1822 it6616_mipi_tx_set_bits(mipi, 0x3c, 0x20, 0x20);
1823 it6616_mipi_tx_set_bits(mipi, 0x6b, 0x01, it6616->mipi.bus_type);
1824 it6616_mipi_tx_set_bits(mipi, 0x10, 0x80, bus->tx_bypass << 7);
1825 it6616_mipi_tx_set_bits(mipi, 0xc1, 0x03, 0x03);
1826 it6616_mipi_tx_set_bits(mipi, 0xa8, 0x01, 0x00);
1827 it6616_mipi_tx_set_bits(mipi, 0x45, 0x0f, bus->lpx_num);
1828
1829 if (it6616->mipi_tx_enable_initial_fire_lp_cmd) {
1830 it6616_mipi_tx_write_lp_cmds(it6616, dcs_table, ARRAY_SIZE(dcs_table),
1831 SET_DISPLAY_ON, 2, CALC_HEADER);
1832 it6616_mipi_tx_write(mipi, 0x05, 0x36);
1833 }
1834
1835 dev_dbg(dev, "mipi_initial chip:0x%02x", it6616_mipi_tx_read(mipi, 0x04));
1836 }
1837
it6616_hdmi_is_5v_on(struct it6616 * it6616)1838 static bool it6616_hdmi_is_5v_on(struct it6616 *it6616)
1839 {
1840 struct regmap *hdmi = it6616->hdmi_regmap;
1841
1842 if (it6616_hdmi_read(hdmi, 0x13) & 0x01)
1843 return true;
1844
1845 return false;
1846 }
1847
it6616_hdmi_is_clock_stable(struct it6616 * it6616)1848 static bool it6616_hdmi_is_clock_stable(struct it6616 *it6616)
1849 {
1850 struct regmap *hdmi = it6616->hdmi_regmap;
1851
1852 if (it6616_hdmi_read(hdmi, 0x13) & 0x10)
1853 return true;
1854
1855 return false;
1856 }
1857
it6616_hdmi_is_symbol_locked(struct it6616 * it6616)1858 static __maybe_unused bool it6616_hdmi_is_symbol_locked(struct it6616 *it6616)
1859 {
1860 struct regmap *hdmi = it6616->hdmi_regmap;
1861 u8 reg14;
1862
1863 reg14 = it6616_hdmi_read(hdmi, 0x14);
1864 if ((reg14 & 0x38) == 0x38)
1865 return true;
1866
1867 return false;
1868 }
1869
it6616_hdmi_is_scdt_on(struct it6616 * it6616)1870 static bool it6616_hdmi_is_scdt_on(struct it6616 *it6616)
1871 {
1872 struct regmap *hdmi = it6616->hdmi_regmap;
1873
1874 if (it6616_hdmi_read(hdmi, 0x19) & BIT(7))
1875 return true;
1876
1877 return false;
1878 }
1879
it6616_hdmi_get_output_color_space(struct it6616 * it6616)1880 static u8 it6616_hdmi_get_output_color_space(struct it6616 *it6616)
1881 {
1882 u8 hdmi_output_color = 0;
1883 u8 mipi_intput_color = it6616->mipi.data_type;
1884
1885 if (it6616->mipi.bus_type == MIPI_CSI) {
1886 switch (mipi_intput_color) {
1887 case CSI_RGB10b:
1888 case CSI_RGB888:
1889 case CSI_RGB666:
1890 case CSI_RGB565:
1891 case CSI_RGB555:
1892 case CSI_RGB444:
1893 hdmi_output_color = HDMI_COLORSPACE_RGB;
1894 break;
1895 case CSI_YCbCr4208b:
1896 hdmi_output_color = HDMI_COLORSPACE_YUV420;
1897 break;
1898 case CSI_YCbCr4228b:
1899 case CSI_YCbCr42210b:
1900 case CSI_YCbCr42212b:
1901 hdmi_output_color = HDMI_COLORSPACE_YUV422;
1902 break;
1903 }
1904 } else {
1905 switch (mipi_intput_color) {
1906 case DSI_RGB_36b:
1907 case DSI_RGB_30b:
1908 case DSI_RGB_24b:
1909 case DSI_RGB_18b_L:
1910 case DSI_RGB_18b:
1911 hdmi_output_color = HDMI_COLORSPACE_RGB;
1912 break;
1913 case DSI_YCbCr_16b:
1914 case DSI_YCbCr_20b:
1915 case DSI_YCbCr_24b:
1916 hdmi_output_color = HDMI_COLORSPACE_YUV422;
1917 break;
1918 }
1919 }
1920 it6616->output_colorspace = hdmi_output_color;
1921
1922 return hdmi_output_color;
1923 }
1924
it6616_hdmi_edid_ram_get(struct it6616 * it6616,u8 * buf)1925 static void it6616_hdmi_edid_ram_get(struct it6616 *it6616, u8 *buf)
1926 {
1927 struct regmap *hdmi = it6616->hdmi_regmap;
1928 struct regmap *edid = it6616->edid_regmap;
1929
1930 it6616_hdmi_write(hdmi, 0x4B, (I2C_ADR_EDID | 0x01));
1931 it6616_hdmi_edid_read(edid, buf, 0, 256);
1932 it6616_hdmi_write(hdmi, 0x4B, (I2C_ADR_EDID));
1933 }
1934
it6616_hdmi_edid_ram_update_chksum(struct it6616 * it6616)1935 static void it6616_hdmi_edid_ram_update_chksum(struct it6616 *it6616)
1936 {
1937 struct regmap *hdmi = it6616->hdmi_regmap;
1938 u16 sum;
1939 u8 offset;
1940 int i;
1941
1942 // cal block 0 sum
1943 sum = 0;
1944 for (i = 0 ; i < 127 ; i++)
1945 sum += it6616->edid_data[i];
1946 sum = (0x100 - sum) & 0xFF;
1947
1948 it6616_hdmi_write(hdmi, 0xC9, sum);
1949
1950 // cal block 1 sum
1951 sum = 0;
1952 offset = it6616_hdmi_read(hdmi, 0xC6);
1953 for (i = 128; i < 128 + 127; i++)
1954 sum += it6616->edid_data[i];
1955
1956 sum -= it6616->edid_data[offset];
1957 sum -= it6616->edid_data[offset + 1];
1958 sum += it6616_hdmi_read(hdmi, 0xC7);
1959 sum += it6616_hdmi_read(hdmi, 0xC8);
1960 sum = (0x100 - sum) & 0xFF;
1961
1962 it6616_hdmi_write(hdmi, 0xCA, sum);
1963 }
1964
it6616_hdmi_edid_ram_init(struct it6616 * it6616)1965 static void it6616_hdmi_edid_ram_init(struct it6616 *it6616)
1966 {
1967 struct regmap *hdmi = it6616->hdmi_regmap;
1968 struct regmap *edid = it6616->edid_regmap;
1969 unsigned int phy_addr_off;
1970 u16 addr;
1971
1972 // write data to EDID RAM
1973 it6616_hdmi_write(hdmi, 0x4B, (I2C_ADR_EDID | 0x01));
1974 it6616_hdmi_edid_write(edid, it6616->edid_data, 0, it6616->edid_len);
1975 it6616_hdmi_write(hdmi, 0x4B, (I2C_ADR_EDID));
1976
1977 // update physical address for VSDB
1978 addr = cec_get_edid_phys_addr(it6616->edid_data, it6616->edid_len, &phy_addr_off);
1979 if (addr != CEC_PHYS_ADDR_INVALID) {
1980 it6616_hdmi_write(hdmi, 0xC6, (u8)phy_addr_off); // VSDB start address
1981 it6616_hdmi_write(hdmi, 0xC7, (addr >> 8) & 0xFF); // addr AB
1982 it6616_hdmi_write(hdmi, 0xC8, addr & 0xFF); // addr CD
1983 }
1984
1985 // recalculate block0/block1 checksum
1986 it6616_hdmi_edid_ram_update_chksum(it6616);
1987
1988 it6616_hdmi_set(hdmi, 0xC5, 0x10, 0x10);
1989 msleep(20);
1990 it6616_hdmi_set(hdmi, 0xC5, 0x10, 0x00);
1991 }
1992
it6616_hdmi_video_reset(struct it6616 * it6616)1993 static void it6616_hdmi_video_reset(struct it6616 *it6616)
1994 {
1995 struct regmap *hdmi = it6616->hdmi_regmap;
1996
1997 it6616_hdmi_set(hdmi, 0x22, BIT(0), BIT(0));
1998 msleep(20);
1999 it6616_hdmi_set(hdmi, 0x22, BIT(0), 0x00);
2000 it6616_hdmi_set(hdmi, 0x10, BIT(1), BIT(1)); // clear vidstable change INT
2001 it6616_hdmi_set(hdmi, 0x12, BIT(7), BIT(7)); // clear vidstable change INT
2002 }
2003
it6616_hdmi_edid_ram_enable(struct it6616 * it6616,u8 enabled)2004 static void it6616_hdmi_edid_ram_enable(struct it6616 *it6616, u8 enabled)
2005 {
2006 struct regmap *hdmi = it6616->hdmi_regmap;
2007
2008 if (enabled)
2009 it6616_hdmi_set(hdmi, 0xC5, 0x3F, 0x02);
2010 else
2011 it6616_hdmi_set(hdmi, 0xC5, 0x3F, 0x13);
2012 }
2013
it6616_hdmi_rx_get_video_info(struct it6616 * it6616)2014 static void it6616_hdmi_rx_get_video_info(struct it6616 *it6616)
2015 {
2016 struct regmap *hdmi = it6616->hdmi_regmap;
2017 struct device *dev = &it6616->hdmi_i2c->dev;
2018 u16 h_sync_pol, v_sync_pol, interlaced;
2019 u16 h_total, h_active, h_front_porch, h_sync_w;
2020 u16 v_total, v_active, v_front_porch, v_sync_w;
2021 u32 frame_rate;
2022
2023 interlaced = (it6616_hdmi_read(hdmi, 0x98) & 0x02) >> 1;
2024
2025 h_total = ((it6616_hdmi_read(hdmi, 0x9C) & 0x3F) << 8) + it6616_hdmi_read(hdmi, 0x9B);
2026 h_active = ((it6616_hdmi_read(hdmi, 0x9E) & 0x3F) << 8) + it6616_hdmi_read(hdmi, 0x9D);
2027 h_front_porch = ((it6616_hdmi_read(hdmi, 0xA1) & 0xF0) << 4) + it6616_hdmi_read(hdmi, 0xA0);
2028 h_sync_w = ((it6616_hdmi_read(hdmi, 0xA1) & 0x01) << 8) + it6616_hdmi_read(hdmi, 0x9F);
2029
2030 v_total = ((it6616_hdmi_read(hdmi, 0xA3) & 0x3F) << 8) + it6616_hdmi_read(hdmi, 0xA2);
2031 v_active = ((it6616_hdmi_read(hdmi, 0xA5) & 0x3F) << 8) + it6616_hdmi_read(hdmi, 0xA4);
2032 v_front_porch = ((it6616_hdmi_read(hdmi, 0xA8) & 0xF0) << 4) + it6616_hdmi_read(hdmi, 0xA7);
2033 v_sync_w = ((it6616_hdmi_read(hdmi, 0xA8) & 0x01) << 8) + it6616_hdmi_read(hdmi, 0xA6);
2034
2035 h_sync_pol = (it6616_hdmi_read(hdmi, 0xAA) & BIT(5)) >> 5;
2036 v_sync_pol = (it6616_hdmi_read(hdmi, 0xAA) & BIT(6)) >> 6;
2037
2038 it6616->vinfo.h_active = h_active;
2039 it6616->vinfo.h_total = h_total;
2040 it6616->vinfo.h_front_porch = h_front_porch;
2041 it6616->vinfo.h_sync_w = h_sync_w;
2042 it6616->vinfo.h_back_porch = (h_total - h_active - h_front_porch - h_sync_w);
2043 it6616->vinfo.v_active = v_active;
2044 it6616->vinfo.v_total = v_total;
2045 it6616->vinfo.v_front_porch = v_front_porch;
2046 it6616->vinfo.v_sync_w = v_sync_w;
2047 it6616->vinfo.v_back_porch = v_total - v_active - v_front_porch - v_sync_w;
2048 it6616->vinfo.interlaced = (interlaced) & 0x01;
2049 it6616->vinfo.v_sync_pol = (v_sync_pol) & 0x01;
2050 it6616->vinfo.h_sync_pol = (h_sync_pol) & 0x01;
2051
2052 frame_rate = (u32)(it6616->vinfo.pclk) * 1000;
2053 frame_rate /= it6616->vinfo.h_total;
2054 frame_rate /= it6616->vinfo.v_total;
2055 it6616->vinfo.frame_rate = frame_rate;
2056
2057 if (it6616->avi_if.colorspace == HDMI_COLORSPACE_YUV420) {
2058 dev_dbg(dev, "HActive = %d\n", it6616->vinfo.h_active*2);
2059 dev_dbg(dev, "HTotal = %d\n", it6616->vinfo.h_total*2);
2060 } else {
2061 dev_dbg(dev, "HActive = %d\n", it6616->vinfo.h_active);
2062 dev_dbg(dev, "HTotal = %d\n", it6616->vinfo.h_total);
2063 }
2064
2065 dev_dbg(dev, "VActive = %d\n", it6616->vinfo.v_active);
2066 dev_dbg(dev, "VTotal = %d\n", it6616->vinfo.v_total);
2067
2068 if (it6616->avi_if.colorspace == HDMI_COLORSPACE_YUV420) {
2069 dev_dbg(dev, "HFrontPorch = %d\n", it6616->vinfo.h_front_porch*2);
2070 dev_dbg(dev, "HSyncWidth = %d\n", it6616->vinfo.h_sync_w*2);
2071 dev_dbg(dev, "HBackPorch = %d\n", it6616->vinfo.h_back_porch*2);
2072 } else {
2073 dev_dbg(dev, "HFrontPorch = %d\n", it6616->vinfo.h_front_porch);
2074 dev_dbg(dev, "HSyncWidth = %d\n", it6616->vinfo.h_sync_w);
2075 dev_dbg(dev, "HBackPorch = %d\n", it6616->vinfo.h_back_porch);
2076 }
2077
2078 dev_dbg(dev, "VFrontPorch = %d\n", it6616->vinfo.v_front_porch);
2079 dev_dbg(dev, "VSyncWidth = %d\n", it6616->vinfo.v_sync_w);
2080 dev_dbg(dev, "VBackPorch = %d\n", it6616->vinfo.v_back_porch);
2081 dev_dbg(dev, "FrameRate = %u\n", it6616->vinfo.frame_rate);
2082
2083 if (it6616->vinfo.interlaced)
2084 dev_dbg(dev, "ScanMode = InterLaced\n");
2085 else
2086 dev_dbg(dev, "ScanMode = Progressive\n");
2087
2088 if (it6616->vinfo.v_sync_pol)
2089 dev_dbg(dev, "VSyncPol = Positive\n");
2090 else
2091 dev_dbg(dev, "VSyncPol = Negative\n");
2092
2093 if (it6616->vinfo.h_sync_pol)
2094 dev_dbg(dev, "HSyncPol = Positive\n");
2095 else
2096 dev_dbg(dev, "HSyncPol = Negative");
2097 }
2098
it6616_hdmi_hpd_output(struct it6616 * it6616,u8 hpd)2099 static void it6616_hdmi_hpd_output(struct it6616 *it6616, u8 hpd)
2100 {
2101 struct regmap *hdmi = it6616->hdmi_regmap;
2102
2103 it6616_hdmi_chgbank(hdmi, 3);
2104
2105 if (hpd)
2106 it6616_hdmi_set(hdmi, 0xAB, 0xC0, 0xC0); // SET PORT0 HPD HIGH
2107 else
2108 it6616_hdmi_set(hdmi, 0xAB, 0xC0, 0x40); // SET PORT0 HPD LOW
2109
2110 it6616_hdmi_chgbank(hdmi, 0);
2111 }
2112
it6616_hdmi_hdcp_reset(struct it6616 * it6616)2113 static void it6616_hdmi_hdcp_reset(struct it6616 *it6616)
2114 {
2115 struct regmap *hdmi = it6616->hdmi_regmap;
2116
2117 it6616_hdmi_set(hdmi, 0x23, 0x02, 0x02);
2118 it6616_hdmi_set(hdmi, 0x23, 0x02, 0x00);
2119 }
2120
it6616_hdmi_get_hdcp_status(struct it6616 * it6616)2121 static bool it6616_hdmi_get_hdcp_status(struct it6616 *it6616)
2122 {
2123 struct regmap *hdmi = it6616->hdmi_regmap;
2124
2125 return it6616_hdmi_read(hdmi, 0xCF) & BIT(5);
2126 }
2127
it6616_get_hdcp_status(struct it6616 * it6616)2128 static bool it6616_get_hdcp_status(struct it6616 *it6616)
2129 {
2130 bool hdcp_status;
2131
2132 hdcp_status = it6616_hdmi_get_hdcp_status(it6616);
2133
2134 return hdcp_status;
2135 }
2136
it6616_hdmi_rx_get_av_mute_state(struct it6616 * it6616)2137 static enum av_mute_state it6616_hdmi_rx_get_av_mute_state(struct it6616 *it6616)
2138 {
2139 struct regmap *hdmi = it6616->hdmi_regmap;
2140 bool av_mute_state;
2141
2142 it6616_hdmi_chgbank(hdmi, 0);
2143 av_mute_state = !!(it6616_hdmi_read(hdmi, 0xAA) & BIT(3));
2144
2145 return av_mute_state ? AV_MUTE_ON : AV_MUTE_OFF;
2146 }
2147
it6616_hdmi_rx_set_av_mute(struct it6616 * it6616,enum av_mute_state mute_state)2148 static void it6616_hdmi_rx_set_av_mute(struct it6616 *it6616, enum av_mute_state mute_state)
2149 {
2150 struct regmap *hdmi = it6616->hdmi_regmap;
2151
2152 it6616_hdmi_chgbank(hdmi, 0);
2153
2154 switch (mute_state) {
2155 case AV_MUTE_OFF:
2156 it6616_hdmi_set(hdmi, 0x4F, BIT(5), 0x00);
2157
2158 if (!it6616->mipi_tx_enable_mipi_output) {
2159 it6616_hdmi_rx_get_video_info(it6616);
2160 it6616_mipi_tx_get_support_format(it6616);
2161 it6616_enable_mipi(it6616);
2162 }
2163 break;
2164 case AV_MUTE_ON:
2165 it6616_hdmi_set(hdmi, 0x4F, BIT(5), BIT(5));
2166 it6616_disable_mipi(it6616);
2167 break;
2168 default:
2169 break;
2170 }
2171 }
2172
it6616_hdmi_update_rs(struct it6616 * it6616,u8 level)2173 static void it6616_hdmi_update_rs(struct it6616 *it6616, u8 level)
2174 {
2175 struct regmap *hdmi = it6616->hdmi_regmap;
2176 u8 rs_val = level;
2177
2178 it6616_hdmi_chgbank(hdmi, 3);
2179 it6616_hdmi_set(hdmi, 0x26, 0x20, 0x00);
2180 it6616_hdmi_write(hdmi, 0x27, rs_val);
2181 it6616_hdmi_write(hdmi, 0x28, rs_val);
2182 it6616_hdmi_write(hdmi, 0x29, rs_val);
2183 it6616_hdmi_chgbank(hdmi, 0);
2184 }
2185
it6616_mipi_tx_calc_rclk(struct it6616 * it6616)2186 static void it6616_mipi_tx_calc_rclk(struct it6616 *it6616)
2187 {
2188 struct regmap *mipi = it6616->mipi_regmap;
2189 struct device *dev = &it6616->mipi_i2c->dev;
2190 unsigned long sum = 0, ul100msCNT = 0;
2191 u8 i, retry = 3;
2192
2193 for (i = 0; i < retry; i++) {
2194 it6616_mipi_tx_set_bits(mipi, 0xE0, 0x80, 0x80); // Enable RCLK 100ms count
2195 msleep(100);
2196 it6616_mipi_tx_set_bits(mipi, 0xE0, 0x80, 0x00); // Disable RCLK 100ms count
2197
2198 ul100msCNT = it6616_mipi_tx_read(mipi, 0xE3);
2199 ul100msCNT = ((ul100msCNT << 8) | (it6616_mipi_tx_read(mipi, 0xE2)));
2200 ul100msCNT = ((ul100msCNT << 8) | (it6616_mipi_tx_read(mipi, 0xE1)));
2201
2202 sum += ul100msCNT;
2203 }
2204 sum /= retry;
2205
2206 it6616->tx_rclk = sum / TIMER_100MS;
2207 dev_dbg(dev, "mipi rclk = %d.%d MHz", it6616->tx_rclk / 1000,
2208 it6616->tx_rclk % 1000);
2209 }
2210
it6616_mipi_tx_calc_mclk(struct it6616 * it6616)2211 static void it6616_mipi_tx_calc_mclk(struct it6616 *it6616)
2212 {
2213 struct regmap *mipi = it6616->mipi_regmap;
2214 struct device *dev = &it6616->mipi_i2c->dev;
2215 unsigned long sum = 0, ulCNT, tx_mclk;
2216 u8 i, retry = 3;
2217
2218 for (i = 0; i < retry; i++) {
2219 it6616_mipi_tx_set_bits(mipi, 0xE7, 0x80, 0x80);
2220 msleep(20);
2221 it6616_mipi_tx_set_bits(mipi, 0xE7, 0x80, 0x00);
2222
2223 ulCNT = it6616_mipi_tx_read(mipi, 0xE7) & 0x0F;
2224 ulCNT = (it6616_mipi_tx_read(mipi, 0xE6) | (ulCNT << 8));
2225
2226 sum += ulCNT;
2227 }
2228
2229 sum /= retry;
2230
2231 //MCLK = 13500*2048/sum;
2232 //MCLK = 27000*2048/sum;
2233 tx_mclk = it6616->tx_rclk * 2048 / sum;
2234 dev_dbg(dev, "mipi mclk = %lu.%lu MHz", tx_mclk / 1000, tx_mclk % 1000);
2235 }
2236
it6616_mipi_tx_calc_pclk(struct it6616 * it6616)2237 static void it6616_mipi_tx_calc_pclk(struct it6616 *it6616)
2238 {
2239 struct regmap *mipi = it6616->mipi_regmap;
2240 struct device *dev = &it6616->mipi_i2c->dev;
2241 unsigned long sum = 0, ulCNT;
2242 u8 i, retry = 3;
2243
2244 for (i = 0; i < retry; i++) {
2245 it6616_mipi_tx_set_bits(mipi, 0xE5, 0x80, 0x80);
2246 msleep(20);
2247 it6616_mipi_tx_set_bits(mipi, 0xE5, 0x80, 0x00);
2248
2249 ulCNT = it6616_mipi_tx_read(mipi, 0xE5) & 0x0F;
2250 ulCNT = it6616_mipi_tx_read(mipi, 0xE4) + (ulCNT << 8);
2251
2252 sum += ulCNT;
2253 }
2254
2255 sum /= retry;
2256
2257 //PCLK = 13500*2048/sum;
2258 //PCLK = 27000*2048/sum;
2259 it6616->tx_pclk = it6616->tx_rclk * 2048 / sum;
2260 dev_dbg(dev, "mipi pclk = %u.%u MHz", it6616->tx_pclk / 1000,
2261 it6616->tx_pclk % 1000);
2262 }
2263
it6616_hdmi_rx_calc_rclk(struct it6616 * it6616)2264 static u32 it6616_hdmi_rx_calc_rclk(struct it6616 *it6616)
2265 {
2266 struct regmap *hdmi = it6616->hdmi_regmap;
2267 struct device *dev = &it6616->hdmi_i2c->dev;
2268 u32 rddata, rclk, sum = 0;
2269 int i, retry = 5;
2270 int t1usint;
2271 int t1usflt;
2272
2273 for (i = 0; i < retry; i++) {
2274 it6616_hdmi_set(hdmi, 0x58, 0x80, 0x80);
2275 msleep(100);
2276 it6616_hdmi_set(hdmi, 0x58, 0x80, 0x00);
2277
2278 rddata = it6616_hdmi_read(hdmi, 0x59);
2279 rddata += (it6616_hdmi_read(hdmi, 0x5A) << 8);
2280 rddata += (it6616_hdmi_read(hdmi, 0x5B) << 16);
2281
2282 sum += rddata;
2283 }
2284
2285 sum /= retry;
2286 rclk = sum / TIMER_100MS;
2287
2288 dev_dbg(dev, "RCLK=%u KHz\n", rclk);
2289
2290 t1usint = rclk / 1000;
2291 t1usflt = (rclk / 1000 - t1usint) * 256;
2292 it6616_hdmi_set(hdmi, 0x1E, 0x3F, t1usint & 0x3F);
2293 it6616_hdmi_write(hdmi, 0x1F, t1usflt);
2294
2295 it6616->rclk = rclk;
2296
2297 return rclk;
2298 }
2299
it6616_hdmi_rx_calc_pclk(struct it6616 * it6616)2300 static u32 it6616_hdmi_rx_calc_pclk(struct it6616 *it6616)
2301 {
2302 struct regmap *hdmi = it6616->hdmi_regmap;
2303 struct device *dev = &it6616->hdmi_i2c->dev;
2304 u32 retry = 5, rddata, i;
2305 u32 pclk, sump = 0;
2306
2307 __recal:
2308 for (i = 0; i < retry; i++) {
2309 msleep(20);
2310 it6616_hdmi_set(hdmi, 0x9A, BIT(7), 0x00);
2311 rddata = ((u32)(it6616_hdmi_read(hdmi, 0x9A) & 0x03) << 8) +
2312 it6616_hdmi_read(hdmi, 0x99);
2313 it6616_hdmi_set(hdmi, 0x9A, BIT(7), BIT(7));
2314 sump += rddata;
2315 }
2316
2317 sump /= retry;
2318
2319 if (sump) {
2320 pclk = it6616->rclk * 512 / sump; // 512=2*256 because of 1T 2 pixel
2321 dev_dbg(dev, "PCLK = %u.%03u MHz", pclk / 1000, pclk % 1000);
2322 it6616->vinfo.pclk = pclk;
2323 } else {
2324 dev_err(dev, "%s: sump == 0", __func__);
2325 goto __recal;
2326 }
2327
2328 return pclk;
2329 }
2330
it6616_hdmi_rx_calc_tmds_clk(struct it6616 * it6616,u8 count)2331 static void it6616_hdmi_rx_calc_tmds_clk(struct it6616 *it6616, u8 count)
2332 {
2333 struct regmap *hdmi = it6616->hdmi_regmap;
2334 struct device *dev = &it6616->hdmi_i2c->dev;
2335 u32 sumt = 0;
2336 u8 rddata = 0, i;
2337
2338 for (i = 0; i < count; i++) {
2339 msleep(20);
2340 rddata = it6616_hdmi_read(hdmi, 0x48) + 1;
2341 sumt += rddata;
2342 }
2343
2344 if (sumt) {
2345 rddata = it6616_hdmi_read(hdmi, 0x43) & 0xE0;
2346
2347 if (rddata & BIT(7))
2348 it6616->vinfo.TMDSCLK = (it6616->rclk * (u32)1024 * i) / sumt;
2349 else if (rddata & BIT(6))
2350 it6616->vinfo.TMDSCLK = (it6616->rclk * (u32)512 * i) / sumt;
2351 else if (rddata & BIT(5))
2352 it6616->vinfo.TMDSCLK = (it6616->rclk * (u32)256 * i) / sumt;
2353 if (rddata == 0x00)
2354 it6616->vinfo.TMDSCLK = (it6616->rclk * (u32)128 * i) / sumt;
2355
2356 dev_dbg(dev, "TMDSCLK = %u.%03uMHz\n",
2357 it6616->vinfo.TMDSCLK / 1000, it6616->vinfo.TMDSCLK % 1000);
2358 } else {
2359 dev_err(dev, "%s - sumt==0\n", __func__);
2360 }
2361 }
2362
it6616_hdmi_receive_avi_infoframe_log(struct it6616 * it6616,u8 * buffer,size_t length)2363 static void it6616_hdmi_receive_avi_infoframe_log(struct it6616 *it6616, u8 *buffer, size_t length)
2364 {
2365 struct device *dev = &it6616->hdmi_i2c->dev;
2366 u8 i;
2367
2368 dev_dbg(dev, "avi infoframe:");
2369 for (i = 0; i < length; i++)
2370 dev_err(dev, "0x%02x", buffer[i]);
2371 }
2372
it6616_hdmi_update_avi_infoframe(struct it6616 * it6616)2373 static int it6616_hdmi_update_avi_infoframe(struct it6616 *it6616)
2374 {
2375 struct regmap *hdmi = it6616->hdmi_regmap;
2376 struct hdmi_avi_infoframe *frame = &it6616->avi_if;
2377 u8 avi_packet[20] = { 0 };
2378
2379 avi_packet[0] = HDMI_INFOFRAME_TYPE_AVI;
2380 it6616_hdmi_chgbank(hdmi, 2);
2381 avi_packet[1] = it6616_hdmi_read(hdmi, REG_RX_AVI_HB1);// version
2382 avi_packet[2] = it6616_hdmi_read(hdmi, REG_RX_AVI_HB2);// version
2383 regmap_bulk_read(hdmi, REG_RX_AVI_DB0, &avi_packet[3], 16);
2384 it6616_hdmi_chgbank(hdmi, 0);
2385
2386 it6616_hdmi_receive_avi_infoframe_log(it6616, avi_packet, ARRAY_SIZE(avi_packet));
2387
2388 return hdmi_infoframe_unpack((union hdmi_infoframe *)frame, avi_packet, sizeof(avi_packet));
2389 }
2390
it6616_hdmi_rx_setup_csc(struct it6616 * it6616)2391 static void it6616_hdmi_rx_setup_csc(struct it6616 *it6616)
2392 {
2393 struct regmap *hdmi = it6616->hdmi_regmap;
2394 struct device *dev = &it6616->hdmi_i2c->dev;
2395 enum hdmi_colorspace color_in;
2396 enum hdmi_colorspace color_out;
2397 enum csc_select csc_select;
2398 enum csc_matrix_type csc_matrix_type;
2399 u8 reg6b = 0;
2400 u8 reg6e = ((HDMI_RX_AUTO_CSC_SELECT << 7) |
2401 (HDMI_RX_QUANT_4LB << 6) |
2402 (HDMI_RX_CRCB_LIMIT << 5) |
2403 (HDMI_RX_COLOR_CLIP << 4) |
2404 (HDMI_RX_ENABLE_DITHER_FCNT_FUNCTION << 2) |
2405 (HDMI_RX_ENABLE_DITHER_FUNCTION << 1) |
2406 HDMI_RX_ENABLE_COLOR_UP_DN_FILTER);
2407
2408 color_in = it6616->avi_if.colorspace;
2409 color_out = it6616_hdmi_get_output_color_space(it6616);
2410
2411 if (color_in == HDMI_COLORSPACE_RGB && color_out != HDMI_COLORSPACE_RGB)
2412 csc_select = CSC_RGB2YUV;
2413 else if (color_in != HDMI_COLORSPACE_RGB && color_out == HDMI_COLORSPACE_RGB)
2414 csc_select = CSC_YUV2RGB;
2415 else
2416 csc_select = CSC_BYPASS;
2417
2418 switch (csc_select) {
2419 case CSC_RGB2YUV:
2420 dev_info(dev, "csc rgb2yuv");
2421 if (it6616->avi_if.colorimetry == HDMI_COLORIMETRY_ITU_709) {
2422 if (it6616->avi_if.quantization_range == HDMI_QUANTIZATION_RANGE_LIMITED)
2423 csc_matrix_type = CSCMtx_RGB2YUV_ITU709_16_235;
2424 else
2425 csc_matrix_type = CSCMtx_RGB2YUV_ITU709_00_255;
2426 } else {/* HDMI_COLORIMETRY_ITU_601 */
2427 if (it6616->avi_if.quantization_range == HDMI_QUANTIZATION_RANGE_LIMITED)
2428 csc_matrix_type = CSCMtx_RGB2YUV_ITU601_16_235;
2429 else
2430 csc_matrix_type = CSCMtx_RGB2YUV_ITU601_00_255;
2431 }
2432 break;
2433
2434 case CSC_YUV2RGB:
2435 dev_info(dev, "csc yuv2rgb");
2436
2437 if (it6616->avi_if.colorimetry == HDMI_COLORIMETRY_ITU_709)
2438 // when 709 format always to RGB full range
2439 csc_matrix_type = CSCMtx_YUV2RGB_ITU709_00_255;
2440 else if (it6616->avi_if.colorimetry == HDMI_COLORIMETRY_EXTENDED &&
2441 (it6616->avi_if.extended_colorimetry == 0x05 ||
2442 it6616->avi_if.extended_colorimetry == 0x06))
2443 // this Matrix is BT2020 YUV to BT2020 RGB, not normal limit/full range RGB
2444 csc_matrix_type = CSCMtx_YUV2RGB_BT2020_00_255; // for BT.2020 CSC
2445 else /* Colormetry_ITU601 */
2446 csc_matrix_type = CSCMtx_YUV2RGB_ITU601_00_255;
2447 break;
2448
2449 case CSC_BYPASS:
2450 dev_info(dev, "csc byass");
2451 break;
2452 }
2453
2454 if (csc_select != CSC_BYPASS) {
2455 it6616_hdmi_chgbank(hdmi, 1);
2456 regmap_bulk_write(hdmi, 0x70, (u8 *)csc_matrix[csc_matrix_type],
2457 sizeof(csc_matrix[0]));
2458 it6616_hdmi_chgbank(hdmi, 0);
2459 }
2460 it6616_hdmi_set(hdmi, 0x6E, 0xF7, reg6e);
2461
2462 it6616_hdmi_set(hdmi, 0x6C, 0x03, csc_select);
2463
2464 switch (color_in) {
2465 case HDMI_COLORSPACE_YUV422:
2466 reg6b = 1 << 4;
2467 break;
2468 case HDMI_COLORSPACE_YUV444:
2469 reg6b = 2 << 4;
2470 break;
2471 case HDMI_COLORSPACE_YUV420:
2472 reg6b = 3 << 4;
2473 break;
2474 case HDMI_COLORSPACE_RGB:
2475 reg6b = 0 << 4;
2476 break;
2477 default:
2478 dev_err(dev, "## unknown input color space %x\n", color_in);
2479 break;
2480 }
2481
2482 switch (color_out) {
2483 case HDMI_COLORSPACE_YUV422:
2484 reg6b |= 1 << 2;
2485 break;
2486 case HDMI_COLORSPACE_YUV444:
2487 reg6b |= 2 << 2;
2488 break;
2489 case HDMI_COLORSPACE_YUV420:
2490 reg6b |= 3 << 2;
2491 break;
2492 case HDMI_COLORSPACE_RGB:
2493 reg6b |= 0 << 2;
2494 break;
2495 default:
2496 dev_err(dev, "## unknown output color space %x\n", color_out);
2497 break;
2498 }
2499
2500 if (it6616->mipi.bus_type == MIPI_CSI) {
2501 switch (it6616->mipi.data_type) {
2502 case CSI_RGB10b:
2503 reg6b |= 1 << 0;
2504 break;
2505 }
2506 } else {
2507 switch (it6616->mipi.data_type) {
2508 case DSI_RGB_36b:
2509 reg6b |= 2 << 0;
2510 break;
2511 case DSI_RGB_30b:
2512 reg6b |= 1 << 0;
2513 break;
2514 }
2515 }
2516
2517 it6616_hdmi_set(hdmi, 0x6B, 0x3F, reg6b);
2518 }
2519
it6616_hdmi_rx_reset_audio_logic(struct it6616 * it6616)2520 static void it6616_hdmi_rx_reset_audio_logic(struct it6616 *it6616)
2521 {
2522 struct regmap *hdmi = it6616->hdmi_regmap;
2523 u8 temp;
2524
2525 it6616_hdmi_set(hdmi, 0x22, BIT(1), BIT(1)); // audio reset
2526 msleep(20);
2527 it6616_hdmi_set(hdmi, 0x22, BIT(1), 0x00);
2528
2529 // RegFS_Set[5:0] : Software set sampling frequency R/W
2530 temp = it6616_hdmi_read(hdmi, 0x8A);
2531 it6616_hdmi_write(hdmi, 0x8A, temp);
2532 it6616_hdmi_write(hdmi, 0x8A, temp);
2533 it6616_hdmi_write(hdmi, 0x8A, temp);
2534 it6616_hdmi_write(hdmi, 0x8A, temp);
2535 }
2536
it6616_hdmi_rx_audio_setup_i2s_justified(struct it6616 * it6616,u8 i2s_justified)2537 static void it6616_hdmi_rx_audio_setup_i2s_justified(struct it6616 *it6616, u8 i2s_justified)
2538 {
2539 struct regmap *hdmi = it6616->hdmi_regmap;
2540
2541 i2s_justified = (i2s_justified == FROM_CONFIG) ?
2542 it6616->audio_i2s_justified : i2s_justified;
2543 it6616_hdmi_set(hdmi, 0x0F, 0x03, 0x00);
2544 it6616_hdmi_set(hdmi, 0x82, 0x03, i2s_justified);
2545 }
2546
it6616_hdmi_tx_audio_setup(struct it6616 * it6616)2547 static void it6616_hdmi_tx_audio_setup(struct it6616 *it6616)
2548 {
2549 struct regmap *hdmi = it6616->hdmi_regmap;
2550 struct device *dev = &it6616->hdmi_i2c->dev;
2551 u32 sum = 0, cts_128;
2552
2553 // RegForce_CTSMode : need to set to 1 for get the cts in the PKT,
2554 // 0 repersent nothing (HW using)
2555 // so set to 1 to get cts in the REG2C1/2C2/2C0
2556 it6616_hdmi_set(hdmi, 0x86, BIT(0), BIT(0));
2557 it6616_hdmi_rx_audio_setup_i2s_justified(it6616, FROM_CONFIG);
2558 it6616_hdmi_chgbank(hdmi, 2);
2559 it6616->ainfo.n = ((u32)it6616_hdmi_read(hdmi, 0xBE) << 12) +
2560 ((u32)it6616_hdmi_read(hdmi, 0xBF) << 4) +
2561 ((u32)it6616_hdmi_read(hdmi, 0xC0) & 0x0F);
2562 it6616->ainfo.cts = it6616_hdmi_read(hdmi, 0xC0) >> 4;
2563 it6616->ainfo.cts |= ((u32)it6616_hdmi_read(hdmi, 0xC1)) << 12;
2564 it6616->ainfo.cts |= ((u32)it6616_hdmi_read(hdmi, 0xC2)) << 4;
2565 it6616_hdmi_chgbank(hdmi, 0);
2566
2567 if (it6616->ainfo.cts == 0) {
2568 dev_info(dev, "WARNING:cts = %u", it6616->ainfo.cts);
2569 return;
2570 }
2571
2572 // in the hdmi2.0 page 84, need bit 24, 25, 26, 27, 30, 31
2573 // Audio_CH_Status : Audio Channel status decoder value[31:24]
2574 // and bit[24:27] = Audio Sampling Rate
2575 it6616->ainfo.channel_status = ((it6616_hdmi_read(hdmi, 0xB5) & 0xC0) >> 2) +
2576 (it6616_hdmi_read(hdmi, 0xB5) & 0x0F);
2577 cts_128 = 128 * it6616->ainfo.cts;
2578 sum = it6616->ainfo.n * it6616->vinfo.TMDSCLK;
2579 it6616->ainfo.sample_freq = sum / cts_128;
2580
2581 dev_info(dev, "n = %u cts = %u\n", it6616->ainfo.n, it6616->ainfo.cts);
2582 dev_info(dev, "tmds clock = %d kHz\n", it6616->vinfo.TMDSCLK);
2583 dev_info(dev, "Audio_CH_Status[24:27 - 30:31][bit0~bit5] = 0x%02x\n",
2584 it6616->ainfo.channel_status);
2585 dev_info(dev, "sw clac sampling frequency = %d.%d kHz\n",
2586 it6616->ainfo.sample_freq, (sum % cts_128) * 100 / cts_128);
2587
2588 if (it6616->ainfo.sample_freq > 25 && it6616->ainfo.sample_freq <= 38)
2589 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_32K;
2590 else if (it6616->ainfo.sample_freq > 38 && it6616->ainfo.sample_freq <= 45)
2591 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_44P1K;
2592 else if (it6616->ainfo.sample_freq > 45 && it6616->ainfo.sample_freq <= 58)
2593 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_48K;
2594 else if (it6616->ainfo.sample_freq > 58 && it6616->ainfo.sample_freq <= 78)
2595 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_64K;
2596 else if (it6616->ainfo.sample_freq > 78 && it6616->ainfo.sample_freq <= 91)
2597 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_88P2K;
2598 else if (it6616->ainfo.sample_freq > 91 && it6616->ainfo.sample_freq <= 106)
2599 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_96K;
2600 else if (it6616->ainfo.sample_freq > 106 && it6616->ainfo.sample_freq <= 166)
2601 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_128K;
2602 else if (it6616->ainfo.sample_freq > 166 && it6616->ainfo.sample_freq <= 182)
2603 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_176P4K;
2604 else if (it6616->ainfo.sample_freq > 182 && it6616->ainfo.sample_freq <= 202)
2605 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_192K;
2606 else if (it6616->ainfo.sample_freq > 224 && it6616->ainfo.sample_freq <= 320)
2607 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_256K;
2608 else if (it6616->ainfo.sample_freq > 320 && it6616->ainfo.sample_freq <= 448)
2609 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_384K;
2610 else if (it6616->ainfo.sample_freq > 448 && it6616->ainfo.sample_freq <= 638)
2611 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_512K;
2612 else if (it6616->ainfo.sample_freq > 638 && it6616->ainfo.sample_freq <= 894)
2613 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_768K;
2614 else if (it6616->ainfo.sample_freq > 894 && it6616->ainfo.sample_freq <= 1324)
2615 it6616->ainfo.force_sample_freq = AUDIO_SAMPLING_1024K;
2616
2617 dev_info(dev, "Sampling_Frequency value 0x%02x", it6616->ainfo.force_sample_freq);
2618
2619 if (it6616->ainfo.channel_status == it6616->ainfo.force_sample_freq) {
2620 dev_dbg(dev, "channel_status == force_sample_freq\n");
2621 if (it6616_hdmi_read(hdmi, 0x81) & BIT(6)) {
2622 // RegForce_FS : 0: Disable Force Audio FS mode
2623 it6616_hdmi_set(hdmi, 0x81, BIT(6), 0x00);
2624 it6616_hdmi_rx_reset_audio_logic(it6616);
2625 }
2626 it6616->audio_sampling_freq_error_count = 0;
2627 return;
2628 }
2629
2630 it6616->audio_sampling_freq_error_count++;
2631 dev_dbg(dev, "it6616->audio_sampling_freq_error_count=%d\n",
2632 (int) it6616->audio_sampling_freq_error_count);
2633
2634 /* exceed max error count , enable Force Sampling Mode */
2635 if (it6616->audio_sampling_freq_error_count > MAX_AUDIO_SAMPLING_FREQ_ERROR_COUNT) {
2636 it6616_hdmi_set(hdmi, 0x81, BIT(6), BIT(6)); // RegForce_FS : Force Audio FS mode
2637 // RegFS_Set[5:0] : Software set sampling frequency
2638 it6616_hdmi_set(hdmi, 0x8A, 0x3F, it6616->ainfo.force_sample_freq);
2639
2640 #if defined(Enable_Audio_Compatibility) && (Enable_Audio_Compatibility == 1)
2641 if (it6616->ainfo.sample_freq <= 182) {
2642 it6616_hdmi_set(hdmi, 0x89, 0x0C, 0x04);
2643 it6616_hdmi_set(hdmi, 0x86, 0x0C, 0x0C);
2644 } else {
2645 it6616_hdmi_set(hdmi, 0x89, 0x0C, 0x0C);
2646 it6616_hdmi_set(hdmi, 0x86, 0x0C, 0x04);
2647 }
2648 #endif
2649 it6616->audio_sampling_freq_error_count = 0;
2650 it6616_hdmi_rx_reset_audio_logic(it6616);
2651 }
2652 }
2653
it6616_hdmi_tx_audio_output_enable(struct it6616 * it6616,u8 output_interface)2654 static void it6616_hdmi_tx_audio_output_enable(struct it6616 *it6616, u8 output_interface)
2655 {
2656 struct regmap *hdmi = it6616->hdmi_regmap;
2657 struct device *dev = &it6616->hdmi_i2c->dev;
2658
2659 it6616_hdmi_chgbank(hdmi, 1);
2660
2661 switch (output_interface) {
2662 case AUDIO_OFF:
2663 dev_info(dev, "audio off");
2664 it6616_hdmi_write(hdmi, 0xC7, 0x7F); // SPDIF/I2S tri-state on
2665 break;
2666
2667 case AUDIO_I2S:
2668 case AUDIO_SPDIF:
2669 dev_info(dev, "enable audio output");
2670 it6616_hdmi_write(hdmi, 0xC7, 0x00); // SPDIF/I2S tri-state off
2671 break;
2672 }
2673
2674 it6616_hdmi_chgbank(hdmi, 0);
2675 }
2676
it6616_hdmi_audio_mute_clear(struct it6616 * it6616)2677 static void it6616_hdmi_audio_mute_clear(struct it6616 *it6616)
2678 {
2679 struct regmap *hdmi = it6616->hdmi_regmap;
2680
2681 it6616_hdmi_set(hdmi, 0x8C, BIT(4), BIT(4)); // set RegHWMuteClr
2682 it6616_hdmi_set(hdmi, 0x8C, BIT(4), 0x00); // clear RegHWMuteClr for clear H/W Mute
2683 }
2684
2685
it6616_hdmi_rx_audio_process(struct it6616 * it6616)2686 static void it6616_hdmi_rx_audio_process(struct it6616 *it6616)
2687 {
2688 it6616_hdmi_tx_audio_output_enable(it6616, AUDIO_OFF);
2689 it6616_hdmi_rx_reset_audio_logic(it6616);
2690 it6616_hdmi_tx_audio_setup(it6616);
2691 it6616_hdmi_audio_mute_clear(it6616);
2692 it6616_hdmi_tx_audio_output_enable(it6616, it6616->audio_interface);
2693 }
2694
it6616_hdmi_initial(struct it6616 * it6616)2695 static void it6616_hdmi_initial(struct it6616 *it6616)
2696 {
2697 struct regmap *hdmi = it6616->hdmi_regmap;
2698 struct device *dev = &it6616->hdmi_i2c->dev;
2699
2700 it6616_hdmi_chgbank(hdmi, 0);
2701 it6616_hdim_write_table(hdmi, it6616_hdmi_init_table);
2702
2703 it6616_hdmi_update_rs(it6616, DEFAULT_RS_LEVEL);
2704 it6616_hdmi_set(hdmi, 0x67, BIT(7), it6616->hdmi_rx_disable_pixel_repeat << 7);
2705 it6616_hdmi_set(hdmi, 0x69, BIT(6) | BIT(5),
2706 it6616->hdmi_rx_video_stable_condition << 5);
2707 dev_dbg(dev,
2708 "set hdmi rx video stable condition, reg0x69[6:5], 0x%02x",
2709 it6616_hdmi_read(hdmi, 0x69));
2710 }
2711
it6616_hdmi_irq_color_depth(struct it6616 * it6616)2712 static void it6616_hdmi_irq_color_depth(struct it6616 *it6616)
2713 {
2714 struct regmap *hdmi = it6616->hdmi_regmap;
2715 struct device *dev = &it6616->hdmi_i2c->dev;
2716 u8 input_color_depth;
2717
2718 input_color_depth = (it6616_hdmi_read(hdmi, 0x98) >> 4) & 0x0F;
2719 dev_dbg(dev, "input color depth = %d bits\n", input_color_depth * 6);
2720 }
2721
it6616_hdmi_irq_new_avi_infoframe(struct it6616 * it6616)2722 static void it6616_hdmi_irq_new_avi_infoframe(struct it6616 *it6616)
2723 {
2724 struct hdmi_avi_infoframe *avi_new;
2725 struct hdmi_avi_infoframe *avi_prev;
2726
2727 if (it6616_hdmi_update_avi_infoframe(it6616) == 0) {
2728 avi_new = &it6616->avi_if;
2729 avi_prev = &it6616->avi_if_prev;
2730 hdmi_infoframe_log(KERN_INFO, &it6616->hdmi_i2c->dev,
2731 (union hdmi_infoframe *)avi_new);
2732
2733 if (avi_prev->video_code != avi_new->video_code)
2734 avi_prev->video_code = avi_new->video_code;
2735 if (avi_prev->colorspace != avi_new->colorspace)
2736 avi_prev->colorspace = avi_new->colorspace;
2737 }
2738 }
2739
it6616_hdmi_hpd_trun_on(struct it6616 * it6616)2740 static void it6616_hdmi_hpd_trun_on(struct it6616 *it6616)
2741 {
2742 it6616_hdmi_edid_ram_enable(it6616, 1);
2743 it6616_hdmi_video_reset(it6616);
2744 it6616_hdmi_rx_reset_audio_logic(it6616);
2745 it6616_hdmi_hpd_output(it6616, true);
2746 }
2747
it6616_hdmi_hpd_trun_off(struct it6616 * it6616)2748 static void it6616_hdmi_hpd_trun_off(struct it6616 *it6616)
2749 {
2750 it6616_hdmi_hpd_output(it6616, false);
2751 it6616_hdmi_edid_ram_enable(it6616, 0);
2752 }
2753
it6616_mipitx_irq(struct it6616 * it6616)2754 static void it6616_mipitx_irq(struct it6616 *it6616)
2755 {
2756 struct regmap *mipi = it6616->mipi_regmap;
2757 struct device *dev = &it6616->mipi_i2c->dev;
2758 u8 reg09h, reg0ah, reg0bh;
2759
2760 reg09h = it6616_mipi_tx_read(mipi, 0x09);
2761 reg0ah = it6616_mipi_tx_read(mipi, 0x0A);
2762 reg0bh = it6616_mipi_tx_read(mipi, 0x0B);
2763
2764 it6616_mipi_tx_write(mipi, 0x0A, reg0ah);
2765 it6616_mipi_tx_write(mipi, 0x0B, reg0bh);
2766
2767 if (reg0bh & 0x10) {
2768 it6616->mipi_tx_video_stable = it6616_mipi_tx_get_video_stable(it6616);
2769 dev_info(dev, "mipi tx Video Stable Change ...");
2770 dev_info(dev, "mipi tx reg09 = 0x%02x, video %sstable",
2771 reg09h, it6616->mipi_tx_video_stable ? "" : "un");
2772
2773 if (it6616->mipi_tx_video_stable) {
2774 it6616_mipi_tx_calc_rclk(it6616);
2775 it6616_mipi_tx_calc_mclk(it6616);
2776 it6616_mipi_tx_calc_pclk(it6616);
2777 }
2778 }
2779
2780 if (reg0ah & 0x70) {
2781 if (reg0ah & 0x20)
2782 dev_err(dev, "Mipi Byte mismatch Err!!!\n");
2783 if (reg0ah & 0x40)
2784 dev_err(dev, "mipi P2M FIFO Err!!!\n");
2785 }
2786 }
2787
it6616_hdmi_irq(struct it6616 * it6616)2788 static void it6616_hdmi_irq(struct it6616 *it6616)
2789 {
2790 struct regmap *hdmi = it6616->hdmi_regmap;
2791 struct device *dev = &it6616->hdmi_i2c->dev;
2792
2793 u8 reg05h, reg06h, Reg08h, Reg09h;
2794 u8 Reg10h, Reg11h, Reg12h;
2795 u8 Reg13h, Reg14h, Reg15h;
2796 u8 Reg1Ah, Reg1Bh;
2797
2798 reg05h = it6616_hdmi_read(hdmi, 0x05);
2799 it6616_hdmi_write(hdmi, 0x05, reg05h);
2800 reg06h = it6616_hdmi_read(hdmi, 0x06);
2801 it6616_hdmi_write(hdmi, 0x06, reg06h);
2802 Reg08h = it6616_hdmi_read(hdmi, 0x08);
2803 it6616_hdmi_write(hdmi, 0x08, Reg08h);
2804 Reg09h = it6616_hdmi_read(hdmi, 0x09);
2805 it6616_hdmi_write(hdmi, 0x09, Reg09h);
2806
2807 Reg10h = it6616_hdmi_read(hdmi, 0x10);
2808 it6616_hdmi_write(hdmi, 0x10, Reg10h);
2809
2810 Reg11h = it6616_hdmi_read(hdmi, 0x11);
2811 it6616_hdmi_write(hdmi, 0x11, Reg11h);
2812
2813 Reg12h = it6616_hdmi_read(hdmi, 0x12);
2814 it6616_hdmi_write(hdmi, 0x12, Reg12h & 0x7F);
2815
2816 Reg13h = it6616_hdmi_read(hdmi, 0x13);
2817 Reg14h = it6616_hdmi_read(hdmi, 0x14);
2818 Reg15h = it6616_hdmi_read(hdmi, 0x15);
2819
2820 if (reg05h != 0x00) {
2821 if (reg05h & 0x10)
2822 dev_info(dev, "# hdmi mode chg #\n");
2823 if (reg05h & 0x20) {
2824 dev_err(dev, "# ECC Error #\n");
2825 it6616_hdmi_hdcp_reset(it6616);
2826 }
2827 if (reg05h & 0x40)
2828 dev_err(dev, "# Deskew Error #\n");
2829 if (reg05h & 0x80)
2830 dev_err(dev, "# H2VSkew Fail #\n");
2831 if (reg05h & 0x04) {
2832 dev_info(dev, "# Input Clock Change Detect #\n");
2833 if (it6616_hdmi_is_clock_stable(it6616))
2834 dev_info(dev, "# Clock Stable #\n");
2835 else
2836 dev_err(dev, "# Clock NOT Stable #\n");
2837 }
2838
2839 if (reg05h & 0x02)
2840 dev_info(dev, "# Rx CKOn Detect #\n");
2841
2842 if (reg05h & 0x01) {
2843 dev_info(dev, "# 5V state change INT #\n");
2844 it6616_hdmi_hdcp_reset(it6616);
2845 if (it6616_hdmi_is_5v_on(it6616))
2846 it6616_hdmi_hpd_trun_on(it6616);
2847 else
2848 it6616_hdmi_hpd_trun_off(it6616);
2849 }
2850 }
2851
2852 if (reg06h != 0x00) {
2853 if (reg06h & 0x80)
2854 dev_err(dev, "# FSM Error #\n");
2855 if (reg06h & 0x40)
2856 dev_err(dev, "# CH2 Symbol lock Rst #\n");
2857 if (reg06h & 0x20)
2858 dev_err(dev, "# CH1 Symbol lock Rst #\n");
2859 if (reg06h & 0x10)
2860 dev_err(dev, "# CH0 Symbol lock Rst #\n");
2861 if (reg06h & 0x08)
2862 dev_err(dev, "# CH2 CDR FIFO Aut0-Rst #\n");
2863 if (reg06h & 0x04)
2864 dev_err(dev, "# CH1 CDR FIFO Aut0-Rst #\n");
2865 if (reg06h & 0x02)
2866 dev_err(dev, "# CH0 CDR FIFO Aut0-Rst #\n");
2867 if (reg06h & 0x01)
2868 dev_info(dev, "# Symbol Lock State Change # ");
2869 }
2870
2871 if (Reg09h != 0x00) {
2872 if (Reg09h & 0x01)
2873 dev_info(dev, "# HDCP Authentication Start #");
2874 if (Reg09h & 0x02) {
2875 dev_info(dev, "# HDCP Authentication Done #");
2876 it6616->hdmi_rx_hdcp_state = true;
2877 }
2878 if (Reg09h & 0x04) {
2879 it6616->hdmi_rx_hdcp_state = it6616_get_hdcp_status(it6616);
2880 dev_info(dev, "HDCP Encryption change interrupt!");
2881 dev_info(dev, "HDCP Encryption %s!",
2882 it6616->hdmi_rx_hdcp_state ? "ON" : "OFF");
2883 }
2884 if (Reg09h & 0x08) {
2885 dev_info(dev, "# HDCP Off #");
2886 it6616->hdmi_rx_hdcp_state = false;
2887 }
2888 }
2889
2890 if (Reg12h != 0x00) {
2891 if (Reg12h & BIT(7)) {
2892 Reg1Ah = it6616_hdmi_read(hdmi, 0x1A);
2893 Reg1Bh = it6616_hdmi_read(hdmi, 0x1B) & 0x07;
2894 dev_info(dev, "# Video Parameters Change #\n");
2895 dev_info(dev, "# VidParaChange_Sts=Reg1Bh=0x%02X Reg1Ah=0x%02X\n",
2896 (int) Reg1Bh, (int) Reg1Ah);
2897 it6616_hdmi_rx_calc_tmds_clk(it6616, 5);
2898 it6616_hdmi_rx_calc_pclk(it6616);
2899 it6616_hdmi_rx_get_video_info(it6616);
2900 // only parameter change need to clear INT here ,
2901 //or register 1A/1B can't be read after clear.
2902 it6616_hdmi_write(hdmi, 0x12, 0x80);
2903 }
2904
2905 if (Reg12h & BIT(6))
2906 dev_info(dev, "# 3D audio Valie Change #\n");
2907 if (Reg12h & BIT(5))
2908 dev_info(dev, "# DRM pkt Change #\n");
2909 if (Reg12h & 0x10)
2910 dev_info(dev, "# New Audio PKT Received #\n");
2911 if (Reg12h & 0x08)
2912 dev_info(dev, "# New ACP PKT Received #\n");
2913 if (Reg12h & 0x04)
2914 dev_info(dev, "# New SPD PKT Received #\n");
2915 if (Reg12h & 0x02)
2916 dev_info(dev, "# New MPEG InfoFrame Received #\n");
2917 if (Reg12h & 0x01) {
2918 dev_info(dev, "# New AVI InfoFrame Received #\n");
2919 it6616_hdmi_irq_new_avi_infoframe(it6616);
2920 it6616_hdmi_rx_setup_csc(it6616);
2921 }
2922 }
2923
2924 if (Reg10h != 0x00) {
2925 if (Reg10h & 0x80) {
2926 dev_err(dev, "# Audio FIFO Error #");
2927 it6616_hdmi_rx_audio_process(it6616);
2928 }
2929 if (Reg10h & 0x40)
2930 dev_info(dev, "# Audio Auto Mute #");
2931 // todo: how about on/off flag at the same time ?
2932 if ((Reg10h & 0x20)) {
2933 dev_info(dev, "# PKT Left Mute #");
2934 it6616_hdmi_rx_set_av_mute(it6616, AV_MUTE_OFF);
2935 }
2936 if ((Reg10h & 0x10)) {
2937 dev_info(dev, "# Set Mute PKT Received #");
2938 it6616_hdmi_rx_set_av_mute(it6616, AV_MUTE_ON);
2939 }
2940 if (Reg10h & 0x08)
2941 dev_info(dev, "# Timer Counter Interrupt #");
2942 if (Reg10h & 0x04)
2943 dev_info(dev, "# Video Mode Changed #");
2944 if (Reg10h & 0x02) {
2945 it6616->hdmi_rx_video_stable = it6616_hdmi_is_scdt_on(it6616);
2946 dev_info(dev, "SCDT %s", it6616->hdmi_rx_video_stable ? "ON" : "OFF");
2947
2948 if (it6616->hdmi_rx_video_stable) {
2949 it6616_hdmi_rx_calc_tmds_clk(it6616, 5);
2950 it6616_hdmi_rx_calc_pclk(it6616);
2951 it6616_hdmi_rx_get_video_info(it6616);
2952 it6616_hdmi_rx_audio_process(it6616);
2953 msleep(400);
2954 it6616_mipi_tx_get_support_format(it6616);
2955 it6616_enable_mipi(it6616);
2956 } else {
2957 it6616_disable_mipi(it6616);
2958 }
2959 }
2960 if (Reg10h & 0x01)
2961 dev_info(dev, "# Video Abnormal Interrupt #\n");
2962 }
2963
2964 if (Reg11h != 0x00) {
2965 if (Reg11h & BIT(5))
2966 dev_info(dev, "# No Audio InfoFrame Received #\n");
2967 if (Reg11h & BIT(4))
2968 dev_info(dev, "# No AVI InfoFrame Received #\n");
2969 if (Reg11h & BIT(3)) {
2970 dev_info(dev, "# CD Detect #\n");
2971 it6616_hdmi_irq_color_depth(it6616);
2972 }
2973 if (Reg11h & BIT(1))
2974 it6616_hdmi_write(hdmi, 0x11, BIT(1));
2975 if (Reg11h & BIT(0))
2976 it6616_hdmi_write(hdmi, 0x11, BIT(0));
2977 }
2978
2979 if (Reg13h != 0x00) {
2980 if (Reg13h & BIT(0))
2981 dev_dbg(dev, "# Port 0 power 5V detect #\n");
2982 if (Reg13h & BIT(1))
2983 dev_dbg(dev, "# Port 0 HDMI mode #\n");
2984 else
2985 dev_dbg(dev, "# Port 0 DVI mode #\n");
2986 }
2987
2988 if (Reg14h != 0x00) {
2989 if (Reg14h & BIT(0))
2990 dev_dbg(dev, "# Port 0 IPLL clock is higher than 100MHz #\n");
2991 }
2992
2993 if (Reg15h != 0x00) {
2994 if (Reg15h & BIT(6))
2995 dev_dbg(dev, "# Port 0 EDID Idle #\n");
2996 else
2997 dev_dbg(dev, "# Port 0 EDID active #\n");
2998 }
2999 }
3000
it6616_get_chip_id(struct it6616 * it6616)3001 static int it6616_get_chip_id(struct it6616 *it6616)
3002 {
3003 struct regmap *hdmi = it6616->hdmi_regmap;
3004 struct device *dev = &it6616->hdmi_i2c->dev;
3005 u8 chip_id[4] = {0x54, 0x49, 0x16, 0x66};
3006 int i, ret;
3007
3008 for (i = 0; i < sizeof(chip_id); i++) {
3009 ret = it6616_hdmi_read(hdmi, i);
3010
3011 if (ret != chip_id[i]) {
3012 dev_err(dev, "not 6616 reg[0x%02x]=0x%02x", i, ret);
3013 return -ENODEV;
3014 }
3015 }
3016
3017 return 0;
3018 }
3019
it6616_poll_threaded_handler(struct it6616 * it6616)3020 static void it6616_poll_threaded_handler(struct it6616 *it6616)
3021 {
3022 struct regmap *hdmi = it6616->hdmi_regmap;
3023 enum av_mute_state mute_state_config = !!(it6616_hdmi_read(hdmi, 0x4F) & BIT(5));
3024 enum av_mute_state current_mute_state;
3025
3026 current_mute_state = it6616_hdmi_rx_get_av_mute_state(it6616);
3027
3028 if (mute_state_config != current_mute_state)
3029 it6616_hdmi_rx_set_av_mute(it6616, current_mute_state);
3030 }
3031
it6616_intp_threaded_handler(int unused,void * data)3032 static irqreturn_t it6616_intp_threaded_handler(int unused, void *data)
3033 {
3034 struct it6616 *it6616 = (struct it6616 *)data;
3035
3036 mutex_lock(&it6616->confctl_mutex);
3037
3038 it6616_hdmi_irq(it6616);
3039 it6616_mipitx_irq(it6616);
3040
3041 mutex_unlock(&it6616->confctl_mutex);
3042
3043 return IRQ_HANDLED;
3044 }
3045
it6616_initial(struct it6616 * it6616)3046 static int it6616_initial(struct it6616 *it6616)
3047 {
3048 struct device *dev = &it6616->hdmi_i2c->dev;
3049
3050 mutex_lock(&it6616->confctl_mutex);
3051
3052 /* get device id */
3053 if (it6616_get_chip_id(it6616)) {
3054 dev_err(dev, "can not find it6616");
3055 return -ENODEV;
3056 }
3057
3058 // init driver variables:
3059 it6616->edid_len = sizeof(default_edid);
3060 memcpy(it6616->edid_data, default_edid, it6616->edid_len);
3061
3062 // mipi common settings:
3063 it6616->mipi.bus_type = MIPI_TX_INTERFACE;
3064 it6616->mipi.lane_cnt = it6616->csi_lanes_in_use;
3065 it6616->mipi.data_type = MIPI_TX_DATA_TYPE;
3066
3067 it6616->mipi_tx_enable_auto_adjust_lane_count =
3068 MIPI_TX_ENABLE_AUTO_ADJUST_LANE_COUNT;
3069 it6616->mipi_tx_enable_h_fire_packet =
3070 MIPI_TX_ENABLE_H_FIRE_PACKET;
3071 it6616->mipi_tx_enable_initial_fire_lp_cmd =
3072 MIPI_TX_ENABLE_INITIAL_FIRE_LP_CMD;
3073 // hdmi settings:
3074 it6616->rs_level = DEFAULT_RS_LEVEL;
3075 it6616->audio_interface = AUDIO_I2S;
3076 it6616->audio_i2s_justified = AUDIO_I2S_JUSTIFIED;
3077 it6616->hdmi_rx_disable_pixel_repeat =
3078 HDMI_RX_DISABLE_PIXEL_REPEAT;
3079 it6616->hdmi_rx_video_stable_condition =
3080 HDMI_RX_VIDEO_STABLE_CONDITION;
3081 it6616->mipi_tx_enable_continuous_clock =
3082 MIPI_TX_ENABLE_CONTINUOUS_CLOCK;
3083 it6616->mipi_tx_enable_manual_adjusted_d_phy =
3084 MIPI_TX_ENABLE_MANUAL_ADJUSTED_D_PHY;
3085 it6616->hdmi_rx_video_stable = false;
3086 it6616->mipi_tx_video_stable = false;
3087 it6616->hdmi_rx_hdcp_state = false;
3088 it6616->mipi_tx_enable_mipi_output = false;
3089
3090 it6616_hdmi_rx_calc_rclk(it6616);
3091
3092 it6616_hdmi_initial(it6616);
3093 it6616_hdmi_edid_ram_init(it6616);
3094 it6616_mipitx_init_bus_para(it6616);
3095 it6616_mipitx_initial(it6616);
3096
3097 mutex_unlock(&it6616->confctl_mutex);
3098
3099 return 0;
3100 }
3101
it6616_set_hpd(struct it6616 * it6616,u8 hpd)3102 static __maybe_unused void it6616_set_hpd(struct it6616 *it6616, u8 hpd)
3103 {
3104 mutex_lock(&it6616->confctl_mutex);
3105
3106 if (hpd)
3107 it6616_hdmi_hpd_trun_on(it6616);
3108 else
3109 it6616_hdmi_hpd_trun_off(it6616);
3110
3111 mutex_unlock(&it6616->confctl_mutex);
3112 }
3113
it6616_update_edid_data(struct it6616 * it6616,u8 * edid,int edid_len)3114 static __maybe_unused void it6616_update_edid_data(struct it6616 *it6616, u8 *edid, int edid_len)
3115 {
3116 mutex_lock(&it6616->confctl_mutex);
3117
3118 memcpy(it6616->edid_data, edid, it6616->edid_len);
3119 it6616->edid_len = edid_len;
3120 it6616_hdmi_edid_ram_init(it6616);
3121
3122 mutex_unlock(&it6616->confctl_mutex);
3123 }
3124
3125 static const struct regmap_range it6616_hdmi_volatile_ranges[] = {
3126 { .range_min = 0, .range_max = 0xff },
3127 };
3128
3129 static const struct regmap_access_table it6616_hdmi_volatile_table = {
3130 .yes_ranges = it6616_hdmi_volatile_ranges,
3131 .n_yes_ranges = ARRAY_SIZE(it6616_hdmi_volatile_ranges),
3132 };
3133
3134 static const struct regmap_config it6616_hdmi_regmap_config = {
3135 .reg_bits = 8,
3136 .val_bits = 8,
3137 .volatile_table = &it6616_hdmi_volatile_table,
3138 .cache_type = REGCACHE_NONE,
3139 };
3140
3141 static const struct regmap_range it6616_mipi_volatile_ranges[] = {
3142 { .range_min = 0, .range_max = 0xff },
3143 };
3144
3145 static const struct regmap_access_table it6616_mipi_volatile_table = {
3146 .yes_ranges = it6616_mipi_volatile_ranges,
3147 .n_yes_ranges = ARRAY_SIZE(it6616_mipi_volatile_ranges),
3148 };
3149
3150 static const struct regmap_config it6616_mipi_regmap_config = {
3151 .reg_bits = 8,
3152 .val_bits = 8,
3153 .volatile_table = &it6616_mipi_volatile_table,
3154 .cache_type = REGCACHE_NONE,
3155 };
3156
3157 static const struct regmap_range it6616_edid_volatile_ranges[] = {
3158 { .range_min = 0, .range_max = 0xff },
3159 };
3160
3161 static const struct regmap_access_table it6616_edid_volatile_table = {
3162 .yes_ranges = it6616_edid_volatile_ranges,
3163 .n_yes_ranges = ARRAY_SIZE(it6616_edid_volatile_ranges),
3164 };
3165
3166 static const struct regmap_config it6616_edid_regmap_config = {
3167 .reg_bits = 8,
3168 .val_bits = 8,
3169 .volatile_table = &it6616_edid_volatile_table,
3170 .cache_type = REGCACHE_NONE,
3171 };
3172
attr_buffer_put(char * buf,char * reg_buf)3173 static ssize_t attr_buffer_put(char *buf, char *reg_buf)
3174 {
3175 int i = 0;
3176 char *str = buf, *end = buf + PAGE_SIZE;
3177
3178 str += scnprintf(str, end - str,
3179 " 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07");
3180 str += scnprintf(str, end - str,
3181 " 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F\n");
3182 str += scnprintf(str, end - str,
3183 "=============================================");
3184 str += scnprintf(str, end - str,
3185 "=======================================");
3186
3187 for (i = 0; i < 256; i++) {
3188 if (i % 16 == 0)
3189 str += scnprintf(str, end - str, "\n[%02X] ", i & 0xF0);
3190 str += scnprintf(str, end - str, "0x%02X ", reg_buf[i]);
3191 }
3192 str += scnprintf(str, end - str, "\n");
3193
3194 return end - str;
3195 }
edid_ram_show(struct device * dev,struct device_attribute * attr,char * buf)3196 static ssize_t edid_ram_show(struct device *dev,
3197 struct device_attribute *attr, char *buf)
3198 {
3199 struct it6616 *it6616 = dev_get_drvdata(dev);
3200
3201 u8 reg_buf[256];
3202
3203 dev_info(dev, "%s(%x)\n", __func__, it6616->attr_hdmi_reg_bank);
3204
3205 mutex_lock(&it6616->confctl_mutex);
3206 it6616_hdmi_edid_ram_get(it6616, reg_buf);
3207 mutex_unlock(&it6616->confctl_mutex);
3208
3209 return attr_buffer_put(buf, reg_buf);
3210 }
3211
hdmi_reg_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3212 static ssize_t hdmi_reg_store(struct device *dev,
3213 struct device_attribute *attr, const char *buf, size_t count)
3214 {
3215 struct it6616 *it6616 = dev_get_drvdata(dev);
3216 int reg_bank;
3217
3218 if (kstrtoint(buf, 10, ®_bank) < 0)
3219 return -EINVAL;
3220
3221 it6616->attr_hdmi_reg_bank = (u8) reg_bank;
3222
3223 dev_info(dev, "%s() %d, %x\n",
3224 __func__, reg_bank, it6616->attr_hdmi_reg_bank);
3225
3226 return count;
3227 }
3228
3229
hdmi_reg_show(struct device * dev,struct device_attribute * attr,char * buf)3230 static ssize_t hdmi_reg_show(struct device *dev,
3231 struct device_attribute *attr, char *buf)
3232 {
3233 struct it6616 *it6616 = dev_get_drvdata(dev);
3234 struct regmap *hdmi = it6616->hdmi_regmap;
3235 int i;
3236 u8 reg_buf[256];
3237
3238 dev_info(dev, "%s(%x)\n", __func__, it6616->attr_hdmi_reg_bank);
3239
3240 mutex_lock(&it6616->confctl_mutex);
3241 it6616_hdmi_chgbank(hdmi, it6616->attr_hdmi_reg_bank);
3242 for (i = 0; i < 256; i++)
3243 reg_buf[i] = it6616_hdmi_read(hdmi, i);
3244 //regmap_bulk_read(dp, 0, reg_buf, 256);
3245 it6616_hdmi_chgbank(hdmi, 0);
3246 mutex_unlock(&it6616->confctl_mutex);
3247
3248 return attr_buffer_put(buf, reg_buf);
3249 }
3250
mipi_reg_show(struct device * dev,struct device_attribute * attr,char * buf)3251 static ssize_t mipi_reg_show(struct device *dev,
3252 struct device_attribute *attr, char *buf)
3253 {
3254 struct it6616 *it6616 = dev_get_drvdata(dev);
3255 struct regmap *mipi = it6616->mipi_regmap;
3256 int i;
3257 u8 reg_buf[256];
3258
3259 mutex_lock(&it6616->confctl_mutex);
3260 for (i = 0; i < 256; i++)
3261 reg_buf[i] = it6616_mipi_tx_read(mipi, i);
3262 //regmap_bulk_read(mipi, 0, reg_buf, 256);
3263 mutex_unlock(&it6616->confctl_mutex);
3264
3265 return attr_buffer_put(buf, reg_buf);
3266 }
3267
mipi_reg_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)3268 static ssize_t mipi_reg_store(struct device *dev,
3269 struct device_attribute *attr, const char *buf, size_t size)
3270 {
3271 struct it6616 *it6616 = dev_get_drvdata(dev);
3272 struct regmap *mipi = it6616->mipi_regmap;
3273 unsigned int addr, val;
3274 int ret;
3275
3276 ret = sscanf(buf, "%X %X ", &addr, &val);
3277 if (ret) {
3278 dev_info(dev, "addr= %2.2X\n", addr);
3279 dev_info(dev, "val = %2.2X\n", val);
3280 if (((addr <= 0xFF) && (addr >= 0x00)) && ((val <= 0xFF) && (val >= 0x00)))
3281 regmap_write(mipi, addr, val);
3282 } else {
3283 dev_info(dev, "it6616_fwrite_mipi_reg , error[%s]\n", buf);
3284 }
3285
3286 return size;
3287 }
3288
3289 static DEVICE_ATTR_RW(mipi_reg);
3290 static DEVICE_ATTR_RO(edid_ram);
3291 static DEVICE_ATTR_RW(hdmi_reg);
3292
3293 static const struct attribute *it6616_attrs[] = {
3294 &dev_attr_hdmi_reg.attr,
3295 &dev_attr_mipi_reg.attr,
3296 &dev_attr_edid_ram.attr,
3297 NULL,
3298 };
3299
tx_5v_power_present(struct v4l2_subdev * sd)3300 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
3301 {
3302 struct it6616 *it6616 = to_it6616(sd);
3303
3304 return it6616_hdmi_is_5v_on(it6616);
3305 }
3306
no_signal(struct v4l2_subdev * sd)3307 static inline bool no_signal(struct v4l2_subdev *sd)
3308 {
3309 struct it6616 *it6616 = to_it6616(sd);
3310
3311 v4l2_dbg(1, debug, sd, "%s no signal:%d\n", __func__,
3312 it6616->nosignal);
3313
3314 return it6616->nosignal;
3315 }
3316
audio_present(struct v4l2_subdev * sd)3317 static inline bool audio_present(struct v4l2_subdev *sd)
3318 {
3319 struct it6616 *it6616 = to_it6616(sd);
3320
3321 return it6616->is_audio_present;
3322 }
3323
get_audio_sampling_rate(struct v4l2_subdev * sd)3324 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
3325 {
3326 struct it6616 *it6616 = to_it6616(sd);
3327
3328 if (no_signal(sd))
3329 return 0;
3330
3331 return code_to_rate_table[it6616->ainfo.force_sample_freq];
3332 }
3333
fps_calc(const struct v4l2_bt_timings * t)3334 static inline unsigned int fps_calc(const struct v4l2_bt_timings *t)
3335 {
3336 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
3337 return 0;
3338
3339 return DIV_ROUND_CLOSEST((unsigned int)t->pixelclock,
3340 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
3341 }
3342
it6616_rcv_supported_res(struct v4l2_subdev * sd,u32 width,u32 height)3343 static bool it6616_rcv_supported_res(struct v4l2_subdev *sd, u32 width,
3344 u32 height)
3345 {
3346 u32 i;
3347
3348 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
3349 if ((supported_modes[i].width == width) &&
3350 (supported_modes[i].height == height)) {
3351 break;
3352 }
3353 }
3354
3355 if (i == ARRAY_SIZE(supported_modes)) {
3356 v4l2_err(sd, "%s do not support res wxh: %dx%d\n", __func__,
3357 width, height);
3358 return false;
3359 } else {
3360 return true;
3361 }
3362 }
3363
it6616_get_detected_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)3364 static int it6616_get_detected_timings(struct v4l2_subdev *sd,
3365 struct v4l2_dv_timings *timings)
3366 {
3367 struct it6616 *it6616 = to_it6616(sd);
3368 struct v4l2_bt_timings *bt = &timings->bt;
3369 u32 fps, htotal, vtotal;
3370
3371 memset(timings, 0, sizeof(struct v4l2_dv_timings));
3372 it6616_hdmi_rx_get_video_info(it6616);
3373
3374 it6616->nosignal = false;
3375 it6616->is_audio_present = tx_5v_power_present(sd) ? true : false;
3376 timings->type = V4L2_DV_BT_656_1120;
3377 bt->interlaced = it6616->vinfo.interlaced;
3378 bt->width = it6616->vinfo.h_active;
3379 bt->height = it6616->vinfo.v_active;
3380 bt->vsync = it6616->vinfo.v_sync_w;
3381 bt->hsync = it6616->vinfo.h_sync_w;
3382 bt->pixelclock = it6616->vinfo.pclk * 1000;
3383 bt->hfrontporch = it6616->vinfo.h_front_porch;
3384 bt->vfrontporch = it6616->vinfo.v_front_porch;
3385 bt->hbackporch = it6616->vinfo.h_back_porch;
3386 bt->vbackporch = it6616->vinfo.v_back_porch;
3387 htotal = it6616->vinfo.h_total;
3388 vtotal = it6616->vinfo.v_total;
3389
3390 if (it6616->avi_if.colorspace == HDMI_COLORSPACE_YUV420) {
3391 bt->width = it6616->vinfo.h_active * 2;
3392 bt->hfrontporch = it6616->vinfo.h_front_porch * 2;
3393 bt->hbackporch = it6616->vinfo.h_back_porch * 2;
3394 bt->hsync = it6616->vinfo.h_sync_w * 2;
3395 htotal = it6616->vinfo.h_total * 2;
3396 }
3397
3398 fps = fps_calc(bt);
3399
3400 if (!it6616_rcv_supported_res(sd, bt->width, bt->height)) {
3401 it6616->nosignal = true;
3402 v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__);
3403 return -EINVAL;
3404 }
3405
3406 /* for interlaced res*/
3407 if (bt->interlaced) {
3408 bt->height *= 2;
3409 bt->il_vsync = bt->vsync + 1;
3410 }
3411
3412 v4l2_dbg(1, debug, sd, "act:%dx%d, total:%dx%d, pixclk:%d, fps:%d\n",
3413 bt->width, bt->height, htotal, vtotal, bt->pixelclock, fps);
3414 v4l2_dbg(1, debug, sd, "hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d\n",
3415 bt->hfrontporch, bt->hsync, bt->hbackporch,
3416 bt->vfrontporch, bt->vsync, bt->vbackporch);
3417 v4l2_dbg(1, debug, sd, "inerlaced:%d,\n", bt->interlaced);
3418
3419 return 0;
3420 }
3421
it6616_s_ctrl_detect_tx_5v(struct v4l2_subdev * sd)3422 static int it6616_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
3423 {
3424 struct it6616 *it6616 = to_it6616(sd);
3425
3426 return v4l2_ctrl_s_ctrl(it6616->detect_tx_5v_ctrl,
3427 tx_5v_power_present(sd));
3428 }
3429
it6616_s_ctrl_audio_sampling_rate(struct v4l2_subdev * sd)3430 static int it6616_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
3431 {
3432 struct it6616 *it6616 = to_it6616(sd);
3433
3434 return v4l2_ctrl_s_ctrl(it6616->audio_sampling_rate_ctrl,
3435 get_audio_sampling_rate(sd));
3436 }
3437
it6616_s_ctrl_audio_present(struct v4l2_subdev * sd)3438 static int it6616_s_ctrl_audio_present(struct v4l2_subdev *sd)
3439 {
3440 struct it6616 *it6616 = to_it6616(sd);
3441
3442 return v4l2_ctrl_s_ctrl(it6616->audio_present_ctrl,
3443 audio_present(sd));
3444 }
3445
it6616_update_controls(struct v4l2_subdev * sd)3446 static int it6616_update_controls(struct v4l2_subdev *sd)
3447 {
3448 int ret = 0;
3449
3450 ret |= it6616_s_ctrl_detect_tx_5v(sd);
3451 ret |= it6616_s_ctrl_audio_sampling_rate(sd);
3452 ret |= it6616_s_ctrl_audio_present(sd);
3453
3454 return ret;
3455 }
3456
it6616_match_dv_timings(const struct v4l2_dv_timings * t1,const struct v4l2_dv_timings * t2)3457 static bool it6616_match_dv_timings(const struct v4l2_dv_timings *t1,
3458 const struct v4l2_dv_timings *t2)
3459 {
3460 if (t1->type != t2->type || t1->type != V4L2_DV_BT_656_1120)
3461 return false;
3462 if (t1->bt.width == t2->bt.width &&
3463 t1->bt.height == t2->bt.height &&
3464 t1->bt.interlaced == t2->bt.interlaced &&
3465 t1->bt.hfrontporch == t2->bt.hfrontporch &&
3466 t1->bt.hsync == t2->bt.hsync &&
3467 t1->bt.hbackporch == t2->bt.hbackporch &&
3468 t1->bt.vfrontporch == t2->bt.vfrontporch &&
3469 t1->bt.vsync == t2->bt.vsync &&
3470 t1->bt.vbackporch == t2->bt.vbackporch &&
3471 (!t1->bt.interlaced ||
3472 (t1->bt.il_vfrontporch == t2->bt.il_vfrontporch &&
3473 t1->bt.il_vsync == t2->bt.il_vsync &&
3474 t1->bt.il_vbackporch == t2->bt.il_vbackporch)))
3475 return true;
3476 return false;
3477 }
3478
it6616_format_change(struct v4l2_subdev * sd)3479 static void it6616_format_change(struct v4l2_subdev *sd)
3480 {
3481 struct it6616 *it6616 = to_it6616(sd);
3482 struct v4l2_dv_timings timings;
3483 const struct v4l2_event it6616_ev_fmt = {
3484 .type = V4L2_EVENT_SOURCE_CHANGE,
3485 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
3486 };
3487
3488 it6616_get_detected_timings(sd, &timings);
3489
3490 if (!it6616_match_dv_timings(&it6616->timings, &timings)) {
3491 /* automatically set timing rather than set by user */
3492 it6616_s_dv_timings(sd, &timings);
3493 v4l2_print_dv_timings(sd->name,
3494 "Format_change: New format: ",
3495 &timings, false);
3496 if (sd->devnode)
3497 v4l2_subdev_notify_event(sd, &it6616_ev_fmt);
3498 }
3499 }
3500
it6616_isr(struct v4l2_subdev * sd,u32 status,bool * handled)3501 static int it6616_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
3502 {
3503 struct it6616 *it6616 = to_it6616(sd);
3504 static struct v4l2_dv_timings default_timing =
3505 V4L2_DV_BT_CEA_640X480P59_94;
3506
3507 if (tx_5v_power_present(sd)) {
3508 it6616_poll_threaded_handler(it6616);
3509 it6616_intp_threaded_handler(0, it6616);
3510 it6616_format_change(sd);
3511 } else {
3512 it6616_s_dv_timings(sd, &default_timing);
3513 it6616->nosignal = true;
3514 v4l2_dbg(1, debug, sd, "%s: HDMI unplug!!!\n", __func__);
3515 }
3516
3517 *handled = true;
3518
3519 return 0;
3520 }
3521
it6616_detect_hot_plug(struct v4l2_subdev * sd)3522 static void it6616_detect_hot_plug(struct v4l2_subdev *sd)
3523 {
3524 struct it6616 *it6616 = to_it6616(sd);
3525
3526 if (it6616->mipi_tx_video_stable && it6616_hdmi_is_5v_on(it6616))
3527 v4l2_ctrl_s_ctrl(it6616->detect_tx_5v_ctrl, 1);
3528 else
3529 v4l2_ctrl_s_ctrl(it6616->detect_tx_5v_ctrl, 0);
3530 }
3531
it6616_work_i2c_poll(struct work_struct * work)3532 static void it6616_work_i2c_poll(struct work_struct *work)
3533 {
3534 struct delayed_work *dwork = to_delayed_work(work);
3535 struct it6616 *it6616 = container_of(dwork,
3536 struct it6616, work_i2c_poll);
3537 bool handled;
3538
3539 it6616_isr(&it6616->sd, 0, &handled);
3540 it6616_detect_hot_plug(&it6616->sd);
3541 schedule_delayed_work(&it6616->work_i2c_poll,
3542 msecs_to_jiffies(POLL_INTERVAL_MS));
3543 }
3544
it6616_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)3545 static int it6616_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
3546 struct v4l2_event_subscription *sub)
3547 {
3548 switch (sub->type) {
3549 case V4L2_EVENT_SOURCE_CHANGE:
3550 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
3551 case V4L2_EVENT_CTRL:
3552 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
3553 default:
3554 return -EINVAL;
3555 }
3556 }
3557
it6616_g_input_status(struct v4l2_subdev * sd,u32 * status)3558 static int it6616_g_input_status(struct v4l2_subdev *sd, u32 *status)
3559 {
3560 *status = 0;
3561 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
3562
3563 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
3564
3565 return 0;
3566 }
3567
it6616_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)3568 static int it6616_s_dv_timings(struct v4l2_subdev *sd,
3569 struct v4l2_dv_timings *timings)
3570 {
3571 struct it6616 *it6616 = to_it6616(sd);
3572
3573 if (!timings)
3574 return -EINVAL;
3575
3576 if (debug)
3577 v4l2_print_dv_timings(sd->name, "s_dv_timings: ",
3578 timings, false);
3579
3580 if (v4l2_match_dv_timings(&it6616->timings, timings, 0, false)) {
3581 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
3582 return 0;
3583 }
3584
3585 if (!v4l2_valid_dv_timings(timings,
3586 &it6616_timings_cap, NULL, NULL)) {
3587 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
3588 return -ERANGE;
3589 }
3590
3591 it6616->timings = *timings;
3592
3593 return 0;
3594 }
3595
it6616_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)3596 static int it6616_g_dv_timings(struct v4l2_subdev *sd,
3597 struct v4l2_dv_timings *timings)
3598 {
3599 struct it6616 *it6616 = to_it6616(sd);
3600
3601 *timings = it6616->timings;
3602
3603 return 0;
3604 }
3605
it6616_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)3606 static int it6616_enum_dv_timings(struct v4l2_subdev *sd,
3607 struct v4l2_enum_dv_timings *timings)
3608 {
3609 if (timings->pad != 0)
3610 return -EINVAL;
3611
3612 return v4l2_enum_dv_timings_cap(timings,
3613 &it6616_timings_cap, NULL, NULL);
3614 }
3615
it6616_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)3616 static int it6616_query_dv_timings(struct v4l2_subdev *sd,
3617 struct v4l2_dv_timings *timings)
3618 {
3619 struct it6616 *it6616 = to_it6616(sd);
3620
3621 *timings = it6616->timings;
3622 if (debug)
3623 v4l2_print_dv_timings(sd->name,
3624 "query_dv_timings: ", timings, false);
3625
3626 if (!v4l2_valid_dv_timings(timings, &it6616_timings_cap, NULL,
3627 NULL)) {
3628 v4l2_dbg(1, debug, sd, "%s: timings out of range\n",
3629 __func__);
3630
3631 return -ERANGE;
3632 }
3633
3634 return 0;
3635 }
3636
it6616_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)3637 static int it6616_dv_timings_cap(struct v4l2_subdev *sd,
3638 struct v4l2_dv_timings_cap *cap)
3639 {
3640 if (cap->pad != 0)
3641 return -EINVAL;
3642
3643 *cap = it6616_timings_cap;
3644
3645 return 0;
3646 }
3647
it6616_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)3648 static int it6616_g_mbus_config(struct v4l2_subdev *sd,
3649 unsigned int pad, struct v4l2_mbus_config *cfg)
3650 {
3651 struct it6616 *it6616 = to_it6616(sd);
3652
3653 cfg->type = V4L2_MBUS_CSI2_DPHY;
3654 cfg->flags = V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
3655 V4L2_MBUS_CSI2_CHANNEL_0;
3656
3657 switch (it6616->csi_lanes_in_use) {
3658 case 1:
3659 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
3660 break;
3661 case 2:
3662 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
3663 break;
3664 case 3:
3665 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
3666 break;
3667 case 4:
3668 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
3669 break;
3670
3671 default:
3672 return -EINVAL;
3673 }
3674
3675 return 0;
3676 }
3677
__it6616_start_stream(struct it6616 * it6616)3678 static int __it6616_start_stream(struct it6616 *it6616)
3679 {
3680 it6616_mipitx_output_disable(it6616);
3681 usleep_range(1000, 2000);
3682 it6616_mipi_tx_output_enable(it6616);
3683
3684 return 0;
3685 }
3686
__it6616_stop_stream(struct it6616 * it6616)3687 static int __it6616_stop_stream(struct it6616 *it6616)
3688 {
3689 it6616_mipitx_output_disable(it6616);
3690
3691 return 0;
3692 }
3693
it6616_s_stream(struct v4l2_subdev * sd,int on)3694 static int it6616_s_stream(struct v4l2_subdev *sd, int on)
3695 {
3696 struct it6616 *it6616 = to_it6616(sd);
3697 struct i2c_client *client = it6616->i2c_client;
3698 int ret = 0;
3699
3700 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
3701 it6616->cur_mode->width,
3702 it6616->cur_mode->height,
3703 DIV_ROUND_CLOSEST(it6616->cur_mode->max_fps.denominator,
3704 it6616->cur_mode->max_fps.numerator));
3705
3706 mutex_lock(&it6616->confctl_mutex);
3707 on = !!on;
3708
3709 if (on) {
3710 ret = __it6616_start_stream(it6616);
3711 if (ret) {
3712 dev_err(it6616->dev, "Failed to start it6616 stream\n");
3713 goto unlock_and_return;
3714 }
3715 } else {
3716 __it6616_stop_stream(it6616);
3717 }
3718
3719
3720 unlock_and_return:
3721 mutex_unlock(&it6616->confctl_mutex);
3722 return 0;
3723 }
3724
it6616_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)3725 static int it6616_enum_mbus_code(struct v4l2_subdev *sd,
3726 struct v4l2_subdev_pad_config *cfg,
3727 struct v4l2_subdev_mbus_code_enum *code)
3728 {
3729 switch (code->index) {
3730 case 0:
3731 code->code = IT6616_MEDIA_BUS_FMT;
3732 break;
3733
3734 default:
3735 return -EINVAL;
3736 }
3737
3738 return 0;
3739 }
3740
it6616_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)3741 static int it6616_enum_frame_sizes(struct v4l2_subdev *sd,
3742 struct v4l2_subdev_pad_config *cfg,
3743 struct v4l2_subdev_frame_size_enum *fse)
3744 {
3745 if (fse->index >= ARRAY_SIZE(supported_modes))
3746 return -EINVAL;
3747
3748 if (fse->code != IT6616_MEDIA_BUS_FMT)
3749 return -EINVAL;
3750
3751 fse->min_width = supported_modes[fse->index].width;
3752 fse->max_width = supported_modes[fse->index].width;
3753 fse->max_height = supported_modes[fse->index].height;
3754 fse->min_height = supported_modes[fse->index].height;
3755
3756 return 0;
3757 }
3758
it6616_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)3759 static int it6616_get_fmt(struct v4l2_subdev *sd,
3760 struct v4l2_subdev_pad_config *cfg,
3761 struct v4l2_subdev_format *format)
3762 {
3763 struct it6616 *it6616 = to_it6616(sd);
3764
3765 mutex_lock(&it6616->confctl_mutex);
3766 format->format.code = it6616->mbus_fmt_code;
3767 format->format.width = it6616->timings.bt.width;
3768 format->format.height = it6616->timings.bt.height;
3769 format->format.field =
3770 it6616->timings.bt.interlaced ?
3771 V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
3772 format->format.colorspace = V4L2_COLORSPACE_SRGB;
3773 mutex_unlock(&it6616->confctl_mutex);
3774
3775 v4l2_dbg(1, debug, sd, "%s: fmt code:%d, w:%d, h:%d, field code:%d\n",
3776 __func__, format->format.code, format->format.width,
3777 format->format.height, format->format.field);
3778
3779 return 0;
3780 }
3781
it6616_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)3782 static int it6616_enum_frame_interval(struct v4l2_subdev *sd,
3783 struct v4l2_subdev_pad_config *cfg,
3784 struct v4l2_subdev_frame_interval_enum *fie)
3785 {
3786 if (fie->index >= ARRAY_SIZE(supported_modes))
3787 return -EINVAL;
3788
3789 fie->code = IT6616_MEDIA_BUS_FMT;
3790
3791 fie->width = supported_modes[fie->index].width;
3792 fie->height = supported_modes[fie->index].height;
3793 fie->interval = supported_modes[fie->index].max_fps;
3794
3795 return 0;
3796 }
3797
it6616_get_reso_dist(const struct it6616_mode * mode,struct v4l2_mbus_framefmt * framefmt)3798 static int it6616_get_reso_dist(const struct it6616_mode *mode,
3799 struct v4l2_mbus_framefmt *framefmt)
3800 {
3801 return abs(mode->width - framefmt->width) +
3802 abs(mode->height - framefmt->height);
3803 }
3804
3805 static const struct it6616_mode *
it6616_find_best_fit(struct v4l2_subdev_format * fmt)3806 it6616_find_best_fit(struct v4l2_subdev_format *fmt)
3807 {
3808 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
3809 int dist;
3810 int cur_best_fit = 0;
3811 int cur_best_fit_dist = -1;
3812 unsigned int i;
3813
3814 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
3815 dist = it6616_get_reso_dist(&supported_modes[i], framefmt);
3816 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
3817 cur_best_fit_dist = dist;
3818 cur_best_fit = i;
3819 }
3820 }
3821
3822 return &supported_modes[cur_best_fit];
3823 }
3824
it6616_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)3825 static int it6616_set_fmt(struct v4l2_subdev *sd,
3826 struct v4l2_subdev_pad_config *cfg,
3827 struct v4l2_subdev_format *format)
3828 {
3829 struct it6616 *it6616 = to_it6616(sd);
3830 const struct it6616_mode *mode;
3831
3832 /* is overwritten by get_fmt */
3833 u32 code = format->format.code;
3834 int ret = it6616_get_fmt(sd, cfg, format);
3835
3836 format->format.code = code;
3837
3838 if (ret)
3839 return ret;
3840
3841 switch (code) {
3842 case IT6616_MEDIA_BUS_FMT:
3843 break;
3844
3845 default:
3846 return -EINVAL;
3847 }
3848
3849 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
3850 return 0;
3851
3852 it6616->mbus_fmt_code = format->format.code;
3853 mode = it6616_find_best_fit(format);
3854 it6616->cur_mode = mode;
3855
3856 return 0;
3857 }
3858
it6616_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)3859 static int it6616_g_frame_interval(struct v4l2_subdev *sd,
3860 struct v4l2_subdev_frame_interval *fi)
3861 {
3862 struct it6616 *it6616 = to_it6616(sd);
3863 const struct it6616_mode *mode = it6616->cur_mode;
3864
3865 mutex_lock(&it6616->confctl_mutex);
3866 fi->interval = mode->max_fps;
3867 mutex_unlock(&it6616->confctl_mutex);
3868
3869 return 0;
3870 }
3871
it6616_get_module_inf(struct it6616 * it6616,struct rkmodule_inf * inf)3872 static void it6616_get_module_inf(struct it6616 *it6616,
3873 struct rkmodule_inf *inf)
3874 {
3875 memset(inf, 0, sizeof(*inf));
3876 strscpy(inf->base.sensor, IT6616_NAME, sizeof(inf->base.sensor));
3877 strscpy(inf->base.module, it6616->module_name, sizeof(inf->base.module));
3878 strscpy(inf->base.lens, it6616->len_name, sizeof(inf->base.lens));
3879 }
3880
it6616_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)3881 static long it6616_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3882 {
3883 struct it6616 *it6616 = to_it6616(sd);
3884 long ret = 0;
3885
3886 switch (cmd) {
3887 case RKMODULE_GET_MODULE_INFO:
3888 it6616_get_module_inf(it6616, (struct rkmodule_inf *)arg);
3889 break;
3890 case RKMODULE_GET_HDMI_MODE:
3891 *(int *)arg = RKMODULE_HDMIIN_MODE;
3892 break;
3893 default:
3894 ret = -ENOIOCTLCMD;
3895 break;
3896 }
3897
3898 return ret;
3899 }
3900
it6616_s_power(struct v4l2_subdev * sd,int on)3901 static int it6616_s_power(struct v4l2_subdev *sd, int on)
3902 {
3903 struct it6616 *it6616 = to_it6616(sd);
3904 int ret = 0;
3905
3906 mutex_lock(&it6616->confctl_mutex);
3907
3908 if (it6616->power_on == !!on)
3909 goto unlock_and_return;
3910
3911 if (on)
3912 it6616->power_on = true;
3913 else
3914 it6616->power_on = false;
3915
3916 unlock_and_return:
3917 mutex_unlock(&it6616->confctl_mutex);
3918
3919 return ret;
3920 }
3921
3922 #ifdef CONFIG_COMPAT
it6616_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)3923 static long it6616_compat_ioctl32(struct v4l2_subdev *sd,
3924 unsigned int cmd, unsigned long arg)
3925 {
3926 void __user *up = compat_ptr(arg);
3927 struct rkmodule_inf *inf;
3928 long ret;
3929 int *seq;
3930
3931 switch (cmd) {
3932 case RKMODULE_GET_MODULE_INFO:
3933 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
3934 if (!inf) {
3935 ret = -ENOMEM;
3936 return ret;
3937 }
3938
3939 ret = it6616_ioctl(sd, cmd, inf);
3940 if (!ret) {
3941 ret = copy_to_user(up, inf, sizeof(*inf));
3942 if (ret)
3943 ret = -EFAULT;
3944 }
3945 kfree(inf);
3946 break;
3947 case RKMODULE_GET_HDMI_MODE:
3948 seq = kzalloc(sizeof(*seq), GFP_KERNEL);
3949 if (!seq) {
3950 ret = -ENOMEM;
3951 return ret;
3952 }
3953
3954 ret = it6616_ioctl(sd, cmd, seq);
3955 if (!ret) {
3956 ret = copy_to_user(up, seq, sizeof(*seq));
3957 if (ret)
3958 ret = -EFAULT;
3959 }
3960 kfree(seq);
3961 break;
3962 default:
3963 ret = -ENOIOCTLCMD;
3964 break;
3965 }
3966
3967 return ret;
3968 }
3969 #endif
3970
3971 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
it6616_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)3972 static int it6616_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
3973 {
3974 struct it6616 *it6616 = to_it6616(sd);
3975 struct v4l2_mbus_framefmt *try_fmt =
3976 v4l2_subdev_get_try_format(sd, fh->pad, 0);
3977 const struct it6616_mode *def_mode = &supported_modes[0];
3978
3979 mutex_lock(&it6616->confctl_mutex);
3980 /* Initialize try_fmt */
3981 try_fmt->width = def_mode->width;
3982 try_fmt->height = def_mode->height;
3983 try_fmt->code = IT6616_MEDIA_BUS_FMT;
3984 try_fmt->field = V4L2_FIELD_NONE;
3985 mutex_unlock(&it6616->confctl_mutex);
3986
3987 return 0;
3988 }
3989 #endif
3990
3991 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
3992 static const struct v4l2_subdev_internal_ops it6616_internal_ops = {
3993 .open = it6616_open,
3994 };
3995 #endif
3996
3997 static const struct v4l2_subdev_core_ops it6616_core_ops = {
3998 .s_power = it6616_s_power,
3999 .interrupt_service_routine = it6616_isr,
4000 .subscribe_event = it6616_subscribe_event,
4001 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
4002 .ioctl = it6616_ioctl,
4003 #ifdef CONFIG_COMPAT
4004 .compat_ioctl32 = it6616_compat_ioctl32,
4005 #endif
4006 };
4007
4008 static const struct v4l2_subdev_video_ops it6616_video_ops = {
4009 .g_input_status = it6616_g_input_status,
4010 .s_dv_timings = it6616_s_dv_timings,
4011 .g_dv_timings = it6616_g_dv_timings,
4012 .query_dv_timings = it6616_query_dv_timings,
4013 .s_stream = it6616_s_stream,
4014 .g_frame_interval = it6616_g_frame_interval,
4015 };
4016
4017 static const struct v4l2_subdev_pad_ops it6616_pad_ops = {
4018 .enum_mbus_code = it6616_enum_mbus_code,
4019 .enum_frame_size = it6616_enum_frame_sizes,
4020 .enum_frame_interval = it6616_enum_frame_interval,
4021 .set_fmt = it6616_set_fmt,
4022 .get_fmt = it6616_get_fmt,
4023 .enum_dv_timings = it6616_enum_dv_timings,
4024 .dv_timings_cap = it6616_dv_timings_cap,
4025 .get_mbus_config = it6616_g_mbus_config,
4026 };
4027
4028 static const struct v4l2_subdev_ops it6616_ops = {
4029 .core = &it6616_core_ops,
4030 .video = &it6616_video_ops,
4031 .pad = &it6616_pad_ops,
4032 };
4033
4034 static const struct v4l2_ctrl_config it6616_ctrl_audio_sampling_rate = {
4035 .id = RK_V4L2_CID_AUDIO_SAMPLING_RATE,
4036 .name = "Audio sampling rate",
4037 .type = V4L2_CTRL_TYPE_INTEGER,
4038 .min = 0,
4039 .max = 768000,
4040 .step = 1,
4041 .def = 0,
4042 .flags = V4L2_CTRL_FLAG_READ_ONLY,
4043 };
4044
4045 static const struct v4l2_ctrl_config it6616_ctrl_audio_present = {
4046 .id = RK_V4L2_CID_AUDIO_PRESENT,
4047 .name = "Audio present",
4048 .type = V4L2_CTRL_TYPE_BOOLEAN,
4049 .min = 0,
4050 .max = 1,
4051 .step = 1,
4052 .def = 0,
4053 .flags = V4L2_CTRL_FLAG_READ_ONLY,
4054 };
4055
it6616_reset(struct it6616 * it6616)4056 static void it6616_reset(struct it6616 *it6616)
4057 {
4058 gpiod_set_value(it6616->reset_gpio, 0);
4059 usleep_range(2000, 2100);
4060 gpiod_set_value(it6616->reset_gpio, 1);
4061 usleep_range(120*1000, 121*1000);
4062 gpiod_set_value(it6616->reset_gpio, 0);
4063 usleep_range(300*1000, 310*1000);
4064 }
4065
it6616_init_v4l2_ctrls(struct it6616 * it6616)4066 static int it6616_init_v4l2_ctrls(struct it6616 *it6616)
4067 {
4068 struct v4l2_subdev *sd;
4069 int ret;
4070
4071 sd = &it6616->sd;
4072 ret = v4l2_ctrl_handler_init(&it6616->hdl, 5);
4073 if (ret)
4074 return ret;
4075
4076 it6616->link_freq = v4l2_ctrl_new_int_menu(&it6616->hdl, NULL,
4077 V4L2_CID_LINK_FREQ,
4078 ARRAY_SIZE(link_freq_menu_items) - 1, 0,
4079 link_freq_menu_items);
4080 it6616->pixel_rate = v4l2_ctrl_new_std(&it6616->hdl, NULL,
4081 V4L2_CID_PIXEL_RATE,
4082 0, IT6616_PIXEL_RATE, 1, IT6616_PIXEL_RATE);
4083
4084 it6616->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&it6616->hdl,
4085 NULL, V4L2_CID_DV_RX_POWER_PRESENT,
4086 0, 1, 0, 0);
4087
4088 it6616->audio_sampling_rate_ctrl =
4089 v4l2_ctrl_new_custom(&it6616->hdl,
4090 &it6616_ctrl_audio_sampling_rate, NULL);
4091 it6616->audio_present_ctrl = v4l2_ctrl_new_custom(&it6616->hdl,
4092 &it6616_ctrl_audio_present, NULL);
4093
4094 sd->ctrl_handler = &it6616->hdl;
4095 if (it6616->hdl.error) {
4096 ret = it6616->hdl.error;
4097 v4l2_err(sd, "cfg v4l2 ctrls failed! ret:%d\n", ret);
4098 return ret;
4099 }
4100
4101 __v4l2_ctrl_s_ctrl(it6616->link_freq, link_freq_menu_items[0]);
4102 __v4l2_ctrl_s_ctrl_int64(it6616->pixel_rate, IT6616_PIXEL_RATE);
4103
4104 if (it6616_update_controls(sd)) {
4105 ret = -ENODEV;
4106 v4l2_err(sd, "update v4l2 ctrls failed! ret:%d\n", ret);
4107 return ret;
4108 }
4109
4110 return 0;
4111 }
4112
4113 #ifdef CONFIG_OF
it6616_probe_of(struct it6616 * it6616)4114 static int it6616_probe_of(struct it6616 *it6616)
4115 {
4116 struct device *dev = &it6616->i2c_client->dev;
4117 struct device_node *node = dev->of_node;
4118 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
4119 struct device_node *ep;
4120 int ret;
4121
4122 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
4123 &it6616->module_index);
4124 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
4125 &it6616->module_facing);
4126 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
4127 &it6616->module_name);
4128 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
4129 &it6616->len_name);
4130 if (ret) {
4131 dev_err(dev, "could not get module information!\n");
4132 return -EINVAL;
4133 }
4134
4135 it6616->power_gpio = devm_gpiod_get_optional(dev, "power",
4136 GPIOD_OUT_LOW);
4137 if (IS_ERR(it6616->power_gpio)) {
4138 dev_err(dev, "failed to get power gpio\n");
4139 ret = PTR_ERR(it6616->power_gpio);
4140 return ret;
4141 }
4142
4143 it6616->reset_gpio = devm_gpiod_get_optional(dev, "reset",
4144 GPIOD_OUT_HIGH);
4145 if (IS_ERR(it6616->reset_gpio)) {
4146 dev_err(dev, "failed to get reset gpio\n");
4147 ret = PTR_ERR(it6616->reset_gpio);
4148 return ret;
4149 }
4150
4151 ep = of_graph_get_next_endpoint(dev->of_node, NULL);
4152 if (!ep) {
4153 dev_err(dev, "missing endpoint node\n");
4154 return -EINVAL;
4155 }
4156
4157 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
4158 if (ret) {
4159 dev_err(dev, "failed to parse endpoint\n");
4160 goto put_node;
4161 }
4162
4163 if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY ||
4164 endpoint.bus.mipi_csi2.num_data_lanes == 0) {
4165 dev_err(dev, "missing CSI-2 properties in endpoint\n");
4166 ret = -EINVAL;
4167 goto free_endpoint;
4168 }
4169
4170 it6616->xvclk = devm_clk_get(dev, "xvclk");
4171 if (IS_ERR(it6616->xvclk)) {
4172 dev_err(dev, "failed to get xvclk\n");
4173 ret = -EINVAL;
4174 goto free_endpoint;
4175 }
4176
4177 ret = clk_prepare_enable(it6616->xvclk);
4178 if (ret) {
4179 dev_err(dev, "Failed! to enable xvclk\n");
4180 goto free_endpoint;
4181 }
4182
4183 it6616->csi_lanes_in_use = endpoint.bus.mipi_csi2.num_data_lanes;
4184 it6616->bus = endpoint.bus.mipi_csi2;
4185
4186 gpiod_set_value(it6616->power_gpio, 1);
4187 it6616_reset(it6616);
4188
4189 ret = 0;
4190
4191 free_endpoint:
4192 v4l2_fwnode_endpoint_free(&endpoint);
4193 put_node:
4194 of_node_put(ep);
4195 return ret;
4196 }
4197 #else
it6616_probe_of(struct it6616 * state)4198 static inline int it6616_probe_of(struct it6616 *state)
4199 {
4200 return -ENODEV;
4201 }
4202 #endif
4203
audio_present_show(struct device * dev,struct device_attribute * attr,char * buf)4204 static ssize_t audio_present_show(struct device *dev,
4205 struct device_attribute *attr, char *buf)
4206 {
4207 struct it6616 *it6616 = g_it6616;
4208
4209 return snprintf(buf, PAGE_SIZE, "%d\n",
4210 tx_5v_power_present(&it6616->sd) ? 1 : 0);
4211 }
4212
audio_rate_show(struct device * dev,struct device_attribute * attr,char * buf)4213 static ssize_t audio_rate_show(struct device *dev,
4214 struct device_attribute *attr, char *buf)
4215 {
4216 struct it6616 *it6616 = g_it6616;
4217
4218 return snprintf(buf, PAGE_SIZE, "%d\n",
4219 code_to_rate_table[it6616->ainfo.force_sample_freq]);
4220 }
4221
4222 static DEVICE_ATTR_RO(audio_present);
4223 static DEVICE_ATTR_RO(audio_rate);
4224
it6616_create_class_attr(struct it6616 * it6616)4225 static int it6616_create_class_attr(struct it6616 *it6616)
4226 {
4227 int ret = 0;
4228
4229 it6616->hdmirx_class = class_create(THIS_MODULE, "hdmirx_it6616");
4230 if (IS_ERR(it6616->hdmirx_class)) {
4231 ret = -ENOMEM;
4232 dev_err(it6616->dev, "failed to create hdmirx_it6616 class!\n");
4233 return ret;
4234 }
4235
4236 it6616->classdev = device_create(it6616->hdmirx_class, NULL,
4237 MKDEV(0, 0), NULL, "hdmirx_it6616");
4238 if (IS_ERR(it6616->classdev)) {
4239 ret = PTR_ERR(it6616->classdev);
4240 dev_err(it6616->dev, "Failed to create device\n");
4241 goto err1;
4242 }
4243
4244 ret = device_create_file(it6616->classdev,
4245 &dev_attr_audio_present);
4246 if (ret) {
4247 dev_err(it6616->dev, "failed to create attr audio_present!\n");
4248 goto err1;
4249 }
4250
4251 ret = device_create_file(it6616->classdev,
4252 &dev_attr_audio_rate);
4253 if (ret) {
4254 dev_err(it6616->dev,
4255 "failed to create attr audio_rate!\n");
4256 goto err;
4257 }
4258
4259 return ret;
4260
4261 err:
4262 device_remove_file(it6616->classdev, &dev_attr_audio_present);
4263 err1:
4264 class_destroy(it6616->hdmirx_class);
4265 return ret;
4266 }
4267
it6616_remove_class_attr(struct it6616 * it6616)4268 static void it6616_remove_class_attr(struct it6616 *it6616)
4269 {
4270 device_remove_file(it6616->classdev, &dev_attr_audio_rate);
4271 device_remove_file(it6616->classdev, &dev_attr_audio_present);
4272 class_destroy(it6616->hdmirx_class);
4273 }
4274
it6616_probe(struct i2c_client * client,const struct i2c_device_id * id)4275 static int it6616_probe(struct i2c_client *client,
4276 const struct i2c_device_id *id)
4277 {
4278 struct it6616 *it6616;
4279 struct v4l2_subdev *sd;
4280 struct device *dev = &client->dev;
4281 char facing[2];
4282 int err = 0;
4283
4284 dev_info(dev, "driver version: %02x.%02x.%02x",
4285 DRIVER_VERSION >> 16,
4286 (DRIVER_VERSION & 0xff00) >> 8,
4287 DRIVER_VERSION & 0x00ff);
4288
4289 it6616 = devm_kzalloc(dev, sizeof(struct it6616), GFP_KERNEL);
4290 if (!it6616)
4291 return -ENOMEM;
4292
4293 sd = &it6616->sd;
4294 it6616->hdmi_i2c = client;
4295 it6616->mipi_i2c = i2c_new_dummy_device(client->adapter,
4296 I2C_ADR_MIPI >> 1);
4297
4298 if (!it6616->mipi_i2c)
4299 return -EIO;
4300
4301 it6616->edid_i2c = i2c_new_dummy_device(client->adapter,
4302 I2C_ADR_EDID >> 1);
4303
4304 if (!it6616->edid_i2c)
4305 goto unregister_mipi_i2c;
4306
4307 it6616->hdmi_regmap = devm_regmap_init_i2c(client,
4308 &it6616_hdmi_regmap_config);
4309 if (IS_ERR(it6616->hdmi_i2c)) {
4310 err = PTR_ERR(it6616->hdmi_i2c);
4311 goto unregister_edid_i2c;
4312 }
4313
4314 it6616->mipi_regmap = devm_regmap_init_i2c(it6616->mipi_i2c,
4315 &it6616_mipi_regmap_config);
4316 if (IS_ERR(it6616->mipi_regmap)) {
4317 err = PTR_ERR(it6616->mipi_regmap);
4318 goto unregister_edid_i2c;
4319 }
4320
4321 it6616->edid_regmap = devm_regmap_init_i2c(it6616->edid_i2c,
4322 &it6616_edid_regmap_config);
4323 if (IS_ERR(it6616->edid_regmap)) {
4324 err = PTR_ERR(it6616->edid_regmap);
4325 goto unregister_edid_i2c;
4326 }
4327
4328 it6616->dev = dev;
4329 it6616->cur_mode = &supported_modes[0];
4330 it6616->i2c_client = client;
4331 it6616->mbus_fmt_code = IT6616_MEDIA_BUS_FMT;
4332 err = it6616_probe_of(it6616);
4333 if (err) {
4334 v4l2_err(sd, "it6616_parse_of failed! err:%d\n", err);
4335 return err;
4336 }
4337 it6616_reset(it6616);
4338
4339 mutex_init(&it6616->confctl_mutex);
4340
4341 err = it6616_initial(it6616);
4342 if (err) {
4343 dev_err(dev, "it6616_initial failed: %d", err);
4344 err = -ENODEV;
4345 goto unregister_edid_i2c;
4346 }
4347
4348 err = sysfs_create_files(&client->dev.kobj, it6616_attrs);
4349 if (err) {
4350 dev_err(dev, "sysfs_create_files failed: %d", err);
4351 goto unregister_edid_i2c;
4352 }
4353
4354 i2c_set_clientdata(client, it6616);
4355 usleep_range(3000, 6000);
4356
4357 err = it6616_init_v4l2_ctrls(it6616);
4358 if (err)
4359 goto err_free_hdl;
4360
4361 client->flags |= I2C_CLIENT_SCCB;
4362 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
4363 v4l2_i2c_subdev_init(sd, client, &it6616_ops);
4364 sd->internal_ops = &it6616_internal_ops;
4365 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
4366 #endif
4367
4368 #if defined(CONFIG_MEDIA_CONTROLLER)
4369 it6616->pad.flags = MEDIA_PAD_FL_SOURCE;
4370 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
4371 err = media_entity_pads_init(&sd->entity, 1, &it6616->pad);
4372 if (err < 0) {
4373 v4l2_err(sd, "media entity init failed! err:%d\n", err);
4374 goto err_free_hdl;
4375 }
4376 #endif
4377 memset(facing, 0, sizeof(facing));
4378 if (strcmp(it6616->module_facing, "back") == 0)
4379 facing[0] = 'b';
4380 else
4381 facing[0] = 'f';
4382
4383 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
4384 it6616->module_index, facing,
4385 IT6616_NAME, dev_name(sd->dev));
4386 err = v4l2_async_register_subdev_sensor_common(sd);
4387 if (err < 0) {
4388 v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
4389 goto err_clean_entity;
4390 }
4391
4392 err = it6616_create_class_attr(it6616);
4393 if (err) {
4394 dev_err(it6616->dev, "create class attr failed! err:%d\n", err);
4395 return -ENODEV;
4396 }
4397
4398 INIT_DELAYED_WORK(&it6616->work_i2c_poll, it6616_work_i2c_poll);
4399 schedule_delayed_work(&it6616->work_i2c_poll, msecs_to_jiffies(500));
4400 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
4401 if (err) {
4402 v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
4403 goto err_work_queues;
4404 }
4405
4406 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
4407 client->addr << 1, client->adapter->name);
4408 g_it6616 = it6616;
4409
4410 return 0;
4411
4412 err_work_queues:
4413 cancel_delayed_work_sync(&it6616->work_i2c_poll);
4414 err_clean_entity:
4415 #if defined(CONFIG_MEDIA_CONTROLLER)
4416 media_entity_cleanup(&sd->entity);
4417 #endif
4418 err_free_hdl:
4419 v4l2_ctrl_handler_free(&it6616->hdl);
4420 mutex_destroy(&it6616->confctl_mutex);
4421 unregister_edid_i2c:
4422 i2c_unregister_device(it6616->edid_i2c);
4423 unregister_mipi_i2c:
4424 i2c_unregister_device(it6616->mipi_i2c);
4425
4426 return err;
4427 }
4428
it6616_remove(struct i2c_client * client)4429 static int it6616_remove(struct i2c_client *client)
4430 {
4431 struct v4l2_subdev *sd = i2c_get_clientdata(client);
4432 struct it6616 *it6616 = to_it6616(sd);
4433
4434 cancel_delayed_work_sync(&it6616->work_i2c_poll);
4435 it6616_remove_class_attr(it6616);
4436 v4l2_async_unregister_subdev(sd);
4437 v4l2_device_unregister_subdev(sd);
4438 #if defined(CONFIG_MEDIA_CONTROLLER)
4439 media_entity_cleanup(&sd->entity);
4440 #endif
4441 v4l2_ctrl_handler_free(&it6616->hdl);
4442 sysfs_remove_files(&client->dev.kobj, it6616_attrs);
4443 mutex_destroy(&it6616->confctl_mutex);
4444
4445 i2c_unregister_device(it6616->mipi_i2c);
4446 i2c_unregister_device(it6616->edid_i2c);
4447 clk_disable_unprepare(it6616->xvclk);
4448
4449 return 0;
4450 }
4451
4452 #if IS_ENABLED(CONFIG_OF)
4453 static const struct of_device_id it6616_of_match[] = {
4454 { .compatible = "ite,it6616" },
4455 {},
4456 };
4457 MODULE_DEVICE_TABLE(of, it6616_of_match);
4458 #endif
4459
4460 static struct i2c_driver it6616_driver = {
4461 .driver = {
4462 .name = IT6616_NAME,
4463 .of_match_table = of_match_ptr(it6616_of_match),
4464 },
4465 .probe = it6616_probe,
4466 .remove = it6616_remove,
4467 };
4468
it6616_driver_init(void)4469 static int __init it6616_driver_init(void)
4470 {
4471 return i2c_add_driver(&it6616_driver);
4472 }
4473
it6616_driver_exit(void)4474 static void __exit it6616_driver_exit(void)
4475 {
4476 i2c_del_driver(&it6616_driver);
4477 }
4478
4479 device_initcall_sync(it6616_driver_init);
4480 module_exit(it6616_driver_exit);
4481
4482 MODULE_DESCRIPTION("ITE it6616 HDMI to CSI-2 bridge driver");
4483 MODULE_AUTHOR("Jianwei Fan <jianwei.fan@rock-chips.com>");
4484 MODULE_AUTHOR("Kenneth Hung<Kenneth.Hung@ite.com.tw>");
4485 MODULE_LICENSE("GPL");
4486