1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx586 driver
4 *
5 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
6 * V0.0X01.0X00 init version.
7 */
8
9 //#define DEBUG
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/sysfs.h>
19 #include <linux/slab.h>
20 #include <linux/version.h>
21 #include <linux/rk-camera-module.h>
22 #include <media/media-entity.h>
23 #include <media/v4l2-async.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-subdev.h>
26 #include <media/v4l2-fwnode.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/of.h>
29 #include <linux/of_device.h>
30 #include <linux/of_graph.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_gpio.h>
33 #include <linux/mfd/syscon.h>
34 #include <linux/rk-preisp.h>
35 #include "otp_eeprom.h"
36
37 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
38
39 #ifndef V4L2_CID_DIGITAL_GAIN
40 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
41 #endif
42
43 #define IMX586_LINK_FREQ_400 400000000 // 800Mbps per lane
44 #define IMX586_LINK_FREQ_625 625000000 // 1250Mbps per lane
45
46 #define IMX586_LANES 4
47
48 #define PIXEL_RATE_WITH_848M_10BIT (IMX586_LINK_FREQ_400 * 2 / 10 * 4)
49 #define PIXEL_RATE_WITH_848M_12BIT (IMX586_LINK_FREQ_400 * 2 / 12 * 4)
50
51 #define IMX586_XVCLK_FREQ 24000000
52
53 #define CHIP_ID 0x0586
54 #define IMX586_REG_CHIP_ID_H 0x0016
55 #define IMX586_REG_CHIP_ID_L 0x0017
56
57 #define IMX586_REG_CTRL_MODE 0x0100
58 #define IMX586_MODE_SW_STANDBY 0x0
59 #define IMX586_MODE_STREAMING 0x1
60
61 #define IMX586_REG_EXPOSURE_H 0x0202
62 #define IMX586_REG_EXPOSURE_L 0x0203
63 #define IMX586_EXPOSURE_MIN 2
64 #define IMX586_EXPOSURE_STEP 1
65 #define IMX586_VTS_MAX 0x7fff
66
67 #define IMX586_REG_GAIN_H 0x0204
68 #define IMX586_REG_GAIN_L 0x0205
69 #define IMX586_GAIN_MIN 0x10
70 #define IMX586_GAIN_MAX 0x400
71 #define IMX586_GAIN_STEP 1
72 #define IMX586_GAIN_DEFAULT 0x80
73
74 #define IMX586_REG_DGAIN 0x3130
75 #define IMX586_DGAIN_MODE BIT(0)
76 #define IMX586_REG_DGAINGR_H 0x020e
77 #define IMX586_REG_DGAINGR_L 0x020f
78 #define IMX586_REG_DGAINR_H 0x0210
79 #define IMX586_REG_DGAINR_L 0x0211
80 #define IMX586_REG_DGAINB_H 0x0212
81 #define IMX586_REG_DGAINB_L 0x0213
82 #define IMX586_REG_DGAINGB_H 0x0214
83 #define IMX586_REG_DGAINGB_L 0x0215
84 #define IMX586_REG_GAIN_GLOBAL_H 0x3ffc
85 #define IMX586_REG_GAIN_GLOBAL_L 0x3ffd
86
87 //#define IMX586_REG_TEST_PATTERN_H 0x0600
88 #define IMX586_REG_TEST_PATTERN 0x0601
89 #define IMX586_TEST_PATTERN_ENABLE 0x1
90 #define IMX586_TEST_PATTERN_DISABLE 0x0
91
92 #define IMX586_REG_VTS_H 0x0340
93 #define IMX586_REG_VTS_L 0x0341
94
95 #define IMX586_FLIP_MIRROR_REG 0x0101
96 #define IMX586_MIRROR_BIT_MASK BIT(0)
97 #define IMX586_FLIP_BIT_MASK BIT(1)
98
99 #define IMX586_FETCH_EXP_H(VAL) (((VAL) >> 8) & 0xFF)
100 #define IMX586_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
101
102 #define IMX586_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
103 #define IMX586_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
104
105 #define IMX586_FETCH_DGAIN_H(VAL) (((VAL) >> 8) & 0x0F)
106 #define IMX586_FETCH_DGAIN_L(VAL) ((VAL) & 0xFF)
107
108 #define IMX586_FETCH_RHS1_H(VAL) (((VAL) >> 16) & 0x0F)
109 #define IMX586_FETCH_RHS1_M(VAL) (((VAL) >> 8) & 0xFF)
110 #define IMX586_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
111
112 #define REG_DELAY 0xFFFE
113 #define REG_NULL 0xFFFF
114
115 #define IMX586_REG_VALUE_08BIT 1
116 #define IMX586_REG_VALUE_16BIT 2
117 #define IMX586_REG_VALUE_24BIT 3
118
119 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
120
121 #define IMX586_NAME "imx586"
122
123 static const char * const imx586_supply_names[] = {
124 "avdd", /* Analog power */
125 "dovdd", /* Digital I/O power */
126 "dvdd", /* Digital core power */
127 };
128
129 #define IMX586_NUM_SUPPLIES ARRAY_SIZE(imx586_supply_names)
130
131 struct regval {
132 u16 addr;
133 u8 val;
134 };
135
136 struct other_data {
137 u32 width;
138 u32 height;
139 u32 bus_fmt;
140 u32 data_type;
141 u32 data_bit;
142 };
143
144 struct imx586_mode {
145 u32 bus_fmt;
146 u32 width;
147 u32 height;
148 struct v4l2_fract max_fps;
149 u32 hts_def;
150 u32 vts_def;
151 u32 exp_def;
152 const struct regval *global_reg_list;
153 const struct regval *reg_list;
154 u32 hdr_mode;
155 u32 mipi_freq_idx;
156 const struct other_data *spd;
157 u32 vc[PAD_MAX];
158 };
159
160 struct imx586 {
161 struct i2c_client *client;
162 struct clk *xvclk;
163 struct gpio_desc *reset_gpio;
164 struct gpio_desc *pwdn_gpio;
165 struct regulator_bulk_data supplies[IMX586_NUM_SUPPLIES];
166
167 struct pinctrl *pinctrl;
168 struct pinctrl_state *pins_default;
169 struct pinctrl_state *pins_sleep;
170
171 struct v4l2_subdev subdev;
172 struct media_pad pad;
173 struct v4l2_ctrl_handler ctrl_handler;
174 struct v4l2_ctrl *exposure;
175 struct v4l2_ctrl *anal_gain;
176 struct v4l2_ctrl *digi_gain;
177 struct v4l2_ctrl *hblank;
178 struct v4l2_ctrl *vblank;
179 struct v4l2_ctrl *h_flip;
180 struct v4l2_ctrl *v_flip;
181 struct v4l2_ctrl *test_pattern;
182 struct v4l2_ctrl *pixel_rate;
183 struct v4l2_ctrl *link_freq;
184 struct mutex mutex;
185 bool streaming;
186 bool power_on;
187 const struct imx586_mode *cur_mode;
188 u32 cfg_num;
189 u32 cur_pixel_rate;
190 u32 cur_link_freq;
191 u32 module_index;
192 const char *module_facing;
193 const char *module_name;
194 const char *len_name;
195 u32 cur_vts;
196 bool has_init_exp;
197 struct preisp_hdrae_exp_s init_hdrae_exp;
198 u8 flip;
199 struct otp_info *otp;
200 u32 spd_id;
201 };
202
203 #define to_imx586(sd) container_of(sd, struct imx586, subdev)
204
205 /*
206 *IMX586LQR All-pixel scan CSI-2_4lane 24Mhz
207 *AD:10bit Output:10bit 1696Mbps Master Mode 30fps
208 *
209 */
210 static const struct regval imx586_linear_10bit_global_regs[] = {
211 /* External Clock Setting */
212 {0x0136, 0x18},
213 {0x0137, 0x00},
214 /* Register version */
215 {0x3C7E, 0x01},
216 {0x3C7F, 0x08},
217
218 /* Signaling mode setting */
219 {0x0111, 0x02},
220
221 /*Global Setting*/
222 {0x380C, 0x00},
223 {0x3C00, 0x10},
224 {0x3C01, 0x10},
225 {0x3C02, 0x10},
226 {0x3C03, 0x10},
227 {0x3C04, 0x10},
228 {0x3C05, 0x01},
229 {0x3C06, 0x00},
230 {0x3C07, 0x00},
231 {0x3C08, 0x03},
232 {0x3C09, 0xFF},
233 {0x3C0A, 0x01},
234 {0x3C0B, 0x00},
235 {0x3C0C, 0x00},
236 {0x3C0D, 0x03},
237 {0x3C0E, 0xFF},
238 {0x3C0F, 0x20},
239 {0x3F88, 0x00},
240 {0x3F8E, 0x00},
241 {0x5282, 0x01},
242 {0x9004, 0x14},
243 {0x9200, 0xF4},
244 {0x9201, 0xA7},
245 {0x9202, 0xF4},
246 {0x9203, 0xAA},
247 {0x9204, 0xF4},
248 {0x9205, 0xAD},
249 {0x9206, 0xF4},
250 {0x9207, 0xB0},
251 {0x9208, 0xF4},
252 {0x9209, 0xB3},
253 {0x920A, 0xB7},
254 {0x920B, 0x34},
255 {0x920C, 0xB7},
256 {0x920D, 0x36},
257 {0x920E, 0xB7},
258 {0x920F, 0x37},
259 {0x9210, 0xB7},
260 {0x9211, 0x38},
261 {0x9212, 0xB7},
262 {0x9213, 0x39},
263 {0x9214, 0xB7},
264 {0x9215, 0x3A},
265 {0x9216, 0xB7},
266 {0x9217, 0x3C},
267 {0x9218, 0xB7},
268 {0x9219, 0x3D},
269 {0x921A, 0xB7},
270 {0x921B, 0x3E},
271 {0x921C, 0xB7},
272 {0x921D, 0x3F},
273 {0x921E, 0x77},
274 {0x921F, 0x77},
275 {0x9222, 0xC4},
276 {0x9223, 0x4B},
277 {0x9224, 0xC4},
278 {0x9225, 0x4C},
279 {0x9226, 0xC4},
280 {0x9227, 0x4D},
281 {0x9810, 0x14},
282 {0x9814, 0x14},
283 {0x99B2, 0x20},
284 {0x99B3, 0x0F},
285 {0x99B4, 0x0F},
286 {0x99B5, 0x0F},
287 {0x99B6, 0x0F},
288 {0x99E4, 0x0F},
289 {0x99E5, 0x0F},
290 {0x99E6, 0x0F},
291 {0x99E7, 0x0F},
292 {0x99E8, 0x0F},
293 {0x99E9, 0x0F},
294 {0x99EA, 0x0F},
295 {0x99EB, 0x0F},
296 {0x99EC, 0x0F},
297 {0x99ED, 0x0F},
298 {0xA569, 0x06},
299 {0xA679, 0x20},
300 {0xC020, 0x01},
301 {0xC61D, 0x00},
302 {0xC625, 0x00},
303 {0xC638, 0x03},
304 {0xC63B, 0x01},
305 {0xE286, 0x31},
306 {0xE2A6, 0x32},
307 {0xE2C6, 0x33},
308 {0xBCF1, 0x00},
309
310 /*Image Quality adjustment setting */
311 {0x9852, 0x00},
312 {0x9954, 0x0F},
313 {0xA7AD, 0x01},
314 {0xA7CB, 0x01},
315 {0xAE09, 0xFF},
316 {0xAE0A, 0xFF},
317 {0xAE12, 0x58},
318 {0xAE13, 0x58},
319 {0xAE15, 0x10},
320 {0xAE16, 0x10},
321 {0xAF05, 0x48},
322 {0xB07C, 0x02},
323
324 {REG_NULL, 0x00},
325 };
326
327 static const struct regval imx586_linear_10bit_4000x3000_30fps_nopd_regs[] = {
328 /* MIPI output setting */
329 {0x0112, 0x0A},
330 {0x0113, 0x0A},
331 {0x0114, 0x03},
332
333 /* Line Length PCK Setting */
334 {0x0342, 0x23}, // 8976
335 {0x0343, 0x10},
336
337 /* Frame Length Lines Setting */
338 {0x0340, 0x0B}, // 3064
339 {0x0341, 0xF8},
340
341 /* ROI Setting */
342 {0x0344, 0x00},
343 {0x0345, 0x00},
344 {0x0346, 0x00},
345 {0x0347, 0x00},
346 {0x0348, 0x1F},
347 {0x0349, 0x3F},
348 {0x034A, 0x17},
349 {0x034B, 0x6F},
350
351 /* Mode Setting */
352 {0x0220, 0x62},
353 {0x0222, 0x01},
354 {0x0900, 0x01},
355 {0x0901, 0x22},
356 {0x0902, 0x08},
357 {0x3140, 0x00},
358 {0x3246, 0x81},
359 {0x3247, 0x81},
360 {0x3F15, 0x00},
361
362 /* Digital Crop & Scaling */
363 {0x0401, 0x00},
364 {0x0404, 0x00},
365 {0x0405, 0x10},
366 {0x0408, 0x00},
367 {0x0409, 0x00},
368 {0x040A, 0x00},
369 {0x040B, 0x00},
370 {0x040C, 0x0F},
371 {0x040D, 0xA0},
372 {0x040E, 0x0B},
373 {0x040F, 0xB8},
374
375 /* Output Size Setting */
376 {0x034C, 0x0F},
377 {0x034D, 0xA0},
378 {0x034E, 0x0B},
379 {0x034F, 0xB8},
380
381 /* Clock Setting */
382 {0x0301, 0x05},
383 {0x0303, 0x04},
384 {0x0305, 0x04},
385 {0x0306, 0x01},
386 {0x0307, 0x58},
387 {0x030B, 0x02},
388 {0x030D, 0x03},
389 {0x030E, 0x01},
390 {0x030F, 0x1F},
391 {0x0310, 0x01},
392
393 /* Other Setting */
394 {0x3620, 0x00},
395 {0x3621, 0x00},
396 {0x3C11, 0x04},
397 {0x3C12, 0x03},
398 {0x3C13, 0x2D},
399 {0x3F0C, 0x00},
400 {0x3F14, 0x00},
401 {0x3F80, 0x01},
402 {0x3F81, 0x90},
403 {0x3F8C, 0x00},
404 {0x3F8D, 0x14},
405 {0x3FF8, 0x01},
406 {0x3FF9, 0x2A},
407 {0x3FFE, 0x00},
408 {0x3FFF, 0x6C},
409
410 /* Integration Setting */
411 {0x0202, 0x0B},
412 {0x0203, 0xC4},
413 {0x0224, 0x01},
414 {0x0225, 0xF4},
415 {0x3FE0, 0x01},
416 {0x3FE1, 0xF4},
417
418 /* Gain Setting */
419 {0x0204, 0x00},
420 {0x0205, 0x70},
421 {0x0216, 0x00},
422 {0x0217, 0x70},
423 {0x0218, 0x01},
424 {0x0219, 0x00},
425 {0x020E, 0x01},
426 {0x020F, 0x00},
427 {0x0210, 0x01},
428 {0x0211, 0x00},
429 {0x0212, 0x01},
430 {0x0213, 0x00},
431 {0x0214, 0x01},
432 {0x0215, 0x00},
433 {0x3FE2, 0x00},
434 {0x3FE3, 0x70},
435 {0x3FE4, 0x01},
436 {0x3FE5, 0x00},
437
438 /* PDAF TYPE1 Setting */
439 {0x3E20, 0x01},
440 {0x3E37, 0x01},
441
442 {REG_NULL, 0x00},
443 };
444
445 static const struct regval imx586_linear_10bit_full_raw_6fps_regs[] = {
446 /* MIPI output setting */
447 {0x0112, 0x0A},
448 {0x0113, 0x0A},
449 {0x0114, 0x03},
450
451 /* Line Length PCK Setting */
452 {0x0342, 0x39},
453 {0x0343, 0x70},
454
455 /* Frame Length Lines Setting */
456 {0x0340, 0x17},
457 {0x0341, 0xAC},
458
459 /* ROI Setting */
460 {0x0344, 0x00},
461 {0x0345, 0x00},
462 {0x0346, 0x00},
463 {0x0347, 0x00},
464 {0x0348, 0x1F},
465 {0x0349, 0x3F},
466 {0x034A, 0x17},
467 {0x034B, 0x6F},
468
469 /* Mode Setting */
470 {0x0220, 0x62},
471 {0x0222, 0x01},
472 {0x0900, 0x00},
473 {0x0901, 0x11},
474 {0x0902, 0x0A},
475 {0x3140, 0x00},
476 {0x3246, 0x01},
477 {0x3247, 0x01},
478 {0x3F15, 0x00},
479
480 /* Digital Crop & Scaling */
481 {0x0401, 0x00},
482 {0x0404, 0x00},
483 {0x0405, 0x10},
484 {0x0408, 0x00},
485 {0x0409, 0x00},
486 {0x040A, 0x00},
487 {0x040B, 0x00},
488 {0x040C, 0x1F},
489 {0x040D, 0x40},
490 {0x040E, 0x17},
491 {0x040F, 0x70},
492
493 /* Output Size Setting */
494 {0x034C, 0x1F},
495 {0x034D, 0x40},
496 {0x034E, 0x17},
497 {0x034F, 0x70},
498
499 /* Clock Setting */
500 {0x0301, 0x05},
501 {0x0303, 0x04},
502 {0x0305, 0x04},
503 {0x0306, 0x00},
504 {0x0307, 0xEE},
505 {0x030B, 0x02},
506 {0x030D, 0x06},
507 {0x030E, 0x01},
508 {0x030F, 0x90},
509 {0x0310, 0x01},
510
511 /* Other Setting */
512 {0x3620, 0x00},
513 {0x3621, 0x01},
514 {0x3C11, 0x08},
515 {0x3C12, 0x08},
516 {0x3C13, 0x2A},
517 {0x3F0C, 0x00},
518 {0x3F14, 0x01},
519 {0x3F80, 0x00},
520 {0x3F81, 0x00},
521 {0x3F8C, 0x00},
522 {0x3F8D, 0x00},
523 {0x3FF8, 0x00},
524 {0x3FF9, 0x00},
525 {0x3FFE, 0x03},
526 {0x3FFF, 0x84},
527
528 /* Integration Setting */
529 {0x0202, 0x17},
530 {0x0203, 0x7C},
531 {0x0224, 0x01},
532 {0x0225, 0xF4},
533 {0x3FE0, 0x01},
534 {0x3FE1, 0xF4},
535
536 /* Gain Setting */
537 {0x0204, 0x00},
538 {0x0205, 0x70},
539 {0x0216, 0x00},
540 {0x0217, 0x70},
541 {0x0218, 0x01},
542 {0x0219, 0x00},
543 {0x020E, 0x01},
544 {0x020F, 0x00},
545 {0x0210, 0x01},
546 {0x0211, 0x00},
547 {0x0212, 0x01},
548 {0x0213, 0x00},
549 {0x0214, 0x01},
550 {0x0215, 0x00},
551 {0x3FE2, 0x00},
552 {0x3FE3, 0x70},
553 {0x3FE4, 0x01},
554 {0x3FE5, 0x00},
555
556 /* PDAF TYPE1 Setting */
557 {0x3E20, 0x01},
558 {0x3E37, 0x01},
559
560 {REG_NULL, 0x00},
561 };
562
563 static const struct regval imx586_linear_10bit_full_remosaic_6fps_regs[] = {
564 /* MIPI output setting */
565 {0x0112, 0x0A},
566 {0x0113, 0x0A},
567 {0x0114, 0x03},
568
569 /* Line Length PCK Setting */
570 {0x0342, 0x39},
571 {0x0343, 0x70},
572
573 /* Frame Length Lines Setting */
574 {0x0340, 0x17},
575 {0x0341, 0xAC},
576
577 /* ROI Setting */
578 {0x0344, 0x00},
579 {0x0345, 0x00},
580 {0x0346, 0x00},
581 {0x0347, 0x00},
582 {0x0348, 0x1F},
583 {0x0349, 0x3F},
584 {0x034A, 0x17},
585 {0x034B, 0x6F},
586
587 /* Mode Setting */
588 {0x0220, 0x62},
589 {0x0222, 0x01},
590 {0x0900, 0x00},
591 {0x0901, 0x11},
592 {0x0902, 0x0A},
593 {0x3140, 0x00},
594 {0x3246, 0x01},
595 {0x3247, 0x01},
596 {0x3F15, 0x00},
597
598 /* Digital Crop & Scaling */
599 {0x0401, 0x00},
600 {0x0404, 0x00},
601 {0x0405, 0x10},
602 {0x0408, 0x00},
603 {0x0409, 0x00},
604 {0x040A, 0x00},
605 {0x040B, 0x00},
606 {0x040C, 0x1F},
607 {0x040D, 0x40},
608 {0x040E, 0x17},
609 {0x040F, 0x70},
610
611 /* Output Size Setting */
612 {0x034C, 0x1F},
613 {0x034D, 0x40},
614 {0x034E, 0x17},
615 {0x034F, 0x70},
616
617 /* Clock Setting */
618 {0x0301, 0x05},
619 {0x0303, 0x04},
620 {0x0305, 0x04},
621 {0x0306, 0x00},
622 {0x0307, 0xEE},
623 {0x030B, 0x02},
624 {0x030D, 0x06},
625 {0x030E, 0x01},
626 {0x030F, 0x90},
627 {0x0310, 0x01},
628
629 /* Other Setting */
630 {0x3620, 0x01},
631 {0x3621, 0x01},
632 {0x3C11, 0x08},
633 {0x3C12, 0x08},
634 {0x3C13, 0x2A},
635 {0x3F0C, 0x00},
636 {0x3F14, 0x01},
637 {0x3F80, 0x00},
638 {0x3F81, 0x14},
639 {0x3F8C, 0x00},
640 {0x3F8D, 0x14},
641 {0x3FF8, 0x00},
642 {0x3FF9, 0x00},
643 {0x3FFE, 0x03},
644 {0x3FFF, 0x52},
645
646 /* Integration Setting */
647 {0x0202, 0x17},
648 {0x0203, 0x7C},
649 {0x0224, 0x01},
650 {0x0225, 0xF4},
651 {0x3FE0, 0x01},
652 {0x3FE1, 0xF4},
653
654 /* Gain Setting */
655 {0x0204, 0x00},
656 {0x0205, 0x70},
657 {0x0216, 0x00},
658 {0x0217, 0x70},
659 {0x0218, 0x01},
660 {0x0219, 0x00},
661 {0x020E, 0x01},
662 {0x020F, 0x00},
663 {0x0210, 0x01},
664 {0x0211, 0x00},
665 {0x0212, 0x01},
666 {0x0213, 0x00},
667 {0x0214, 0x01},
668 {0x0215, 0x00},
669 {0x3FE2, 0x00},
670 {0x3FE3, 0x70},
671 {0x3FE4, 0x01},
672 {0x3FE5, 0x00},
673
674 /* PDAF TYPE1 Setting */
675 {0x3E20, 0x01},
676 {0x3E37, 0x01},
677
678 {REG_NULL, 0x00},
679 };
680
681 static const struct regval imx586_linear_10bit_full_remosaic_10fps_regs[] = {
682 /* MIPI output setting */
683 {0x0112, 0x0A},
684 {0x0113, 0x0A},
685 {0x0114, 0x03},
686
687 /* Line Length PCK Setting */
688 {0x0342, 0x39},
689 {0x0343, 0x70},
690
691 /* Frame Length Lines Setting */
692 {0x0340, 0x17},
693 {0x0341, 0xAC},
694
695 /* ROI Setting */
696 {0x0344, 0x00},
697 {0x0345, 0x00},
698 {0x0346, 0x00},
699 {0x0347, 0x00},
700 {0x0348, 0x1F},
701 {0x0349, 0x3F},
702 {0x034A, 0x17},
703 {0x034B, 0x6F},
704
705 /* Mode Setting */
706 {0x0220, 0x62},
707 {0x0222, 0x01},
708 {0x0900, 0x00},
709 {0x0901, 0x11},
710 {0x0902, 0x0A},
711 {0x3140, 0x00},
712 {0x3246, 0x01},
713 {0x3247, 0x01},
714 {0x3F15, 0x00},
715
716 /* Digital Crop & Scaling */
717 {0x0401, 0x00},
718 {0x0404, 0x00},
719 {0x0405, 0x10},
720 {0x0408, 0x00},
721 {0x0409, 0x00},
722 {0x040A, 0x00},
723 {0x040B, 0x00},
724 {0x040C, 0x1F},
725 {0x040D, 0x40},
726 {0x040E, 0x17},
727 {0x040F, 0x70},
728
729 /* Output Size Setting */
730 {0x034C, 0x1F},
731 {0x034D, 0x40},
732 {0x034E, 0x17},
733 {0x034F, 0x70},
734
735 /* Clock Setting */
736 {0x0301, 0x05},
737 {0x0303, 0x04},
738 {0x0305, 0x04},
739 {0x0306, 0x01},
740 {0x0307, 0x68},
741 {0x030B, 0x02},
742 {0x030D, 0x06},
743 {0x030E, 0x02},
744 {0x030F, 0x71},
745 {0x0310, 0x01},
746
747 /* Other Setting */
748 {0x3620, 0x01},
749 {0x3621, 0x01},
750 {0x3C11, 0x08},
751 {0x3C12, 0x08},
752 {0x3C13, 0x2A},
753 {0x3F0C, 0x00},
754 {0x3F14, 0x01},
755 {0x3F80, 0x00},
756 {0x3F81, 0x14},
757 {0x3F8C, 0x00},
758 {0x3F8D, 0x14},
759 {0x3FF8, 0x00},
760 {0x3FF9, 0x00},
761 {0x3FFE, 0x03},
762 {0x3FFF, 0x52},
763
764 /* Integration Setting */
765 {0x0202, 0x17},
766 {0x0203, 0x7C},
767 {0x0224, 0x01},
768 {0x0225, 0xF4},
769 {0x3FE0, 0x01},
770 {0x3FE1, 0xF4},
771
772 /* Gain Setting */
773 {0x0204, 0x00},
774 {0x0205, 0x70},
775 {0x0216, 0x00},
776 {0x0217, 0x70},
777 {0x0218, 0x01},
778 {0x0219, 0x00},
779 {0x020E, 0x01},
780 {0x020F, 0x00},
781 {0x0210, 0x01},
782 {0x0211, 0x00},
783 {0x0212, 0x01},
784 {0x0213, 0x00},
785 {0x0214, 0x01},
786 {0x0215, 0x00},
787 {0x3FE2, 0x00},
788 {0x3FE3, 0x70},
789 {0x3FE4, 0x01},
790 {0x3FE5, 0x00},
791
792 /* PDAF TYPE1 Setting */
793 {0x3E20, 0x01},
794 {0x3E37, 0x01},
795
796 {REG_NULL, 0x00},
797 };
798
799 static const struct imx586_mode supported_modes[] = {
800 {
801 .width = 4000,
802 .height = 3000,
803 .max_fps = {
804 .numerator = 10000,
805 .denominator = 300000,
806 },
807 .exp_def = 0x0B00,
808 .hts_def = 0x2310,
809 .vts_def = 0x0BF8,
810 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
811 .global_reg_list = imx586_linear_10bit_global_regs,
812 .reg_list = imx586_linear_10bit_4000x3000_30fps_nopd_regs,
813 .hdr_mode = NO_HDR,
814 .mipi_freq_idx = 0,
815 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
816 },
817 {
818 .width = 8000,
819 .height = 6000,
820 .max_fps = {
821 .numerator = 10000,
822 .denominator = 64100,
823 },
824 .exp_def = 0x0B00,
825 .hts_def = 0x3970,
826 .vts_def = 0x17AC,
827 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
828 .global_reg_list = imx586_linear_10bit_global_regs,
829 .reg_list = imx586_linear_10bit_full_raw_6fps_regs,
830 .hdr_mode = NO_HDR,
831 .mipi_freq_idx = 0,
832 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
833 },
834 {
835 .width = 8000,
836 .height = 6000,
837 .max_fps = {
838 .numerator = 10000,
839 .denominator = 64100,
840 },
841 .exp_def = 0x0B00,
842 .hts_def = 0x3970,
843 .vts_def = 0x17AC,
844 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
845 .global_reg_list = imx586_linear_10bit_global_regs,
846 .reg_list = imx586_linear_10bit_full_remosaic_6fps_regs,
847 .hdr_mode = NO_HDR,
848 .mipi_freq_idx = 0,
849 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
850 },
851 {
852 .width = 8000,
853 .height = 6000,
854 .max_fps = {
855 .numerator = 10000,
856 .denominator = 97000,
857 },
858 .exp_def = 0x0B00,
859 .hts_def = 0x3970,
860 .vts_def = 0x17AC,
861 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
862 .global_reg_list = imx586_linear_10bit_global_regs,
863 .reg_list = imx586_linear_10bit_full_remosaic_10fps_regs,
864 .hdr_mode = NO_HDR,
865 .mipi_freq_idx = 1,
866 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
867 },
868 };
869
870 static const s64 link_freq_items[] = {
871 IMX586_LINK_FREQ_400,
872 IMX586_LINK_FREQ_625,
873 };
874
875 static const char * const imx586_test_pattern_menu[] = {
876 "Disabled",
877 "Solid color",
878 "100% color bars",
879 "Fade to grey color bars",
880 "PN9"
881 };
882
883 /* Write registers up to 4 at a time */
imx586_write_reg(struct i2c_client * client,u16 reg,int len,u32 val)884 static int imx586_write_reg(struct i2c_client *client, u16 reg,
885 int len, u32 val)
886 {
887 u32 buf_i, val_i;
888 u8 buf[6];
889 u8 *val_p;
890 __be32 val_be;
891
892 if (len > 4)
893 return -EINVAL;
894
895 buf[0] = reg >> 8;
896 buf[1] = reg & 0xff;
897
898 val_be = cpu_to_be32(val);
899 val_p = (u8 *)&val_be;
900 buf_i = 2;
901 val_i = 4 - len;
902
903 while (val_i < 4)
904 buf[buf_i++] = val_p[val_i++];
905
906 if (i2c_master_send(client, buf, len + 2) != len + 2)
907 return -EIO;
908
909 return 0;
910 }
911
imx586_write_array(struct i2c_client * client,const struct regval * regs)912 static int imx586_write_array(struct i2c_client *client,
913 const struct regval *regs)
914 {
915 u32 i;
916 int ret = 0;
917
918 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
919 if (unlikely(regs[i].addr == REG_DELAY))
920 usleep_range(regs[i].val, regs[i].val * 2);
921 else
922 ret = imx586_write_reg(client, regs[i].addr,
923 IMX586_REG_VALUE_08BIT,
924 regs[i].val);
925
926 return ret;
927 }
928
929 /* Read registers up to 4 at a time */
imx586_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)930 static int imx586_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
931 u32 *val)
932 {
933 struct i2c_msg msgs[2];
934 u8 *data_be_p;
935 __be32 data_be = 0;
936 __be16 reg_addr_be = cpu_to_be16(reg);
937 int ret, i;
938
939 if (len > 4 || !len)
940 return -EINVAL;
941
942 data_be_p = (u8 *)&data_be;
943 /* Write register address */
944 msgs[0].addr = client->addr;
945 msgs[0].flags = 0;
946 msgs[0].len = 2;
947 msgs[0].buf = (u8 *)®_addr_be;
948
949 /* Read data from register */
950 msgs[1].addr = client->addr;
951 msgs[1].flags = I2C_M_RD;
952 msgs[1].len = len;
953 msgs[1].buf = &data_be_p[4 - len];
954
955 for (i = 0; i < 3; i++) {
956 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
957 if (ret == ARRAY_SIZE(msgs))
958 break;
959 }
960 if (ret != ARRAY_SIZE(msgs) && i == 3)
961 return -EIO;
962
963 *val = be32_to_cpu(data_be);
964
965 return 0;
966 }
967
imx586_get_reso_dist(const struct imx586_mode * mode,struct v4l2_mbus_framefmt * framefmt)968 static int imx586_get_reso_dist(const struct imx586_mode *mode,
969 struct v4l2_mbus_framefmt *framefmt)
970 {
971 return abs(mode->width - framefmt->width) +
972 abs(mode->height - framefmt->height);
973 }
974
975 static const struct imx586_mode *
imx586_find_best_fit(struct imx586 * imx586,struct v4l2_subdev_format * fmt)976 imx586_find_best_fit(struct imx586 *imx586, struct v4l2_subdev_format *fmt)
977 {
978 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
979 int dist;
980 int cur_best_fit = 0;
981 int cur_best_fit_dist = -1;
982 unsigned int i;
983
984 for (i = 0; i < imx586->cfg_num; i++) {
985 dist = imx586_get_reso_dist(&supported_modes[i], framefmt);
986 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
987 cur_best_fit_dist = dist;
988 cur_best_fit = i;
989 }
990 }
991
992 return &supported_modes[cur_best_fit];
993 }
994
imx586_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)995 static int imx586_set_fmt(struct v4l2_subdev *sd,
996 struct v4l2_subdev_pad_config *cfg,
997 struct v4l2_subdev_format *fmt)
998 {
999 struct imx586 *imx586 = to_imx586(sd);
1000 const struct imx586_mode *mode;
1001 s64 h_blank, vblank_def;
1002 u64 pixel_rate = 0;
1003
1004 mutex_lock(&imx586->mutex);
1005
1006 mode = imx586_find_best_fit(imx586, fmt);
1007 fmt->format.code = mode->bus_fmt;
1008 fmt->format.width = mode->width;
1009 fmt->format.height = mode->height;
1010 fmt->format.field = V4L2_FIELD_NONE;
1011 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1012 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1013 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1014 #else
1015 mutex_unlock(&imx586->mutex);
1016 return -ENOTTY;
1017 #endif
1018 } else {
1019 imx586->cur_mode = mode;
1020 h_blank = mode->hts_def - mode->width;
1021 __v4l2_ctrl_modify_range(imx586->hblank, h_blank,
1022 h_blank, 1, h_blank);
1023 vblank_def = mode->vts_def - mode->height;
1024 __v4l2_ctrl_modify_range(imx586->vblank, vblank_def,
1025 IMX586_VTS_MAX - mode->height,
1026 1, vblank_def);
1027
1028 __v4l2_ctrl_s_ctrl(imx586->vblank, vblank_def);
1029 __v4l2_ctrl_s_ctrl(imx586->link_freq, mode->mipi_freq_idx);
1030 pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / 10 * 2 * IMX586_LANES;
1031 __v4l2_ctrl_s_ctrl_int64(imx586->pixel_rate,
1032 pixel_rate);
1033 }
1034
1035 dev_info(&imx586->client->dev, "%s: mode->mipi_freq_idx(%d)",
1036 __func__, mode->mipi_freq_idx);
1037
1038 mutex_unlock(&imx586->mutex);
1039
1040 return 0;
1041 }
1042
imx586_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1043 static int imx586_get_fmt(struct v4l2_subdev *sd,
1044 struct v4l2_subdev_pad_config *cfg,
1045 struct v4l2_subdev_format *fmt)
1046 {
1047 struct imx586 *imx586 = to_imx586(sd);
1048 const struct imx586_mode *mode = imx586->cur_mode;
1049
1050 mutex_lock(&imx586->mutex);
1051 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1052 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1053 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1054 #else
1055 mutex_unlock(&imx586->mutex);
1056 return -ENOTTY;
1057 #endif
1058 } else {
1059 fmt->format.width = mode->width;
1060 fmt->format.height = mode->height;
1061 if (imx586->flip & IMX586_MIRROR_BIT_MASK) {
1062 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1063 if (imx586->flip & IMX586_FLIP_BIT_MASK)
1064 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
1065 } else if (imx586->flip & IMX586_FLIP_BIT_MASK) {
1066 fmt->format.code = MEDIA_BUS_FMT_SGBRG10_1X10;
1067 } else {
1068 fmt->format.code = mode->bus_fmt;
1069 }
1070 fmt->format.field = V4L2_FIELD_NONE;
1071 /* format info: width/height/data type/virctual channel */
1072 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
1073 fmt->reserved[0] = mode->vc[fmt->pad];
1074 else
1075 fmt->reserved[0] = mode->vc[PAD0];
1076 }
1077 mutex_unlock(&imx586->mutex);
1078
1079 return 0;
1080 }
1081
imx586_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1082 static int imx586_enum_mbus_code(struct v4l2_subdev *sd,
1083 struct v4l2_subdev_pad_config *cfg,
1084 struct v4l2_subdev_mbus_code_enum *code)
1085 {
1086 struct imx586 *imx586 = to_imx586(sd);
1087
1088 if (code->index != 0)
1089 return -EINVAL;
1090 code->code = imx586->cur_mode->bus_fmt;
1091
1092 return 0;
1093 }
1094
imx586_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1095 static int imx586_enum_frame_sizes(struct v4l2_subdev *sd,
1096 struct v4l2_subdev_pad_config *cfg,
1097 struct v4l2_subdev_frame_size_enum *fse)
1098 {
1099 struct imx586 *imx586 = to_imx586(sd);
1100
1101 if (fse->index >= imx586->cfg_num)
1102 return -EINVAL;
1103
1104 if (fse->code != supported_modes[0].bus_fmt)
1105 return -EINVAL;
1106
1107 fse->min_width = supported_modes[fse->index].width;
1108 fse->max_width = supported_modes[fse->index].width;
1109 fse->max_height = supported_modes[fse->index].height;
1110 fse->min_height = supported_modes[fse->index].height;
1111
1112 return 0;
1113 }
1114
imx586_enable_test_pattern(struct imx586 * imx586,u32 pattern)1115 static int imx586_enable_test_pattern(struct imx586 *imx586, u32 pattern)
1116 {
1117 u32 val;
1118
1119 if (pattern)
1120 val = (pattern - 1) | IMX586_TEST_PATTERN_ENABLE;
1121 else
1122 val = IMX586_TEST_PATTERN_DISABLE;
1123
1124 return imx586_write_reg(imx586->client,
1125 IMX586_REG_TEST_PATTERN,
1126 IMX586_REG_VALUE_08BIT,
1127 val);
1128 }
1129
imx586_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1130 static int imx586_g_frame_interval(struct v4l2_subdev *sd,
1131 struct v4l2_subdev_frame_interval *fi)
1132 {
1133 struct imx586 *imx586 = to_imx586(sd);
1134 const struct imx586_mode *mode = imx586->cur_mode;
1135
1136 fi->interval = mode->max_fps;
1137
1138 return 0;
1139 }
1140
imx586_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1141 static int imx586_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1142 struct v4l2_mbus_config *config)
1143 {
1144 struct imx586 *imx586 = to_imx586(sd);
1145 const struct imx586_mode *mode = imx586->cur_mode;
1146 u32 val = 0;
1147
1148 if (mode->hdr_mode == NO_HDR)
1149 val = 1 << (IMX586_LANES - 1) |
1150 V4L2_MBUS_CSI2_CHANNEL_0 |
1151 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1152
1153 if (mode->hdr_mode == HDR_X2)
1154 val = 1 << (IMX586_LANES - 1) |
1155 V4L2_MBUS_CSI2_CHANNEL_0 |
1156 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
1157 V4L2_MBUS_CSI2_CHANNEL_1;
1158
1159 config->type = V4L2_MBUS_CSI2_DPHY;
1160 config->flags = val;
1161
1162 return 0;
1163 }
1164
imx586_get_otp(struct otp_info * otp,struct rkmodule_inf * inf)1165 static void imx586_get_otp(struct otp_info *otp,
1166 struct rkmodule_inf *inf)
1167 {
1168 u32 i, j;
1169 u32 w, h;
1170
1171 /* awb */
1172 if (otp->awb_data.flag) {
1173 inf->awb.flag = 1;
1174 inf->awb.r_value = otp->awb_data.r_ratio;
1175 inf->awb.b_value = otp->awb_data.b_ratio;
1176 inf->awb.gr_value = otp->awb_data.g_ratio;
1177 inf->awb.gb_value = 0x0;
1178
1179 inf->awb.golden_r_value = otp->awb_data.r_golden;
1180 inf->awb.golden_b_value = otp->awb_data.b_golden;
1181 inf->awb.golden_gr_value = otp->awb_data.g_golden;
1182 inf->awb.golden_gb_value = 0x0;
1183 }
1184
1185 /* lsc */
1186 if (otp->lsc_data.flag) {
1187 inf->lsc.flag = 1;
1188 inf->lsc.width = otp->basic_data.size.width;
1189 inf->lsc.height = otp->basic_data.size.height;
1190 inf->lsc.table_size = otp->lsc_data.table_size;
1191
1192 for (i = 0; i < 289; i++) {
1193 inf->lsc.lsc_r[i] = (otp->lsc_data.data[i * 2] << 8) |
1194 otp->lsc_data.data[i * 2 + 1];
1195 inf->lsc.lsc_gr[i] = (otp->lsc_data.data[i * 2 + 578] << 8) |
1196 otp->lsc_data.data[i * 2 + 579];
1197 inf->lsc.lsc_gb[i] = (otp->lsc_data.data[i * 2 + 1156] << 8) |
1198 otp->lsc_data.data[i * 2 + 1157];
1199 inf->lsc.lsc_b[i] = (otp->lsc_data.data[i * 2 + 1734] << 8) |
1200 otp->lsc_data.data[i * 2 + 1735];
1201 }
1202 }
1203
1204 /* pdaf */
1205 if (otp->pdaf_data.flag) {
1206 inf->pdaf.flag = 1;
1207 inf->pdaf.gainmap_width = otp->pdaf_data.gainmap_width;
1208 inf->pdaf.gainmap_height = otp->pdaf_data.gainmap_height;
1209 inf->pdaf.dcc_mode = otp->pdaf_data.dcc_mode;
1210 inf->pdaf.dcc_dir = otp->pdaf_data.dcc_dir;
1211 inf->pdaf.dccmap_width = otp->pdaf_data.dccmap_width;
1212 inf->pdaf.dccmap_height = otp->pdaf_data.dccmap_height;
1213 w = otp->pdaf_data.gainmap_width;
1214 h = otp->pdaf_data.gainmap_height;
1215 for (i = 0; i < h; i++) {
1216 for (j = 0; j < w; j++) {
1217 inf->pdaf.gainmap[i * w + j] =
1218 (otp->pdaf_data.gainmap[(i * w + j) * 2] << 8) |
1219 otp->pdaf_data.gainmap[(i * w + j) * 2 + 1];
1220 }
1221 }
1222 w = otp->pdaf_data.dccmap_width;
1223 h = otp->pdaf_data.dccmap_height;
1224 for (i = 0; i < h; i++) {
1225 for (j = 0; j < w; j++) {
1226 inf->pdaf.dccmap[i * w + j] =
1227 (otp->pdaf_data.dccmap[(i * w + j) * 2] << 8) |
1228 otp->pdaf_data.dccmap[(i * w + j) * 2 + 1];
1229 }
1230 }
1231 }
1232
1233 /* af */
1234 if (otp->af_data.flag) {
1235 inf->af.flag = 1;
1236 inf->af.dir_cnt = 1;
1237 inf->af.af_otp[0].vcm_start = otp->af_data.af_inf;
1238 inf->af.af_otp[0].vcm_end = otp->af_data.af_macro;
1239 inf->af.af_otp[0].vcm_dir = 0;
1240 }
1241
1242 }
1243
imx586_get_module_inf(struct imx586 * imx586,struct rkmodule_inf * inf)1244 static void imx586_get_module_inf(struct imx586 *imx586,
1245 struct rkmodule_inf *inf)
1246 {
1247 struct otp_info *otp = imx586->otp;
1248
1249 memset(inf, 0, sizeof(*inf));
1250 strscpy(inf->base.sensor, IMX586_NAME, sizeof(inf->base.sensor));
1251 strscpy(inf->base.module, imx586->module_name,
1252 sizeof(inf->base.module));
1253 strscpy(inf->base.lens, imx586->len_name, sizeof(inf->base.lens));
1254 if (otp)
1255 imx586_get_otp(otp, inf);
1256
1257 }
1258
imx586_get_channel_info(struct imx586 * imx586,struct rkmodule_channel_info * ch_info)1259 static int imx586_get_channel_info(struct imx586 *imx586, struct rkmodule_channel_info *ch_info)
1260 {
1261 const struct imx586_mode *mode = imx586->cur_mode;
1262
1263 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1264 return -EINVAL;
1265
1266 if (ch_info->index == imx586->spd_id && mode->spd) {
1267 ch_info->vc = V4L2_MBUS_CSI2_CHANNEL_0;
1268 ch_info->width = mode->spd->width;
1269 ch_info->height = mode->spd->height;
1270 ch_info->bus_fmt = mode->spd->bus_fmt;
1271 ch_info->data_type = mode->spd->data_type;
1272 ch_info->data_bit = mode->spd->data_bit;
1273 } else {
1274 ch_info->vc = imx586->cur_mode->vc[ch_info->index];
1275 ch_info->width = imx586->cur_mode->width;
1276 ch_info->height = imx586->cur_mode->height;
1277 ch_info->bus_fmt = imx586->cur_mode->bus_fmt;
1278 }
1279 return 0;
1280 }
1281
imx586_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1282 static long imx586_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1283 {
1284 struct imx586 *imx586 = to_imx586(sd);
1285 struct rkmodule_hdr_cfg *hdr;
1286 struct rkmodule_channel_info *ch_info;
1287 long ret = 0;
1288 u32 i, h, w;
1289 u32 stream = 0;
1290
1291 switch (cmd) {
1292 case PREISP_CMD_SET_HDRAE_EXP:
1293 break;
1294 case RKMODULE_GET_MODULE_INFO:
1295 imx586_get_module_inf(imx586, (struct rkmodule_inf *)arg);
1296 break;
1297 case RKMODULE_GET_HDR_CFG:
1298 hdr = (struct rkmodule_hdr_cfg *)arg;
1299 hdr->esp.mode = HDR_NORMAL_VC;
1300 hdr->hdr_mode = imx586->cur_mode->hdr_mode;
1301 break;
1302 case RKMODULE_SET_HDR_CFG:
1303 hdr = (struct rkmodule_hdr_cfg *)arg;
1304 w = imx586->cur_mode->width;
1305 h = imx586->cur_mode->height;
1306 for (i = 0; i < imx586->cfg_num; i++) {
1307 if (w == supported_modes[i].width &&
1308 h == supported_modes[i].height &&
1309 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1310 imx586->cur_mode = &supported_modes[i];
1311 break;
1312 }
1313 }
1314 if (i == imx586->cfg_num) {
1315 dev_err(&imx586->client->dev,
1316 "not find hdr mode:%d %dx%d config\n",
1317 hdr->hdr_mode, w, h);
1318 ret = -EINVAL;
1319 } else {
1320 w = imx586->cur_mode->hts_def -
1321 imx586->cur_mode->width;
1322 h = imx586->cur_mode->vts_def -
1323 imx586->cur_mode->height;
1324 __v4l2_ctrl_modify_range(imx586->hblank, w, w, 1, w);
1325 __v4l2_ctrl_modify_range(imx586->vblank, h,
1326 IMX586_VTS_MAX -
1327 imx586->cur_mode->height,
1328 1, h);
1329
1330 if (imx586->cur_mode->bus_fmt ==
1331 MEDIA_BUS_FMT_SRGGB10_1X10) {
1332 imx586->cur_link_freq = 0;
1333 imx586->cur_pixel_rate =
1334 PIXEL_RATE_WITH_848M_10BIT;
1335 } else if (imx586->cur_mode->bus_fmt ==
1336 MEDIA_BUS_FMT_SRGGB12_1X12) {
1337 imx586->cur_link_freq = 0;
1338 imx586->cur_pixel_rate =
1339 PIXEL_RATE_WITH_848M_12BIT;
1340 }
1341
1342 __v4l2_ctrl_s_ctrl_int64(imx586->pixel_rate,
1343 imx586->cur_pixel_rate);
1344 __v4l2_ctrl_s_ctrl(imx586->link_freq,
1345 imx586->cur_link_freq);
1346 }
1347 break;
1348 case RKMODULE_SET_QUICK_STREAM:
1349
1350 stream = *((u32 *)arg);
1351
1352 if (stream)
1353 ret = imx586_write_reg(imx586->client, IMX586_REG_CTRL_MODE,
1354 IMX586_REG_VALUE_08BIT, IMX586_MODE_STREAMING);
1355 else
1356 ret = imx586_write_reg(imx586->client, IMX586_REG_CTRL_MODE,
1357 IMX586_REG_VALUE_08BIT, IMX586_MODE_SW_STANDBY);
1358 break;
1359 case RKMODULE_GET_CHANNEL_INFO:
1360 ch_info = (struct rkmodule_channel_info *)arg;
1361 ret = imx586_get_channel_info(imx586, ch_info);
1362 break;
1363 default:
1364 ret = -ENOIOCTLCMD;
1365 break;
1366 }
1367
1368 return ret;
1369 }
1370
1371 #ifdef CONFIG_COMPAT
imx586_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1372 static long imx586_compat_ioctl32(struct v4l2_subdev *sd,
1373 unsigned int cmd, unsigned long arg)
1374 {
1375 void __user *up = compat_ptr(arg);
1376 struct rkmodule_inf *inf;
1377 struct rkmodule_awb_cfg *cfg;
1378 struct rkmodule_hdr_cfg *hdr;
1379 struct preisp_hdrae_exp_s *hdrae;
1380 struct rkmodule_channel_info *ch_info;
1381 long ret;
1382 u32 stream = 0;
1383
1384 switch (cmd) {
1385 case RKMODULE_GET_MODULE_INFO:
1386 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1387 if (!inf) {
1388 ret = -ENOMEM;
1389 return ret;
1390 }
1391
1392 ret = imx586_ioctl(sd, cmd, inf);
1393 if (!ret) {
1394 ret = copy_to_user(up, inf, sizeof(*inf));
1395 if (ret)
1396 ret = -EFAULT;
1397 }
1398 kfree(inf);
1399 break;
1400 case RKMODULE_AWB_CFG:
1401 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1402 if (!cfg) {
1403 ret = -ENOMEM;
1404 return ret;
1405 }
1406
1407 ret = copy_from_user(cfg, up, sizeof(*cfg));
1408 if (!ret)
1409 ret = imx586_ioctl(sd, cmd, cfg);
1410 else
1411 ret = -EFAULT;
1412 kfree(cfg);
1413 break;
1414 case RKMODULE_GET_HDR_CFG:
1415 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1416 if (!hdr) {
1417 ret = -ENOMEM;
1418 return ret;
1419 }
1420
1421 ret = imx586_ioctl(sd, cmd, hdr);
1422 if (!ret) {
1423 ret = copy_to_user(up, hdr, sizeof(*hdr));
1424 if (ret)
1425 ret = -EFAULT;
1426 }
1427 kfree(hdr);
1428 break;
1429 case RKMODULE_SET_HDR_CFG:
1430 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1431 if (!hdr) {
1432 ret = -ENOMEM;
1433 return ret;
1434 }
1435 ret = copy_from_user(hdr, up, sizeof(*hdr));
1436 if (!ret)
1437 ret = imx586_ioctl(sd, cmd, hdr);
1438 else
1439 ret = -EFAULT;
1440 kfree(hdr);
1441 break;
1442 case PREISP_CMD_SET_HDRAE_EXP:
1443 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1444 if (!hdrae) {
1445 ret = -ENOMEM;
1446 return ret;
1447 }
1448 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1449 if (!ret)
1450 ret = imx586_ioctl(sd, cmd, hdrae);
1451 else
1452 ret = -EFAULT;
1453 kfree(hdrae);
1454 break;
1455 case RKMODULE_SET_QUICK_STREAM:
1456 ret = copy_from_user(&stream, up, sizeof(u32));
1457 if (!ret)
1458 ret = imx586_ioctl(sd, cmd, &stream);
1459 else
1460 ret = -EFAULT;
1461 break;
1462 case RKMODULE_GET_CHANNEL_INFO:
1463 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1464 if (!ch_info) {
1465 ret = -ENOMEM;
1466 return ret;
1467 }
1468 ret = imx586_ioctl(sd, cmd, ch_info);
1469 if (!ret) {
1470 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1471 if (ret)
1472 ret = -EFAULT;
1473 }
1474 kfree(ch_info);
1475 break;
1476 default:
1477 ret = -ENOIOCTLCMD;
1478 break;
1479 }
1480
1481 return ret;
1482 }
1483 #endif
1484
imx586_set_flip(struct imx586 * imx586)1485 static int imx586_set_flip(struct imx586 *imx586)
1486 {
1487 int ret = 0;
1488 u32 val = 0;
1489
1490 ret = imx586_read_reg(imx586->client, IMX586_FLIP_MIRROR_REG,
1491 IMX586_REG_VALUE_08BIT, &val);
1492 if (imx586->flip & IMX586_MIRROR_BIT_MASK)
1493 val |= IMX586_MIRROR_BIT_MASK;
1494 else
1495 val &= ~IMX586_MIRROR_BIT_MASK;
1496 if (imx586->flip & IMX586_FLIP_BIT_MASK)
1497 val |= IMX586_FLIP_BIT_MASK;
1498 else
1499 val &= ~IMX586_FLIP_BIT_MASK;
1500 ret |= imx586_write_reg(imx586->client, IMX586_FLIP_MIRROR_REG,
1501 IMX586_REG_VALUE_08BIT, val);
1502
1503 return ret;
1504 }
1505
__imx586_start_stream(struct imx586 * imx586)1506 static int __imx586_start_stream(struct imx586 *imx586)
1507 {
1508 int ret;
1509
1510 ret = imx586_write_array(imx586->client, imx586->cur_mode->global_reg_list);
1511 if (ret)
1512 return ret;
1513
1514 ret = imx586_write_array(imx586->client, imx586->cur_mode->reg_list);
1515 if (ret)
1516 return ret;
1517 imx586->cur_vts = imx586->cur_mode->vts_def;
1518 /* In case these controls are set before streaming */
1519 ret = __v4l2_ctrl_handler_setup(&imx586->ctrl_handler);
1520 if (ret)
1521 return ret;
1522 if (imx586->has_init_exp && imx586->cur_mode->hdr_mode != NO_HDR) {
1523 ret = imx586_ioctl(&imx586->subdev, PREISP_CMD_SET_HDRAE_EXP,
1524 &imx586->init_hdrae_exp);
1525 if (ret) {
1526 dev_err(&imx586->client->dev,
1527 "init exp fail in hdr mode\n");
1528 return ret;
1529 }
1530 }
1531
1532 imx586_set_flip(imx586);
1533
1534 return imx586_write_reg(imx586->client, IMX586_REG_CTRL_MODE,
1535 IMX586_REG_VALUE_08BIT, IMX586_MODE_STREAMING);
1536 }
1537
__imx586_stop_stream(struct imx586 * imx586)1538 static int __imx586_stop_stream(struct imx586 *imx586)
1539 {
1540 return imx586_write_reg(imx586->client, IMX586_REG_CTRL_MODE,
1541 IMX586_REG_VALUE_08BIT, IMX586_MODE_SW_STANDBY);
1542 }
1543
imx586_s_stream(struct v4l2_subdev * sd,int on)1544 static int imx586_s_stream(struct v4l2_subdev *sd, int on)
1545 {
1546 struct imx586 *imx586 = to_imx586(sd);
1547 struct i2c_client *client = imx586->client;
1548 int ret = 0;
1549
1550 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1551 imx586->cur_mode->width,
1552 imx586->cur_mode->height,
1553 DIV_ROUND_CLOSEST(imx586->cur_mode->max_fps.denominator,
1554 imx586->cur_mode->max_fps.numerator));
1555
1556 mutex_lock(&imx586->mutex);
1557 on = !!on;
1558 if (on == imx586->streaming)
1559 goto unlock_and_return;
1560
1561 if (on) {
1562 ret = pm_runtime_get_sync(&client->dev);
1563 if (ret < 0) {
1564 pm_runtime_put_noidle(&client->dev);
1565 goto unlock_and_return;
1566 }
1567
1568 ret = __imx586_start_stream(imx586);
1569 if (ret) {
1570 v4l2_err(sd, "start stream failed while write regs\n");
1571 pm_runtime_put(&client->dev);
1572 goto unlock_and_return;
1573 }
1574 } else {
1575 __imx586_stop_stream(imx586);
1576 pm_runtime_put(&client->dev);
1577 }
1578
1579 imx586->streaming = on;
1580
1581 unlock_and_return:
1582 mutex_unlock(&imx586->mutex);
1583
1584 return ret;
1585 }
1586
imx586_s_power(struct v4l2_subdev * sd,int on)1587 static int imx586_s_power(struct v4l2_subdev *sd, int on)
1588 {
1589 struct imx586 *imx586 = to_imx586(sd);
1590 struct i2c_client *client = imx586->client;
1591 int ret = 0;
1592
1593 mutex_lock(&imx586->mutex);
1594
1595 /* If the power state is not modified - no work to do. */
1596 if (imx586->power_on == !!on)
1597 goto unlock_and_return;
1598
1599 if (on) {
1600 ret = pm_runtime_get_sync(&client->dev);
1601 if (ret < 0) {
1602 pm_runtime_put_noidle(&client->dev);
1603 goto unlock_and_return;
1604 }
1605
1606 imx586->power_on = true;
1607 } else {
1608 pm_runtime_put(&client->dev);
1609 imx586->power_on = false;
1610 }
1611
1612 unlock_and_return:
1613 mutex_unlock(&imx586->mutex);
1614
1615 return ret;
1616 }
1617
1618 /* Calculate the delay in us by clock rate and clock cycles */
imx586_cal_delay(u32 cycles)1619 static inline u32 imx586_cal_delay(u32 cycles)
1620 {
1621 return DIV_ROUND_UP(cycles, IMX586_XVCLK_FREQ / 1000 / 1000);
1622 }
1623
__imx586_power_on(struct imx586 * imx586)1624 static int __imx586_power_on(struct imx586 *imx586)
1625 {
1626 int ret;
1627 u32 delay_us;
1628 struct device *dev = &imx586->client->dev;
1629
1630 ret = clk_set_rate(imx586->xvclk, IMX586_XVCLK_FREQ);
1631 if (ret < 0) {
1632 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
1633 return ret;
1634 }
1635 if (clk_get_rate(imx586->xvclk) != IMX586_XVCLK_FREQ)
1636 dev_warn(dev, "xvclk mismatched, modes are based on 37.125MHz\n");
1637 ret = clk_prepare_enable(imx586->xvclk);
1638 if (ret < 0) {
1639 dev_err(dev, "Failed to enable xvclk\n");
1640 return ret;
1641 }
1642
1643 if (!IS_ERR(imx586->reset_gpio))
1644 gpiod_set_value_cansleep(imx586->reset_gpio, 0);
1645
1646 ret = regulator_bulk_enable(IMX586_NUM_SUPPLIES, imx586->supplies);
1647 if (ret < 0) {
1648 dev_err(dev, "Failed to enable regulators\n");
1649 goto disable_clk;
1650 }
1651
1652 if (!IS_ERR(imx586->reset_gpio))
1653 gpiod_set_value_cansleep(imx586->reset_gpio, 1);
1654
1655 /* need wait 8ms to set register */
1656 usleep_range(8000, 10000);
1657
1658 if (!IS_ERR(imx586->pwdn_gpio))
1659 gpiod_set_value_cansleep(imx586->pwdn_gpio, 1);
1660
1661 /* 8192 cycles prior to first SCCB transaction */
1662 delay_us = imx586_cal_delay(8192);
1663 usleep_range(delay_us, delay_us * 2);
1664
1665 return 0;
1666
1667 disable_clk:
1668 clk_disable_unprepare(imx586->xvclk);
1669
1670 return ret;
1671 }
1672
__imx586_power_off(struct imx586 * imx586)1673 static void __imx586_power_off(struct imx586 *imx586)
1674 {
1675
1676 if (!IS_ERR(imx586->pwdn_gpio))
1677 gpiod_set_value_cansleep(imx586->pwdn_gpio, 0);
1678 clk_disable_unprepare(imx586->xvclk);
1679 if (!IS_ERR(imx586->reset_gpio))
1680 gpiod_set_value_cansleep(imx586->reset_gpio, 0);
1681 regulator_bulk_disable(IMX586_NUM_SUPPLIES, imx586->supplies);
1682 }
1683
imx586_runtime_resume(struct device * dev)1684 static int imx586_runtime_resume(struct device *dev)
1685 {
1686 struct i2c_client *client = to_i2c_client(dev);
1687 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1688 struct imx586 *imx586 = to_imx586(sd);
1689
1690 return __imx586_power_on(imx586);
1691 }
1692
imx586_runtime_suspend(struct device * dev)1693 static int imx586_runtime_suspend(struct device *dev)
1694 {
1695 struct i2c_client *client = to_i2c_client(dev);
1696 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1697 struct imx586 *imx586 = to_imx586(sd);
1698
1699 __imx586_power_off(imx586);
1700
1701 return 0;
1702 }
1703
1704 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx586_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1705 static int imx586_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1706 {
1707 struct imx586 *imx586 = to_imx586(sd);
1708 struct v4l2_mbus_framefmt *try_fmt =
1709 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1710 const struct imx586_mode *def_mode = &supported_modes[0];
1711
1712 mutex_lock(&imx586->mutex);
1713 /* Initialize try_fmt */
1714 try_fmt->width = def_mode->width;
1715 try_fmt->height = def_mode->height;
1716 try_fmt->code = def_mode->bus_fmt;
1717 try_fmt->field = V4L2_FIELD_NONE;
1718
1719 mutex_unlock(&imx586->mutex);
1720 /* No crop or compose */
1721
1722 return 0;
1723 }
1724 #endif
1725
imx586_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1726 static int imx586_enum_frame_interval(struct v4l2_subdev *sd,
1727 struct v4l2_subdev_pad_config *cfg,
1728 struct v4l2_subdev_frame_interval_enum *fie)
1729 {
1730 struct imx586 *imx586 = to_imx586(sd);
1731
1732 if (fie->index >= imx586->cfg_num)
1733 return -EINVAL;
1734
1735 fie->code = supported_modes[fie->index].bus_fmt;
1736 fie->width = supported_modes[fie->index].width;
1737 fie->height = supported_modes[fie->index].height;
1738 fie->interval = supported_modes[fie->index].max_fps;
1739 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1740 return 0;
1741 }
1742
1743 static const struct dev_pm_ops imx586_pm_ops = {
1744 SET_RUNTIME_PM_OPS(imx586_runtime_suspend,
1745 imx586_runtime_resume, NULL)
1746 };
1747
1748 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1749 static const struct v4l2_subdev_internal_ops imx586_internal_ops = {
1750 .open = imx586_open,
1751 };
1752 #endif
1753
1754 static const struct v4l2_subdev_core_ops imx586_core_ops = {
1755 .s_power = imx586_s_power,
1756 .ioctl = imx586_ioctl,
1757 #ifdef CONFIG_COMPAT
1758 .compat_ioctl32 = imx586_compat_ioctl32,
1759 #endif
1760 };
1761
1762 static const struct v4l2_subdev_video_ops imx586_video_ops = {
1763 .s_stream = imx586_s_stream,
1764 .g_frame_interval = imx586_g_frame_interval,
1765 };
1766
1767 static const struct v4l2_subdev_pad_ops imx586_pad_ops = {
1768 .enum_mbus_code = imx586_enum_mbus_code,
1769 .enum_frame_size = imx586_enum_frame_sizes,
1770 .enum_frame_interval = imx586_enum_frame_interval,
1771 .get_fmt = imx586_get_fmt,
1772 .set_fmt = imx586_set_fmt,
1773 .get_mbus_config = imx586_g_mbus_config,
1774 };
1775
1776 static const struct v4l2_subdev_ops imx586_subdev_ops = {
1777 .core = &imx586_core_ops,
1778 .video = &imx586_video_ops,
1779 .pad = &imx586_pad_ops,
1780 };
1781
imx586_set_ctrl(struct v4l2_ctrl * ctrl)1782 static int imx586_set_ctrl(struct v4l2_ctrl *ctrl)
1783 {
1784 struct imx586 *imx586 = container_of(ctrl->handler,
1785 struct imx586, ctrl_handler);
1786 struct i2c_client *client = imx586->client;
1787 s64 max;
1788 int ret = 0;
1789 u32 again = 0;
1790
1791 /* Propagate change of current control to all related controls */
1792 switch (ctrl->id) {
1793 case V4L2_CID_VBLANK:
1794 /* Update max exposure while meeting expected vblanking */
1795 max = imx586->cur_mode->height + ctrl->val - 4;
1796 __v4l2_ctrl_modify_range(imx586->exposure,
1797 imx586->exposure->minimum, max,
1798 imx586->exposure->step,
1799 imx586->exposure->default_value);
1800 break;
1801 }
1802
1803 if (!pm_runtime_get_if_in_use(&client->dev))
1804 return 0;
1805
1806 switch (ctrl->id) {
1807 case V4L2_CID_EXPOSURE:
1808 /* 4 least significant bits of expsoure are fractional part */
1809 ret = imx586_write_reg(imx586->client,
1810 IMX586_REG_EXPOSURE_H,
1811 IMX586_REG_VALUE_08BIT,
1812 IMX586_FETCH_EXP_H(ctrl->val));
1813 ret |= imx586_write_reg(imx586->client,
1814 IMX586_REG_EXPOSURE_L,
1815 IMX586_REG_VALUE_08BIT,
1816 IMX586_FETCH_EXP_L(ctrl->val));
1817 dev_dbg(&client->dev, "set exposure 0x%x\n",
1818 ctrl->val);
1819 break;
1820 case V4L2_CID_ANALOGUE_GAIN:
1821 /* gain_reg = 1024 - 1024 / gain_ana
1822 * manual multiple 16 to add accuracy:
1823 * then formula change to:
1824 * gain_reg = 1024 - 1024 * 16 / (gain_ana * 16)
1825 */
1826 if (ctrl->val > 0x400)
1827 ctrl->val = 0x400;
1828 if (ctrl->val < 0x10)
1829 ctrl->val = 0x10;
1830
1831 again = 1024 - 1024 * 16 / ctrl->val;
1832 ret = imx586_write_reg(imx586->client, IMX586_REG_GAIN_H,
1833 IMX586_REG_VALUE_08BIT,
1834 IMX586_FETCH_AGAIN_H(again));
1835 ret |= imx586_write_reg(imx586->client, IMX586_REG_GAIN_L,
1836 IMX586_REG_VALUE_08BIT,
1837 IMX586_FETCH_AGAIN_L(again));
1838
1839 dev_dbg(&client->dev, "set analog gain 0x%x\n",
1840 ctrl->val);
1841 break;
1842 case V4L2_CID_VBLANK:
1843 ret = imx586_write_reg(imx586->client,
1844 IMX586_REG_VTS_H,
1845 IMX586_REG_VALUE_08BIT,
1846 (ctrl->val + imx586->cur_mode->height)
1847 >> 8);
1848 ret |= imx586_write_reg(imx586->client,
1849 IMX586_REG_VTS_L,
1850 IMX586_REG_VALUE_08BIT,
1851 (ctrl->val + imx586->cur_mode->height)
1852 & 0xff);
1853 imx586->cur_vts = ctrl->val + imx586->cur_mode->height;
1854
1855 dev_dbg(&client->dev, "set vblank 0x%x\n",
1856 ctrl->val);
1857 break;
1858 case V4L2_CID_HFLIP:
1859 if (ctrl->val)
1860 imx586->flip |= IMX586_MIRROR_BIT_MASK;
1861 else
1862 imx586->flip &= ~IMX586_MIRROR_BIT_MASK;
1863 dev_dbg(&client->dev, "set hflip 0x%x\n",
1864 ctrl->val);
1865 break;
1866 case V4L2_CID_VFLIP:
1867 if (ctrl->val)
1868 imx586->flip |= IMX586_FLIP_BIT_MASK;
1869 else
1870 imx586->flip &= ~IMX586_FLIP_BIT_MASK;
1871 dev_dbg(&client->dev, "set vflip 0x%x\n",
1872 ctrl->val);
1873 break;
1874 case V4L2_CID_TEST_PATTERN:
1875 dev_dbg(&client->dev, "set testpattern 0x%x\n",
1876 ctrl->val);
1877 ret = imx586_enable_test_pattern(imx586, ctrl->val);
1878 break;
1879 default:
1880 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1881 __func__, ctrl->id, ctrl->val);
1882 break;
1883 }
1884
1885 pm_runtime_put(&client->dev);
1886
1887 return ret;
1888 }
1889
1890 static const struct v4l2_ctrl_ops imx586_ctrl_ops = {
1891 .s_ctrl = imx586_set_ctrl,
1892 };
1893
imx586_initialize_controls(struct imx586 * imx586)1894 static int imx586_initialize_controls(struct imx586 *imx586)
1895 {
1896 const struct imx586_mode *mode;
1897 struct v4l2_ctrl_handler *handler;
1898 s64 exposure_max, vblank_def;
1899 u32 h_blank;
1900 int ret;
1901
1902 handler = &imx586->ctrl_handler;
1903 mode = imx586->cur_mode;
1904 ret = v4l2_ctrl_handler_init(handler, 9);
1905 if (ret)
1906 return ret;
1907 handler->lock = &imx586->mutex;
1908
1909 imx586->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1910 V4L2_CID_LINK_FREQ,
1911 ARRAY_SIZE(link_freq_items) - 1, 0,
1912 link_freq_items);
1913
1914 if (imx586->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10) {
1915 imx586->cur_link_freq = 0;
1916 imx586->cur_pixel_rate = PIXEL_RATE_WITH_848M_10BIT;
1917 } else if (imx586->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB12_1X12) {
1918 imx586->cur_link_freq = 0;
1919 imx586->cur_pixel_rate = PIXEL_RATE_WITH_848M_12BIT;
1920 }
1921
1922 imx586->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1923 V4L2_CID_PIXEL_RATE,
1924 0, PIXEL_RATE_WITH_848M_10BIT,
1925 1, imx586->cur_pixel_rate);
1926 v4l2_ctrl_s_ctrl(imx586->link_freq,
1927 imx586->cur_link_freq);
1928
1929 h_blank = mode->hts_def - mode->width;
1930 imx586->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1931 h_blank, h_blank, 1, h_blank);
1932 if (imx586->hblank)
1933 imx586->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1934
1935 vblank_def = mode->vts_def - mode->height;
1936 imx586->vblank = v4l2_ctrl_new_std(handler, &imx586_ctrl_ops,
1937 V4L2_CID_VBLANK, vblank_def,
1938 IMX586_VTS_MAX - mode->height,
1939 1, vblank_def);
1940 imx586->cur_vts = mode->vts_def;
1941 exposure_max = mode->vts_def - 4;
1942 imx586->exposure = v4l2_ctrl_new_std(handler, &imx586_ctrl_ops,
1943 V4L2_CID_EXPOSURE,
1944 IMX586_EXPOSURE_MIN,
1945 exposure_max,
1946 IMX586_EXPOSURE_STEP,
1947 mode->exp_def);
1948 imx586->anal_gain = v4l2_ctrl_new_std(handler, &imx586_ctrl_ops,
1949 V4L2_CID_ANALOGUE_GAIN,
1950 IMX586_GAIN_MIN,
1951 IMX586_GAIN_MAX,
1952 IMX586_GAIN_STEP,
1953 IMX586_GAIN_DEFAULT);
1954 imx586->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1955 &imx586_ctrl_ops,
1956 V4L2_CID_TEST_PATTERN,
1957 ARRAY_SIZE(imx586_test_pattern_menu) - 1,
1958 0, 0, imx586_test_pattern_menu);
1959
1960 imx586->h_flip = v4l2_ctrl_new_std(handler, &imx586_ctrl_ops,
1961 V4L2_CID_HFLIP, 0, 1, 1, 0);
1962
1963 imx586->v_flip = v4l2_ctrl_new_std(handler, &imx586_ctrl_ops,
1964 V4L2_CID_VFLIP, 0, 1, 1, 0);
1965 imx586->flip = 0;
1966
1967 if (handler->error) {
1968 ret = handler->error;
1969 dev_err(&imx586->client->dev,
1970 "Failed to init controls( %d )\n", ret);
1971 goto err_free_handler;
1972 }
1973
1974 imx586->subdev.ctrl_handler = handler;
1975 imx586->has_init_exp = false;
1976 return 0;
1977
1978 err_free_handler:
1979 v4l2_ctrl_handler_free(handler);
1980
1981 return ret;
1982 }
1983
imx586_check_sensor_id(struct imx586 * imx586,struct i2c_client * client)1984 static int imx586_check_sensor_id(struct imx586 *imx586,
1985 struct i2c_client *client)
1986 {
1987 struct device *dev = &imx586->client->dev;
1988 u16 id = 0;
1989 u32 reg_H = 0;
1990 u32 reg_L = 0;
1991 int ret;
1992
1993 ret = imx586_read_reg(client, IMX586_REG_CHIP_ID_H,
1994 IMX586_REG_VALUE_08BIT, ®_H);
1995 ret |= imx586_read_reg(client, IMX586_REG_CHIP_ID_L,
1996 IMX586_REG_VALUE_08BIT, ®_L);
1997 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
1998 if (!(reg_H == (CHIP_ID >> 8) || reg_L == (CHIP_ID & 0xff))) {
1999 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
2000 return -ENODEV;
2001 }
2002 dev_info(dev, "detected imx586 %04x sensor\n", id);
2003 return 0;
2004 }
2005
imx586_configure_regulators(struct imx586 * imx586)2006 static int imx586_configure_regulators(struct imx586 *imx586)
2007 {
2008 unsigned int i;
2009
2010 for (i = 0; i < IMX586_NUM_SUPPLIES; i++)
2011 imx586->supplies[i].supply = imx586_supply_names[i];
2012
2013 return devm_regulator_bulk_get(&imx586->client->dev,
2014 IMX586_NUM_SUPPLIES,
2015 imx586->supplies);
2016 }
2017
imx586_probe(struct i2c_client * client,const struct i2c_device_id * id)2018 static int imx586_probe(struct i2c_client *client,
2019 const struct i2c_device_id *id)
2020 {
2021 struct device *dev = &client->dev;
2022 struct device_node *node = dev->of_node;
2023 struct imx586 *imx586;
2024 struct v4l2_subdev *sd;
2025 char facing[2];
2026 int ret;
2027 u32 i, hdr_mode = 0;
2028 struct device_node *eeprom_ctrl_node;
2029 struct i2c_client *eeprom_ctrl_client;
2030 struct v4l2_subdev *eeprom_ctrl;
2031 struct otp_info *otp_ptr;
2032
2033 dev_info(dev, "driver version: %02x.%02x.%02x",
2034 DRIVER_VERSION >> 16,
2035 (DRIVER_VERSION & 0xff00) >> 8,
2036 DRIVER_VERSION & 0x00ff);
2037
2038 imx586 = devm_kzalloc(dev, sizeof(*imx586), GFP_KERNEL);
2039 if (!imx586)
2040 return -ENOMEM;
2041
2042 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2043 &imx586->module_index);
2044 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2045 &imx586->module_facing);
2046 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2047 &imx586->module_name);
2048 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2049 &imx586->len_name);
2050 if (ret) {
2051 dev_err(dev, "could not get module information!\n");
2052 return -EINVAL;
2053 }
2054
2055 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
2056 if (ret) {
2057 hdr_mode = NO_HDR;
2058 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
2059 }
2060
2061 imx586->client = client;
2062 imx586->cfg_num = ARRAY_SIZE(supported_modes);
2063 for (i = 0; i < imx586->cfg_num; i++) {
2064 if (hdr_mode == supported_modes[i].hdr_mode) {
2065 imx586->cur_mode = &supported_modes[i];
2066 break;
2067 }
2068 }
2069
2070 if (i == imx586->cfg_num)
2071 imx586->cur_mode = &supported_modes[0];
2072
2073 imx586->xvclk = devm_clk_get(dev, "xvclk");
2074 if (IS_ERR(imx586->xvclk)) {
2075 dev_err(dev, "Failed to get xvclk\n");
2076 return -EINVAL;
2077 }
2078
2079 imx586->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2080 if (IS_ERR(imx586->reset_gpio))
2081 dev_warn(dev, "Failed to get reset-gpios\n");
2082
2083 imx586->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
2084 if (IS_ERR(imx586->pwdn_gpio))
2085 dev_warn(dev, "Failed to get pwdn-gpios\n");
2086
2087 ret = of_property_read_u32(node,
2088 "rockchip,spd-id",
2089 &imx586->spd_id);
2090 if (ret != 0) {
2091 imx586->spd_id = PAD_MAX;
2092 dev_err(dev,
2093 "failed get spd_id, will not to use spd\n");
2094 }
2095
2096 ret = imx586_configure_regulators(imx586);
2097 if (ret) {
2098 dev_err(dev, "Failed to get power regulators\n");
2099 return ret;
2100 }
2101
2102 mutex_init(&imx586->mutex);
2103
2104 sd = &imx586->subdev;
2105 v4l2_i2c_subdev_init(sd, client, &imx586_subdev_ops);
2106
2107 ret = imx586_initialize_controls(imx586);
2108 if (ret)
2109 goto err_destroy_mutex;
2110
2111 ret = __imx586_power_on(imx586);
2112 if (ret)
2113 goto err_free_handler;
2114
2115 ret = imx586_check_sensor_id(imx586, client);
2116 if (ret)
2117 goto err_power_off;
2118 eeprom_ctrl_node = of_parse_phandle(node, "eeprom-ctrl", 0);
2119 if (eeprom_ctrl_node) {
2120 eeprom_ctrl_client =
2121 of_find_i2c_device_by_node(eeprom_ctrl_node);
2122 of_node_put(eeprom_ctrl_node);
2123 if (IS_ERR_OR_NULL(eeprom_ctrl_client)) {
2124 dev_err(dev, "can not get node\n");
2125 goto continue_probe;
2126 }
2127 eeprom_ctrl = i2c_get_clientdata(eeprom_ctrl_client);
2128 if (IS_ERR_OR_NULL(eeprom_ctrl)) {
2129 dev_err(dev, "can not get eeprom i2c client\n");
2130 } else {
2131 otp_ptr = devm_kzalloc(dev, sizeof(*otp_ptr), GFP_KERNEL);
2132 if (!otp_ptr)
2133 return -ENOMEM;
2134 ret = v4l2_subdev_call(eeprom_ctrl,
2135 core, ioctl, 0, otp_ptr);
2136 if (!ret) {
2137 imx586->otp = otp_ptr;
2138 } else {
2139 imx586->otp = NULL;
2140 devm_kfree(dev, otp_ptr);
2141 }
2142 }
2143 }
2144 continue_probe:
2145
2146 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2147 sd->internal_ops = &imx586_internal_ops;
2148 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2149 #endif
2150 #if defined(CONFIG_MEDIA_CONTROLLER)
2151 imx586->pad.flags = MEDIA_PAD_FL_SOURCE;
2152 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2153 ret = media_entity_pads_init(&sd->entity, 1, &imx586->pad);
2154 if (ret < 0)
2155 goto err_power_off;
2156 #endif
2157
2158 memset(facing, 0, sizeof(facing));
2159 if (strcmp(imx586->module_facing, "back") == 0)
2160 facing[0] = 'b';
2161 else
2162 facing[0] = 'f';
2163
2164 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2165 imx586->module_index, facing,
2166 IMX586_NAME, dev_name(sd->dev));
2167 ret = v4l2_async_register_subdev_sensor_common(sd);
2168 if (ret) {
2169 dev_err(dev, "v4l2 async register subdev failed\n");
2170 goto err_clean_entity;
2171 }
2172
2173 pm_runtime_set_active(dev);
2174 pm_runtime_enable(dev);
2175 pm_runtime_idle(dev);
2176
2177 return 0;
2178
2179 err_clean_entity:
2180 #if defined(CONFIG_MEDIA_CONTROLLER)
2181 media_entity_cleanup(&sd->entity);
2182 #endif
2183 err_power_off:
2184 __imx586_power_off(imx586);
2185 err_free_handler:
2186 v4l2_ctrl_handler_free(&imx586->ctrl_handler);
2187 err_destroy_mutex:
2188 mutex_destroy(&imx586->mutex);
2189
2190 return ret;
2191 }
2192
imx586_remove(struct i2c_client * client)2193 static int imx586_remove(struct i2c_client *client)
2194 {
2195 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2196 struct imx586 *imx586 = to_imx586(sd);
2197
2198 v4l2_async_unregister_subdev(sd);
2199 #if defined(CONFIG_MEDIA_CONTROLLER)
2200 media_entity_cleanup(&sd->entity);
2201 #endif
2202 v4l2_ctrl_handler_free(&imx586->ctrl_handler);
2203 mutex_destroy(&imx586->mutex);
2204
2205 pm_runtime_disable(&client->dev);
2206 if (!pm_runtime_status_suspended(&client->dev))
2207 __imx586_power_off(imx586);
2208 pm_runtime_set_suspended(&client->dev);
2209
2210 return 0;
2211 }
2212
2213 #if IS_ENABLED(CONFIG_OF)
2214 static const struct of_device_id imx586_of_match[] = {
2215 { .compatible = "sony,imx586" },
2216 {},
2217 };
2218 MODULE_DEVICE_TABLE(of, imx586_of_match);
2219 #endif
2220
2221 static const struct i2c_device_id imx586_match_id[] = {
2222 { "sony,imx586", 0 },
2223 { },
2224 };
2225
2226 static struct i2c_driver imx586_i2c_driver = {
2227 .driver = {
2228 .name = IMX586_NAME,
2229 .pm = &imx586_pm_ops,
2230 .of_match_table = of_match_ptr(imx586_of_match),
2231 },
2232 .probe = &imx586_probe,
2233 .remove = &imx586_remove,
2234 .id_table = imx586_match_id,
2235 };
2236
sensor_mod_init(void)2237 static int __init sensor_mod_init(void)
2238 {
2239 return i2c_add_driver(&imx586_i2c_driver);
2240 }
2241
sensor_mod_exit(void)2242 static void __exit sensor_mod_exit(void)
2243 {
2244 i2c_del_driver(&imx586_i2c_driver);
2245 }
2246
2247 device_initcall_sync(sensor_mod_init);
2248 module_exit(sensor_mod_exit);
2249
2250 MODULE_DESCRIPTION("Sony imx586 sensor driver");
2251 MODULE_LICENSE("GPL");
2252