1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx577 camera driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01 add full size 30fps.
9 * V0.0X01.0X02 fix gain and exposure setting.
10 * V0.0X01.0X03
11 * 1.support 10bit HDR DOL2.
12 * 2.4056*3040 @ 25fps
13 * V0.0X01.0X04 add dgain ctrl
14 * V0.0X01.0X05 fix 4056*3040 HDRx2 30fps
15 *
16 */
17
18 // #define DEBUG
19 #include <linux/clk.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/i2c.h>
24 #include <linux/module.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/sysfs.h>
28 #include <linux/slab.h>
29 #include <linux/version.h>
30 #include <linux/compat.h>
31 #include <linux/rk-camera-module.h>
32 #include <media/media-entity.h>
33 #include <media/v4l2-async.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-subdev.h>
36 #include <media/v4l2-fwnode.h>
37 #include <media/v4l2-mediabus.h>
38 #include <linux/of_graph.h>
39 #include <linux/pinctrl/consumer.h>
40 #include <linux/rk-preisp.h>
41
42 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
43
44 #ifndef V4L2_CID_DIGITAL_GAIN
45 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
46 #endif
47
48 #define IMX577_LINK_FREQ_1050MHZ 1050000000U
49 #define IMX577_LINK_FREQ_498MHZ 498000000U
50 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
51 #define IMX577_PIXEL_RATE_1050M_10BIT (IMX577_LINK_FREQ_1050MHZ * 2LL * 4LL / 10LL)
52 #define IMX577_PIXEL_RATE_1050M_12BIT (IMX577_LINK_FREQ_1050MHZ * 2LL * 4LL / 12LL)
53
54 #define IMX577_XVCLK_FREQ 24000000
55
56 #define CHIP_ID 0x0577
57 #define IMX577_REG_CHIP_ID 0x0016
58
59 #define IMX577_REG_CTRL_MODE 0x0100
60 #define IMX577_MODE_SW_STANDBY 0x0
61 #define IMX577_MODE_STREAMING BIT(0)
62
63 #define IMX577_REG_EXPOSURE_H 0x0202
64 #define IMX577_REG_EXPOSURE_L 0x0203
65 #define IMX577_EXPOSURE_MIN 4
66 #define IMX577_EXPOSURE_STEP 1
67 #define IMX577_VTS_MAX 0xffff
68
69 #define IMX577_REG_GAIN_H 0x0204
70 #define IMX577_REG_GAIN_L 0x0205
71 #define IMX577_GAIN_MIN 0x10
72 #define IMX577_GAIN_MAX 0x1600
73 #define IMX577_GAIN_STEP 0x1
74 #define IMX577_GAIN_DEFAULT 0x20
75
76 #define IMX577_REG_DGAIN 0x3ff9
77 #define IMX577_DGAIN_MODE 1
78 #define IMX577_REG_DGAINGR_H 0x020e
79 #define IMX577_REG_DGAINGR_L 0x020f
80 #define IMX577_REG_DGAINR_H 0x0210
81 #define IMX577_REG_DGAINR_L 0x0211
82 #define IMX577_REG_DGAINB_H 0x0212
83 #define IMX577_REG_DGAINB_L 0x0213
84 #define IMX577_REG_DGAINGB_H 0x0214
85 #define IMX577_REG_DGAINGB_L 0x0215
86
87 #define IMX577_LF_GAIN_REG_H 0x00f0
88 #define IMX577_LF_GAIN_REG_L 0x00f1
89 #define IMX577_SEF1_GAIN_REG_H 0x00f2
90 #define IMX577_SEF1_GAIN_REG_L 0x00f3
91 #define IMX577_SEF2_GAIN_REG_H 0x00f4
92 #define IMX577_SEF2_GAIN_REG_L 0x00f5
93
94 #define IMX577_LF_DGAIN_REG_H 0x00f6
95 #define IMX577_LF_DGAIN_REG_L 0x00f7
96 #define IMX577_SEF1_DGAIN_REG_H 0x00f8
97 #define IMX577_SEF1_DGAIN_REG_L 0x00f9
98 #define IMX577_SEF2_DGAIN_REG_H 0x00fa
99 #define IMX577_SEF2_DGAIN_REG_L 0x00fb
100
101 #define IMX577_LF_EXPO_REG_H 0x00ea
102 #define IMX577_LF_EXPO_REG_L 0x00eb
103 #define IMX577_SEF1_EXPO_REG_H 0x00ec
104 #define IMX577_SEF1_EXPO_REG_L 0x00ed
105 #define IMX577_SEF2_EXPO_REG_H 0x00ee
106 #define IMX577_SEF2_EXPO_REG_L 0x00ef
107
108 #define IMX577_RHS1_REG_H 0x00e6
109 #define IMX577_RHS1_REG_L 0x00e7
110 #define IMX577_RHS2_REG_H 0x00e8
111 #define IMX577_RHS2_REG_L 0x00e9
112
113 #define IMX577_REG_TEST_PATTERN 0x0600
114 #define IMX577_TEST_PATTERN_ENABLE 0x02
115 #define IMX577_TEST_PATTERN_DISABLE 0x0
116
117 #define IMX577_REG_VTS 0x0340
118
119 #define IMX577_FETCH_EXP_H(VAL) (((VAL) >> 8) & 0xFF)
120 #define IMX577_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
121
122 #define IMX577_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
123 #define IMX577_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
124
125 #define IMX577_FETCH_DGAIN_H(VAL) (((VAL) >> 8) & 0x0F)
126 #define IMX577_FETCH_DGAIN_L(VAL) ((VAL) & 0xFF)
127
128 #define IMX577_FETCH_GAIN_H(VAL) (((VAL) >> 8) & 0xFF)
129 #define IMX577_FETCH_GAIN_L(VAL) ((VAL) & 0xFF)
130
131 #define IMX577_FETCH_RHS1_H(VAL) (((VAL) >> 8) & 0xFF)
132 #define IMX577_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
133
134 #define REG_NULL 0xFFFF
135
136 #define IMX577_REG_VALUE_08BIT 1
137 #define IMX577_REG_VALUE_16BIT 2
138 #define IMX577_REG_VALUE_24BIT 3
139
140 #define IMX577_GROUP_HOLD_REG 0x0104
141 #define IMX577_GROUP_HOLD_START 0x01
142 #define IMX577_GROUP_HOLD_END 0x00
143
144 /* Basic Readout Lines. Number of necessary readout lines in sensor */
145 #define BRL_FULL 3077
146 #define CIT_MARGIN 22
147
148 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
149 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
150 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
151
152 #define IMX577_NAME "imx577"
153
154 static const char * const imx577_supply_names[] = {
155 "avdd", /* Analog power */
156 "dovdd", /* Digital I/O power */
157 "dvdd", /* Digital core power */
158 };
159
160 #define IMX577_NUM_SUPPLIES ARRAY_SIZE(imx577_supply_names)
161
162 struct regval {
163 u16 addr;
164 u16 val;
165 };
166
167 struct imx577_mode {
168 u32 bus_fmt;
169 u32 width;
170 u32 height;
171 struct v4l2_fract max_fps;
172 u32 hts_def;
173 u32 vts_def;
174 u32 exp_def;
175 u32 link_freq_idx;
176 u32 bpp;
177 const struct regval *reg_list;
178 u32 hdr_mode;
179 u32 vc[PAD_MAX];
180 };
181
182 struct imx577 {
183 struct i2c_client *client;
184 struct clk *xvclk;
185 struct gpio_desc *power_gpio;
186 struct gpio_desc *reset_gpio;
187 struct gpio_desc *pwdn_gpio;
188 struct regulator_bulk_data supplies[IMX577_NUM_SUPPLIES];
189
190 struct pinctrl *pinctrl;
191 struct pinctrl_state *pins_default;
192 struct pinctrl_state *pins_sleep;
193
194 struct v4l2_subdev subdev;
195 struct media_pad pad;
196 struct v4l2_ctrl_handler ctrl_handler;
197 struct v4l2_ctrl *exposure;
198 struct v4l2_ctrl *anal_gain;
199 struct v4l2_ctrl *digi_gain;
200 struct v4l2_ctrl *hblank;
201 struct v4l2_ctrl *vblank;
202 struct v4l2_ctrl *pixel_rate;
203 struct v4l2_ctrl *link_freq;
204 struct v4l2_ctrl *test_pattern;
205 struct mutex mutex;
206 bool streaming;
207 bool power_on;
208 const struct imx577_mode *cur_mode;
209 bool has_init_exp;
210 struct preisp_hdrae_exp_s init_hdrae_exp;
211 u32 cur_pixel_rate;
212 u32 cur_link_freq;
213 u32 module_index;
214 u32 cur_vts;
215 const char *module_facing;
216 const char *module_name;
217 const char *len_name;
218 struct v4l2_fwnode_endpoint bus_cfg;
219 struct rkmodule_awb_cfg awb_cfg;
220 struct rkmodule_lsc_cfg lsc_cfg;
221 };
222
223 #define to_imx577(sd) container_of(sd, struct imx577, subdev)
224
225 static __maybe_unused const struct regval imx577_global_regs[] = {
226 {0x0136, 0x18},
227 {0x0137, 0x00},
228 {0x3C7E, 0x01},
229 {0x3C7F, 0x02},
230 {0x38A8, 0x1F},
231 {0x38A9, 0xFF},
232 {0x38AA, 0x1F},
233 {0x38AB, 0xFF},
234 {0x55D4, 0x00},
235 {0x55D5, 0x00},
236 {0x55D6, 0x07},
237 {0x55D7, 0xFF},
238 {0x55E8, 0x07},
239 {0x55E9, 0xFF},
240 {0x55EA, 0x00},
241 {0x55EB, 0x00},
242 {0x575C, 0x07},
243 {0x575D, 0xFF},
244 {0x575E, 0x00},
245 {0x575F, 0x00},
246 {0x5764, 0x00},
247 {0x5765, 0x00},
248 {0x5766, 0x07},
249 {0x5767, 0xFF},
250 {0x5974, 0x04},
251 {0x5975, 0x01},
252 {0x5F10, 0x09},
253 {0x5F11, 0x92},
254 {0x5F12, 0x32},
255 {0x5F13, 0x72},
256 {0x5F14, 0x16},
257 {0x5F15, 0xBA},
258 {0x5F17, 0x13},
259 {0x5F18, 0x24},
260 {0x5F19, 0x60},
261 {0x5F1A, 0xE3},
262 {0x5F1B, 0xAD},
263 {0x5F1C, 0x74},
264 {0x5F2D, 0x25},
265 {0x5F5C, 0xD0},
266 {0x6A22, 0x00},
267 {0x6A23, 0x1D},
268 {0x7BA8, 0x00},
269 {0x7BA9, 0x00},
270 {0x886B, 0x00},
271 {0x9002, 0x0A},
272 {0x9004, 0x1A},
273 {0x9214, 0x93},
274 {0x9215, 0x69},
275 {0x9216, 0x93},
276 {0x9217, 0x6B},
277 {0x9218, 0x93},
278 {0x9219, 0x6D},
279 {0x921A, 0x57},
280 {0x921B, 0x58},
281 {0x921C, 0x57},
282 {0x921D, 0x59},
283 {0x921E, 0x57},
284 {0x921F, 0x5A},
285 {0x9220, 0x57},
286 {0x9221, 0x5B},
287 {0x9222, 0x93},
288 {0x9223, 0x02},
289 {0x9224, 0x93},
290 {0x9225, 0x03},
291 {0x9226, 0x93},
292 {0x9227, 0x04},
293 {0x9228, 0x93},
294 {0x9229, 0x05},
295 {0x922A, 0x98},
296 {0x922B, 0x21},
297 {0x922C, 0xB2},
298 {0x922D, 0xDB},
299 {0x922E, 0xB2},
300 {0x922F, 0xDC},
301 {0x9230, 0xB2},
302 {0x9231, 0xDD},
303 {0x9232, 0xB2},
304 {0x9233, 0xE1},
305 {0x9234, 0xB2},
306 {0x9235, 0xE2},
307 {0x9236, 0xB2},
308 {0x9237, 0xE3},
309 {0x9238, 0xB7},
310 {0x9239, 0xB9},
311 {0x923A, 0xB7},
312 {0x923B, 0xBB},
313 {0x923C, 0xB7},
314 {0x923D, 0xBC},
315 {0x923E, 0xB7},
316 {0x923F, 0xC5},
317 {0x9240, 0xB7},
318 {0x9241, 0xC7},
319 {0x9242, 0xB7},
320 {0x9243, 0xC9},
321 {0x9244, 0x98},
322 {0x9245, 0x56},
323 {0x9246, 0x98},
324 {0x9247, 0x55},
325 {0x9380, 0x00},
326 {0x9381, 0x62},
327 {0x9382, 0x00},
328 {0x9383, 0x56},
329 {0x9384, 0x00},
330 {0x9385, 0x52},
331 {0x9388, 0x00},
332 {0x9389, 0x55},
333 {0x938A, 0x00},
334 {0x938B, 0x55},
335 {0x938C, 0x00},
336 {0x938D, 0x41},
337 {REG_NULL, 0x00},
338 };
339
340 static __maybe_unused const struct regval imx577_linear_10bit_4056x3040_60fps_regs[] = {
341 {0x0112, 0x0A},
342 {0x0113, 0x0A},
343 {0x0114, 0x03},
344 {0x0342, 0x11},
345 {0x0343, 0xA0},
346 {0x0340, 0x0C},
347 {0x0341, 0x1E},
348 {0x3210, 0x00},
349 {0x0344, 0x00},
350 {0x0345, 0x00},
351 {0x0346, 0x00},
352 {0x0347, 0x00},
353 {0x0348, 0x0F},
354 {0x0349, 0xD7},
355 {0x034A, 0x0B},
356 {0x034B, 0xDF},
357 {0x00E3, 0x00},
358 {0x00E4, 0x00},
359 {0x00E5, 0x01},
360 {0x00FC, 0x0A},
361 {0x00FD, 0x0A},
362 {0x00FE, 0x0A},
363 {0x00FF, 0x0A},
364 {0xE013, 0x00},
365 {0x0220, 0x00},
366 {0x0221, 0x11},
367 {0x0381, 0x01},
368 {0x0383, 0x01},
369 {0x0385, 0x01},
370 {0x0387, 0x01},
371 {0x0900, 0x00},
372 {0x0901, 0x11},
373 {0x0902, 0x00},
374 {0x3140, 0x02},
375 {0x3241, 0x11},
376 {0x3250, 0x03},
377 {0x3E10, 0x00},
378 {0x3E11, 0x00},
379 {0x3F0D, 0x00},
380 {0x3F42, 0x00},
381 {0x3F43, 0x00},
382 {0x0401, 0x00},
383 {0x0404, 0x00},
384 {0x0405, 0x10},
385 {0x0408, 0x00},
386 {0x0409, 0x00},
387 {0x040A, 0x00},
388 {0x040B, 0x00},
389 {0x040C, 0x0F},
390 {0x040D, 0xD8},
391 {0x040E, 0x0B},
392 {0x040F, 0xE0},
393 {0x034C, 0x0F},
394 {0x034D, 0xD8},
395 {0x034E, 0x0B},
396 {0x034F, 0xE0},
397 {0x0301, 0x05},
398 {0x0303, 0x02},
399 {0x0305, 0x04},
400 {0x0306, 0x01},
401 {0x0307, 0x5E},
402 {0x0309, 0x0A},
403 {0x030B, 0x01},
404 {0x030D, 0x02},
405 {0x030E, 0x01},
406 {0x030F, 0x5E},
407 {0x0310, 0x00},
408 {0x0820, 0x20},
409 {0x0821, 0xD0},
410 {0x0822, 0x00},
411 {0x0823, 0x00},
412 {0x3E20, 0x01},
413 {0x3E37, 0x00},
414 {0x3F50, 0x00},
415 {0x3F56, 0x00},
416 {0x3F57, 0x82},
417 {0x3C0A, 0x5A},
418 {0x3C0B, 0x55},
419 {0x3C0C, 0x28},
420 {0x3C0D, 0x07},
421 {0x3C0E, 0xFF},
422 {0x3C0F, 0x00},
423 {0x3C10, 0x00},
424 {0x3C11, 0x02},
425 {0x3C12, 0x00},
426 {0x3C13, 0x03},
427 {0x3C14, 0x00},
428 {0x3C15, 0x00},
429 {0x3C16, 0x0C},
430 {0x3C17, 0x0C},
431 {0x3C18, 0x0C},
432 {0x3C19, 0x0A},
433 {0x3C1A, 0x0A},
434 {0x3C1B, 0x0A},
435 {0x3C1C, 0x00},
436 {0x3C1D, 0x00},
437 {0x3C1E, 0x00},
438 {0x3C1F, 0x00},
439 {0x3C20, 0x00},
440 {0x3C21, 0x00},
441 {0x3C22, 0x3F},
442 {0x3C23, 0x0A},
443 {0x3E35, 0x01},
444 {0x3F4A, 0x03},
445 {0x3F4B, 0xBF},
446 {0x3F26, 0x00},
447 {0x0202, 0x0C},
448 {0x0203, 0x08},
449 {0x0204, 0x00},
450 {0x0205, 0x00},
451 {0x020E, 0x01},
452 {0x020F, 0x00},
453 {0x0210, 0x01},
454 {0x0211, 0x00},
455 {0x0212, 0x01},
456 {0x0213, 0x00},
457 {0x0214, 0x01},
458 {0x0215, 0x00},
459 {REG_NULL, 0x00},
460 };
461
462 static __maybe_unused const struct regval imx577_linear_10bit_4056x3040_30fps_regs[] = {
463 {0x0112, 0x0A},
464 {0x0113, 0x0A},
465 {0x0114, 0x03},
466 {0x0342, 0x23},
467 {0x0343, 0x18},
468 {0x0340, 0x0C},
469 {0x0341, 0x2c},
470 {0x3210, 0x00},
471 {0x0344, 0x00},
472 {0x0345, 0x00},
473 {0x0346, 0x00},
474 {0x0347, 0x00},
475 {0x0348, 0x0F},
476 {0x0349, 0xD7},
477 {0x034A, 0x0B},
478 {0x034B, 0xDF},
479 {0x00E3, 0x00},
480 {0x00E4, 0x00},
481 {0x00E5, 0x01},
482 {0x00FC, 0x0A},
483 {0x00FD, 0x0A},
484 {0x00FE, 0x0A},
485 {0x00FF, 0x0A},
486 {0x0220, 0x00},
487 {0x0221, 0x11},
488 {0x0381, 0x01},
489 {0x0383, 0x01},
490 {0x0385, 0x01},
491 {0x0387, 0x01},
492 {0x0900, 0x00},
493 {0x0901, 0x11},
494 {0x0902, 0x00},
495 {0x3140, 0x02},
496 {0x3241, 0x11},
497 {0x3250, 0x03},
498 {0x3E10, 0x00},
499 {0x3E11, 0x00},
500 {0x3F0D, 0x00},
501 {0x3F42, 0x00},
502 {0x3F43, 0x00},
503 {0x0401, 0x00},
504 {0x0404, 0x00},
505 {0x0405, 0x10},
506 {0x0408, 0x00},
507 {0x0409, 0x00},
508 {0x040A, 0x00},
509 {0x040B, 0x00},
510 {0x040C, 0x0F},
511 {0x040D, 0xD8},
512 {0x040E, 0x0B},
513 {0x040F, 0xE0},
514 {0x034C, 0x0F},
515 {0x034D, 0xD8},
516 {0x034E, 0x0B},
517 {0x034F, 0xE0},
518 {0x0301, 0x05},
519 {0x0303, 0x02},
520 {0x0305, 0x04},
521 {0x0306, 0x01},
522 {0x0307, 0x5E},
523 {0x0309, 0x0A},
524 {0x030B, 0x02},
525 {0x030D, 0x02},
526 {0x030E, 0x00},
527 {0x030F, 0xA6},
528 {0x0310, 0x01},
529 {0x0820, 0x0F},
530 {0x0821, 0x90},
531 {0x0822, 0x00},
532 {0x0823, 0x00},
533 {0x3E20, 0x01},
534 {0x3E37, 0x00},
535 {0x3F50, 0x00},
536 {0x3F56, 0x00},
537 {0x3F57, 0x41},
538 {0x3C0A, 0x5A},
539 {0x3C0B, 0x55},
540 {0x3C0C, 0x28},
541 {0x3C0D, 0x07},
542 {0x3C0E, 0xFF},
543 {0x3C0F, 0x00},
544 {0x3C10, 0x00},
545 {0x3C11, 0x02},
546 {0x3C12, 0x00},
547 {0x3C13, 0x03},
548 {0x3C14, 0x00},
549 {0x3C15, 0x00},
550 {0x3C16, 0x0C},
551 {0x3C17, 0x0C},
552 {0x3C18, 0x0C},
553 {0x3C19, 0x0A},
554 {0x3C1A, 0x0A},
555 {0x3C1B, 0x0A},
556 {0x3C1C, 0x00},
557 {0x3C1D, 0x00},
558 {0x3C1E, 0x00},
559 {0x3C1F, 0x00},
560 {0x3C20, 0x00},
561 {0x3C21, 0x00},
562 {0x3C22, 0x3F},
563 {0x3C23, 0x0A},
564 {0x3E35, 0x01},
565 {0x3F4A, 0x03},
566 {0x3F4B, 0xBF},
567 {0x3F26, 0x00},
568 {0x0202, 0x0C},
569 {0x0203, 0x16},
570 {0x0204, 0x00},
571 {0x0205, 0x00},
572 {0x020E, 0x01},
573 {0x020F, 0x00},
574 {0x0210, 0x01},
575 {0x0211, 0x00},
576 {0x0212, 0x01},
577 {0x0213, 0x00},
578 {0x0214, 0x01},
579 {0x0215, 0x00},
580 {REG_NULL, 0x00},
581 };
582
583 static __maybe_unused const struct regval imx577_hdr2_10bit_4056x3040_15fps_regs[] = {
584 {0x0112, 0x0A},
585 {0x0113, 0x0A},
586 {0x0114, 0x03},
587 {0x0342, 0x11},
588 {0x0343, 0xA0},
589 {0x0340, 0x18},
590 {0x0341, 0x3D},
591 {0x3210, 0x00},
592 {0x0344, 0x00},
593 {0x0345, 0x00},
594 {0x0346, 0x00},
595 {0x0347, 0x00},
596 {0x0348, 0x0F},
597 {0x0349, 0xD7},
598 {0x034A, 0x0B},
599 {0x034B, 0xDF},
600 {0x00E3, 0x01},
601 {0x00E4, 0x01},
602 {0x00E5, 0x00},//vc:0 LI:1
603 {0x00FC, 0x0A},
604 {0x00FD, 0x0A},
605 {0x00FE, 0x0A},
606 {0x00FF, 0x0A},
607 {0xE013, 0x01},//VC:1 LI:0
608 {0x0220, 0x00},
609 {0x0221, 0x11},
610 {0x0381, 0x01},
611 {0x0383, 0x01},
612 {0x0385, 0x01},
613 {0x0387, 0x01},
614 {0x0900, 0x00},
615 {0x0901, 0x11},
616 {0x0902, 0x00},
617 {0x3140, 0x02},
618 {0x3241, 0x11},
619 {0x3250, 0x03},
620 {0x3E10, 0x01},//VC:1 LI:0
621 {0x3E11, 0x02},//VC:2 LI:0
622 {0x3F0D, 0x00},
623 {0x3F42, 0x00},
624 {0x3F43, 0x00},
625 {0x0401, 0x00},
626 {0x0404, 0x00},
627 {0x0405, 0x10},
628 {0x0408, 0x00},
629 {0x0409, 0x00},
630 {0x040A, 0x00},
631 {0x040B, 0x00},
632 {0x040C, 0x0F},
633 {0x040D, 0xD8},
634 {0x040E, 0x0B},
635 {0x040F, 0xE0},
636 {0x034C, 0x0F},
637 {0x034D, 0xDC},
638 {0x034E, 0x0B},
639 {0x034F, 0xE0},
640 {0x0301, 0x05},
641 {0x0303, 0x02},
642 {0x0305, 0x04},
643 {0x0306, 0x01},
644 {0x0307, 0x5E},
645 {0x0309, 0x0A},
646 {0x030B, 0x01},
647 {0x030D, 0x02},
648 {0x030E, 0x01},
649 {0x030F, 0x5E},
650 {0x0310, 0x00},
651 {0x0820, 0x20},
652 {0x0821, 0xD0},
653 {0x0822, 0x00},
654 {0x0823, 0x00},
655 {0x3E20, 0x01},
656 {0x3E37, 0x00},
657 {0x3F50, 0x00},
658 {0x3F56, 0x00},
659 {0x3F57, 0x82},
660 {0x3C0A, 0x5A},
661 {0x3C0B, 0x55},
662 {0x3C0C, 0x28},
663 {0x3C0D, 0x07},
664 {0x3C0E, 0xFF},
665 {0x3C0F, 0x00},
666 {0x3C10, 0x00},
667 {0x3C11, 0x02},
668 {0x3C12, 0x00},
669 {0x3C13, 0x03},
670 {0x3C14, 0x00},
671 {0x3C15, 0x00},
672 {0x3C16, 0x0C},
673 {0x3C17, 0x0C},
674 {0x3C18, 0x0C},
675 {0x3C19, 0x0A},
676 {0x3C1A, 0x0A},
677 {0x3C1B, 0x0A},
678 {0x3C1C, 0x00},
679 {0x3C1D, 0x00},
680 {0x3C1E, 0x00},
681 {0x3C1F, 0x00},
682 {0x3C20, 0x00},
683 {0x3C21, 0x00},
684 {0x3C22, 0x3F},
685 {0x3C23, 0x0A},
686 {0x3E35, 0x01},
687 {0x3F4A, 0x03},
688 {0x3F4B, 0xBF},
689 {0x3F26, 0x00},
690 {0x0202, 0x18},
691 {0x0203, 0x27},
692 {0x0204, 0x00},
693 {0x0205, 0x00},
694 {0x020E, 0x01},
695 {0x020F, 0x00},
696 {0x0210, 0x01},
697 {0x0211, 0x00},
698 {0x0212, 0x01},
699 {0x0213, 0x00},
700 {0x0214, 0x01},
701 {0x0215, 0x00},
702 {REG_NULL, 0x00},
703 };
704
705 static __maybe_unused const struct regval imx577_hdr2_10bit_4056x3040_30fps_regs[] = {
706 {0x0112, 0x0A},
707 {0x0113, 0x0A},
708 {0x0114, 0x03},
709 {0x0342, 0x11},
710 {0x0343, 0xA0},
711 {0x0340, 0x0C},
712 {0x0341, 0x1E},
713 {0x3210, 0x00},
714 {0x0344, 0x00},
715 {0x0345, 0x00},
716 {0x0346, 0x00},
717 {0x0347, 0x00},
718 {0x0348, 0x0F},
719 {0x0349, 0xD7},
720 {0x034A, 0x0B},
721 {0x034B, 0xDF},
722 {0x00E3, 0x01},
723 {0x00E4, 0x01},
724 {0x00E5, 0x00},//vc:0
725 {0x00FC, 0x0A},
726 {0x00FD, 0x0A},
727 {0x00FE, 0x0A},
728 {0x00FF, 0x0A},
729 {0xE013, 0x01},//vc:1
730 {0x0220, 0x00},
731 {0x0221, 0x11},
732 {0x0381, 0x01},
733 {0x0383, 0x01},
734 {0x0385, 0x01},
735 {0x0387, 0x01},
736 {0x0900, 0x00},
737 {0x0901, 0x11},
738 {0x0902, 0x00},
739 {0x3140, 0x02},
740 {0x3241, 0x11},
741 {0x3250, 0x03},
742 {0x3E10, 0x01},//vc:1 li:0
743 {0x3E11, 0x02},//vc:2 li:0
744 {0x3F0D, 0x00},
745 {0x3F42, 0x00},
746 {0x3F43, 0x00},
747 {0x0401, 0x00},
748 {0x0404, 0x00},
749 {0x0405, 0x10},
750 {0x0408, 0x00},
751 {0x0409, 0x00},
752 {0x040A, 0x00},
753 {0x040B, 0x00},
754 {0x040C, 0x0F},
755 {0x040D, 0xD8},
756 {0x040E, 0x0B},
757 {0x040F, 0xE0},
758 {0x034C, 0x0F},
759 {0x034D, 0xDC},
760 {0x034E, 0x0B},
761 {0x034F, 0xE0},
762 {0x0301, 0x05},
763 {0x0303, 0x02},
764 {0x0305, 0x04},
765 {0x0306, 0x01},
766 {0x0307, 0x5E},
767 {0x0309, 0x0A},
768 {0x030B, 0x01},
769 {0x030D, 0x02},
770 {0x030E, 0x01},
771 {0x030F, 0x5E},
772 {0x0310, 0x00},
773 {0x0820, 0x20},
774 {0x0821, 0xD0},
775 {0x0822, 0x00},
776 {0x0823, 0x00},
777 {0x3E20, 0x01},
778 {0x3E37, 0x00},
779 {0x3F50, 0x00},
780 {0x3F56, 0x00},
781 {0x3F57, 0x82},
782 {0x3C0A, 0x5A},
783 {0x3C0B, 0x55},
784 {0x3C0C, 0x28},
785 {0x3C0D, 0x07},
786 {0x3C0E, 0xFF},
787 {0x3C0F, 0x00},
788 {0x3C10, 0x00},
789 {0x3C11, 0x02},
790 {0x3C12, 0x00},
791 {0x3C13, 0x03},
792 {0x3C14, 0x00},
793 {0x3C15, 0x00},
794 {0x3C16, 0x0C},
795 {0x3C17, 0x0C},
796 {0x3C18, 0x0C},
797 {0x3C19, 0x0A},
798 {0x3C1A, 0x0A},
799 {0x3C1B, 0x0A},
800 {0x3C1C, 0x00},
801 {0x3C1D, 0x00},
802 {0x3C1E, 0x00},
803 {0x3C1F, 0x00},
804 {0x3C20, 0x00},
805 {0x3C21, 0x00},
806 {0x3C22, 0x3F},
807 {0x3C23, 0x0A},
808 {0x3E35, 0x01},
809 {0x3F4A, 0x03},
810 {0x3F4B, 0xBF},
811 {0x3F26, 0x00},
812 {0x0202, 0x0C},
813 {0x0203, 0x08},
814 {0x0204, 0x00},
815 {0x0205, 0x00},
816 {0x020E, 0x01},
817 {0x020F, 0x00},
818 {0x0210, 0x01},
819 {0x0211, 0x00},
820 {0x0212, 0x01},
821 {0x0213, 0x00},
822 {0x0214, 0x01},
823 {0x0215, 0x00},
824 {REG_NULL, 0x00},
825 };
826
827 static __maybe_unused const struct regval imx577_linear_12bit_4056x3040_40fps_regs[] = {
828 {0x0112, 0x0C},
829 {0x0113, 0x0C},
830 {0x0114, 0x03},
831 {0x0342, 0x18},
832 {0x0343, 0x50},
833 {0x0340, 0x0D},
834 {0x0341, 0x2E},
835 {0x3210, 0x00},
836 {0x0344, 0x00},
837 {0x0345, 0x00},
838 {0x0346, 0x00},
839 {0x0347, 0x00},
840 {0x0348, 0x0F},
841 {0x0349, 0xD7},
842 {0x034A, 0x0B},
843 {0x034B, 0xDF},
844 {0x00E3, 0x00},
845 {0x00E4, 0x00},
846 {0x00E5, 0x01},
847 {0x00FC, 0x0A},
848 {0x00FD, 0x0A},
849 {0x00FE, 0x0A},
850 {0x00FF, 0x0A},
851 {0xE013, 0x00},
852 {0x0220, 0x00},
853 {0x0221, 0x11},
854 {0x0381, 0x01},
855 {0x0383, 0x01},
856 {0x0385, 0x01},
857 {0x0387, 0x01},
858 {0x0900, 0x00},
859 {0x0901, 0x11},
860 {0x0902, 0x00},
861 {0x3140, 0x02},
862 {0x3241, 0x11},
863 {0x3250, 0x03},
864 {0x3E10, 0x00},
865 {0x3E11, 0x00},
866 {0x3F0D, 0x01},
867 {0x3F42, 0x00},
868 {0x3F43, 0x00},
869 {0x0401, 0x00},
870 {0x0404, 0x00},
871 {0x0405, 0x10},
872 {0x0408, 0x00},
873 {0x0409, 0x00},
874 {0x040A, 0x00},
875 {0x040B, 0x00},
876 {0x040C, 0x0F},
877 {0x040D, 0xD8},
878 {0x040E, 0x0B},
879 {0x040F, 0xE0},
880 {0x034C, 0x0F},
881 {0x034D, 0xD8},
882 {0x034E, 0x0B},
883 {0x034F, 0xE0},
884 {0x0301, 0x05},
885 {0x0303, 0x02},
886 {0x0305, 0x04},
887 {0x0306, 0x01},
888 {0x0307, 0x5E},
889 {0x0309, 0x0C},
890 {0x030B, 0x01},
891 {0x030D, 0x02},
892 {0x030E, 0x01},
893 {0x030F, 0x5E},
894 {0x0310, 0x00},
895 {0x0820, 0x20},
896 {0x0821, 0xD0},
897 {0x0822, 0x00},
898 {0x0823, 0x00},
899 {0x3E20, 0x01},
900 {0x3E37, 0x00},
901 {0x3F50, 0x00},
902 {0x3F56, 0x00},
903 {0x3F57, 0xB2},
904 {0x3C0A, 0x5A},
905 {0x3C0B, 0x55},
906 {0x3C0C, 0x28},
907 {0x3C0D, 0x07},
908 {0x3C0E, 0xFF},
909 {0x3C0F, 0x00},
910 {0x3C10, 0x00},
911 {0x3C11, 0x02},
912 {0x3C12, 0x00},
913 {0x3C13, 0x03},
914 {0x3C14, 0x00},
915 {0x3C15, 0x00},
916 {0x3C16, 0x0C},
917 {0x3C17, 0x0C},
918 {0x3C18, 0x0C},
919 {0x3C19, 0x0A},
920 {0x3C1A, 0x0A},
921 {0x3C1B, 0x0A},
922 {0x3C1C, 0x00},
923 {0x3C1D, 0x00},
924 {0x3C1E, 0x00},
925 {0x3C1F, 0x00},
926 {0x3C20, 0x00},
927 {0x3C21, 0x00},
928 {0x3C22, 0x3F},
929 {0x3C23, 0x0A},
930 {0x3E35, 0x01},
931 {0x3F4A, 0x03},
932 {0x3F4B, 0x85},
933 {0x3F26, 0x00},
934 {0x0202, 0x0D},
935 {0x0203, 0x18},
936 {0x0204, 0x00},
937 {0x0205, 0x00},
938 {0x020E, 0x01},
939 {0x020F, 0x00},
940 {0x0210, 0x01},
941 {0x0211, 0x00},
942 {0x0212, 0x01},
943 {0x0213, 0x00},
944 {0x0214, 0x01},
945 {0x0215, 0x00},
946 {REG_NULL, 0x00},
947 };
948
949 static const struct imx577_mode supported_modes[] = {
950 {
951 .width = 4056,
952 .height = 3040,
953 .max_fps = {
954 .numerator = 10000,
955 .denominator = 300000,
956 },
957 .exp_def = 0x0c10,
958 .hts_def = 0x2318,
959 .vts_def = 0x0c2c,
960 .bpp = 10,
961 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
962 .reg_list = imx577_linear_10bit_4056x3040_30fps_regs,
963 .hdr_mode = NO_HDR,
964 .link_freq_idx = 1,
965 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
966 },
967 {
968 .width = 4056,
969 .height = 3040,
970 .max_fps = {
971 .numerator = 10000,
972 .denominator = 300000,
973 },
974 .exp_def = 0x0c10,
975 .hts_def = 0x11a0,
976 .vts_def = 0x0c1e,
977 .bpp = 10,
978 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
979 .reg_list = imx577_hdr2_10bit_4056x3040_30fps_regs,
980 .link_freq_idx = 0,
981 .hdr_mode = HDR_X2,
982 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
983 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
984 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
985 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
986 },
987 {
988 .width = 4056,
989 .height = 3040,
990 .max_fps = {
991 .numerator = 10000,
992 .denominator = 600000,
993 },
994 .exp_def = 0x0c10,
995 .hts_def = 0x11a0,
996 .vts_def = 0x0c1e,
997 .bpp = 10,
998 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
999 .reg_list = imx577_linear_10bit_4056x3040_60fps_regs,
1000 .hdr_mode = NO_HDR,
1001 .link_freq_idx = 0,
1002 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1003 },
1004 {
1005 .width = 4056,
1006 .height = 3040,
1007 .max_fps = {
1008 .numerator = 10000,
1009 .denominator = 400000,
1010 },
1011 .exp_def = 0x0c10,
1012 .hts_def = 0x11a0,
1013 .vts_def = 0x0d2e,
1014 .bpp = 12,
1015 .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
1016 .reg_list = imx577_linear_12bit_4056x3040_40fps_regs,
1017 .hdr_mode = NO_HDR,
1018 .link_freq_idx = 0,
1019 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1020 },
1021 };
1022
1023 static const s64 link_freq_items[] = {
1024 IMX577_LINK_FREQ_1050MHZ,
1025 IMX577_LINK_FREQ_498MHZ,
1026 };
1027
1028 static const char * const imx577_test_pattern_menu[] = {
1029 "Disabled",
1030 "Vertical Color Bar Type 1",
1031 "Vertical Color Bar Type 2",
1032 "Vertical Color Bar Type 3"
1033 };
1034
1035 /* Write registers up to 4 at a time */
imx577_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)1036 static int imx577_write_reg(struct i2c_client *client, u16 reg,
1037 u32 len, u32 val)
1038 {
1039 u32 buf_i, val_i;
1040 u8 buf[6];
1041 u8 *val_p;
1042 __be32 val_be;
1043
1044 dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
1045
1046 if (len > 4)
1047 return -EINVAL;
1048
1049 buf[0] = reg >> 8;
1050 buf[1] = reg & 0xff;
1051
1052 val_be = cpu_to_be32(val);
1053 val_p = (u8 *)&val_be;
1054 buf_i = 2;
1055 val_i = 4 - len;
1056
1057 while (val_i < 4)
1058 buf[buf_i++] = val_p[val_i++];
1059
1060 if (i2c_master_send(client, buf, len + 2) != len + 2)
1061 return -EIO;
1062
1063 return 0;
1064 }
1065
imx577_write_array(struct i2c_client * client,const struct regval * regs)1066 static int imx577_write_array(struct i2c_client *client,
1067 const struct regval *regs)
1068 {
1069 u32 i;
1070 int ret = 0;
1071
1072 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
1073 ret = imx577_write_reg(client, regs[i].addr,
1074 IMX577_REG_VALUE_08BIT,
1075 regs[i].val);
1076
1077 return ret;
1078 }
1079
1080 /* Read registers up to 4 at a time */
imx577_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)1081 static int imx577_read_reg(struct i2c_client *client, u16 reg,
1082 unsigned int len, u32 *val)
1083 {
1084 struct i2c_msg msgs[2];
1085 u8 *data_be_p;
1086 __be32 data_be = 0;
1087 __be16 reg_addr_be = cpu_to_be16(reg);
1088 int ret;
1089
1090 if (len > 4 || !len)
1091 return -EINVAL;
1092
1093 data_be_p = (u8 *)&data_be;
1094 /* Write register address */
1095 msgs[0].addr = client->addr;
1096 msgs[0].flags = 0;
1097 msgs[0].len = 2;
1098 msgs[0].buf = (u8 *)®_addr_be;
1099
1100 /* Read data from register */
1101 msgs[1].addr = client->addr;
1102 msgs[1].flags = I2C_M_RD;
1103 msgs[1].len = len;
1104 msgs[1].buf = &data_be_p[4 - len];
1105
1106 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1107 if (ret != ARRAY_SIZE(msgs))
1108 return -EIO;
1109
1110 *val = be32_to_cpu(data_be);
1111
1112 return 0;
1113 }
1114
imx577_get_reso_dist(const struct imx577_mode * mode,struct v4l2_mbus_framefmt * framefmt)1115 static int imx577_get_reso_dist(const struct imx577_mode *mode,
1116 struct v4l2_mbus_framefmt *framefmt)
1117 {
1118 return abs(mode->width - framefmt->width) +
1119 abs(mode->height - framefmt->height);
1120 }
1121
1122 static const struct imx577_mode *
imx577_find_best_fit(struct v4l2_subdev_format * fmt)1123 imx577_find_best_fit(struct v4l2_subdev_format *fmt)
1124 {
1125 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1126 int dist;
1127 int cur_best_fit = 0;
1128 int cur_best_fit_dist = -1;
1129 unsigned int i;
1130
1131 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1132 dist = imx577_get_reso_dist(&supported_modes[i], framefmt);
1133 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1134 cur_best_fit_dist = dist;
1135 cur_best_fit = i;
1136 }
1137 }
1138
1139 return &supported_modes[cur_best_fit];
1140 }
1141
imx577_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1142 static int imx577_set_fmt(struct v4l2_subdev *sd,
1143 struct v4l2_subdev_pad_config *cfg,
1144 struct v4l2_subdev_format *fmt)
1145 {
1146 struct imx577 *imx577 = to_imx577(sd);
1147 const struct imx577_mode *mode;
1148 s64 h_blank, vblank_def;
1149 u64 pixel_rate = 0;
1150 u32 lane_num = imx577->bus_cfg.bus.mipi_csi2.num_data_lanes;
1151
1152 mutex_lock(&imx577->mutex);
1153
1154 mode = imx577_find_best_fit(fmt);
1155 fmt->format.code = mode->bus_fmt;
1156 fmt->format.width = mode->width;
1157 fmt->format.height = mode->height;
1158 fmt->format.field = V4L2_FIELD_NONE;
1159 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1160 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1161 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1162 #else
1163 mutex_unlock(&imx577->mutex);
1164 return -ENOTTY;
1165 #endif
1166 } else {
1167 imx577->cur_mode = mode;
1168 imx577->cur_vts = imx577->cur_mode->vts_def;
1169 h_blank = mode->hts_def - mode->width;
1170 __v4l2_ctrl_modify_range(imx577->hblank, h_blank,
1171 h_blank, 1, h_blank);
1172 vblank_def = mode->vts_def - mode->height;
1173 __v4l2_ctrl_modify_range(imx577->vblank, vblank_def,
1174 IMX577_VTS_MAX - mode->height,
1175 1, vblank_def);
1176 pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1177
1178 __v4l2_ctrl_s_ctrl_int64(imx577->pixel_rate,
1179 pixel_rate);
1180 __v4l2_ctrl_s_ctrl(imx577->link_freq,
1181 mode->link_freq_idx);
1182 }
1183
1184 mutex_unlock(&imx577->mutex);
1185
1186 return 0;
1187 }
1188
imx577_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1189 static int imx577_get_fmt(struct v4l2_subdev *sd,
1190 struct v4l2_subdev_pad_config *cfg,
1191 struct v4l2_subdev_format *fmt)
1192 {
1193 struct imx577 *imx577 = to_imx577(sd);
1194 const struct imx577_mode *mode = imx577->cur_mode;
1195
1196 mutex_lock(&imx577->mutex);
1197 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1198 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1199 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1200 #else
1201 mutex_unlock(&imx577->mutex);
1202 return -ENOTTY;
1203 #endif
1204 } else {
1205 fmt->format.width = mode->width;
1206 fmt->format.height = mode->height;
1207 fmt->format.code = mode->bus_fmt;
1208 fmt->format.field = V4L2_FIELD_NONE;
1209 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
1210 fmt->reserved[0] = mode->vc[fmt->pad];
1211 else
1212 fmt->reserved[0] = mode->vc[PAD0];
1213 }
1214 mutex_unlock(&imx577->mutex);
1215
1216 return 0;
1217 }
1218
imx577_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1219 static int imx577_enum_mbus_code(struct v4l2_subdev *sd,
1220 struct v4l2_subdev_pad_config *cfg,
1221 struct v4l2_subdev_mbus_code_enum *code)
1222 {
1223 struct imx577 *imx577 = to_imx577(sd);
1224
1225 if (code->index != 0)
1226 return -EINVAL;
1227 code->code = imx577->cur_mode->bus_fmt;
1228
1229 return 0;
1230 }
1231
imx577_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1232 static int imx577_enum_frame_sizes(struct v4l2_subdev *sd,
1233 struct v4l2_subdev_pad_config *cfg,
1234 struct v4l2_subdev_frame_size_enum *fse)
1235 {
1236 if (fse->index >= ARRAY_SIZE(supported_modes))
1237 return -EINVAL;
1238
1239 if (fse->code != supported_modes[fse->index].bus_fmt)
1240 return -EINVAL;
1241
1242 fse->min_width = supported_modes[fse->index].width;
1243 fse->max_width = supported_modes[fse->index].width;
1244 fse->max_height = supported_modes[fse->index].height;
1245 fse->min_height = supported_modes[fse->index].height;
1246
1247 return 0;
1248 }
1249
imx577_enable_test_pattern(struct imx577 * imx577,u32 pattern)1250 static int imx577_enable_test_pattern(struct imx577 *imx577, u32 pattern)
1251 {
1252 u32 val;
1253
1254 if (pattern)
1255 val = (pattern - 1) | IMX577_TEST_PATTERN_ENABLE;
1256 else
1257 val = IMX577_TEST_PATTERN_DISABLE;
1258
1259 return imx577_write_reg(imx577->client,
1260 IMX577_REG_TEST_PATTERN,
1261 IMX577_REG_VALUE_08BIT,
1262 val);
1263 }
1264
imx577_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1265 static int imx577_g_frame_interval(struct v4l2_subdev *sd,
1266 struct v4l2_subdev_frame_interval *fi)
1267 {
1268 struct imx577 *imx577 = to_imx577(sd);
1269 const struct imx577_mode *mode = imx577->cur_mode;
1270
1271 fi->interval = mode->max_fps;
1272
1273 return 0;
1274 }
1275
imx577_get_module_inf(struct imx577 * imx577,struct rkmodule_inf * inf)1276 static void imx577_get_module_inf(struct imx577 *imx577,
1277 struct rkmodule_inf *inf)
1278 {
1279 memset(inf, 0, sizeof(*inf));
1280 strscpy(inf->base.sensor, IMX577_NAME, sizeof(inf->base.sensor));
1281 strscpy(inf->base.module, imx577->module_name,
1282 sizeof(inf->base.module));
1283 strscpy(inf->base.lens, imx577->len_name, sizeof(inf->base.lens));
1284 }
1285
imx577_set_awb_cfg(struct imx577 * imx577,struct rkmodule_awb_cfg * cfg)1286 static void imx577_set_awb_cfg(struct imx577 *imx577,
1287 struct rkmodule_awb_cfg *cfg)
1288 {
1289 mutex_lock(&imx577->mutex);
1290 memcpy(&imx577->awb_cfg, cfg, sizeof(*cfg));
1291 mutex_unlock(&imx577->mutex);
1292 }
1293
imx577_set_lsc_cfg(struct imx577 * imx577,struct rkmodule_lsc_cfg * cfg)1294 static void imx577_set_lsc_cfg(struct imx577 *imx577,
1295 struct rkmodule_lsc_cfg *cfg)
1296 {
1297 mutex_lock(&imx577->mutex);
1298 memcpy(&imx577->lsc_cfg, cfg, sizeof(*cfg));
1299 mutex_unlock(&imx577->mutex);
1300 }
1301
imx577_set_hdrae(struct imx577 * imx577,struct preisp_hdrae_exp_s * ae)1302 static int imx577_set_hdrae(struct imx577 *imx577,
1303 struct preisp_hdrae_exp_s *ae)
1304 {
1305 struct i2c_client *client = imx577->client;
1306 u32 l_exp_time, m_exp_time, s_exp_time;
1307 u32 l_a_gain, m_a_gain, s_a_gain;
1308 u32 l_d_gain, s_d_gain;
1309 int ret = 0;
1310 u32 fll, dol_cit1, dol_cit2, dol_off2;
1311
1312 if (!imx577->has_init_exp && !imx577->streaming) {
1313 imx577->init_hdrae_exp = *ae;
1314 imx577->has_init_exp = true;
1315 dev_dbg(&imx577->client->dev, "imx577 is not streaming, save hdr ae!\n");
1316 return ret;
1317 }
1318 l_exp_time = ae->long_exp_reg;
1319 m_exp_time = ae->middle_exp_reg;
1320 s_exp_time = ae->short_exp_reg;
1321 l_a_gain = ae->long_gain_reg;
1322 m_a_gain = ae->middle_gain_reg;
1323 s_a_gain = ae->short_gain_reg;
1324 dev_dbg(&client->dev,
1325 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
1326 l_exp_time, m_exp_time, s_exp_time,
1327 l_a_gain, m_a_gain, s_a_gain);
1328
1329 if (imx577->cur_mode->hdr_mode == HDR_X2) {
1330 l_a_gain = m_a_gain;
1331 l_exp_time = m_exp_time;
1332 }
1333
1334 ret = imx577_write_reg(client, IMX577_GROUP_HOLD_REG,
1335 IMX577_REG_VALUE_08BIT, IMX577_GROUP_HOLD_START);
1336 /* gain effect n+1 */
1337 if (l_a_gain > 0x1600)
1338 l_a_gain = 0x1600;
1339 if (l_a_gain < 0x10)
1340 l_a_gain = 0x10;
1341 if (s_a_gain > 0x1600)
1342 s_a_gain = 0x1600;
1343 if (s_a_gain < 0x10)
1344 s_a_gain = 0x10;
1345 l_d_gain = l_a_gain > 0x160 ? (l_a_gain * 256 / 22 / 16) : 256;
1346 l_a_gain = l_a_gain > 0x160 ? 0x160 : l_a_gain;
1347 l_a_gain = 1024 - 1024 * 16 / l_a_gain;
1348 s_d_gain = s_a_gain > 0x160 ? (s_a_gain * 256 / 22 / 16) : 256;
1349 s_a_gain = s_a_gain > 0x160 ? 0x160 : s_a_gain;
1350 s_a_gain = 1024 - 1024 * 16 / s_a_gain;
1351
1352 ret |= imx577_write_reg(client, IMX577_LF_GAIN_REG_H,
1353 IMX577_REG_VALUE_08BIT, IMX577_FETCH_GAIN_H(l_a_gain));
1354 ret |= imx577_write_reg(client, IMX577_LF_GAIN_REG_L,
1355 IMX577_REG_VALUE_08BIT, IMX577_FETCH_GAIN_L(l_a_gain));
1356 ret |= imx577_write_reg(client, IMX577_SEF1_GAIN_REG_H,
1357 IMX577_REG_VALUE_08BIT, IMX577_FETCH_GAIN_H(s_a_gain));
1358 ret |= imx577_write_reg(client, IMX577_SEF1_GAIN_REG_L,
1359 IMX577_REG_VALUE_08BIT, IMX577_FETCH_GAIN_L(s_a_gain));
1360
1361 if (IMX577_DGAIN_MODE && l_d_gain > 0 && s_d_gain > 0) {
1362 ret |= imx577_write_reg(client, IMX577_LF_DGAIN_REG_H,
1363 IMX577_REG_VALUE_08BIT, IMX577_FETCH_DGAIN_H(l_d_gain));
1364 ret |= imx577_write_reg(client, IMX577_LF_DGAIN_REG_L,
1365 IMX577_REG_VALUE_08BIT, IMX577_FETCH_DGAIN_L(l_d_gain));
1366 ret |= imx577_write_reg(client, IMX577_SEF1_DGAIN_REG_H,
1367 IMX577_REG_VALUE_08BIT, IMX577_FETCH_DGAIN_H(s_d_gain));
1368 ret |= imx577_write_reg(client, IMX577_SEF1_DGAIN_REG_L,
1369 IMX577_REG_VALUE_08BIT, IMX577_FETCH_DGAIN_L(s_d_gain));
1370 }
1371
1372 fll = imx577->cur_vts;
1373 dol_cit1 = l_exp_time >> 1;
1374 dol_cit2 = s_exp_time >> 1;
1375
1376 /*dol_cit1 dol_cit2 dol_off2 should be even*/
1377 if (dol_cit1 < 2)
1378 dol_cit1 = 2;
1379 else if (dol_cit1 > fll - 2 * CIT_MARGIN - 2)
1380 dol_cit1 = fll - 2 * CIT_MARGIN - 2;
1381 dol_cit1 &= (~0x1);
1382
1383 if (dol_cit2 < 2)
1384 dol_cit2 = 2;
1385 else if (dol_cit2 > fll - BRL_FULL - CIT_MARGIN)
1386 dol_cit2 = fll - BRL_FULL - CIT_MARGIN;
1387 dol_cit2 &= (~0x1);
1388
1389 dol_off2 = (dol_cit2 + CIT_MARGIN) & (~0x1);
1390 if (dol_off2 < dol_cit2 + CIT_MARGIN)
1391 dol_off2 = (dol_cit2 + CIT_MARGIN) & (~0x1);
1392 else if (dol_off2 > fll - BRL_FULL)
1393 dol_off2 = (fll - BRL_FULL) & (~0x1);
1394
1395 dev_dbg(&client->dev,
1396 "l_exp_time=%d,s_exp_time=%d,fll=%d,rhs1=%d,l_a_gain=%d,s_a_gain=%d\n",
1397 l_exp_time, s_exp_time, fll, dol_off2, l_a_gain, s_a_gain);
1398
1399 ret |= imx577_write_reg(client,
1400 IMX577_RHS1_REG_L,
1401 IMX577_REG_VALUE_08BIT,
1402 IMX577_FETCH_RHS1_L(dol_off2));
1403 ret |= imx577_write_reg(client,
1404 IMX577_RHS1_REG_H,
1405 IMX577_REG_VALUE_08BIT,
1406 IMX577_FETCH_RHS1_H(dol_off2));
1407
1408 ret |= imx577_write_reg(client,
1409 IMX577_SEF1_EXPO_REG_L,
1410 IMX577_REG_VALUE_08BIT,
1411 IMX577_FETCH_EXP_L(dol_cit2));
1412 ret |= imx577_write_reg(client,
1413 IMX577_SEF1_EXPO_REG_H,
1414 IMX577_REG_VALUE_08BIT,
1415 IMX577_FETCH_EXP_H(dol_cit2));
1416 ret |= imx577_write_reg(client,
1417 IMX577_LF_EXPO_REG_L,
1418 IMX577_REG_VALUE_08BIT,
1419 IMX577_FETCH_EXP_L(dol_cit1));
1420 ret |= imx577_write_reg(client,
1421 IMX577_LF_EXPO_REG_H,
1422 IMX577_REG_VALUE_08BIT,
1423 IMX577_FETCH_EXP_H(dol_cit1));
1424
1425 ret |= imx577_write_reg(client, IMX577_GROUP_HOLD_REG,
1426 IMX577_REG_VALUE_08BIT, IMX577_GROUP_HOLD_END);
1427
1428 return ret;
1429 }
1430
imx577_get_channel_info(struct imx577 * imx577,struct rkmodule_channel_info * ch_info)1431 static int imx577_get_channel_info(struct imx577 *imx577, struct rkmodule_channel_info *ch_info)
1432 {
1433 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1434 return -EINVAL;
1435 ch_info->vc = imx577->cur_mode->vc[ch_info->index];
1436 ch_info->width = imx577->cur_mode->width;
1437 ch_info->height = imx577->cur_mode->height;
1438 ch_info->bus_fmt = imx577->cur_mode->bus_fmt;
1439
1440 return 0;
1441 }
1442
imx577_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1443 static long imx577_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1444 {
1445 struct imx577 *imx577 = to_imx577(sd);
1446 struct rkmodule_hdr_cfg *hdr;
1447 struct rkmodule_channel_info *ch_info;
1448 long ret = 0;
1449 u32 i, h, w;
1450 s64 dst_pixel_rate = 0;
1451 u32 stream = 0;
1452 const struct imx577_mode *mode;
1453 u32 lane_num = imx577->bus_cfg.bus.mipi_csi2.num_data_lanes;
1454
1455 switch (cmd) {
1456 case PREISP_CMD_SET_HDRAE_EXP:
1457 if (imx577->cur_mode->hdr_mode == HDR_X2)
1458 ret = imx577_set_hdrae(imx577, arg);
1459 break;
1460 case RKMODULE_GET_MODULE_INFO:
1461 imx577_get_module_inf(imx577, (struct rkmodule_inf *)arg);
1462 break;
1463 case RKMODULE_GET_HDR_CFG:
1464 hdr = (struct rkmodule_hdr_cfg *)arg;
1465 hdr->esp.mode = HDR_NORMAL_VC;
1466 hdr->hdr_mode = imx577->cur_mode->hdr_mode;
1467 break;
1468 case RKMODULE_SET_HDR_CFG:
1469 hdr = (struct rkmodule_hdr_cfg *)arg;
1470 w = imx577->cur_mode->width;
1471 h = imx577->cur_mode->height;
1472 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1473 if (w == supported_modes[i].width &&
1474 h == supported_modes[i].height &&
1475 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1476 imx577->cur_mode = &supported_modes[i];
1477 break;
1478 }
1479 }
1480 if (i == ARRAY_SIZE(supported_modes)) {
1481 dev_err(&imx577->client->dev,
1482 "not find hdr mode:%d %dx%d config\n",
1483 hdr->hdr_mode, w, h);
1484 ret = -EINVAL;
1485 } else {
1486 mode = imx577->cur_mode;
1487 imx577->cur_vts = mode->vts_def;
1488 w = mode->hts_def - mode->width;
1489 h = mode->vts_def - mode->height;
1490 mutex_lock(&imx577->mutex);
1491 __v4l2_ctrl_modify_range(imx577->hblank, w, w, 1, w);
1492 __v4l2_ctrl_modify_range(imx577->vblank, h,
1493 IMX577_VTS_MAX - mode->height,
1494 1, h);
1495 __v4l2_ctrl_s_ctrl(imx577->link_freq, mode->link_freq_idx);
1496 dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] /
1497 mode->bpp * 2 * lane_num;
1498 __v4l2_ctrl_s_ctrl_int64(imx577->pixel_rate,
1499 dst_pixel_rate);
1500 mutex_unlock(&imx577->mutex);
1501 }
1502 break;
1503 case RKMODULE_AWB_CFG:
1504 imx577_set_awb_cfg(imx577, (struct rkmodule_awb_cfg *)arg);
1505 break;
1506 case RKMODULE_LSC_CFG:
1507 imx577_set_lsc_cfg(imx577, (struct rkmodule_lsc_cfg *)arg);
1508 break;
1509 case RKMODULE_SET_QUICK_STREAM:
1510
1511 stream = *((u32 *)arg);
1512
1513 if (stream)
1514 ret = imx577_write_reg(imx577->client,
1515 IMX577_REG_CTRL_MODE,
1516 IMX577_REG_VALUE_08BIT,
1517 IMX577_MODE_STREAMING);
1518 else
1519 ret = imx577_write_reg(imx577->client,
1520 IMX577_REG_CTRL_MODE,
1521 IMX577_REG_VALUE_08BIT,
1522 IMX577_MODE_SW_STANDBY);
1523 break;
1524 case RKMODULE_GET_CHANNEL_INFO:
1525 ch_info = (struct rkmodule_channel_info *)arg;
1526 ret = imx577_get_channel_info(imx577, ch_info);
1527 break;
1528 default:
1529 ret = -ENOIOCTLCMD;
1530 break;
1531 }
1532
1533 return ret;
1534 }
1535
1536 #ifdef CONFIG_COMPAT
imx577_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1537 static long imx577_compat_ioctl32(struct v4l2_subdev *sd,
1538 unsigned int cmd, unsigned long arg)
1539 {
1540 void __user *up = compat_ptr(arg);
1541 struct rkmodule_inf *inf;
1542 struct rkmodule_awb_cfg *cfg;
1543 struct rkmodule_hdr_cfg *hdr;
1544 struct preisp_hdrae_exp_s *hdrae;
1545 struct rkmodule_lsc_cfg *lsc_cfg;
1546 struct rkmodule_channel_info *ch_info;
1547 long ret = 0;
1548 u32 stream = 0;
1549
1550 switch (cmd) {
1551 case RKMODULE_GET_MODULE_INFO:
1552 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1553 if (!inf) {
1554 ret = -ENOMEM;
1555 return ret;
1556 }
1557
1558 ret = imx577_ioctl(sd, cmd, inf);
1559 if (!ret) {
1560 ret = copy_to_user(up, inf, sizeof(*inf));
1561 if (ret)
1562 ret = -EFAULT;
1563 }
1564 kfree(inf);
1565 break;
1566 case RKMODULE_AWB_CFG:
1567 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1568 if (!cfg) {
1569 ret = -ENOMEM;
1570 return ret;
1571 }
1572
1573 ret = copy_from_user(cfg, up, sizeof(*cfg));
1574 if (!ret)
1575 ret = imx577_ioctl(sd, cmd, cfg);
1576 else
1577 ret = -EFAULT;
1578 kfree(cfg);
1579 break;
1580 case RKMODULE_GET_HDR_CFG:
1581 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1582 if (!hdr) {
1583 ret = -ENOMEM;
1584 return ret;
1585 }
1586
1587 ret = imx577_ioctl(sd, cmd, hdr);
1588 if (!ret) {
1589 if (copy_to_user(up, hdr, sizeof(*hdr))) {
1590 kfree(hdr);
1591 return -EFAULT;
1592 }
1593 }
1594 kfree(hdr);
1595 break;
1596 case RKMODULE_SET_HDR_CFG:
1597 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1598 if (!hdr) {
1599 ret = -ENOMEM;
1600 return ret;
1601 }
1602
1603 if (copy_from_user(hdr, up, sizeof(*hdr))) {
1604 kfree(hdr);
1605 return -EFAULT;
1606 }
1607 ret = imx577_ioctl(sd, cmd, hdr);
1608 kfree(hdr);
1609 break;
1610 case PREISP_CMD_SET_HDRAE_EXP:
1611 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1612 if (!hdrae) {
1613 ret = -ENOMEM;
1614 return ret;
1615 }
1616
1617 if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
1618 kfree(hdrae);
1619 return -EFAULT;
1620 }
1621 ret = imx577_ioctl(sd, cmd, hdrae);
1622 kfree(hdrae);
1623 break;
1624 case RKMODULE_LSC_CFG:
1625 lsc_cfg = kzalloc(sizeof(*lsc_cfg), GFP_KERNEL);
1626 if (!lsc_cfg) {
1627 ret = -ENOMEM;
1628 return ret;
1629 }
1630
1631 ret = copy_from_user(lsc_cfg, up, sizeof(*lsc_cfg));
1632 if (!ret)
1633 ret = imx577_ioctl(sd, cmd, lsc_cfg);
1634 else
1635 ret = -EFAULT;
1636 kfree(lsc_cfg);
1637 break;
1638 case RKMODULE_SET_QUICK_STREAM:
1639 ret = copy_from_user(&stream, up, sizeof(u32));
1640 if (!ret)
1641 ret = imx577_ioctl(sd, cmd, &stream);
1642 else
1643 ret = -EFAULT;
1644 break;
1645 case RKMODULE_GET_CHANNEL_INFO:
1646 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1647 if (!ch_info) {
1648 ret = -ENOMEM;
1649 return ret;
1650 }
1651
1652 ret = imx577_ioctl(sd, cmd, ch_info);
1653 if (!ret) {
1654 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1655 if (ret)
1656 ret = -EFAULT;
1657 }
1658 kfree(ch_info);
1659 break;
1660 default:
1661 ret = -ENOIOCTLCMD;
1662 break;
1663 }
1664
1665 return ret;
1666 }
1667 #endif
1668
__imx577_start_stream(struct imx577 * imx577)1669 static int __imx577_start_stream(struct imx577 *imx577)
1670 {
1671 int ret;
1672
1673 ret = imx577_write_array(imx577->client, imx577->cur_mode->reg_list);
1674 if (ret)
1675 return ret;
1676
1677 /* In case these controls are set before streaming */
1678 ret = __v4l2_ctrl_handler_setup(&imx577->ctrl_handler);
1679 if (ret)
1680 return ret;
1681
1682 if (imx577->has_init_exp && imx577->cur_mode->hdr_mode != NO_HDR) {
1683 ret = imx577_ioctl(&imx577->subdev, PREISP_CMD_SET_HDRAE_EXP,
1684 &imx577->init_hdrae_exp);
1685 if (ret) {
1686 dev_err(&imx577->client->dev,
1687 "init exp fail in hdr mode\n");
1688 return ret;
1689 }
1690 }
1691 return imx577_write_reg(imx577->client,
1692 IMX577_REG_CTRL_MODE,
1693 IMX577_REG_VALUE_08BIT,
1694 IMX577_MODE_STREAMING);
1695 }
1696
__imx577_stop_stream(struct imx577 * imx577)1697 static int __imx577_stop_stream(struct imx577 *imx577)
1698 {
1699 imx577->has_init_exp = false;
1700 return imx577_write_reg(imx577->client,
1701 IMX577_REG_CTRL_MODE,
1702 IMX577_REG_VALUE_08BIT,
1703 IMX577_MODE_SW_STANDBY);
1704 }
1705
imx577_s_stream(struct v4l2_subdev * sd,int on)1706 static int imx577_s_stream(struct v4l2_subdev *sd, int on)
1707 {
1708 struct imx577 *imx577 = to_imx577(sd);
1709 struct i2c_client *client = imx577->client;
1710 int ret = 0;
1711
1712 dev_info(&client->dev, "%s: on: %d, %dx%d@%d, hdr: %d, bpp: %d\n",
1713 __func__, on, imx577->cur_mode->width,
1714 imx577->cur_mode->height,
1715 DIV_ROUND_CLOSEST(imx577->cur_mode->max_fps.denominator,
1716 imx577->cur_mode->max_fps.numerator),
1717 imx577->cur_mode->hdr_mode, imx577->cur_mode->bpp);
1718
1719 mutex_lock(&imx577->mutex);
1720 on = !!on;
1721 if (on == imx577->streaming)
1722 goto unlock_and_return;
1723
1724 if (on) {
1725 ret = pm_runtime_get_sync(&client->dev);
1726 if (ret < 0) {
1727 pm_runtime_put_noidle(&client->dev);
1728 goto unlock_and_return;
1729 }
1730
1731 ret = __imx577_start_stream(imx577);
1732 if (ret) {
1733 v4l2_err(sd, "start stream failed while write regs\n");
1734 pm_runtime_put(&client->dev);
1735 goto unlock_and_return;
1736 }
1737 } else {
1738 __imx577_stop_stream(imx577);
1739 pm_runtime_put(&client->dev);
1740 }
1741
1742 imx577->streaming = on;
1743
1744 unlock_and_return:
1745 mutex_unlock(&imx577->mutex);
1746
1747 return ret;
1748 }
1749
imx577_s_power(struct v4l2_subdev * sd,int on)1750 static int imx577_s_power(struct v4l2_subdev *sd, int on)
1751 {
1752 struct imx577 *imx577 = to_imx577(sd);
1753 struct i2c_client *client = imx577->client;
1754 int ret = 0;
1755
1756 mutex_lock(&imx577->mutex);
1757
1758 /* If the power state is not modified - no work to do. */
1759 if (imx577->power_on == !!on)
1760 goto unlock_and_return;
1761
1762 if (on) {
1763 ret = pm_runtime_get_sync(&client->dev);
1764 if (ret < 0) {
1765 pm_runtime_put_noidle(&client->dev);
1766 goto unlock_and_return;
1767 }
1768
1769 ret = imx577_write_array(imx577->client, imx577_global_regs);
1770 if (ret) {
1771 v4l2_err(sd, "could not set init registers\n");
1772 pm_runtime_put_noidle(&client->dev);
1773 goto unlock_and_return;
1774 }
1775
1776 imx577->power_on = true;
1777 } else {
1778 pm_runtime_put(&client->dev);
1779 imx577->power_on = false;
1780 }
1781
1782 unlock_and_return:
1783 mutex_unlock(&imx577->mutex);
1784
1785 return ret;
1786 }
1787
1788 /* Calculate the delay in us by clock rate and clock cycles */
imx577_cal_delay(u32 cycles)1789 static inline u32 imx577_cal_delay(u32 cycles)
1790 {
1791 return DIV_ROUND_UP(cycles, IMX577_XVCLK_FREQ / 1000 / 1000);
1792 }
1793
__imx577_power_on(struct imx577 * imx577)1794 static int __imx577_power_on(struct imx577 *imx577)
1795 {
1796 int ret;
1797 u32 delay_us;
1798 struct device *dev = &imx577->client->dev;
1799
1800 if (!IS_ERR(imx577->power_gpio))
1801 gpiod_set_value_cansleep(imx577->power_gpio, 1);
1802
1803 usleep_range(1000, 2000);
1804
1805 if (!IS_ERR_OR_NULL(imx577->pins_default)) {
1806 ret = pinctrl_select_state(imx577->pinctrl,
1807 imx577->pins_default);
1808 if (ret < 0)
1809 dev_err(dev, "could not set pins\n");
1810 }
1811 ret = clk_set_rate(imx577->xvclk, IMX577_XVCLK_FREQ);
1812 if (ret < 0)
1813 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1814 if (clk_get_rate(imx577->xvclk) != IMX577_XVCLK_FREQ)
1815 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1816 ret = clk_prepare_enable(imx577->xvclk);
1817 if (ret < 0) {
1818 dev_err(dev, "Failed to enable xvclk\n");
1819 return ret;
1820 }
1821 if (!IS_ERR(imx577->reset_gpio))
1822 gpiod_set_value_cansleep(imx577->reset_gpio, 0);
1823
1824 ret = regulator_bulk_enable(IMX577_NUM_SUPPLIES, imx577->supplies);
1825 if (ret < 0) {
1826 dev_err(dev, "Failed to enable regulators\n");
1827 goto disable_clk;
1828 }
1829
1830 if (!IS_ERR(imx577->reset_gpio))
1831 gpiod_set_value_cansleep(imx577->reset_gpio, 1);
1832
1833 usleep_range(500, 1000);
1834 if (!IS_ERR(imx577->pwdn_gpio))
1835 gpiod_set_value_cansleep(imx577->pwdn_gpio, 1);
1836
1837 /* 8192 cycles prior to first SCCB transaction */
1838 delay_us = imx577_cal_delay(8192);
1839 usleep_range(delay_us, delay_us * 2);
1840
1841 return 0;
1842
1843 disable_clk:
1844 clk_disable_unprepare(imx577->xvclk);
1845
1846 return ret;
1847 }
1848
__imx577_power_off(struct imx577 * imx577)1849 static void __imx577_power_off(struct imx577 *imx577)
1850 {
1851 int ret;
1852 struct device *dev = &imx577->client->dev;
1853
1854 if (!IS_ERR(imx577->pwdn_gpio))
1855 gpiod_set_value_cansleep(imx577->pwdn_gpio, 0);
1856 clk_disable_unprepare(imx577->xvclk);
1857 if (!IS_ERR(imx577->reset_gpio))
1858 gpiod_set_value_cansleep(imx577->reset_gpio, 0);
1859
1860 if (!IS_ERR_OR_NULL(imx577->pins_sleep)) {
1861 ret = pinctrl_select_state(imx577->pinctrl,
1862 imx577->pins_sleep);
1863 if (ret < 0)
1864 dev_dbg(dev, "could not set pins\n");
1865 }
1866 if (!IS_ERR(imx577->power_gpio))
1867 gpiod_set_value_cansleep(imx577->power_gpio, 0);
1868
1869 regulator_bulk_disable(IMX577_NUM_SUPPLIES, imx577->supplies);
1870 }
1871
imx577_runtime_resume(struct device * dev)1872 static int imx577_runtime_resume(struct device *dev)
1873 {
1874 struct i2c_client *client = to_i2c_client(dev);
1875 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1876 struct imx577 *imx577 = to_imx577(sd);
1877
1878 return __imx577_power_on(imx577);
1879 }
1880
imx577_runtime_suspend(struct device * dev)1881 static int imx577_runtime_suspend(struct device *dev)
1882 {
1883 struct i2c_client *client = to_i2c_client(dev);
1884 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1885 struct imx577 *imx577 = to_imx577(sd);
1886
1887 __imx577_power_off(imx577);
1888
1889 return 0;
1890 }
1891
1892 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx577_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1893 static int imx577_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1894 {
1895 struct imx577 *imx577 = to_imx577(sd);
1896 struct v4l2_mbus_framefmt *try_fmt =
1897 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1898 const struct imx577_mode *def_mode = &supported_modes[0];
1899
1900 mutex_lock(&imx577->mutex);
1901 /* Initialize try_fmt */
1902 try_fmt->width = def_mode->width;
1903 try_fmt->height = def_mode->height;
1904 try_fmt->code = def_mode->bus_fmt;
1905 try_fmt->field = V4L2_FIELD_NONE;
1906
1907 mutex_unlock(&imx577->mutex);
1908 /* No crop or compose */
1909
1910 return 0;
1911 }
1912 #endif
1913
imx577_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1914 static int imx577_enum_frame_interval(struct v4l2_subdev *sd,
1915 struct v4l2_subdev_pad_config *cfg,
1916 struct v4l2_subdev_frame_interval_enum *fie)
1917 {
1918 if (fie->index >= ARRAY_SIZE(supported_modes))
1919 return -EINVAL;
1920
1921 fie->code = supported_modes[fie->index].bus_fmt;
1922 fie->width = supported_modes[fie->index].width;
1923 fie->height = supported_modes[fie->index].height;
1924 fie->interval = supported_modes[fie->index].max_fps;
1925 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1926
1927 return 0;
1928 }
1929
imx577_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)1930 static int imx577_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1931 struct v4l2_mbus_config *config)
1932 {
1933 struct imx577 *imx577 = to_imx577(sd);
1934 const struct imx577_mode *mode = imx577->cur_mode;
1935 u32 lane_num = imx577->bus_cfg.bus.mipi_csi2.num_data_lanes;
1936 u32 val = 0;
1937
1938 val = 1 << (lane_num - 1) |
1939 V4L2_MBUS_CSI2_CHANNEL_0 |
1940 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1941 if (mode->hdr_mode != NO_HDR)
1942 val |= V4L2_MBUS_CSI2_CHANNEL_1;
1943
1944 config->type = V4L2_MBUS_CSI2_DPHY;
1945 config->flags = val;
1946
1947 return 0;
1948 }
1949
1950 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1951 #define DST_WIDTH_4048 4048
1952
imx577_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1953 static int imx577_get_selection(struct v4l2_subdev *sd,
1954 struct v4l2_subdev_pad_config *cfg,
1955 struct v4l2_subdev_selection *sel)
1956 {
1957 struct imx577 *imx577 = to_imx577(sd);
1958
1959 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1960 if (imx577->cur_mode->width == 4056) {
1961 sel->r.left = CROP_START(imx577->cur_mode->width, DST_WIDTH_4048);
1962 sel->r.width = DST_WIDTH_4048;
1963 sel->r.top = CROP_START(imx577->cur_mode->height, imx577->cur_mode->height);
1964 sel->r.height = imx577->cur_mode->height;
1965 } else {
1966 sel->r.left = CROP_START(imx577->cur_mode->width,
1967 imx577->cur_mode->width);
1968 sel->r.width = imx577->cur_mode->width;
1969 sel->r.top = CROP_START(imx577->cur_mode->height,
1970 imx577->cur_mode->height);
1971 sel->r.height = imx577->cur_mode->height;
1972 }
1973 return 0;
1974 }
1975
1976 return -EINVAL;
1977 }
1978
1979 static const struct dev_pm_ops imx577_pm_ops = {
1980 SET_RUNTIME_PM_OPS(imx577_runtime_suspend,
1981 imx577_runtime_resume, NULL)
1982 };
1983
1984 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1985 static const struct v4l2_subdev_internal_ops imx577_internal_ops = {
1986 .open = imx577_open,
1987 };
1988 #endif
1989
1990 static const struct v4l2_subdev_core_ops imx577_core_ops = {
1991 .s_power = imx577_s_power,
1992 .ioctl = imx577_ioctl,
1993 #ifdef CONFIG_COMPAT
1994 .compat_ioctl32 = imx577_compat_ioctl32,
1995 #endif
1996 };
1997
1998 static const struct v4l2_subdev_video_ops imx577_video_ops = {
1999 .s_stream = imx577_s_stream,
2000 .g_frame_interval = imx577_g_frame_interval,
2001 };
2002
2003 static const struct v4l2_subdev_pad_ops imx577_pad_ops = {
2004 .enum_mbus_code = imx577_enum_mbus_code,
2005 .enum_frame_size = imx577_enum_frame_sizes,
2006 .enum_frame_interval = imx577_enum_frame_interval,
2007 .get_fmt = imx577_get_fmt,
2008 .set_fmt = imx577_set_fmt,
2009 .get_selection = imx577_get_selection,
2010 .get_mbus_config = imx577_g_mbus_config,
2011 };
2012
2013 static const struct v4l2_subdev_ops imx577_subdev_ops = {
2014 .core = &imx577_core_ops,
2015 .video = &imx577_video_ops,
2016 .pad = &imx577_pad_ops,
2017 };
2018
imx577_set_ctrl(struct v4l2_ctrl * ctrl)2019 static int imx577_set_ctrl(struct v4l2_ctrl *ctrl)
2020 {
2021 struct imx577 *imx577 = container_of(ctrl->handler,
2022 struct imx577, ctrl_handler);
2023 struct i2c_client *client = imx577->client;
2024 s64 max;
2025 int ret = 0;
2026 u32 again = 0;
2027 u32 dgain = 0;
2028
2029 /* Propagate change of current control to all related controls */
2030 switch (ctrl->id) {
2031 case V4L2_CID_VBLANK:
2032 if (imx577->cur_mode->hdr_mode == NO_HDR) {
2033 /* Update max exposure while meeting expected vblanking */
2034 max = imx577->cur_mode->height + ctrl->val - 4;
2035 __v4l2_ctrl_modify_range(imx577->exposure,
2036 imx577->exposure->minimum, max,
2037 imx577->exposure->step,
2038 imx577->exposure->default_value);
2039 }
2040 break;
2041 }
2042
2043 if (!pm_runtime_get_if_in_use(&client->dev))
2044 return 0;
2045
2046 switch (ctrl->id) {
2047 case V4L2_CID_EXPOSURE:
2048 /* 4 least significant bits of expsoure are fractional part */
2049 if (imx577->cur_mode->hdr_mode != NO_HDR)
2050 goto ctrl_end;
2051 ret = imx577_write_reg(imx577->client,
2052 IMX577_REG_EXPOSURE_H,
2053 IMX577_REG_VALUE_08BIT,
2054 IMX577_FETCH_EXP_H(ctrl->val));
2055 ret |= imx577_write_reg(imx577->client,
2056 IMX577_REG_EXPOSURE_L,
2057 IMX577_REG_VALUE_08BIT,
2058 IMX577_FETCH_EXP_L(ctrl->val));
2059 dev_dbg(&client->dev, "set exposure 0x%x\n",
2060 ctrl->val);
2061 break;
2062 case V4L2_CID_ANALOGUE_GAIN:
2063 /* gain_reg = 1024 - 1024 / gain_ana
2064 * manual multiple 16 to add accuracy:
2065 * then formula change to:
2066 * gain_reg = 1024 - 1024 * 16 / (gain_ana * 16)
2067 */
2068 if (imx577->cur_mode->hdr_mode != NO_HDR)
2069 goto ctrl_end;
2070 if (ctrl->val > 0x1600)
2071 ctrl->val = 0x1600;
2072 if (ctrl->val < 0x10)
2073 ctrl->val = 0x10;
2074
2075 dgain = ctrl->val > 0x160 ? (ctrl->val * 256 / 22 / 16) : 256;
2076 again = ctrl->val > 0x160 ? 0x160 : ctrl->val;
2077 again = 1024 - 1024 * 16 / again;
2078 ret = imx577_write_reg(imx577->client, IMX577_REG_GAIN_H,
2079 IMX577_REG_VALUE_08BIT,
2080 IMX577_FETCH_AGAIN_H(again));
2081 ret |= imx577_write_reg(imx577->client, IMX577_REG_GAIN_L,
2082 IMX577_REG_VALUE_08BIT,
2083 IMX577_FETCH_AGAIN_L(again));
2084 ret |= imx577_write_reg(imx577->client, IMX577_REG_DGAIN,
2085 IMX577_REG_VALUE_08BIT,
2086 IMX577_DGAIN_MODE);
2087 if (IMX577_DGAIN_MODE && dgain > 0) {
2088 ret |= imx577_write_reg(imx577->client,
2089 IMX577_REG_DGAINGR_H,
2090 IMX577_REG_VALUE_08BIT,
2091 IMX577_FETCH_DGAIN_H(dgain));
2092 ret |= imx577_write_reg(imx577->client,
2093 IMX577_REG_DGAINGR_L,
2094 IMX577_REG_VALUE_08BIT,
2095 IMX577_FETCH_DGAIN_L(dgain));
2096 } else if (dgain > 0) {
2097 ret |= imx577_write_reg(imx577->client,
2098 IMX577_REG_DGAINR_H,
2099 IMX577_REG_VALUE_08BIT,
2100 IMX577_FETCH_DGAIN_H(dgain));
2101 ret |= imx577_write_reg(imx577->client,
2102 IMX577_REG_DGAINR_L,
2103 IMX577_REG_VALUE_08BIT,
2104 IMX577_FETCH_DGAIN_L(dgain));
2105 ret |= imx577_write_reg(imx577->client,
2106 IMX577_REG_DGAINB_H,
2107 IMX577_REG_VALUE_08BIT,
2108 IMX577_FETCH_DGAIN_H(dgain));
2109 ret |= imx577_write_reg(imx577->client,
2110 IMX577_REG_DGAINB_L,
2111 IMX577_REG_VALUE_08BIT,
2112 IMX577_FETCH_DGAIN_L(dgain));
2113 ret |= imx577_write_reg(imx577->client,
2114 IMX577_REG_DGAINGB_H,
2115 IMX577_REG_VALUE_08BIT,
2116 IMX577_FETCH_DGAIN_H(dgain));
2117 ret |= imx577_write_reg(imx577->client,
2118 IMX577_REG_DGAINGB_L,
2119 IMX577_REG_VALUE_08BIT,
2120 IMX577_FETCH_DGAIN_L(dgain));
2121 }
2122 dev_dbg(&client->dev, "set analog gain 0x%x\n",
2123 ctrl->val);
2124 break;
2125 case V4L2_CID_VBLANK:
2126 ret = imx577_write_reg(imx577->client,
2127 IMX577_REG_VTS,
2128 IMX577_REG_VALUE_16BIT,
2129 ctrl->val + imx577->cur_mode->height);
2130 break;
2131 case V4L2_CID_TEST_PATTERN:
2132 ret = imx577_enable_test_pattern(imx577, ctrl->val);
2133 break;
2134 default:
2135 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
2136 __func__, ctrl->id, ctrl->val);
2137 break;
2138 }
2139
2140 ctrl_end:
2141 pm_runtime_put(&client->dev);
2142
2143 return ret;
2144 }
2145
2146 static const struct v4l2_ctrl_ops imx577_ctrl_ops = {
2147 .s_ctrl = imx577_set_ctrl,
2148 };
2149
imx577_initialize_controls(struct imx577 * imx577)2150 static int imx577_initialize_controls(struct imx577 *imx577)
2151 {
2152 const struct imx577_mode *mode;
2153 struct v4l2_ctrl_handler *handler;
2154 s64 exposure_max, vblank_def;
2155 u32 h_blank;
2156 int ret;
2157
2158 handler = &imx577->ctrl_handler;
2159 mode = imx577->cur_mode;
2160 ret = v4l2_ctrl_handler_init(handler, 8);
2161 if (ret)
2162 return ret;
2163 handler->lock = &imx577->mutex;
2164
2165 imx577->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
2166 V4L2_CID_LINK_FREQ,
2167 ARRAY_SIZE(link_freq_items) - 1, 0,
2168 link_freq_items);
2169
2170 if (imx577->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10) {
2171 imx577->cur_link_freq = 0;
2172 imx577->cur_pixel_rate = IMX577_PIXEL_RATE_1050M_10BIT;
2173 } else if (imx577->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB12_1X12) {
2174 imx577->cur_link_freq = 0;
2175 imx577->cur_pixel_rate = IMX577_PIXEL_RATE_1050M_12BIT;
2176 }
2177
2178 imx577->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
2179 V4L2_CID_PIXEL_RATE,
2180 0, IMX577_PIXEL_RATE_1050M_10BIT,
2181 1, imx577->cur_pixel_rate);
2182
2183 __v4l2_ctrl_s_ctrl(imx577->link_freq,
2184 mode->link_freq_idx);
2185
2186 h_blank = mode->hts_def - mode->width;
2187 imx577->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
2188 h_blank, h_blank, 1, h_blank);
2189 if (imx577->hblank)
2190 imx577->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2191
2192 vblank_def = mode->vts_def - mode->height;
2193 imx577->vblank = v4l2_ctrl_new_std(handler, &imx577_ctrl_ops,
2194 V4L2_CID_VBLANK, vblank_def,
2195 IMX577_VTS_MAX - mode->height,
2196 1, vblank_def);
2197 imx577->cur_vts = mode->vts_def;
2198 exposure_max = mode->vts_def - 4;
2199 imx577->exposure = v4l2_ctrl_new_std(handler, &imx577_ctrl_ops,
2200 V4L2_CID_EXPOSURE, IMX577_EXPOSURE_MIN,
2201 exposure_max, IMX577_EXPOSURE_STEP,
2202 mode->exp_def);
2203
2204 imx577->anal_gain = v4l2_ctrl_new_std(handler, &imx577_ctrl_ops,
2205 V4L2_CID_ANALOGUE_GAIN, IMX577_GAIN_MIN,
2206 IMX577_GAIN_MAX, IMX577_GAIN_STEP,
2207 IMX577_GAIN_DEFAULT);
2208
2209 imx577->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
2210 &imx577_ctrl_ops, V4L2_CID_TEST_PATTERN,
2211 ARRAY_SIZE(imx577_test_pattern_menu) - 1,
2212 0, 0, imx577_test_pattern_menu);
2213
2214 if (handler->error) {
2215 ret = handler->error;
2216 dev_err(&imx577->client->dev,
2217 "Failed to init controls(%d)\n", ret);
2218 goto err_free_handler;
2219 }
2220
2221 imx577->subdev.ctrl_handler = handler;
2222 imx577->has_init_exp = false;
2223
2224 return 0;
2225
2226 err_free_handler:
2227 v4l2_ctrl_handler_free(handler);
2228
2229 return ret;
2230 }
2231
imx577_check_sensor_id(struct imx577 * imx577,struct i2c_client * client)2232 static int imx577_check_sensor_id(struct imx577 *imx577,
2233 struct i2c_client *client)
2234 {
2235 struct device *dev = &imx577->client->dev;
2236 u32 id = 0;
2237 int ret;
2238
2239 ret = imx577_read_reg(client, IMX577_REG_CHIP_ID,
2240 IMX577_REG_VALUE_16BIT, &id);
2241 if (id != CHIP_ID) {
2242 dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
2243 return -ENODEV;
2244 }
2245
2246 dev_info(dev, "Detected Sony imx%04x sensor\n", CHIP_ID);
2247
2248 return 0;
2249 }
2250
imx577_configure_regulators(struct imx577 * imx577)2251 static int imx577_configure_regulators(struct imx577 *imx577)
2252 {
2253 unsigned int i;
2254
2255 for (i = 0; i < IMX577_NUM_SUPPLIES; i++)
2256 imx577->supplies[i].supply = imx577_supply_names[i];
2257
2258 return devm_regulator_bulk_get(&imx577->client->dev,
2259 IMX577_NUM_SUPPLIES,
2260 imx577->supplies);
2261 }
2262
imx577_probe(struct i2c_client * client,const struct i2c_device_id * id)2263 static int imx577_probe(struct i2c_client *client,
2264 const struct i2c_device_id *id)
2265 {
2266 struct device *dev = &client->dev;
2267 struct device_node *node = dev->of_node;
2268 struct imx577 *imx577;
2269 struct v4l2_subdev *sd;
2270 struct device_node *endpoint;
2271 char facing[2];
2272 int ret;
2273 u32 i, hdr_mode = 0;
2274
2275 dev_info(dev, "driver version: %02x.%02x.%02x",
2276 DRIVER_VERSION >> 16,
2277 (DRIVER_VERSION & 0xff00) >> 8,
2278 DRIVER_VERSION & 0x00ff);
2279
2280 imx577 = devm_kzalloc(dev, sizeof(*imx577), GFP_KERNEL);
2281 if (!imx577)
2282 return -ENOMEM;
2283
2284 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2285 &imx577->module_index);
2286 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2287 &imx577->module_facing);
2288 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2289 &imx577->module_name);
2290 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2291 &imx577->len_name);
2292 if (ret) {
2293 dev_err(dev, "could not get module information!\n");
2294 return -EINVAL;
2295 }
2296
2297 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
2298 if (ret) {
2299 hdr_mode = NO_HDR;
2300 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
2301 }
2302
2303 imx577->client = client;
2304 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
2305 if (hdr_mode == supported_modes[i].hdr_mode) {
2306 imx577->cur_mode = &supported_modes[i];
2307 break;
2308 }
2309 }
2310
2311 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
2312 if (!endpoint) {
2313 dev_err(dev, "Failed to get endpoint\n");
2314 return -EINVAL;
2315 }
2316 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
2317 &imx577->bus_cfg);
2318 if (ret) {
2319 dev_err(dev, "Failed to get bus cfg\n");
2320 return ret;
2321 }
2322
2323 imx577->xvclk = devm_clk_get(dev, "xvclk");
2324 if (IS_ERR(imx577->xvclk)) {
2325 dev_err(dev, "Failed to get xvclk\n");
2326 return -EINVAL;
2327 }
2328
2329 imx577->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
2330 if (IS_ERR(imx577->power_gpio))
2331 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
2332
2333 imx577->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2334 if (IS_ERR(imx577->reset_gpio))
2335 dev_warn(dev, "Failed to get reset-gpios\n");
2336
2337 imx577->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
2338 if (IS_ERR(imx577->pwdn_gpio))
2339 dev_warn(dev, "Failed to get pwdn-gpios\n");
2340
2341 ret = imx577_configure_regulators(imx577);
2342 if (ret) {
2343 dev_err(dev, "Failed to get power regulators\n");
2344 return ret;
2345 }
2346
2347 imx577->pinctrl = devm_pinctrl_get(dev);
2348 if (!IS_ERR(imx577->pinctrl)) {
2349 imx577->pins_default =
2350 pinctrl_lookup_state(imx577->pinctrl,
2351 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2352 if (IS_ERR(imx577->pins_default))
2353 dev_err(dev, "could not get default pinstate\n");
2354
2355 imx577->pins_sleep =
2356 pinctrl_lookup_state(imx577->pinctrl,
2357 OF_CAMERA_PINCTRL_STATE_SLEEP);
2358 if (IS_ERR(imx577->pins_sleep))
2359 dev_err(dev, "could not get sleep pinstate\n");
2360 }
2361
2362 mutex_init(&imx577->mutex);
2363
2364 sd = &imx577->subdev;
2365 v4l2_i2c_subdev_init(sd, client, &imx577_subdev_ops);
2366 ret = imx577_initialize_controls(imx577);
2367 if (ret)
2368 goto err_destroy_mutex;
2369
2370 ret = __imx577_power_on(imx577);
2371 if (ret)
2372 goto err_free_handler;
2373
2374 ret = imx577_check_sensor_id(imx577, client);
2375 if (ret)
2376 goto err_power_off;
2377
2378 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2379 sd->internal_ops = &imx577_internal_ops;
2380 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2381 V4L2_SUBDEV_FL_HAS_EVENTS;
2382 #endif
2383 #if defined(CONFIG_MEDIA_CONTROLLER)
2384 imx577->pad.flags = MEDIA_PAD_FL_SOURCE;
2385 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2386 ret = media_entity_pads_init(&sd->entity, 1, &imx577->pad);
2387 if (ret < 0)
2388 goto err_power_off;
2389 #endif
2390
2391 memset(facing, 0, sizeof(facing));
2392 if (strcmp(imx577->module_facing, "back") == 0)
2393 facing[0] = 'b';
2394 else
2395 facing[0] = 'f';
2396
2397 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2398 imx577->module_index, facing,
2399 IMX577_NAME, dev_name(sd->dev));
2400 ret = v4l2_async_register_subdev_sensor_common(sd);
2401 if (ret) {
2402 dev_err(dev, "v4l2 async register subdev failed\n");
2403 goto err_clean_entity;
2404 }
2405
2406 pm_runtime_set_active(dev);
2407 pm_runtime_enable(dev);
2408 pm_runtime_idle(dev);
2409
2410 return 0;
2411
2412 err_clean_entity:
2413 #if defined(CONFIG_MEDIA_CONTROLLER)
2414 media_entity_cleanup(&sd->entity);
2415 #endif
2416 err_power_off:
2417 __imx577_power_off(imx577);
2418 err_free_handler:
2419 v4l2_ctrl_handler_free(&imx577->ctrl_handler);
2420 err_destroy_mutex:
2421 mutex_destroy(&imx577->mutex);
2422
2423 return ret;
2424 }
2425
imx577_remove(struct i2c_client * client)2426 static int imx577_remove(struct i2c_client *client)
2427 {
2428 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2429 struct imx577 *imx577 = to_imx577(sd);
2430
2431 v4l2_async_unregister_subdev(sd);
2432 #if defined(CONFIG_MEDIA_CONTROLLER)
2433 media_entity_cleanup(&sd->entity);
2434 #endif
2435 v4l2_ctrl_handler_free(&imx577->ctrl_handler);
2436 mutex_destroy(&imx577->mutex);
2437
2438 pm_runtime_disable(&client->dev);
2439 if (!pm_runtime_status_suspended(&client->dev))
2440 __imx577_power_off(imx577);
2441 pm_runtime_set_suspended(&client->dev);
2442
2443 return 0;
2444 }
2445
2446 #if IS_ENABLED(CONFIG_OF)
2447 static const struct of_device_id imx577_of_match[] = {
2448 { .compatible = "sony,imx577" },
2449 {},
2450 };
2451 MODULE_DEVICE_TABLE(of, imx577_of_match);
2452 #endif
2453
2454 static const struct i2c_device_id imx577_match_id[] = {
2455 { "sony,imx577", 0 },
2456 {},
2457 };
2458
2459 static struct i2c_driver imx577_i2c_driver = {
2460 .driver = {
2461 .name = IMX577_NAME,
2462 .pm = &imx577_pm_ops,
2463 .of_match_table = of_match_ptr(imx577_of_match),
2464 },
2465 .probe = &imx577_probe,
2466 .remove = &imx577_remove,
2467 .id_table = imx577_match_id,
2468 };
2469
sensor_mod_init(void)2470 static int __init sensor_mod_init(void)
2471 {
2472 return i2c_add_driver(&imx577_i2c_driver);
2473 }
2474
sensor_mod_exit(void)2475 static void __exit sensor_mod_exit(void)
2476 {
2477 i2c_del_driver(&imx577_i2c_driver);
2478 }
2479
2480 device_initcall_sync(sensor_mod_init);
2481 module_exit(sensor_mod_exit);
2482
2483 MODULE_DESCRIPTION("Sony imx577 sensor driver");
2484 MODULE_LICENSE("GPL");
2485