1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx335 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version
8 * V0.0X01.0X01 support 10bit DOL3
9 * V0.0X01.0X02 fix set sensor vertical invert failed
10 * V0.0X01.0X03 add hdr_mode in enum frame interval
11 * V0.0X01.0X04 fix hdr ae error
12 * V0.0X01.0X05 add quick stream on/off
13 * V0.0X01.0X06 Increase hdr exposure restrictions
14 */
15
16 #define DEBUG
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/i2c.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/sysfs.h>
26 #include <linux/slab.h>
27 #include <linux/version.h>
28 #include <linux/rk-camera-module.h>
29 #include <media/media-entity.h>
30 #include <media/v4l2-async.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-subdev.h>
33 #include <linux/pinctrl/consumer.h>
34 #include <linux/rk-preisp.h>
35
36 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
37
38 #ifndef V4L2_CID_DIGITAL_GAIN
39 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
40 #endif
41
42 #define MIPI_FREQ_594M 594000000
43
44 #define IMX335_4LANES 4
45
46 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
47
48 #define IMX335_XVCLK_FREQ_37M 37125000
49
50 /* TODO: Get the real chip id from reg */
51 #define CHIP_ID 0x03
52 #define IMX335_REG_CHIP_ID 0x3A01
53
54 #define IMX335_REG_CTRL_MODE 0x3000
55 #define IMX335_MODE_SW_STANDBY BIT(0)
56 #define IMX335_MODE_STREAMING 0x0
57
58 #define IMX335_LF_GAIN_REG_H 0x30E9
59 #define IMX335_LF_GAIN_REG_L 0x30E8
60
61 #define IMX335_SF1_GAIN_REG_H 0x30EB
62 #define IMX335_SF1_GAIN_REG_L 0x30EA
63
64 #define IMX335_SF2_GAIN_REG_H 0x30ED
65 #define IMX335_SF2_GAIN_REG_L 0x30EC
66
67 #define IMX335_LF_EXPO_REG_H 0x305A
68 #define IMX335_LF_EXPO_REG_M 0x3059
69 #define IMX335_LF_EXPO_REG_L 0x3058
70
71 #define IMX335_SF1_EXPO_REG_H 0x305E
72 #define IMX335_SF1_EXPO_REG_M 0x305D
73 #define IMX335_SF1_EXPO_REG_L 0x305C
74
75 #define IMX335_RHS1_REG_H 0x306A
76 #define IMX335_RHS1_REG_M 0x3069
77 #define IMX335_RHS1_REG_L 0x3068
78 #define IMX335_RHS1_DEFAULT 0x0122
79 #define IMX335_RHS1_X3_DEFAULT 0x012E
80
81 #define IMX335_SF2_EXPO_REG_H 0x3062
82 #define IMX335_SF2_EXPO_REG_M 0x3061
83 #define IMX335_SF2_EXPO_REG_L 0x3060
84
85 #define IMX335_RHS2_REG_H 0x306E
86 #define IMX335_RHS2_REG_M 0x306D
87 #define IMX335_RHS2_REG_L 0x306C
88 #define IMX335_RHS2_X3_DEFAULT 0x016C
89
90 /*
91 * The linear shr0 shall be:
92 * 9 <= shr0 <= VMAX - 1.
93 * 1 <= expo = VMAX - shr0 <= VMAX - 9
94 * == VMAX - SHR0_MIN
95 *
96 */
97 #define IMX335_EXPOSURE_MIN 1
98 #define IMX335_EXPOSURE_STEP 1
99 #define SHR0_MIN 9
100 #define IMX335_VTS_MAX 0x7fff
101
102 #define IMX335_GAIN_MIN 0x00
103 #define IMX335_GAIN_MAX 0xf0
104 #define IMX335_GAIN_STEP 1
105 #define IMX335_GAIN_DEFAULT 0x00
106
107 #define IMX335_FETCH_GAIN_H(VAL) (((VAL) >> 8) & 0x07)
108 #define IMX335_FETCH_GAIN_L(VAL) ((VAL) & 0xFF)
109
110 #define IMX335_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0x0F)
111 #define IMX335_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF)
112 #define IMX335_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
113
114 #define IMX335_FETCH_RHS1_H(VAL) (((VAL) >> 16) & 0x0F)
115 #define IMX335_FETCH_RHS1_M(VAL) (((VAL) >> 8) & 0xFF)
116 #define IMX335_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
117
118 #define IMX335_FETCH_VTS_H(VAL) (((VAL) >> 16) & 0x0F)
119 #define IMX335_FETCH_VTS_M(VAL) (((VAL) >> 8) & 0xFF)
120 #define IMX335_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
121
122 #define IMX335_VTS_REG_L 0x3030
123 #define IMX335_VTS_REG_M 0x3031
124 #define IMX335_VTS_REG_H 0x3032
125
126 #define IMX335_HREVERSE_REG 0x304E
127 #define IMX335_VREVERSE_REG 0x304F
128
129 #define REG_NULL 0xFFFF
130
131 #define IMX335_REG_VALUE_08BIT 1
132 #define IMX335_REG_VALUE_16BIT 2
133 #define IMX335_REG_VALUE_24BIT 3
134
135 #define IMX335_GROUP_HOLD_REG 0x3001
136 #define IMX335_GROUP_HOLD_START 0x01
137 #define IMX335_GROUP_HOLD_END 0x00
138
139 /* Basic Readout Lines. Number of necessary readout lines in sensor */
140 #define BRL (1984u * 2)
141 #define RHS1_MAX (BRL * 2 - 1)
142 #define SHR1_MIN 18u
143
144 /* Readout timing setting of SEF1(DOL3): RHS1 < 3 * BRL and should be 12n + 2 */
145 #define RHS1_MAX_X3 ((BRL * 3 - 1) / 12 * 12 + 2)
146 #define SHR1_MIN_X3 26u
147
148 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
149 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
150
151 #define IMX335_NAME "imx335"
152
153 static const char * const imx335_supply_names[] = {
154 "dvdd", /* Digital core power */
155 "dovdd", /* Digital I/O power */
156 "avdd", /* Analog power */
157 };
158
159 #define IMX335_NUM_SUPPLIES ARRAY_SIZE(imx335_supply_names)
160
161 struct regval {
162 u16 addr;
163 u8 val;
164 };
165
166 struct imx335_mode {
167 u32 bus_fmt;
168 u32 width;
169 u32 height;
170 struct v4l2_fract max_fps;
171 u32 hts_def;
172 u32 vts_def;
173 u32 exp_def;
174 u32 bpp;
175 const struct regval *reg_list;
176 u32 hdr_mode;
177 u32 vc[PAD_MAX];
178 };
179
180 struct imx335 {
181 struct i2c_client *client;
182 struct clk *xvclk;
183 struct gpio_desc *reset_gpio;
184 struct regulator_bulk_data supplies[IMX335_NUM_SUPPLIES];
185
186 struct pinctrl *pinctrl;
187 struct pinctrl_state *pins_default;
188 struct pinctrl_state *pins_sleep;
189
190 struct v4l2_subdev subdev;
191 struct media_pad pad;
192 struct v4l2_ctrl_handler ctrl_handler;
193 struct v4l2_ctrl *exposure;
194 struct v4l2_ctrl *anal_a_gain;
195 struct v4l2_ctrl *digi_gain;
196 struct v4l2_ctrl *hblank;
197 struct v4l2_ctrl *vblank;
198 struct v4l2_ctrl *pixel_rate;
199 struct v4l2_ctrl *link_freq;
200 struct mutex mutex;
201 bool streaming;
202 bool power_on;
203 const struct imx335_mode *cur_mode;
204 u32 module_index;
205 u32 cfg_num;
206 const char *module_facing;
207 const char *module_name;
208 const char *len_name;
209 u32 cur_vts;
210 bool has_init_exp;
211 struct preisp_hdrae_exp_s init_hdrae_exp;
212 };
213
214 #define to_imx335(sd) container_of(sd, struct imx335, subdev)
215
216 /*
217 * Xclk 37.125Mhz
218 */
219 static const struct regval imx335_linear_10bit_2592x1944_regs[] = {
220 {0x3002, 0x00},
221 {0x300C, 0x5B},
222 {0x300D, 0x40},
223 {0x3034, 0x26},
224 {0x3035, 0x02},
225 {0x3048, 0x00},
226 {0x3049, 0x00},
227 {0x304A, 0x03},
228 {0x304B, 0x01},
229 {0x304C, 0x14},
230 {0x3050, 0x00},
231 {0x3058, 0x09},
232 {0x3059, 0x00},
233 {0x305C, 0x12},
234 {0x3060, 0xE8},
235 {0x3061, 0x00},
236 {0x3068, 0xce},
237 {0x3069, 0x00},
238 {0x306C, 0x88},
239 {0x306D, 0x06},
240 {0x30E8, 0x00},
241 {0x315A, 0x02},
242 {0x316A, 0x7E},
243 {0x319D, 0x00},
244 {0x31A1, 0x00},
245 {0x31D7, 0x00},
246 {0x3200, 0x01}, /* Each frame gain adjustment disabed in linear mode */
247 {0x3288, 0x21},
248 {0x328A, 0x02},
249 {0x3414, 0x05},
250 {0x3416, 0x18},
251 {0x341C, 0xFF},
252 {0x341D, 0x01},
253 {0x3648, 0x01},
254 {0x364A, 0x04},
255 {0x364C, 0x04},
256 {0x3678, 0x01},
257 {0x367C, 0x31},
258 {0x367E, 0x31},
259 {0x3706, 0x10},
260 {0x3708, 0x03},
261 {0x3714, 0x02},
262 {0x3715, 0x02},
263 {0x3716, 0x01},
264 {0x3717, 0x03},
265 {0x371C, 0x3D},
266 {0x371D, 0x3F},
267 {0x372C, 0x00},
268 {0x372D, 0x00},
269 {0x372E, 0x46},
270 {0x372F, 0x00},
271 {0x3730, 0x89},
272 {0x3731, 0x00},
273 {0x3732, 0x08},
274 {0x3733, 0x01},
275 {0x3734, 0xFE},
276 {0x3735, 0x05},
277 {0x3740, 0x02},
278 {0x375D, 0x00},
279 {0x375E, 0x00},
280 {0x375F, 0x11},
281 {0x3760, 0x01},
282 {0x3768, 0x1B},
283 {0x3769, 0x1B},
284 {0x376A, 0x1B},
285 {0x376B, 0x1B},
286 {0x376C, 0x1A},
287 {0x376D, 0x17},
288 {0x376E, 0x0F},
289 {0x3776, 0x00},
290 {0x3777, 0x00},
291 {0x3778, 0x46},
292 {0x3779, 0x00},
293 {0x377A, 0x89},
294 {0x377B, 0x00},
295 {0x377C, 0x08},
296 {0x377D, 0x01},
297 {0x377E, 0x23},
298 {0x377F, 0x02},
299 {0x3780, 0xD9},
300 {0x3781, 0x03},
301 {0x3782, 0xF5},
302 {0x3783, 0x06},
303 {0x3784, 0xA5},
304 {0x3788, 0x0F},
305 {0x378A, 0xD9},
306 {0x378B, 0x03},
307 {0x378C, 0xEB},
308 {0x378D, 0x05},
309 {0x378E, 0x87},
310 {0x378F, 0x06},
311 {0x3790, 0xF5},
312 {0x3792, 0x43},
313 {0x3794, 0x7A},
314 {0x3796, 0xA1},
315 {REG_NULL, 0x00},
316 };
317
318 static const struct regval imx335_hdr2_10bit_2592x1944_regs[] = {
319 {0x3002, 0x00},
320 {0x300C, 0x5B},
321 {0x300D, 0x40},
322 {0x3034, 0x13},
323 {0x3035, 0x01},
324 {0x3048, 0x01},
325 {0x3049, 0x01},
326 {0x304A, 0x04},
327 {0x304B, 0x03},
328 {0x304C, 0x13},
329 {0x3050, 0x00},
330 {0x3058, 0x48},
331 {0x3059, 0x12},
332 {0x305C, 0x12},
333 {0x3060, 0xE8},
334 {0x3061, 0x00},
335 {0x3068, 0x22},
336 {0x3069, 0x01},
337 {0x306C, 0x68},
338 {0x306D, 0x06},
339 {0x30E8, 0x00},
340 {0x315A, 0x02},
341 {0x316A, 0x7E},
342 {0x319D, 0x00},
343 {0x31A1, 0x00},
344 {0x31D7, 0x01},
345 {0x3200, 0x00}, /* Each frame gain adjustment EN */
346 {0x3288, 0x21},
347 {0x328A, 0x02},
348 {0x3414, 0x05},
349 {0x3416, 0x18},
350 {0x341C, 0xFF},
351 {0x341D, 0x01},
352 {0x3648, 0x01},
353 {0x364A, 0x04},
354 {0x364C, 0x04},
355 {0x3678, 0x01},
356 {0x367C, 0x31},
357 {0x367E, 0x31},
358 {0x3706, 0x10},
359 {0x3708, 0x03},
360 {0x3714, 0x02},
361 {0x3715, 0x02},
362 {0x3716, 0x01},
363 {0x3717, 0x03},
364 {0x371C, 0x3D},
365 {0x371D, 0x3F},
366 {0x372C, 0x00},
367 {0x372D, 0x00},
368 {0x372E, 0x46},
369 {0x372F, 0x00},
370 {0x3730, 0x89},
371 {0x3731, 0x00},
372 {0x3732, 0x08},
373 {0x3733, 0x01},
374 {0x3734, 0xFE},
375 {0x3735, 0x05},
376 {0x3740, 0x02},
377 {0x375D, 0x00},
378 {0x375E, 0x00},
379 {0x375F, 0x11},
380 {0x3760, 0x01},
381 {0x3768, 0x1B},
382 {0x3769, 0x1B},
383 {0x376A, 0x1B},
384 {0x376B, 0x1B},
385 {0x376C, 0x1A},
386 {0x376D, 0x17},
387 {0x376E, 0x0F},
388 {0x3776, 0x00},
389 {0x3777, 0x00},
390 {0x3778, 0x46},
391 {0x3779, 0x00},
392 {0x377A, 0x89},
393 {0x377B, 0x00},
394 {0x377C, 0x08},
395 {0x377D, 0x01},
396 {0x377E, 0x23},
397 {0x377F, 0x02},
398 {0x3780, 0xD9},
399 {0x3781, 0x03},
400 {0x3782, 0xF5},
401 {0x3783, 0x06},
402 {0x3784, 0xA5},
403 {0x3788, 0x0F},
404 {0x378A, 0xD9},
405 {0x378B, 0x03},
406 {0x378C, 0xEB},
407 {0x378D, 0x05},
408 {0x378E, 0x87},
409 {0x378F, 0x06},
410 {0x3790, 0xF5},
411 {0x3792, 0x43},
412 {0x3794, 0x7A},
413 {0x3796, 0xA1},
414 {REG_NULL, 0x00},
415 };
416
417 static const struct regval imx335_hdr3_10bit_2592x1944_regs[] = {
418 {0x3002, 0x00},
419 {0x300C, 0x5B},
420 {0x300D, 0x40},
421 {0x3034, 0x13},
422 {0x3035, 0x01},
423 {0x3048, 0x01},
424 {0x3049, 0x02},
425 {0x304A, 0x05},
426 {0x304B, 0x03},
427 {0x304C, 0x13},
428 {0x3050, 0x00},
429 {0x3058, 0xC4},
430 {0x3059, 0x3B},
431 {0x305C, 0x1A},
432 {0x3060, 0x4E},
433 {0x3061, 0x01},
434 {0x3068, 0x2E},
435 {0x3069, 0x01},
436 {0x306C, 0x6C},
437 {0x306D, 0x01},
438 {0x30E8, 0x14},
439 {0x315A, 0x02},
440 {0x316A, 0x7E},
441 {0x319D, 0x00},
442 {0x31A1, 0x00},
443 {0x31D7, 0x03},
444 {0x3200, 0x00}, /* Each frame gain adjustment EN */
445 {0x3288, 0x21},
446 {0x328A, 0x02},
447 {0x3414, 0x05},
448 {0x3416, 0x18},
449 {0x341C, 0xFF},
450 {0x341D, 0x01},
451 {0x3648, 0x01},
452 {0x364A, 0x04},
453 {0x364C, 0x04},
454 {0x3678, 0x01},
455 {0x367C, 0x31},
456 {0x367E, 0x31},
457 {0x3706, 0x10},
458 {0x3708, 0x03},
459 {0x3714, 0x02},
460 {0x3715, 0x02},
461 {0x3716, 0x01},
462 {0x3717, 0x03},
463 {0x371C, 0x3D},
464 {0x371D, 0x3F},
465 {0x372C, 0x00},
466 {0x372D, 0x00},
467 {0x372E, 0x46},
468 {0x372F, 0x00},
469 {0x3730, 0x89},
470 {0x3731, 0x00},
471 {0x3732, 0x08},
472 {0x3733, 0x01},
473 {0x3734, 0xFE},
474 {0x3735, 0x05},
475 {0x3740, 0x02},
476 {0x375D, 0x00},
477 {0x375E, 0x00},
478 {0x375F, 0x11},
479 {0x3760, 0x01},
480 {0x3768, 0x1B},
481 {0x3769, 0x1B},
482 {0x376A, 0x1B},
483 {0x376B, 0x1B},
484 {0x376C, 0x1A},
485 {0x376D, 0x17},
486 {0x376E, 0x0F},
487 {0x3776, 0x00},
488 {0x3777, 0x00},
489 {0x3778, 0x46},
490 {0x3779, 0x00},
491 {0x377A, 0x89},
492 {0x377B, 0x00},
493 {0x377C, 0x08},
494 {0x377D, 0x01},
495 {0x377E, 0x23},
496 {0x377F, 0x02},
497 {0x3780, 0xD9},
498 {0x3781, 0x03},
499 {0x3782, 0xF5},
500 {0x3783, 0x06},
501 {0x3784, 0xA5},
502 {0x3788, 0x0F},
503 {0x378A, 0xD9},
504 {0x378B, 0x03},
505 {0x378C, 0xEB},
506 {0x378D, 0x05},
507 {0x378E, 0x87},
508 {0x378F, 0x06},
509 {0x3790, 0xF5},
510 {0x3792, 0x43},
511 {0x3794, 0x7A},
512 {0x3796, 0xA1},
513 {REG_NULL, 0x00},
514 };
515
516 /*
517 * The width and height must be configured to be
518 * the same as the current output resolution of the sensor.
519 * The input width of the isp needs to be 16 aligned.
520 * The input height of the isp needs to be 8 aligned.
521 * If the width or height does not meet the alignment rules,
522 * you can configure the cropping parameters with the following function to
523 * crop out the appropriate resolution.
524 * struct v4l2_subdev_pad_ops {
525 * .get_selection
526 * }
527 */
528
529 static const struct imx335_mode supported_modes[] = {
530 {
531 /* 1H period = 7.4us */
532 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
533 .width = 2616,
534 .height = 1964,
535 .max_fps = {
536 .numerator = 10000,
537 .denominator = 300000,
538 },
539 .exp_def = 0x1194 - 0x09,
540 .hts_def = 0x0226 * IMX335_4LANES * 2,
541 .vts_def = 0x1194,
542 .reg_list = imx335_linear_10bit_2592x1944_regs,
543 .hdr_mode = NO_HDR,
544 .bpp = 10,
545 },
546 {
547 /* 1H period = 3.70us */
548 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
549 .width = 2616,
550 .height = 1964,
551 .max_fps = {
552 .numerator = 10000,
553 .denominator = 300000,
554 },
555 .exp_def = 0x1194 * 2 - 0x1248,
556 .hts_def = 0x0113 * IMX335_4LANES * 2 * 2,
557 /*
558 * IMX335 HDR mode T-line is a half of Linear mode,
559 * make vts double(that is FSC) to workaround.
560 */
561 .vts_def = 0x1194 * 2,
562 .reg_list = imx335_hdr2_10bit_2592x1944_regs,
563 .hdr_mode = HDR_X2,
564 .bpp = 10,
565 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
566 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
567 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
568 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
569 },
570 {
571 /* 1H period = 3.70us */
572 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
573 .width = 2616,
574 .height = 1964,
575 .max_fps = {
576 .numerator = 10000,
577 .denominator = 150000,
578 },
579 .exp_def = 0x1194 * 2 - 0x1248,
580 .hts_def = 0x0113 * IMX335_4LANES * 2 * 2,
581 /*
582 * IMX335 HDR mode T-line is a half of Linear mode,
583 * make vts double(that is FSC) to workaround.
584 */
585 .vts_def = 0x1194 * 4,
586 .reg_list = imx335_hdr3_10bit_2592x1944_regs,
587 .hdr_mode = HDR_X3,
588 .bpp = 10,
589 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
590 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
591 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
592 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
593 },
594 };
595
596 static const s64 link_freq_items[] = {
597 MIPI_FREQ_594M,
598 };
599
600 /* Write registers up to 4 at a time */
imx335_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)601 static int imx335_write_reg(struct i2c_client *client, u16 reg,
602 u32 len, u32 val)
603 {
604 u32 buf_i, val_i;
605 u8 buf[6];
606 u8 *val_p;
607 __be32 val_be;
608
609 if (len > 4)
610 return -EINVAL;
611
612 buf[0] = reg >> 8;
613 buf[1] = reg & 0xff;
614
615 val_be = cpu_to_be32(val);
616 val_p = (u8 *)&val_be;
617 buf_i = 2;
618 val_i = 4 - len;
619
620 while (val_i < 4)
621 buf[buf_i++] = val_p[val_i++];
622
623 if (i2c_master_send(client, buf, len + 2) != len + 2)
624 return -EIO;
625
626 return 0;
627 }
628
imx335_write_array(struct i2c_client * client,const struct regval * regs)629 static int imx335_write_array(struct i2c_client *client,
630 const struct regval *regs)
631 {
632 u32 i;
633 int ret = 0;
634
635 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
636 ret = imx335_write_reg(client, regs[i].addr,
637 IMX335_REG_VALUE_08BIT, regs[i].val);
638 }
639 return ret;
640 }
641
642 /* Read registers up to 4 at a time */
imx335_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)643 static int imx335_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
644 u32 *val)
645 {
646 struct i2c_msg msgs[2];
647 u8 *data_be_p;
648 __be32 data_be = 0;
649 __be16 reg_addr_be = cpu_to_be16(reg);
650 int ret;
651
652 if (len > 4 || !len)
653 return -EINVAL;
654
655 data_be_p = (u8 *)&data_be;
656 /* Write register address */
657 msgs[0].addr = client->addr;
658 msgs[0].flags = 0;
659 msgs[0].len = 2;
660 msgs[0].buf = (u8 *)®_addr_be;
661
662 /* Read data from register */
663 msgs[1].addr = client->addr;
664 msgs[1].flags = I2C_M_RD;
665 msgs[1].len = len;
666 msgs[1].buf = &data_be_p[4 - len];
667
668 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
669 if (ret != ARRAY_SIZE(msgs))
670 return -EIO;
671
672 *val = be32_to_cpu(data_be);
673
674 return 0;
675 }
676
imx335_get_reso_dist(const struct imx335_mode * mode,struct v4l2_mbus_framefmt * framefmt)677 static int imx335_get_reso_dist(const struct imx335_mode *mode,
678 struct v4l2_mbus_framefmt *framefmt)
679 {
680 return abs(mode->width - framefmt->width) +
681 abs(mode->height - framefmt->height);
682 }
683
684 static const struct imx335_mode *
imx335_find_best_fit(struct imx335 * imx335,struct v4l2_subdev_format * fmt)685 imx335_find_best_fit(struct imx335 *imx335, struct v4l2_subdev_format *fmt)
686 {
687 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
688 int dist;
689 int cur_best_fit = 0;
690 int cur_best_fit_dist = -1;
691 unsigned int i;
692
693 for (i = 0; i < imx335->cfg_num; i++) {
694 dist = imx335_get_reso_dist(&supported_modes[i], framefmt);
695 if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
696 supported_modes[i].bus_fmt == framefmt->code) {
697 cur_best_fit_dist = dist;
698 cur_best_fit = i;
699 }
700 }
701
702 return &supported_modes[cur_best_fit];
703 }
704
imx335_change_mode(struct imx335 * imx335,const struct imx335_mode * mode)705 static void imx335_change_mode(struct imx335 *imx335, const struct imx335_mode *mode)
706 {
707 imx335->cur_mode = mode;
708 imx335->cur_vts = imx335->cur_mode->vts_def;
709 dev_dbg(&imx335->client->dev, "set fmt: cur_mode: %dx%d, hdr: %d\n",
710 mode->width, mode->height, mode->hdr_mode);
711 }
712
imx335_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)713 static int imx335_set_fmt(struct v4l2_subdev *sd,
714 struct v4l2_subdev_pad_config *cfg,
715 struct v4l2_subdev_format *fmt)
716 {
717 struct imx335 *imx335 = to_imx335(sd);
718 const struct imx335_mode *mode;
719 s64 h_blank, vblank_def;
720
721 mutex_lock(&imx335->mutex);
722
723 mode = imx335_find_best_fit(imx335, fmt);
724 fmt->format.code = mode->bus_fmt;
725 fmt->format.width = mode->width;
726 fmt->format.height = mode->height;
727 fmt->format.field = V4L2_FIELD_NONE;
728 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
729 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
730
731 } else {
732 imx335_change_mode(imx335, mode);
733 h_blank = mode->hts_def - mode->width;
734 __v4l2_ctrl_modify_range(imx335->hblank, h_blank,
735 h_blank, 1, h_blank);
736 vblank_def = mode->vts_def - mode->height;
737 __v4l2_ctrl_modify_range(imx335->vblank, vblank_def,
738 IMX335_VTS_MAX - mode->height,
739 1, vblank_def);
740 }
741
742 mutex_unlock(&imx335->mutex);
743
744 return 0;
745 }
746
imx335_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)747 static int imx335_get_fmt(struct v4l2_subdev *sd,
748 struct v4l2_subdev_pad_config *cfg,
749 struct v4l2_subdev_format *fmt)
750 {
751 struct imx335 *imx335 = to_imx335(sd);
752 const struct imx335_mode *mode = imx335->cur_mode;
753
754 mutex_lock(&imx335->mutex);
755 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
756 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
757 } else {
758 fmt->format.width = mode->width;
759 fmt->format.height = mode->height;
760 fmt->format.code = mode->bus_fmt;
761 fmt->format.field = V4L2_FIELD_NONE;
762 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
763 fmt->reserved[0] = mode->vc[fmt->pad];
764 else
765 fmt->reserved[0] = mode->vc[PAD0];
766 }
767 mutex_unlock(&imx335->mutex);
768
769 return 0;
770 }
771
imx335_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)772 static int imx335_enum_mbus_code(struct v4l2_subdev *sd,
773 struct v4l2_subdev_pad_config *cfg,
774 struct v4l2_subdev_mbus_code_enum *code)
775 {
776 struct imx335 *imx335 = to_imx335(sd);
777
778 if (code->index != 0)
779 return -EINVAL;
780 code->code = imx335->cur_mode->bus_fmt;
781
782 return 0;
783 }
784
imx335_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)785 static int imx335_enum_frame_sizes(struct v4l2_subdev *sd,
786 struct v4l2_subdev_pad_config *cfg,
787 struct v4l2_subdev_frame_size_enum *fse)
788 {
789 struct imx335 *imx335 = to_imx335(sd);
790
791 if (fse->index >= imx335->cfg_num)
792 return -EINVAL;
793
794 if (fse->code != supported_modes[fse->index].bus_fmt)
795 return -EINVAL;
796
797 fse->min_width = supported_modes[fse->index].width;
798 fse->max_width = supported_modes[fse->index].width;
799 fse->max_height = supported_modes[fse->index].height;
800 fse->min_height = supported_modes[fse->index].height;
801
802 return 0;
803 }
804
imx335_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)805 static int imx335_g_frame_interval(struct v4l2_subdev *sd,
806 struct v4l2_subdev_frame_interval *fi)
807 {
808 struct imx335 *imx335 = to_imx335(sd);
809 const struct imx335_mode *mode = imx335->cur_mode;
810
811 fi->interval = mode->max_fps;
812
813 return 0;
814 }
815
imx335_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)816 static int imx335_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
817 struct v4l2_mbus_config *config)
818 {
819 u32 val = 0;
820 struct imx335 *imx335 = to_imx335(sd);
821 const struct imx335_mode *mode = imx335->cur_mode;
822
823 val = 1 << (IMX335_4LANES - 1) |
824 V4L2_MBUS_CSI2_CHANNEL_0 |
825 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
826 if (mode->hdr_mode != NO_HDR)
827 val |= V4L2_MBUS_CSI2_CHANNEL_1;
828 if (mode->hdr_mode == HDR_X3)
829 val |= V4L2_MBUS_CSI2_CHANNEL_2;
830 config->type = V4L2_MBUS_CSI2_DPHY;
831 config->flags = val;
832
833 return 0;
834 }
835
imx335_get_module_inf(struct imx335 * imx335,struct rkmodule_inf * inf)836 static void imx335_get_module_inf(struct imx335 *imx335,
837 struct rkmodule_inf *inf)
838 {
839 memset(inf, 0, sizeof(*inf));
840 strlcpy(inf->base.sensor, IMX335_NAME, sizeof(inf->base.sensor));
841 strlcpy(inf->base.module, imx335->module_name,
842 sizeof(inf->base.module));
843 strlcpy(inf->base.lens, imx335->len_name, sizeof(inf->base.lens));
844 }
845
imx335_set_hdrae(struct imx335 * imx335,struct preisp_hdrae_exp_s * ae)846 static int imx335_set_hdrae(struct imx335 *imx335,
847 struct preisp_hdrae_exp_s *ae)
848 {
849 struct i2c_client *client = imx335->client;
850 u32 l_exp_time, m_exp_time, s_exp_time;
851 u32 l_a_gain, m_a_gain, s_a_gain;
852 int shr1, shr0, rhs1, rhs1_max, rhs1_min;
853 static int rhs1_old = IMX335_RHS1_DEFAULT;
854 int ret = 0;
855 u32 fsc;
856
857 if (!imx335->has_init_exp && !imx335->streaming) {
858 imx335->init_hdrae_exp = *ae;
859 imx335->has_init_exp = true;
860 dev_dbg(&imx335->client->dev, "imx335 is not streaming, save hdr ae!\n");
861 return ret;
862 }
863 l_exp_time = ae->long_exp_reg;
864 m_exp_time = ae->middle_exp_reg;
865 s_exp_time = ae->short_exp_reg;
866 l_a_gain = ae->long_gain_reg;
867 m_a_gain = ae->middle_gain_reg;
868 s_a_gain = ae->short_gain_reg;
869 dev_dbg(&client->dev,
870 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
871 l_exp_time, l_a_gain, m_exp_time, m_a_gain, s_exp_time, s_a_gain);
872
873 if (imx335->cur_mode->hdr_mode == HDR_X2) {
874 l_a_gain = m_a_gain;
875 l_exp_time = m_exp_time;
876 }
877
878 ret = imx335_write_reg(client, IMX335_GROUP_HOLD_REG,
879 IMX335_REG_VALUE_08BIT, IMX335_GROUP_HOLD_START);
880 /* gain effect n+1 */
881 ret |= imx335_write_reg(client, IMX335_LF_GAIN_REG_H,
882 IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_H(l_a_gain));
883 ret |= imx335_write_reg(client, IMX335_LF_GAIN_REG_L,
884 IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_L(l_a_gain));
885 ret |= imx335_write_reg(client, IMX335_SF1_GAIN_REG_H,
886 IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_H(s_a_gain));
887 ret |= imx335_write_reg(client, IMX335_SF1_GAIN_REG_L,
888 IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_L(s_a_gain));
889
890 /* Restrictions
891 * FSC = 2 * VMAX = 4n (4n, align with 4)
892 * SHR1 + 18 <= SHR0 <= (FSC - 4)
893 *
894 * exp_l = FSC - SHR0
895 * SHR0 = FSC - exp_l (4n, align with 4)
896 *
897 * exp_s = RHS1 - SHR1
898 * SHR1 + 4 <= RHS1 < BRL * 2 (8n + 2)
899 * SHR1 + 4 <= RHS1 <= SHR0 - 18
900 * 18 <= SHR1 <= RHS1 - 4 (4n + 2)
901 *
902 * RHS1(n+1) >= (RHS1(n) + BRL * 2) - FSC + 2
903 *
904 * RHS1 and SHR1 shall be even value.
905 *
906 * T(l_exp) = FSC - SHR0, unit: H
907 * T(s_exp) = RHS1 - SHR1, unit: H
908 * Exposure ratio: T(l_exp) / T(s_exp) >= 1
909 */
910
911 /* The HDR mode vts is already double by default to workaround T-line */
912 fsc = imx335->cur_vts;
913
914 shr0 = fsc - l_exp_time;
915
916 rhs1_max = min(RHS1_MAX, shr0 - SHR1_MIN);
917 rhs1_max = (rhs1_max & ~0x7) + 2;
918 rhs1_min = max(SHR1_MIN + 4u, rhs1_old + 2 * BRL - fsc + 2);
919 rhs1_min = (rhs1_min + 7u) / 8 * 8 + 2;
920 if (rhs1_max < rhs1_min) {
921 dev_err(&client->dev,
922 "The total exposure limit makes rhs1 max is %d,but old rhs1 limit makes rhs1 min is %d\n",
923 rhs1_max, rhs1_min);
924 return -EINVAL;
925 }
926
927 rhs1 = SHR1_MIN + s_exp_time;
928 rhs1 = (rhs1 & ~0x7) + 2; /* shall be 8n + 2 */
929 if (rhs1 > rhs1_max)
930 rhs1 = rhs1_max;
931 if (rhs1 < rhs1_min)
932 rhs1 = rhs1_min;
933 dev_dbg(&client->dev,
934 "line(%d) rhs1 %d, short time %d rhs1_old %d, rhs1_new %d, rhs1_min %d rhs1_max %d\n",
935 __LINE__, rhs1, s_exp_time, rhs1_old, rhs1, rhs1_min, rhs1_max);
936
937 rhs1_old = rhs1;
938
939 /* shr1 = rhs1 - s_exp_time */
940 if (rhs1 - s_exp_time <= SHR1_MIN) {
941 shr1 = SHR1_MIN;
942 s_exp_time = rhs1 - shr1;
943 } else {
944 shr1 = rhs1 - s_exp_time;
945 }
946 shr1 = (shr1 & ~0x3) + 2; /* shall be 4n + 2 */
947
948 if (shr0 < rhs1 + 18)
949 shr0 = rhs1 + 18;
950 else if (shr0 > fsc - 4)
951 shr0 = fsc - 4;
952
953 shr0 &= (~0x3); /* align with 4 */
954
955 dev_dbg(&client->dev,
956 "fsc=%d,RHS1_MAX=%d,SHR1_MIN=%d,rhs1_max=%d\n",
957 fsc, RHS1_MAX, SHR1_MIN, rhs1_max);
958 dev_dbg(&client->dev,
959 "l_exp_time=%d,s_exp_time=%d,shr0=%d,shr1=%d,rhs1=%d,l_a_gain=%d,s_a_gain=%d\n",
960 l_exp_time, s_exp_time, shr0, shr1, rhs1, l_a_gain, s_a_gain);
961 /* time effect n+2 */
962 ret |= imx335_write_reg(client,
963 IMX335_RHS1_REG_L,
964 IMX335_REG_VALUE_08BIT,
965 IMX335_FETCH_RHS1_L(rhs1));
966 ret |= imx335_write_reg(client,
967 IMX335_RHS1_REG_M,
968 IMX335_REG_VALUE_08BIT,
969 IMX335_FETCH_RHS1_M(rhs1));
970 ret |= imx335_write_reg(client,
971 IMX335_RHS1_REG_H,
972 IMX335_REG_VALUE_08BIT,
973 IMX335_FETCH_RHS1_H(rhs1));
974
975 ret |= imx335_write_reg(client,
976 IMX335_SF1_EXPO_REG_L,
977 IMX335_REG_VALUE_08BIT,
978 IMX335_FETCH_EXP_L(shr1));
979 ret |= imx335_write_reg(client,
980 IMX335_SF1_EXPO_REG_M,
981 IMX335_REG_VALUE_08BIT,
982 IMX335_FETCH_EXP_M(shr1));
983 ret |= imx335_write_reg(client,
984 IMX335_SF1_EXPO_REG_H,
985 IMX335_REG_VALUE_08BIT,
986 IMX335_FETCH_EXP_H(shr1));
987 ret |= imx335_write_reg(client,
988 IMX335_LF_EXPO_REG_L,
989 IMX335_REG_VALUE_08BIT,
990 IMX335_FETCH_EXP_L(shr0));
991 ret |= imx335_write_reg(client,
992 IMX335_LF_EXPO_REG_M,
993 IMX335_REG_VALUE_08BIT,
994 IMX335_FETCH_EXP_M(shr0));
995 ret |= imx335_write_reg(client,
996 IMX335_LF_EXPO_REG_H,
997 IMX335_REG_VALUE_08BIT,
998 IMX335_FETCH_EXP_H(shr0));
999
1000 ret |= imx335_write_reg(client, IMX335_GROUP_HOLD_REG,
1001 IMX335_REG_VALUE_08BIT, IMX335_GROUP_HOLD_END);
1002 return ret;
1003 }
1004
imx335_set_hdrae_3frame(struct imx335 * imx335,struct preisp_hdrae_exp_s * ae)1005 static int imx335_set_hdrae_3frame(struct imx335 *imx335,
1006 struct preisp_hdrae_exp_s *ae)
1007 {
1008 struct i2c_client *client = imx335->client;
1009 u32 l_exp_time, m_exp_time, s_exp_time;
1010 u32 l_a_gain, m_a_gain, s_a_gain;
1011 int shr2, shr1, shr0, rhs2, rhs1 = 0;
1012 int rhs1_change_limit, rhs2_change_limit = 0;
1013 static int rhs1_old = IMX335_RHS1_X3_DEFAULT;
1014 static int rhs2_old = IMX335_RHS2_X3_DEFAULT;
1015 int ret = 0;
1016 u32 fsc;
1017 int rhs1_max = 0;
1018 int shr2_min = 0;
1019
1020 if (!imx335->has_init_exp && !imx335->streaming) {
1021 imx335->init_hdrae_exp = *ae;
1022 imx335->has_init_exp = true;
1023 dev_dbg(&imx335->client->dev, "imx335 is not streaming, save hdr ae!\n");
1024 return ret;
1025 }
1026 l_exp_time = ae->long_exp_reg;
1027 m_exp_time = ae->middle_exp_reg;
1028 s_exp_time = ae->short_exp_reg;
1029 l_a_gain = ae->long_gain_reg;
1030 m_a_gain = ae->middle_gain_reg;
1031 s_a_gain = ae->short_gain_reg;
1032 dev_dbg(&client->dev,
1033 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
1034 l_exp_time, l_a_gain, m_exp_time, m_a_gain, s_exp_time, s_a_gain);
1035
1036 ret = imx335_write_reg(client, IMX335_GROUP_HOLD_REG,
1037 IMX335_REG_VALUE_08BIT, IMX335_GROUP_HOLD_START);
1038 /* gain effect n+1 */
1039 ret |= imx335_write_reg(client, IMX335_LF_GAIN_REG_H,
1040 IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_H(l_a_gain));
1041 ret |= imx335_write_reg(client, IMX335_LF_GAIN_REG_L,
1042 IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_L(l_a_gain));
1043 ret |= imx335_write_reg(client, IMX335_SF1_GAIN_REG_H,
1044 IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_H(m_a_gain));
1045 ret |= imx335_write_reg(client, IMX335_SF1_GAIN_REG_L,
1046 IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_L(m_a_gain));
1047 ret |= imx335_write_reg(client, IMX335_SF2_GAIN_REG_H,
1048 IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_H(s_a_gain));
1049 ret |= imx335_write_reg(client, IMX335_SF2_GAIN_REG_L,
1050 IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_L(s_a_gain));
1051
1052 /* Restrictions
1053 * FSC = 4 * VMAX and FSC should be 6n;
1054 * exp_l = FSC - SHR0 + Toffset;
1055 *
1056 * SHR0 = FSC - exp_l + Toffset;
1057 * SHR0 <= (FSC -6);
1058 * SHR0 >= RHS2 + 26;
1059 * SHR0 should be 6n;
1060 *
1061 * exp_m = RHS1 - SHR1 + Toffset;
1062 *
1063 * RHS1 < BRL * 3;
1064 * RHS1 <= SHR2 - 26;
1065 * RHS1 >= SHR1 + 6;
1066 * SHR1 >= 26;
1067 * SHR1 <= RHS1 - 6;
1068 * RHS1(n+1) >= RHS1(n) + BRL * 3 -FSC + 3;
1069 *
1070 * SHR1 should be 6n+2 and RHS1 should be 12n+2;
1071 *
1072 * exp_s = RHS2 - SHR2 + Toffset;
1073 *
1074 * RHS2 < BRL * 3 + RHS1;
1075 * RHS2 <= SHR0 - 26;
1076 * RHS2 >= SHR2 + 6;
1077 * SHR2 >= RHS1 + 26;
1078 * SHR2 <= RHS2 - 6;
1079 * RHS1(n+1) >= RHS1(n) + BRL * 3 -FSC + 3;
1080 *
1081 * SHR2 should be 6n+4 and RHS2 should be 12n+4;
1082 */
1083
1084 /* The HDR mode vts is double by default to workaround T-line */
1085 fsc = imx335->cur_vts;
1086 fsc = fsc / 6 * 6;
1087 shr0 = fsc - l_exp_time;
1088 dev_dbg(&client->dev,
1089 "line(%d) shr0 %d, l_exp_time %d, fsc %d\n",
1090 __LINE__, shr0, l_exp_time, fsc);
1091
1092 rhs1 = (SHR1_MIN_X3 + m_exp_time + 11) / 12 * 12 + 2;
1093 rhs1_max = RHS1_MAX_X3;
1094 if (rhs1 < 32)
1095 rhs1 = 32;
1096 else if (rhs1 > rhs1_max)
1097 rhs1 = rhs1_max;
1098 dev_dbg(&client->dev,
1099 "line(%d) rhs1 %d, m_exp_time %d rhs1_old %d\n",
1100 __LINE__, rhs1, m_exp_time, rhs1_old);
1101
1102 //Dynamic adjustment rhs2 must meet the following conditions
1103 rhs1_change_limit = rhs1_old + 3 * BRL - fsc + 3;
1104 rhs1_change_limit = (rhs1_change_limit < 32) ? 32 : rhs1_change_limit;
1105 rhs1_change_limit = (rhs1_change_limit + 11) / 12 * 12 + 2;
1106 if (rhs1_max < rhs1_change_limit) {
1107 dev_err(&client->dev,
1108 "The total exposure limit makes rhs1 max is %d,but old rhs1 limit makes rhs1 min is %d\n",
1109 rhs1_max, rhs1_change_limit);
1110 return -EINVAL;
1111 }
1112 if (rhs1 < rhs1_change_limit)
1113 rhs1 = rhs1_change_limit;
1114
1115 dev_dbg(&client->dev,
1116 "line(%d) m_exp_time %d rhs1_old %d, rhs1_new %d\n",
1117 __LINE__, m_exp_time, rhs1_old, rhs1);
1118
1119 rhs1_old = rhs1;
1120
1121 /* shr1 = rhs1 - s_exp_time */
1122 if (rhs1 - m_exp_time <= SHR1_MIN_X3) {
1123 shr1 = SHR1_MIN_X3;
1124 m_exp_time = rhs1 - shr1;
1125 } else {
1126 shr1 = rhs1 - m_exp_time;
1127 }
1128
1129 shr2_min = rhs1 + 26;
1130 rhs2 = (shr2_min + s_exp_time + 11) / 12 * 12 + 4;
1131 if (rhs2 > (shr0 - 26))
1132 rhs2 = shr0 - 26;
1133 else if (rhs2 < 64)
1134 rhs2 = 64;
1135 dev_dbg(&client->dev,
1136 "line(%d) rhs2 %d, s_exp_time %d, rhs2_old %d\n",
1137 __LINE__, rhs2, s_exp_time, rhs2_old);
1138
1139 //Dynamic adjustment rhs2 must meet the following conditions
1140 rhs2_change_limit = rhs2_old + 3 * BRL - fsc + 3;
1141 rhs2_change_limit = (rhs2_change_limit < 64) ? 64 : rhs2_change_limit;
1142 rhs2_change_limit = (rhs2_change_limit + 11) / 12 * 12 + 4;
1143 if ((shr0 - 26) < rhs2_change_limit) {
1144 dev_err(&client->dev,
1145 "The total exposure limit makes rhs2 max is %d,but old rhs1 limit makes rhs2 min is %d\n",
1146 shr0 - 26, rhs2_change_limit);
1147 return -EINVAL;
1148 }
1149 if (rhs2 < rhs2_change_limit)
1150 rhs2 = rhs2_change_limit;
1151
1152 rhs2_old = rhs2;
1153
1154 /* shr2 = rhs2 - s_exp_time */
1155 if (rhs2 - s_exp_time <= shr2_min) {
1156 shr2 = shr2_min;
1157 s_exp_time = rhs2 - shr2;
1158 } else {
1159 shr2 = rhs2 - s_exp_time;
1160 }
1161 dev_dbg(&client->dev,
1162 "line(%d) rhs2_new %d, s_exp_time %d shr2 %d, rhs2_change_limit %d\n",
1163 __LINE__, rhs2, s_exp_time, shr2, rhs2_change_limit);
1164
1165 if (shr0 < rhs2 + 26)
1166 shr0 = rhs2 + 26;
1167 else if (shr0 > fsc - 6)
1168 shr0 = fsc - 6;
1169
1170 dev_dbg(&client->dev,
1171 "long exposure: l_exp_time=%d, fsc=%d, shr0=%d, l_a_gain=%d\n",
1172 l_exp_time, fsc, shr0, l_a_gain);
1173 dev_dbg(&client->dev,
1174 "middle exposure(SEF1): m_exp_time=%d, rhs1=%d, shr1=%d, m_a_gain=%d\n",
1175 m_exp_time, rhs1, shr1, m_a_gain);
1176 dev_dbg(&client->dev,
1177 "short exposure(SEF2): s_exp_time=%d, rhs2=%d, shr2=%d, s_a_gain=%d\n",
1178 s_exp_time, rhs2, shr2, s_a_gain);
1179 /* time effect n+1 */
1180 /* write SEF2 exposure RHS2 regs*/
1181 ret |= imx335_write_reg(client,
1182 IMX335_RHS2_REG_L,
1183 IMX335_REG_VALUE_08BIT,
1184 IMX335_FETCH_RHS1_L(rhs2));
1185 ret |= imx335_write_reg(client,
1186 IMX335_RHS2_REG_M,
1187 IMX335_REG_VALUE_08BIT,
1188 IMX335_FETCH_RHS1_M(rhs2));
1189 ret |= imx335_write_reg(client,
1190 IMX335_RHS2_REG_H,
1191 IMX335_REG_VALUE_08BIT,
1192 IMX335_FETCH_RHS1_H(rhs2));
1193 /* write SEF2 exposure SHR2 regs*/
1194 ret |= imx335_write_reg(client,
1195 IMX335_SF2_EXPO_REG_L,
1196 IMX335_REG_VALUE_08BIT,
1197 IMX335_FETCH_EXP_L(shr2));
1198 ret |= imx335_write_reg(client,
1199 IMX335_SF2_EXPO_REG_M,
1200 IMX335_REG_VALUE_08BIT,
1201 IMX335_FETCH_EXP_M(shr2));
1202 ret |= imx335_write_reg(client,
1203 IMX335_SF2_EXPO_REG_H,
1204 IMX335_REG_VALUE_08BIT,
1205 IMX335_FETCH_EXP_H(shr2));
1206 /* write SEF1 exposure RHS1 regs*/
1207 ret |= imx335_write_reg(client,
1208 IMX335_RHS1_REG_L,
1209 IMX335_REG_VALUE_08BIT,
1210 IMX335_FETCH_RHS1_L(rhs1));
1211 ret |= imx335_write_reg(client,
1212 IMX335_RHS1_REG_M,
1213 IMX335_REG_VALUE_08BIT,
1214 IMX335_FETCH_RHS1_M(rhs1));
1215 ret |= imx335_write_reg(client,
1216 IMX335_RHS1_REG_H,
1217 IMX335_REG_VALUE_08BIT,
1218 IMX335_FETCH_RHS1_H(rhs1));
1219 /* write SEF1 exposure SHR1 regs*/
1220 ret |= imx335_write_reg(client,
1221 IMX335_SF1_EXPO_REG_L,
1222 IMX335_REG_VALUE_08BIT,
1223 IMX335_FETCH_EXP_L(shr1));
1224 ret |= imx335_write_reg(client,
1225 IMX335_SF1_EXPO_REG_M,
1226 IMX335_REG_VALUE_08BIT,
1227 IMX335_FETCH_EXP_M(shr1));
1228 ret |= imx335_write_reg(client,
1229 IMX335_SF1_EXPO_REG_H,
1230 IMX335_REG_VALUE_08BIT,
1231 IMX335_FETCH_EXP_H(shr1));
1232 /* write LF exposure SHR0 regs*/
1233 ret |= imx335_write_reg(client,
1234 IMX335_LF_EXPO_REG_L,
1235 IMX335_REG_VALUE_08BIT,
1236 IMX335_FETCH_EXP_L(shr0));
1237 ret |= imx335_write_reg(client,
1238 IMX335_LF_EXPO_REG_M,
1239 IMX335_REG_VALUE_08BIT,
1240 IMX335_FETCH_EXP_M(shr0));
1241 ret |= imx335_write_reg(client,
1242 IMX335_LF_EXPO_REG_H,
1243 IMX335_REG_VALUE_08BIT,
1244 IMX335_FETCH_EXP_H(shr0));
1245
1246 ret |= imx335_write_reg(client, IMX335_GROUP_HOLD_REG,
1247 IMX335_REG_VALUE_08BIT, IMX335_GROUP_HOLD_END);
1248 return ret;
1249 }
1250
imx335_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1251 static long imx335_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1252 {
1253 struct imx335 *imx335 = to_imx335(sd);
1254 struct rkmodule_hdr_cfg *hdr;
1255 u32 i, h, w;
1256 long ret = 0;
1257 u32 stream = 0;
1258
1259 switch (cmd) {
1260 case PREISP_CMD_SET_HDRAE_EXP:
1261 if (imx335->cur_mode->hdr_mode == HDR_X2)
1262 ret = imx335_set_hdrae(imx335, arg);
1263 else if (imx335->cur_mode->hdr_mode == HDR_X3)
1264 ret = imx335_set_hdrae_3frame(imx335, arg);
1265 break;
1266 case RKMODULE_GET_MODULE_INFO:
1267 imx335_get_module_inf(imx335, (struct rkmodule_inf *)arg);
1268 break;
1269 case RKMODULE_GET_HDR_CFG:
1270 hdr = (struct rkmodule_hdr_cfg *)arg;
1271 hdr->esp.mode = HDR_NORMAL_VC;
1272 hdr->hdr_mode = imx335->cur_mode->hdr_mode;
1273 break;
1274 case RKMODULE_SET_HDR_CFG:
1275 hdr = (struct rkmodule_hdr_cfg *)arg;
1276 w = imx335->cur_mode->width;
1277 h = imx335->cur_mode->height;
1278 for (i = 0; i < imx335->cfg_num; i++) {
1279 if (w == supported_modes[i].width &&
1280 h == supported_modes[i].height &&
1281 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1282 imx335_change_mode(imx335, &supported_modes[i]);
1283 break;
1284 }
1285 }
1286 if (i == imx335->cfg_num) {
1287 dev_err(&imx335->client->dev,
1288 "not find hdr mode:%d %dx%d config\n",
1289 hdr->hdr_mode, w, h);
1290 ret = -EINVAL;
1291 } else {
1292 w = imx335->cur_mode->hts_def - imx335->cur_mode->width;
1293 h = imx335->cur_mode->vts_def - imx335->cur_mode->height;
1294 __v4l2_ctrl_modify_range(imx335->hblank, w, w, 1, w);
1295 __v4l2_ctrl_modify_range(imx335->vblank, h,
1296 IMX335_VTS_MAX - imx335->cur_mode->height,
1297 1, h);
1298 }
1299 break;
1300 case RKMODULE_SET_QUICK_STREAM:
1301
1302 stream = *((u32 *)arg);
1303
1304 if (stream)
1305 imx335_write_reg(imx335->client, IMX335_REG_CTRL_MODE,
1306 IMX335_REG_VALUE_08BIT, 0);
1307 else
1308 imx335_write_reg(imx335->client, IMX335_REG_CTRL_MODE,
1309 IMX335_REG_VALUE_08BIT, 1);
1310 break;
1311 default:
1312 ret = -ENOIOCTLCMD;
1313 break;
1314 }
1315
1316 return ret;
1317 }
1318
1319 #ifdef CONFIG_COMPAT
imx335_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1320 static long imx335_compat_ioctl32(struct v4l2_subdev *sd,
1321 unsigned int cmd, unsigned long arg)
1322 {
1323 void __user *up = compat_ptr(arg);
1324 struct rkmodule_inf *inf;
1325 struct rkmodule_awb_cfg *cfg;
1326 struct rkmodule_hdr_cfg *hdr;
1327 struct preisp_hdrae_exp_s *hdrae;
1328 long ret;
1329 u32 stream = 0;
1330
1331 switch (cmd) {
1332 case RKMODULE_GET_MODULE_INFO:
1333 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1334 if (!inf) {
1335 ret = -ENOMEM;
1336 return ret;
1337 }
1338
1339 ret = imx335_ioctl(sd, cmd, inf);
1340 if (!ret)
1341 ret = copy_to_user(up, inf, sizeof(*inf));
1342 kfree(inf);
1343 break;
1344 case RKMODULE_AWB_CFG:
1345 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1346 if (!cfg) {
1347 ret = -ENOMEM;
1348 return ret;
1349 }
1350
1351 ret = copy_from_user(cfg, up, sizeof(*cfg));
1352 if (!ret)
1353 ret = imx335_ioctl(sd, cmd, cfg);
1354 kfree(cfg);
1355 break;
1356 case RKMODULE_GET_HDR_CFG:
1357 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1358 if (!hdr) {
1359 ret = -ENOMEM;
1360 return ret;
1361 }
1362
1363 ret = imx335_ioctl(sd, cmd, hdr);
1364 if (!ret)
1365 ret = copy_to_user(up, hdr, sizeof(*hdr));
1366 kfree(hdr);
1367 break;
1368 case RKMODULE_SET_HDR_CFG:
1369 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1370 if (!hdr) {
1371 ret = -ENOMEM;
1372 return ret;
1373 }
1374
1375 ret = copy_from_user(hdr, up, sizeof(*hdr));
1376 if (!ret)
1377 ret = imx335_ioctl(sd, cmd, hdr);
1378 kfree(hdr);
1379 break;
1380 case PREISP_CMD_SET_HDRAE_EXP:
1381 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1382 if (!hdrae) {
1383 ret = -ENOMEM;
1384 return ret;
1385 }
1386
1387 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1388 if (!ret)
1389 ret = imx335_ioctl(sd, cmd, hdrae);
1390 kfree(hdrae);
1391 break;
1392 case RKMODULE_SET_QUICK_STREAM:
1393 ret = copy_from_user(&stream, up, sizeof(u32));
1394 if (!ret)
1395 ret = imx335_ioctl(sd, cmd, &stream);
1396 break;
1397 default:
1398 ret = -ENOIOCTLCMD;
1399 break;
1400 }
1401
1402 return ret;
1403 }
1404 #endif
1405
__imx335_start_stream(struct imx335 * imx335)1406 static int __imx335_start_stream(struct imx335 *imx335)
1407 {
1408 int ret;
1409
1410 ret = imx335_write_array(imx335->client, imx335->cur_mode->reg_list);
1411 if (ret)
1412 return ret;
1413
1414 /* In case these controls are set before streaming */
1415 ret = __v4l2_ctrl_handler_setup(&imx335->ctrl_handler);
1416 if (ret)
1417 return ret;
1418
1419 if (imx335->has_init_exp && imx335->cur_mode->hdr_mode != NO_HDR) {
1420 ret = imx335_ioctl(&imx335->subdev, PREISP_CMD_SET_HDRAE_EXP,
1421 &imx335->init_hdrae_exp);
1422 if (ret) {
1423 dev_err(&imx335->client->dev,
1424 "init exp fail in hdr mode\n");
1425 return ret;
1426 }
1427 }
1428 return imx335_write_reg(imx335->client, IMX335_REG_CTRL_MODE,
1429 IMX335_REG_VALUE_08BIT, 0);
1430 }
1431
__imx335_stop_stream(struct imx335 * imx335)1432 static int __imx335_stop_stream(struct imx335 *imx335)
1433 {
1434 imx335->has_init_exp = false;
1435 return imx335_write_reg(imx335->client, IMX335_REG_CTRL_MODE,
1436 IMX335_REG_VALUE_08BIT, 1);
1437 }
1438
imx335_s_stream(struct v4l2_subdev * sd,int on)1439 static int imx335_s_stream(struct v4l2_subdev *sd, int on)
1440 {
1441 struct imx335 *imx335 = to_imx335(sd);
1442 struct i2c_client *client = imx335->client;
1443 int ret = 0;
1444
1445 dev_dbg(&imx335->client->dev, "s_stream: %d. %dx%d, hdr: %d, bpp: %d\n",
1446 on, imx335->cur_mode->width, imx335->cur_mode->height,
1447 imx335->cur_mode->hdr_mode, imx335->cur_mode->bpp);
1448
1449 mutex_lock(&imx335->mutex);
1450 on = !!on;
1451 if (on == imx335->streaming)
1452 goto unlock_and_return;
1453
1454 if (on) {
1455 ret = pm_runtime_get_sync(&client->dev);
1456 if (ret < 0) {
1457 pm_runtime_put_noidle(&client->dev);
1458 goto unlock_and_return;
1459 }
1460
1461 ret = __imx335_start_stream(imx335);
1462 if (ret) {
1463 v4l2_err(sd, "start stream failed while write regs\n");
1464 pm_runtime_put(&client->dev);
1465 goto unlock_and_return;
1466 }
1467 } else {
1468 __imx335_stop_stream(imx335);
1469 pm_runtime_put(&client->dev);
1470 }
1471
1472 imx335->streaming = on;
1473
1474 unlock_and_return:
1475 mutex_unlock(&imx335->mutex);
1476
1477 return ret;
1478 }
1479
imx335_s_power(struct v4l2_subdev * sd,int on)1480 static int imx335_s_power(struct v4l2_subdev *sd, int on)
1481 {
1482 struct imx335 *imx335 = to_imx335(sd);
1483 struct i2c_client *client = imx335->client;
1484 int ret = 0;
1485
1486 mutex_lock(&imx335->mutex);
1487
1488 if (imx335->power_on == !!on)
1489 goto unlock_and_return;
1490
1491 if (on) {
1492 ret = pm_runtime_get_sync(&client->dev);
1493 if (ret < 0) {
1494 pm_runtime_put_noidle(&client->dev);
1495 goto unlock_and_return;
1496 }
1497 imx335->power_on = true;
1498 } else {
1499 pm_runtime_put(&client->dev);
1500 imx335->power_on = false;
1501 }
1502
1503 unlock_and_return:
1504 mutex_unlock(&imx335->mutex);
1505
1506 return ret;
1507 }
1508
__imx335_power_on(struct imx335 * imx335)1509 static int __imx335_power_on(struct imx335 *imx335)
1510 {
1511 int ret;
1512 struct device *dev = &imx335->client->dev;
1513
1514 if (!IS_ERR_OR_NULL(imx335->pins_default)) {
1515 ret = pinctrl_select_state(imx335->pinctrl,
1516 imx335->pins_default);
1517 if (ret < 0)
1518 dev_err(dev, "could not set pins\n");
1519 }
1520
1521 ret = regulator_bulk_enable(IMX335_NUM_SUPPLIES, imx335->supplies);
1522 if (ret < 0) {
1523 dev_err(dev, "Failed to enable regulators\n");
1524 goto err_pinctrl;
1525 }
1526
1527 if (!IS_ERR(imx335->reset_gpio))
1528 gpiod_set_value_cansleep(imx335->reset_gpio, 1);
1529
1530 /* At least 500ns between power raising and Reset */
1531 udelay(10);
1532 if (!IS_ERR(imx335->reset_gpio))
1533 gpiod_set_value_cansleep(imx335->reset_gpio, 0);
1534
1535 ret = clk_set_rate(imx335->xvclk, IMX335_XVCLK_FREQ_37M);
1536 if (ret < 0)
1537 dev_warn(dev, "Failed to set xvclk rate\n");
1538 if (clk_get_rate(imx335->xvclk) != IMX335_XVCLK_FREQ_37M)
1539 dev_warn(dev, "xvclk mismatched\n");
1540 ret = clk_prepare_enable(imx335->xvclk);
1541 if (ret < 0) {
1542 dev_err(dev, "Failed to enable xvclk\n");
1543 goto err_clk;
1544 }
1545
1546 /* At least 20us between Reset and I2C communication */
1547 usleep_range(20, 30);
1548
1549 return 0;
1550
1551 err_clk:
1552 if (!IS_ERR(imx335->reset_gpio))
1553 gpiod_set_value_cansleep(imx335->reset_gpio, 1);
1554 regulator_bulk_disable(IMX335_NUM_SUPPLIES, imx335->supplies);
1555
1556 err_pinctrl:
1557 if (!IS_ERR_OR_NULL(imx335->pins_sleep))
1558 pinctrl_select_state(imx335->pinctrl, imx335->pins_sleep);
1559
1560 return ret;
1561 }
1562
__imx335_power_off(struct imx335 * imx335)1563 static void __imx335_power_off(struct imx335 *imx335)
1564 {
1565 int ret;
1566 struct device *dev = &imx335->client->dev;
1567
1568 if (!IS_ERR(imx335->reset_gpio))
1569 gpiod_set_value_cansleep(imx335->reset_gpio, 1);
1570 clk_disable_unprepare(imx335->xvclk);
1571 if (!IS_ERR_OR_NULL(imx335->pins_sleep)) {
1572 ret = pinctrl_select_state(imx335->pinctrl,
1573 imx335->pins_sleep);
1574 if (ret < 0)
1575 dev_dbg(dev, "could not set pins\n");
1576 }
1577 regulator_bulk_disable(IMX335_NUM_SUPPLIES, imx335->supplies);
1578 }
1579
imx335_runtime_resume(struct device * dev)1580 static int imx335_runtime_resume(struct device *dev)
1581 {
1582 struct i2c_client *client = to_i2c_client(dev);
1583 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1584 struct imx335 *imx335 = to_imx335(sd);
1585
1586 return __imx335_power_on(imx335);
1587 }
1588
imx335_runtime_suspend(struct device * dev)1589 static int imx335_runtime_suspend(struct device *dev)
1590 {
1591 struct i2c_client *client = to_i2c_client(dev);
1592 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1593 struct imx335 *imx335 = to_imx335(sd);
1594
1595 __imx335_power_off(imx335);
1596
1597 return 0;
1598 }
1599
imx335_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1600 static int imx335_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1601 {
1602 struct imx335 *imx335 = to_imx335(sd);
1603 struct v4l2_mbus_framefmt *try_fmt =
1604 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1605 const struct imx335_mode *def_mode = &supported_modes[0];
1606
1607 mutex_lock(&imx335->mutex);
1608 /* Initialize try_fmt */
1609 try_fmt->width = def_mode->width;
1610 try_fmt->height = def_mode->height;
1611 try_fmt->code = def_mode->bus_fmt;
1612 try_fmt->field = V4L2_FIELD_NONE;
1613
1614 mutex_unlock(&imx335->mutex);
1615 /* No crop or compose */
1616
1617 return 0;
1618 }
1619
imx335_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1620 static int imx335_enum_frame_interval(struct v4l2_subdev *sd,
1621 struct v4l2_subdev_pad_config *cfg,
1622 struct v4l2_subdev_frame_interval_enum *fie)
1623 {
1624 struct imx335 *imx335 = to_imx335(sd);
1625
1626 if (fie->index >= imx335->cfg_num)
1627 return -EINVAL;
1628
1629 fie->code = supported_modes[fie->index].bus_fmt;
1630 fie->width = supported_modes[fie->index].width;
1631 fie->height = supported_modes[fie->index].height;
1632 fie->interval = supported_modes[fie->index].max_fps;
1633 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1634 return 0;
1635 }
1636
1637 #define DST_WIDTH 2592
1638 #define DST_HEIGHT 1944
1639
1640 /*
1641 * The resolution of the driver configuration needs to be exactly
1642 * the same as the current output resolution of the sensor,
1643 * the input width of the isp needs to be 16 aligned,
1644 * the input height of the isp needs to be 8 aligned.
1645 * Can be cropped to standard resolution by this function,
1646 * otherwise it will crop out strange resolution according
1647 * to the alignment rules.
1648 */
imx335_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1649 static int imx335_get_selection(struct v4l2_subdev *sd,
1650 struct v4l2_subdev_pad_config *cfg,
1651 struct v4l2_subdev_selection *sel)
1652 {
1653 /*
1654 * From "Pixel Array Image Drawing in All scan mode",
1655 * there are 12 pixel offset on horizontal and vertical.
1656 */
1657 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1658 sel->r.left = 12;
1659 sel->r.width = DST_WIDTH;
1660 sel->r.top = 12;
1661 sel->r.height = DST_HEIGHT;
1662 return 0;
1663 }
1664 return -EINVAL;
1665 }
1666
1667 static const struct dev_pm_ops imx335_pm_ops = {
1668 SET_RUNTIME_PM_OPS(imx335_runtime_suspend,
1669 imx335_runtime_resume, NULL)
1670 };
1671
1672 static const struct v4l2_subdev_internal_ops imx335_internal_ops = {
1673 .open = imx335_open,
1674 };
1675
1676 static const struct v4l2_subdev_core_ops imx335_core_ops = {
1677 .s_power = imx335_s_power,
1678 .ioctl = imx335_ioctl,
1679 #ifdef CONFIG_COMPAT
1680 .compat_ioctl32 = imx335_compat_ioctl32,
1681 #endif
1682 };
1683
1684 static const struct v4l2_subdev_video_ops imx335_video_ops = {
1685 .s_stream = imx335_s_stream,
1686 .g_frame_interval = imx335_g_frame_interval,
1687 };
1688
1689 static const struct v4l2_subdev_pad_ops imx335_pad_ops = {
1690 .enum_mbus_code = imx335_enum_mbus_code,
1691 .enum_frame_size = imx335_enum_frame_sizes,
1692 .enum_frame_interval = imx335_enum_frame_interval,
1693 .get_fmt = imx335_get_fmt,
1694 .set_fmt = imx335_set_fmt,
1695 .get_selection = imx335_get_selection,
1696 .get_mbus_config = imx335_g_mbus_config,
1697 };
1698
1699 static const struct v4l2_subdev_ops imx335_subdev_ops = {
1700 .core = &imx335_core_ops,
1701 .video = &imx335_video_ops,
1702 .pad = &imx335_pad_ops,
1703 };
1704
imx335_set_ctrl(struct v4l2_ctrl * ctrl)1705 static int imx335_set_ctrl(struct v4l2_ctrl *ctrl)
1706 {
1707 struct imx335 *imx335 = container_of(ctrl->handler,
1708 struct imx335, ctrl_handler);
1709 struct i2c_client *client = imx335->client;
1710 s64 max;
1711 u32 vts = 0;
1712 int ret = 0;
1713 u32 shr0 = 0;
1714
1715 /* Propagate change of current control to all related controls */
1716 switch (ctrl->id) {
1717 case V4L2_CID_VBLANK:
1718 if (imx335->cur_mode->hdr_mode == NO_HDR) {
1719 /* Update max exposure while meeting expected vblanking */
1720 max = imx335->cur_mode->height + ctrl->val - SHR0_MIN;
1721 __v4l2_ctrl_modify_range(imx335->exposure,
1722 imx335->exposure->minimum, max,
1723 imx335->exposure->step,
1724 imx335->exposure->default_value);
1725 }
1726 break;
1727 }
1728
1729 if (!pm_runtime_get_if_in_use(&client->dev))
1730 return 0;
1731
1732 switch (ctrl->id) {
1733 case V4L2_CID_EXPOSURE:
1734 if (imx335->cur_mode->hdr_mode != NO_HDR)
1735 goto ctrl_end;
1736 shr0 = imx335->cur_vts - ctrl->val;
1737 ret = imx335_write_reg(imx335->client, IMX335_LF_EXPO_REG_L,
1738 IMX335_REG_VALUE_08BIT,
1739 IMX335_FETCH_EXP_L(shr0));
1740 ret |= imx335_write_reg(imx335->client, IMX335_LF_EXPO_REG_M,
1741 IMX335_REG_VALUE_08BIT,
1742 IMX335_FETCH_EXP_M(shr0));
1743 ret |= imx335_write_reg(imx335->client, IMX335_LF_EXPO_REG_H,
1744 IMX335_REG_VALUE_08BIT,
1745 IMX335_FETCH_EXP_H(shr0));
1746 dev_dbg(&client->dev, "set exposure(shr0) %d = cur_vts(%d) - val(%d)\n",
1747 shr0, imx335->cur_vts, ctrl->val);
1748 break;
1749 case V4L2_CID_ANALOGUE_GAIN:
1750 if (imx335->cur_mode->hdr_mode != NO_HDR)
1751 goto ctrl_end;
1752 ret = imx335_write_reg(imx335->client, IMX335_LF_GAIN_REG_H,
1753 IMX335_REG_VALUE_08BIT,
1754 IMX335_FETCH_GAIN_H(ctrl->val));
1755 ret |= imx335_write_reg(imx335->client, IMX335_LF_GAIN_REG_L,
1756 IMX335_REG_VALUE_08BIT,
1757 IMX335_FETCH_GAIN_L(ctrl->val));
1758 dev_dbg(&client->dev, "set analog gain 0x%x\n", ctrl->val);
1759 break;
1760 case V4L2_CID_VBLANK:
1761 vts = ctrl->val + imx335->cur_mode->height;
1762 /*
1763 * vts of hdr mode is double to correct T-line calculation.
1764 * Restore before write to reg.
1765 */
1766 if (imx335->cur_mode->hdr_mode == HDR_X2) {
1767 vts = (vts + 3) / 4 * 4;
1768 imx335->cur_vts = vts;
1769 vts /= 2;
1770 } else if (imx335->cur_mode->hdr_mode == HDR_X3) {
1771 vts = (vts + 11) / 12 * 12;
1772 imx335->cur_vts = vts;
1773 vts /= 4;
1774 } else {
1775 imx335->cur_vts = vts;
1776 }
1777 ret = imx335_write_reg(imx335->client, IMX335_VTS_REG_L,
1778 IMX335_REG_VALUE_08BIT,
1779 IMX335_FETCH_VTS_L(vts));
1780 ret |= imx335_write_reg(imx335->client, IMX335_VTS_REG_M,
1781 IMX335_REG_VALUE_08BIT,
1782 IMX335_FETCH_VTS_M(vts));
1783 ret |= imx335_write_reg(imx335->client, IMX335_VTS_REG_H,
1784 IMX335_REG_VALUE_08BIT,
1785 IMX335_FETCH_VTS_H(vts));
1786 dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
1787 break;
1788 case V4L2_CID_HFLIP:
1789 ret = imx335_write_reg(imx335->client, IMX335_HREVERSE_REG,
1790 IMX335_REG_VALUE_08BIT, !!ctrl->val);
1791 break;
1792 case V4L2_CID_VFLIP:
1793 if (ctrl->val) {
1794 ret = imx335_write_reg(imx335->client, IMX335_VREVERSE_REG,
1795 IMX335_REG_VALUE_08BIT, !!ctrl->val);
1796 ret |= imx335_write_reg(imx335->client, 0x3081,
1797 IMX335_REG_VALUE_08BIT, 0xfe);
1798 ret |= imx335_write_reg(imx335->client, 0x3083,
1799 IMX335_REG_VALUE_08BIT, 0xfe);
1800 ret |= imx335_write_reg(imx335->client, 0x30b6,
1801 IMX335_REG_VALUE_08BIT, 0xfa);
1802 ret |= imx335_write_reg(imx335->client, 0x30b7,
1803 IMX335_REG_VALUE_08BIT, 0x01);
1804 ret |= imx335_write_reg(imx335->client, 0x3116,
1805 IMX335_REG_VALUE_08BIT, 0x02);
1806 ret |= imx335_write_reg(imx335->client, 0x3117,
1807 IMX335_REG_VALUE_08BIT, 0x00);
1808 } else {
1809 ret = imx335_write_reg(imx335->client, IMX335_VREVERSE_REG,
1810 IMX335_REG_VALUE_08BIT, !!ctrl->val);
1811 ret |= imx335_write_reg(imx335->client, 0x3081,
1812 IMX335_REG_VALUE_08BIT, 0x02);
1813 ret |= imx335_write_reg(imx335->client, 0x3083,
1814 IMX335_REG_VALUE_08BIT, 0x02);
1815 ret |= imx335_write_reg(imx335->client, 0x30b6,
1816 IMX335_REG_VALUE_08BIT, 0x00);
1817 ret |= imx335_write_reg(imx335->client, 0x30b7,
1818 IMX335_REG_VALUE_08BIT, 0x00);
1819 ret |= imx335_write_reg(imx335->client, 0x3116,
1820 IMX335_REG_VALUE_08BIT, 0x08);
1821 ret |= imx335_write_reg(imx335->client, 0x3117,
1822 IMX335_REG_VALUE_08BIT, 0x00);
1823 }
1824 break;
1825 default:
1826 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1827 __func__, ctrl->id, ctrl->val);
1828 break;
1829 }
1830
1831 ctrl_end:
1832 pm_runtime_put(&client->dev);
1833
1834 return ret;
1835 }
1836
1837 static const struct v4l2_ctrl_ops imx335_ctrl_ops = {
1838 .s_ctrl = imx335_set_ctrl,
1839 };
1840
imx335_initialize_controls(struct imx335 * imx335)1841 static int imx335_initialize_controls(struct imx335 *imx335)
1842 {
1843 const struct imx335_mode *mode;
1844 struct v4l2_ctrl_handler *handler;
1845 s64 exposure_max, vblank_def;
1846 u64 pixel_rate;
1847 u32 h_blank;
1848 int ret;
1849
1850 handler = &imx335->ctrl_handler;
1851 mode = imx335->cur_mode;
1852 ret = v4l2_ctrl_handler_init(handler, 8);
1853 if (ret)
1854 return ret;
1855 handler->lock = &imx335->mutex;
1856
1857 imx335->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1858 V4L2_CID_LINK_FREQ,
1859 ARRAY_SIZE(link_freq_items) - 1, 0,
1860 link_freq_items);
1861
1862 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1863 pixel_rate = (u32)link_freq_items[0] / mode->bpp * 2 * IMX335_4LANES;
1864 imx335->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1865 V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1, pixel_rate);
1866
1867 h_blank = mode->hts_def - mode->width;
1868 imx335->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1869 h_blank, h_blank, 1, h_blank);
1870 if (imx335->hblank)
1871 imx335->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1872
1873 vblank_def = mode->vts_def - mode->height;
1874 imx335->vblank = v4l2_ctrl_new_std(handler, &imx335_ctrl_ops,
1875 V4L2_CID_VBLANK, vblank_def,
1876 IMX335_VTS_MAX - mode->height,
1877 1, vblank_def);
1878 imx335->cur_vts = mode->vts_def;
1879
1880 exposure_max = mode->vts_def - SHR0_MIN;
1881 imx335->exposure = v4l2_ctrl_new_std(handler, &imx335_ctrl_ops,
1882 V4L2_CID_EXPOSURE, IMX335_EXPOSURE_MIN,
1883 exposure_max, IMX335_EXPOSURE_STEP,
1884 mode->exp_def);
1885
1886 imx335->anal_a_gain = v4l2_ctrl_new_std(handler, &imx335_ctrl_ops,
1887 V4L2_CID_ANALOGUE_GAIN, IMX335_GAIN_MIN,
1888 IMX335_GAIN_MAX, IMX335_GAIN_STEP,
1889 IMX335_GAIN_DEFAULT);
1890
1891 v4l2_ctrl_new_std(handler, &imx335_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1892 v4l2_ctrl_new_std(handler, &imx335_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1893
1894 if (handler->error) {
1895 ret = handler->error;
1896 dev_err(&imx335->client->dev,
1897 "Failed to init controls(%d)\n", ret);
1898 goto err_free_handler;
1899 }
1900
1901 imx335->subdev.ctrl_handler = handler;
1902 imx335->has_init_exp = false;
1903
1904 return 0;
1905
1906 err_free_handler:
1907 v4l2_ctrl_handler_free(handler);
1908
1909 return ret;
1910 }
1911
imx335_check_sensor_id(struct imx335 * imx335,struct i2c_client * client)1912 static int imx335_check_sensor_id(struct imx335 *imx335,
1913 struct i2c_client *client)
1914 {
1915 struct device *dev = &imx335->client->dev;
1916 u32 id = 0;
1917 int ret;
1918
1919 ret = imx335_read_reg(client, IMX335_REG_CHIP_ID,
1920 IMX335_REG_VALUE_08BIT, &id);
1921 if (id != CHIP_ID) {
1922 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1923 return -ENODEV;
1924 }
1925
1926 dev_info(dev, "Detected imx335 id %06x\n", CHIP_ID);
1927
1928 return 0;
1929 }
1930
imx335_configure_regulators(struct imx335 * imx335)1931 static int imx335_configure_regulators(struct imx335 *imx335)
1932 {
1933 unsigned int i;
1934
1935 for (i = 0; i < IMX335_NUM_SUPPLIES; i++)
1936 imx335->supplies[i].supply = imx335_supply_names[i];
1937
1938 return devm_regulator_bulk_get(&imx335->client->dev,
1939 IMX335_NUM_SUPPLIES,
1940 imx335->supplies);
1941 }
1942
imx335_probe(struct i2c_client * client,const struct i2c_device_id * id)1943 static int imx335_probe(struct i2c_client *client,
1944 const struct i2c_device_id *id)
1945 {
1946 struct device *dev = &client->dev;
1947 struct device_node *node = dev->of_node;
1948 struct imx335 *imx335;
1949 struct v4l2_subdev *sd;
1950 char facing[2];
1951 int ret;
1952 u32 i, hdr_mode = 0;
1953
1954 dev_info(dev, "driver version: %02x.%02x.%02x",
1955 DRIVER_VERSION >> 16,
1956 (DRIVER_VERSION & 0xff00) >> 8,
1957 DRIVER_VERSION & 0x00ff);
1958
1959 imx335 = devm_kzalloc(dev, sizeof(*imx335), GFP_KERNEL);
1960 if (!imx335)
1961 return -ENOMEM;
1962
1963 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1964 &imx335->module_index);
1965 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1966 &imx335->module_facing);
1967 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1968 &imx335->module_name);
1969 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1970 &imx335->len_name);
1971 if (ret) {
1972 dev_err(dev, "could not get module information!\n");
1973 return -EINVAL;
1974 }
1975
1976 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1977 if (ret) {
1978 hdr_mode = NO_HDR;
1979 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
1980 }
1981 imx335->client = client;
1982 imx335->cfg_num = ARRAY_SIZE(supported_modes);
1983 for (i = 0; i < imx335->cfg_num; i++) {
1984 if (hdr_mode == supported_modes[i].hdr_mode) {
1985 imx335->cur_mode = &supported_modes[i];
1986 break;
1987 }
1988 }
1989
1990 imx335->xvclk = devm_clk_get(dev, "xvclk");
1991 if (IS_ERR(imx335->xvclk)) {
1992 dev_err(dev, "Failed to get xvclk\n");
1993 return -EINVAL;
1994 }
1995
1996 imx335->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1997 if (IS_ERR(imx335->reset_gpio))
1998 dev_warn(dev, "Failed to get reset-gpios\n");
1999
2000 imx335->pinctrl = devm_pinctrl_get(dev);
2001 if (!IS_ERR(imx335->pinctrl)) {
2002 imx335->pins_default =
2003 pinctrl_lookup_state(imx335->pinctrl,
2004 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2005 if (IS_ERR(imx335->pins_default))
2006 dev_info(dev, "could not get default pinstate\n");
2007
2008 imx335->pins_sleep =
2009 pinctrl_lookup_state(imx335->pinctrl,
2010 OF_CAMERA_PINCTRL_STATE_SLEEP);
2011 if (IS_ERR(imx335->pins_sleep))
2012 dev_info(dev, "could not get sleep pinstate\n");
2013 } else {
2014 dev_info(dev, "no pinctrl\n");
2015 }
2016
2017 ret = imx335_configure_regulators(imx335);
2018 if (ret) {
2019 dev_err(dev, "Failed to get power regulators\n");
2020 return ret;
2021 }
2022
2023 mutex_init(&imx335->mutex);
2024
2025 sd = &imx335->subdev;
2026 v4l2_i2c_subdev_init(sd, client, &imx335_subdev_ops);
2027 ret = imx335_initialize_controls(imx335);
2028 if (ret)
2029 goto err_destroy_mutex;
2030
2031 ret = __imx335_power_on(imx335);
2032 if (ret)
2033 goto err_free_handler;
2034
2035 ret = imx335_check_sensor_id(imx335, client);
2036 if (ret)
2037 goto err_power_off;
2038
2039 sd->internal_ops = &imx335_internal_ops;
2040 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2041 V4L2_SUBDEV_FL_HAS_EVENTS;
2042
2043 #if defined(CONFIG_MEDIA_CONTROLLER)
2044 imx335->pad.flags = MEDIA_PAD_FL_SOURCE;
2045 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2046 ret = media_entity_pads_init(&sd->entity, 1, &imx335->pad);
2047 if (ret < 0)
2048 goto err_power_off;
2049 #endif
2050
2051 memset(facing, 0, sizeof(facing));
2052 if (strcmp(imx335->module_facing, "back") == 0)
2053 facing[0] = 'b';
2054 else
2055 facing[0] = 'f';
2056
2057 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2058 imx335->module_index, facing,
2059 IMX335_NAME, dev_name(sd->dev));
2060 ret = v4l2_async_register_subdev_sensor_common(sd);
2061 if (ret) {
2062 dev_err(dev, "v4l2 async register subdev failed\n");
2063 goto err_clean_entity;
2064 }
2065
2066 pm_runtime_set_active(dev);
2067 pm_runtime_enable(dev);
2068 pm_runtime_idle(dev);
2069
2070 return 0;
2071
2072 err_clean_entity:
2073 #if defined(CONFIG_MEDIA_CONTROLLER)
2074 media_entity_cleanup(&sd->entity);
2075 #endif
2076 err_power_off:
2077 __imx335_power_off(imx335);
2078 err_free_handler:
2079 v4l2_ctrl_handler_free(&imx335->ctrl_handler);
2080 err_destroy_mutex:
2081 mutex_destroy(&imx335->mutex);
2082
2083 return ret;
2084 }
2085
imx335_remove(struct i2c_client * client)2086 static int imx335_remove(struct i2c_client *client)
2087 {
2088 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2089 struct imx335 *imx335 = to_imx335(sd);
2090
2091 v4l2_async_unregister_subdev(sd);
2092 #if defined(CONFIG_MEDIA_CONTROLLER)
2093 media_entity_cleanup(&sd->entity);
2094 #endif
2095 v4l2_ctrl_handler_free(&imx335->ctrl_handler);
2096 mutex_destroy(&imx335->mutex);
2097
2098 pm_runtime_disable(&client->dev);
2099 if (!pm_runtime_status_suspended(&client->dev))
2100 __imx335_power_off(imx335);
2101 pm_runtime_set_suspended(&client->dev);
2102
2103 return 0;
2104 }
2105
2106 #if IS_ENABLED(CONFIG_OF)
2107 static const struct of_device_id imx335_of_match[] = {
2108 { .compatible = "sony,imx335" },
2109 {},
2110 };
2111 MODULE_DEVICE_TABLE(of, imx335_of_match);
2112 #endif
2113
2114 static const struct i2c_device_id imx335_match_id[] = {
2115 { "sony,imx335", 0 },
2116 { },
2117 };
2118
2119 static struct i2c_driver imx335_i2c_driver = {
2120 .driver = {
2121 .name = IMX335_NAME,
2122 .pm = &imx335_pm_ops,
2123 .of_match_table = of_match_ptr(imx335_of_match),
2124 },
2125 .probe = &imx335_probe,
2126 .remove = &imx335_remove,
2127 .id_table = imx335_match_id,
2128 };
2129
sensor_mod_init(void)2130 static int __init sensor_mod_init(void)
2131 {
2132 return i2c_add_driver(&imx335_i2c_driver);
2133 }
2134
sensor_mod_exit(void)2135 static void __exit sensor_mod_exit(void)
2136 {
2137 i2c_del_driver(&imx335_i2c_driver);
2138 }
2139
2140 device_initcall_sync(sensor_mod_init);
2141 module_exit(sensor_mod_exit);
2142
2143 MODULE_DESCRIPTION("Sony imx335 sensor driver");
2144 MODULE_LICENSE("GPL v2");
2145