xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/imx323.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * imx323 driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * V0.0X01.0X01 add poweron function.
8*4882a593Smuzhiyun  * V0.0X01.0X02 add enum_frame_interval function.
9*4882a593Smuzhiyun  * V0.0X01.0X03 add quick stream on/off
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/clk.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/pm_runtime.h>
19*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun #include <linux/sysfs.h>
22*4882a593Smuzhiyun #include <linux/version.h>
23*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
24*4882a593Smuzhiyun #include <media/media-entity.h>
25*4882a593Smuzhiyun #include <media/v4l2-async.h>
26*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
27*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x03)
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
32*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN		V4L2_CID_GAIN
33*4882a593Smuzhiyun #endif
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /* 74.25Mhz */
36*4882a593Smuzhiyun #define IMX323_PIXEL_RATE		(74250 * 1000)
37*4882a593Smuzhiyun #define IMX323_XVCLK_FREQ		37125000
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define CHIP_ID				0xa
40*4882a593Smuzhiyun #define IMX323_REG_CHIP_ID		0x0112
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define IMX323_REG_CTRL_MODE		0x0100
43*4882a593Smuzhiyun #define IMX323_MODE_SW_STANDBY		0x0
44*4882a593Smuzhiyun #define IMX323_MODE_STREAMING		BIT(0)
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define IMX323_REG_EXPOSURE		0x0202
47*4882a593Smuzhiyun #define IMX323_EXPOSURE_MIN		0
48*4882a593Smuzhiyun #define IMX323_EXPOSURE_STEP		1
49*4882a593Smuzhiyun #define IMX323_VTS_MAX			0x465
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define IMX323_REG_ANALOG_GAIN		0x301e
52*4882a593Smuzhiyun #define ANALOG_GAIN_MIN			0x0
53*4882a593Smuzhiyun #define ANALOG_GAIN_MAX			0x78
54*4882a593Smuzhiyun #define ANALOG_GAIN_STEP		1
55*4882a593Smuzhiyun #define ANALOG_GAIN_DEFAULT		0x10
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define IMX323_REG_VTS			0x0340
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define IMX323_REG_ORIENTATION		0x0101
60*4882a593Smuzhiyun #define IMX323_ORIENTATION_H		0x1
61*4882a593Smuzhiyun #define IMX323_ORIENTATION_V		0x2
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define REG_NULL			0xFFFF
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define IMX323_REG_VALUE_08BIT		1
66*4882a593Smuzhiyun #define IMX323_REG_VALUE_16BIT		2
67*4882a593Smuzhiyun #define IMX323_REG_VALUE_24BIT		3
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /* h_offs 35 v_offs 14 */
70*4882a593Smuzhiyun #define PIX_FORMAT MEDIA_BUS_FMT_SBGGR10_1X10
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define IMX323_NAME			"imx323"
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun struct cam_regulator {
75*4882a593Smuzhiyun 	char name[32];
76*4882a593Smuzhiyun 	int val;
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun static const struct cam_regulator imx323_regulator[] = {
80*4882a593Smuzhiyun 	{"avdd", 2800000},	/* Analog power */
81*4882a593Smuzhiyun 	{"dovdd", 1800000},	/* Digital I/O power */
82*4882a593Smuzhiyun 	{"dvdd", 1200000},	/* Digital core power */
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define IMX323_NUM_SUPPLIES ARRAY_SIZE(imx323_regulator)
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun struct regval {
88*4882a593Smuzhiyun 	u16 addr;
89*4882a593Smuzhiyun 	u8 val;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun struct imx323_mode {
93*4882a593Smuzhiyun 	u32 width;
94*4882a593Smuzhiyun 	u32 height;
95*4882a593Smuzhiyun 	struct v4l2_fract max_fps;
96*4882a593Smuzhiyun 	u32 hts_def;
97*4882a593Smuzhiyun 	u32 vts_def;
98*4882a593Smuzhiyun 	u32 exp_def;
99*4882a593Smuzhiyun 	const struct regval *reg_list;
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun struct imx323 {
103*4882a593Smuzhiyun 	struct i2c_client	*client;
104*4882a593Smuzhiyun 	struct clk		*xvclk;
105*4882a593Smuzhiyun 	struct gpio_desc	*reset_gpio;
106*4882a593Smuzhiyun 	struct gpio_desc	*pwdn_gpio;
107*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[IMX323_NUM_SUPPLIES];
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	struct v4l2_subdev	subdev;
110*4882a593Smuzhiyun 	struct media_pad	pad;
111*4882a593Smuzhiyun 	struct v4l2_ctrl_handler ctrl_handler;
112*4882a593Smuzhiyun 	struct v4l2_ctrl	*exposure;
113*4882a593Smuzhiyun 	struct v4l2_ctrl	*anal_gain;
114*4882a593Smuzhiyun 	struct v4l2_ctrl	*digi_gain;
115*4882a593Smuzhiyun 	struct v4l2_ctrl	*hblank;
116*4882a593Smuzhiyun 	struct v4l2_ctrl	*vblank;
117*4882a593Smuzhiyun 	struct v4l2_ctrl	*test_pattern;
118*4882a593Smuzhiyun 	struct mutex		mutex;
119*4882a593Smuzhiyun 	bool			streaming;
120*4882a593Smuzhiyun 	bool			power_on;
121*4882a593Smuzhiyun 	const struct imx323_mode *cur_mode;
122*4882a593Smuzhiyun 	u32			module_index;
123*4882a593Smuzhiyun 	const char		*module_facing;
124*4882a593Smuzhiyun 	const char		*module_name;
125*4882a593Smuzhiyun 	const char		*len_name;
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun #define to_imx323(sd) container_of(sd, struct imx323, subdev)
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun /*
131*4882a593Smuzhiyun  * Xclk 37.125Mhz
132*4882a593Smuzhiyun  * Pclk 74.25Mhz
133*4882a593Smuzhiyun  * linelength 2200(0x44c * 2)
134*4882a593Smuzhiyun  * framelength 1125(0x465)
135*4882a593Smuzhiyun  * grabwindow_width 1920
136*4882a593Smuzhiyun  * grabwindow_height 1080
137*4882a593Smuzhiyun  * max_framerate 30fps
138*4882a593Smuzhiyun  * dvp bt656 10bit
139*4882a593Smuzhiyun  */
140*4882a593Smuzhiyun static const struct regval imx323_regs[] = {
141*4882a593Smuzhiyun 	{0x0100, 0x00},
142*4882a593Smuzhiyun 	{0x0009, 0x3f},
143*4882a593Smuzhiyun 	{0x0340, 0x04},
144*4882a593Smuzhiyun 	{0x0341, 0x65},
145*4882a593Smuzhiyun 	{0x0342, 0x04},
146*4882a593Smuzhiyun 	{0x0343, 0x4c},
147*4882a593Smuzhiyun 	{0x3000, 0x31},
148*4882a593Smuzhiyun 	{0x3002, 0x0f},
149*4882a593Smuzhiyun 	{0x3011, 0x00},
150*4882a593Smuzhiyun 	{0x3013, 0x40},
151*4882a593Smuzhiyun 	{0x3016, 0x3c},
152*4882a593Smuzhiyun 	{0x301a, 0x51},
153*4882a593Smuzhiyun 	{0x301f, 0x73},
154*4882a593Smuzhiyun 	{0x3021, 0x80},
155*4882a593Smuzhiyun 	{0x3022, 0x40},
156*4882a593Smuzhiyun 	{0x3027, 0x20},
157*4882a593Smuzhiyun 	{0x302c, 0x00},
158*4882a593Smuzhiyun 	{0x302d, 0x48}, /* low 10bit */
159*4882a593Smuzhiyun 	{0x304f, 0x47},
160*4882a593Smuzhiyun 	{0x3054, 0x10},
161*4882a593Smuzhiyun 	{0x307a, 0x40},
162*4882a593Smuzhiyun 	{0x307b, 0x02},
163*4882a593Smuzhiyun 	{0x3117, 0x0d},
164*4882a593Smuzhiyun 	{REG_NULL, 0x00},
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun static const struct imx323_mode supported_modes[] = {
168*4882a593Smuzhiyun 	{
169*4882a593Smuzhiyun 		.width = 2200,
170*4882a593Smuzhiyun 		.height = 1125,
171*4882a593Smuzhiyun 		.max_fps = {
172*4882a593Smuzhiyun 			.numerator = 10000,
173*4882a593Smuzhiyun 			.denominator = 300000,
174*4882a593Smuzhiyun 		},
175*4882a593Smuzhiyun 		.exp_def = 0x0100,
176*4882a593Smuzhiyun 		.hts_def = 0x044c * 2,
177*4882a593Smuzhiyun 		.vts_def = 0x0465,
178*4882a593Smuzhiyun 		.reg_list = imx323_regs,
179*4882a593Smuzhiyun 	}
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun static const char * const imx323_test_pattern_menu[] = {
183*4882a593Smuzhiyun 	"Disabled",
184*4882a593Smuzhiyun 	"Vertical Color Bar Type 1",
185*4882a593Smuzhiyun 	"Vertical Color Bar Type 2",
186*4882a593Smuzhiyun 	"Vertical Color Bar Type 3",
187*4882a593Smuzhiyun 	"Vertical Color Bar Type 4"
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun /* Write registers up to 4 at a time */
imx323_write_reg(struct i2c_client * client,u16 reg,int len,u32 val)191*4882a593Smuzhiyun static int imx323_write_reg(struct i2c_client *client, u16 reg,
192*4882a593Smuzhiyun 			    int len, u32 val)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	u32 buf_i, val_i;
195*4882a593Smuzhiyun 	u8 buf[6];
196*4882a593Smuzhiyun 	u8 *val_p;
197*4882a593Smuzhiyun 	__be32 val_be;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	if (len > 4)
200*4882a593Smuzhiyun 		return -EINVAL;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	buf[0] = reg >> 8;
203*4882a593Smuzhiyun 	buf[1] = reg & 0xff;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	val_be = cpu_to_be32(val);
206*4882a593Smuzhiyun 	val_p = (u8 *)&val_be;
207*4882a593Smuzhiyun 	buf_i = 2;
208*4882a593Smuzhiyun 	val_i = 4 - len;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	while (val_i < 4)
211*4882a593Smuzhiyun 		buf[buf_i++] = val_p[val_i++];
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	if (i2c_master_send(client, buf, len + 2) != len + 2)
214*4882a593Smuzhiyun 		return -EIO;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	return 0;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun 
imx323_write_array(struct i2c_client * client,const struct regval * regs)219*4882a593Smuzhiyun static int imx323_write_array(struct i2c_client *client,
220*4882a593Smuzhiyun 			      const struct regval *regs)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	u32 i;
223*4882a593Smuzhiyun 	int ret = 0;
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
226*4882a593Smuzhiyun 		ret = imx323_write_reg(client, regs[i].addr,
227*4882a593Smuzhiyun 				       IMX323_REG_VALUE_08BIT, regs[i].val);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	return ret;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun /* Read registers up to 4 at a time */
imx323_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)233*4882a593Smuzhiyun static int imx323_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
234*4882a593Smuzhiyun 			   u32 *val)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun 	struct i2c_msg msgs[2];
237*4882a593Smuzhiyun 	u8 *data_be_p;
238*4882a593Smuzhiyun 	__be32 data_be = 0;
239*4882a593Smuzhiyun 	__be16 reg_addr_be = cpu_to_be16(reg);
240*4882a593Smuzhiyun 	int ret;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	if (len > 4 || !len)
243*4882a593Smuzhiyun 		return -EINVAL;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	data_be_p = (u8 *)&data_be;
246*4882a593Smuzhiyun 	/* Write register address */
247*4882a593Smuzhiyun 	msgs[0].addr = client->addr;
248*4882a593Smuzhiyun 	msgs[0].flags = 0;
249*4882a593Smuzhiyun 	msgs[0].len = 2;
250*4882a593Smuzhiyun 	msgs[0].buf = (u8 *)&reg_addr_be;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	/* Read data from register */
253*4882a593Smuzhiyun 	msgs[1].addr = client->addr;
254*4882a593Smuzhiyun 	msgs[1].flags = I2C_M_RD;
255*4882a593Smuzhiyun 	msgs[1].len = len;
256*4882a593Smuzhiyun 	msgs[1].buf = &data_be_p[4 - len];
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
259*4882a593Smuzhiyun 	if (ret != ARRAY_SIZE(msgs))
260*4882a593Smuzhiyun 		return -EIO;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	*val = be32_to_cpu(data_be);
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	return 0;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
imx323_get_reso_dist(const struct imx323_mode * mode,struct v4l2_mbus_framefmt * framefmt)267*4882a593Smuzhiyun static int imx323_get_reso_dist(const struct imx323_mode *mode,
268*4882a593Smuzhiyun 				struct v4l2_mbus_framefmt *framefmt)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun 	return abs(mode->width - framefmt->width) +
271*4882a593Smuzhiyun 	       abs(mode->height - framefmt->height);
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun static const struct imx323_mode *
imx323_find_best_fit(struct v4l2_subdev_format * fmt)275*4882a593Smuzhiyun imx323_find_best_fit(struct v4l2_subdev_format *fmt)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *framefmt = &fmt->format;
278*4882a593Smuzhiyun 	int dist;
279*4882a593Smuzhiyun 	int cur_best_fit = 0;
280*4882a593Smuzhiyun 	int cur_best_fit_dist = -1;
281*4882a593Smuzhiyun 	u32 i;
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
284*4882a593Smuzhiyun 		dist = imx323_get_reso_dist(&supported_modes[i], framefmt);
285*4882a593Smuzhiyun 		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
286*4882a593Smuzhiyun 			cur_best_fit_dist = dist;
287*4882a593Smuzhiyun 			cur_best_fit = i;
288*4882a593Smuzhiyun 		}
289*4882a593Smuzhiyun 	}
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	return &supported_modes[cur_best_fit];
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun 
imx323_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)294*4882a593Smuzhiyun static int imx323_set_fmt(struct v4l2_subdev *sd,
295*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
296*4882a593Smuzhiyun 			  struct v4l2_subdev_format *fmt)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun 	struct imx323 *imx323 = to_imx323(sd);
299*4882a593Smuzhiyun 	const struct imx323_mode *mode;
300*4882a593Smuzhiyun 	s64 h_blank, vblank_def;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	mutex_lock(&imx323->mutex);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	mode = imx323_find_best_fit(fmt);
305*4882a593Smuzhiyun 	fmt->format.code = PIX_FORMAT;
306*4882a593Smuzhiyun 	fmt->format.width = mode->width;
307*4882a593Smuzhiyun 	fmt->format.height = mode->height;
308*4882a593Smuzhiyun 	fmt->format.field = V4L2_FIELD_NONE;
309*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
310*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
311*4882a593Smuzhiyun 		*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
312*4882a593Smuzhiyun #else
313*4882a593Smuzhiyun 		mutex_unlock(&imx323->mutex);
314*4882a593Smuzhiyun 		return -ENOTTY;
315*4882a593Smuzhiyun #endif
316*4882a593Smuzhiyun 	} else {
317*4882a593Smuzhiyun 		imx323->cur_mode = mode;
318*4882a593Smuzhiyun 		h_blank = mode->hts_def - mode->width;
319*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(imx323->hblank, h_blank,
320*4882a593Smuzhiyun 					 h_blank, 1, h_blank);
321*4882a593Smuzhiyun 		vblank_def = mode->vts_def - mode->height;
322*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(imx323->vblank, vblank_def,
323*4882a593Smuzhiyun 					 IMX323_VTS_MAX - mode->height,
324*4882a593Smuzhiyun 					 1, vblank_def);
325*4882a593Smuzhiyun 	}
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	mutex_unlock(&imx323->mutex);
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	return 0;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun 
imx323_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)332*4882a593Smuzhiyun static int imx323_get_fmt(struct v4l2_subdev *sd,
333*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
334*4882a593Smuzhiyun 			  struct v4l2_subdev_format *fmt)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun 	struct imx323 *imx323 = to_imx323(sd);
337*4882a593Smuzhiyun 	const struct imx323_mode *mode = imx323->cur_mode;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	mutex_lock(&imx323->mutex);
340*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
341*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
342*4882a593Smuzhiyun 		fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
343*4882a593Smuzhiyun #else
344*4882a593Smuzhiyun 		mutex_unlock(&imx323->mutex);
345*4882a593Smuzhiyun 		return -ENOTTY;
346*4882a593Smuzhiyun #endif
347*4882a593Smuzhiyun 	} else {
348*4882a593Smuzhiyun 		fmt->format.width = mode->width;
349*4882a593Smuzhiyun 		fmt->format.height = mode->height;
350*4882a593Smuzhiyun 		fmt->format.code = PIX_FORMAT;
351*4882a593Smuzhiyun 		fmt->format.field = V4L2_FIELD_NONE;
352*4882a593Smuzhiyun 	}
353*4882a593Smuzhiyun 	mutex_unlock(&imx323->mutex);
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	return 0;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun 
imx323_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)358*4882a593Smuzhiyun static int imx323_enum_mbus_code(struct v4l2_subdev *sd,
359*4882a593Smuzhiyun 				 struct v4l2_subdev_pad_config *cfg,
360*4882a593Smuzhiyun 				 struct v4l2_subdev_mbus_code_enum *code)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun 	if (code->index != 0)
363*4882a593Smuzhiyun 		return -EINVAL;
364*4882a593Smuzhiyun 	code->code = PIX_FORMAT;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	return 0;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun 
imx323_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)369*4882a593Smuzhiyun static int imx323_enum_frame_sizes(struct v4l2_subdev *sd,
370*4882a593Smuzhiyun 				   struct v4l2_subdev_pad_config *cfg,
371*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_size_enum *fse)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun 	if (fse->index >= ARRAY_SIZE(supported_modes))
374*4882a593Smuzhiyun 		return -EINVAL;
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	if (fse->code != PIX_FORMAT)
377*4882a593Smuzhiyun 		return -EINVAL;
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	fse->min_width  = supported_modes[fse->index].width;
380*4882a593Smuzhiyun 	fse->max_width  = supported_modes[fse->index].width;
381*4882a593Smuzhiyun 	fse->max_height = supported_modes[fse->index].height;
382*4882a593Smuzhiyun 	fse->min_height = supported_modes[fse->index].height;
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	return 0;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun 
imx323_enable_test_pattern(struct imx323 * imx323,u32 pattern)387*4882a593Smuzhiyun static int imx323_enable_test_pattern(struct imx323 *imx323, u32 pattern)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun 	return 0;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun 
imx323_get_module_inf(struct imx323 * imx323,struct rkmodule_inf * inf)392*4882a593Smuzhiyun static void imx323_get_module_inf(struct imx323 *imx323,
393*4882a593Smuzhiyun 				  struct rkmodule_inf *inf)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun 	memset(inf, 0, sizeof(*inf));
396*4882a593Smuzhiyun 	strlcpy(inf->base.sensor, IMX323_NAME, sizeof(inf->base.sensor));
397*4882a593Smuzhiyun 	strlcpy(inf->base.module, imx323->module_name,
398*4882a593Smuzhiyun 		sizeof(inf->base.module));
399*4882a593Smuzhiyun 	strlcpy(inf->base.lens, imx323->len_name, sizeof(inf->base.lens));
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun 
imx323_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)402*4882a593Smuzhiyun static long imx323_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun 	struct imx323 *imx323 = to_imx323(sd);
405*4882a593Smuzhiyun 	long ret = 0;
406*4882a593Smuzhiyun 	u32 stream = 0;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	switch (cmd) {
409*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
410*4882a593Smuzhiyun 		imx323_get_module_inf(imx323, (struct rkmodule_inf *)arg);
411*4882a593Smuzhiyun 		break;
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	case RKMODULE_SET_QUICK_STREAM:
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 		stream = *((u32 *)arg);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 		if (stream)
418*4882a593Smuzhiyun 			imx323_write_reg(imx323->client, IMX323_REG_CTRL_MODE,
419*4882a593Smuzhiyun 				IMX323_REG_VALUE_08BIT, IMX323_MODE_STREAMING);
420*4882a593Smuzhiyun 		else
421*4882a593Smuzhiyun 			imx323_write_reg(imx323->client, IMX323_REG_CTRL_MODE,
422*4882a593Smuzhiyun 				IMX323_REG_VALUE_08BIT, IMX323_MODE_SW_STANDBY);
423*4882a593Smuzhiyun 		break;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	case RKMODULE_GET_BT656_INTF_TYPE:
426*4882a593Smuzhiyun 		*(__u32 *)arg = BT656_SONY_RAW;
427*4882a593Smuzhiyun 		break;
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	default:
430*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
431*4882a593Smuzhiyun 		break;
432*4882a593Smuzhiyun 	}
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	return ret;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
imx323_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)438*4882a593Smuzhiyun static long imx323_compat_ioctl32(struct v4l2_subdev *sd,
439*4882a593Smuzhiyun 				  unsigned int cmd, unsigned long arg)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun 	void __user *up = compat_ptr(arg);
442*4882a593Smuzhiyun 	struct rkmodule_inf *inf;
443*4882a593Smuzhiyun 	struct rkmodule_awb_cfg *cfg;
444*4882a593Smuzhiyun 	__u32 intf;
445*4882a593Smuzhiyun 	long ret;
446*4882a593Smuzhiyun 	u32 stream = 0;
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	switch (cmd) {
449*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
450*4882a593Smuzhiyun 		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
451*4882a593Smuzhiyun 		if (!inf) {
452*4882a593Smuzhiyun 			ret = -ENOMEM;
453*4882a593Smuzhiyun 			return ret;
454*4882a593Smuzhiyun 		}
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 		ret = imx323_ioctl(sd, cmd, inf);
457*4882a593Smuzhiyun 		if (!ret)
458*4882a593Smuzhiyun 			ret = copy_to_user(up, inf, sizeof(*inf));
459*4882a593Smuzhiyun 		kfree(inf);
460*4882a593Smuzhiyun 		break;
461*4882a593Smuzhiyun 	case RKMODULE_AWB_CFG:
462*4882a593Smuzhiyun 		cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
463*4882a593Smuzhiyun 		if (!cfg) {
464*4882a593Smuzhiyun 			ret = -ENOMEM;
465*4882a593Smuzhiyun 			return ret;
466*4882a593Smuzhiyun 		}
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 		ret = copy_from_user(cfg, up, sizeof(*cfg));
469*4882a593Smuzhiyun 		if (!ret)
470*4882a593Smuzhiyun 			ret = imx323_ioctl(sd, cmd, cfg);
471*4882a593Smuzhiyun 		kfree(cfg);
472*4882a593Smuzhiyun 		break;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	case RKMODULE_SET_QUICK_STREAM:
475*4882a593Smuzhiyun 		ret = copy_from_user(&stream, up, sizeof(u32));
476*4882a593Smuzhiyun 		if (!ret)
477*4882a593Smuzhiyun 			ret = imx323_ioctl(sd, cmd, &stream);
478*4882a593Smuzhiyun 		break;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	case RKMODULE_GET_BT656_INTF_TYPE:
481*4882a593Smuzhiyun 		intf = BT656_SONY_RAW;
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 		ret = copy_to_user(up, &intf, sizeof(intf));
484*4882a593Smuzhiyun 		break;
485*4882a593Smuzhiyun 	default:
486*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
487*4882a593Smuzhiyun 		break;
488*4882a593Smuzhiyun 	}
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	return ret;
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun #endif
493*4882a593Smuzhiyun 
__imx323_start_stream(struct imx323 * imx323)494*4882a593Smuzhiyun static int __imx323_start_stream(struct imx323 *imx323)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun 	int ret;
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 	ret = imx323_write_array(imx323->client, imx323->cur_mode->reg_list);
499*4882a593Smuzhiyun 	if (ret)
500*4882a593Smuzhiyun 		return ret;
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	/* In case these controls are set before streaming */
503*4882a593Smuzhiyun 	mutex_unlock(&imx323->mutex);
504*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_setup(&imx323->ctrl_handler);
505*4882a593Smuzhiyun 	mutex_lock(&imx323->mutex);
506*4882a593Smuzhiyun 	if (ret)
507*4882a593Smuzhiyun 		return ret;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	return imx323_write_reg(imx323->client, IMX323_REG_CTRL_MODE,
510*4882a593Smuzhiyun 				IMX323_REG_VALUE_08BIT, IMX323_MODE_STREAMING);
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun 
__imx323_stop_stream(struct imx323 * imx323)513*4882a593Smuzhiyun static int __imx323_stop_stream(struct imx323 *imx323)
514*4882a593Smuzhiyun {
515*4882a593Smuzhiyun 	return imx323_write_reg(imx323->client, IMX323_REG_CTRL_MODE,
516*4882a593Smuzhiyun 				IMX323_REG_VALUE_08BIT, IMX323_MODE_SW_STANDBY);
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun 
imx323_s_stream(struct v4l2_subdev * sd,int on)519*4882a593Smuzhiyun static int imx323_s_stream(struct v4l2_subdev *sd, int on)
520*4882a593Smuzhiyun {
521*4882a593Smuzhiyun 	struct imx323 *imx323 = to_imx323(sd);
522*4882a593Smuzhiyun 	struct i2c_client *client = imx323->client;
523*4882a593Smuzhiyun 	int ret = 0;
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 	mutex_lock(&imx323->mutex);
526*4882a593Smuzhiyun 	on = !!on;
527*4882a593Smuzhiyun 	if (on == imx323->streaming)
528*4882a593Smuzhiyun 		goto unlock_and_return;
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	if (on) {
531*4882a593Smuzhiyun 		ret = pm_runtime_get_sync(&client->dev);
532*4882a593Smuzhiyun 		if (ret < 0) {
533*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
534*4882a593Smuzhiyun 			goto unlock_and_return;
535*4882a593Smuzhiyun 		}
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 		ret = __imx323_start_stream(imx323);
538*4882a593Smuzhiyun 		if (ret) {
539*4882a593Smuzhiyun 			v4l2_err(sd, "start stream failed while write regs\n");
540*4882a593Smuzhiyun 			pm_runtime_put(&client->dev);
541*4882a593Smuzhiyun 			goto unlock_and_return;
542*4882a593Smuzhiyun 		}
543*4882a593Smuzhiyun 	} else {
544*4882a593Smuzhiyun 		__imx323_stop_stream(imx323);
545*4882a593Smuzhiyun 		pm_runtime_put(&client->dev);
546*4882a593Smuzhiyun 	}
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	imx323->streaming = on;
549*4882a593Smuzhiyun unlock_and_return:
550*4882a593Smuzhiyun 	mutex_unlock(&imx323->mutex);
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	return ret;
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun 
imx323_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)555*4882a593Smuzhiyun static int imx323_g_frame_interval(struct v4l2_subdev *sd,
556*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_interval *fi)
557*4882a593Smuzhiyun {
558*4882a593Smuzhiyun 	struct imx323 *imx323 = to_imx323(sd);
559*4882a593Smuzhiyun 	const struct imx323_mode *mode = imx323->cur_mode;
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	fi->interval = mode->max_fps;
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 	return 0;
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun 
imx323_s_power(struct v4l2_subdev * sd,int on)566*4882a593Smuzhiyun static int imx323_s_power(struct v4l2_subdev *sd, int on)
567*4882a593Smuzhiyun {
568*4882a593Smuzhiyun 	struct imx323 *imx323 = to_imx323(sd);
569*4882a593Smuzhiyun 	struct i2c_client *client = imx323->client;
570*4882a593Smuzhiyun 	int ret = 0;
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	mutex_lock(&imx323->mutex);
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun 	/* If the power state is not modified - no work to do. */
575*4882a593Smuzhiyun 	if (imx323->power_on == !!on)
576*4882a593Smuzhiyun 		goto unlock_and_return;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	if (on) {
579*4882a593Smuzhiyun 		ret = pm_runtime_get_sync(&client->dev);
580*4882a593Smuzhiyun 		if (ret < 0) {
581*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
582*4882a593Smuzhiyun 			goto unlock_and_return;
583*4882a593Smuzhiyun 		}
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 		imx323->power_on = true;
586*4882a593Smuzhiyun 	} else {
587*4882a593Smuzhiyun 		pm_runtime_put(&client->dev);
588*4882a593Smuzhiyun 		imx323->power_on = false;
589*4882a593Smuzhiyun 	}
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun unlock_and_return:
592*4882a593Smuzhiyun 	mutex_unlock(&imx323->mutex);
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	return ret;
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun /* Calculate the delay in us by clock rate and clock cycles */
imx323_cal_delay(u32 cycles)598*4882a593Smuzhiyun static inline u32 imx323_cal_delay(u32 cycles)
599*4882a593Smuzhiyun {
600*4882a593Smuzhiyun 	return DIV_ROUND_UP(cycles, IMX323_XVCLK_FREQ / 1000 / 1000);
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun 
__imx323_power_on(struct imx323 * imx323)603*4882a593Smuzhiyun static int __imx323_power_on(struct imx323 *imx323)
604*4882a593Smuzhiyun {
605*4882a593Smuzhiyun 	int ret;
606*4882a593Smuzhiyun 	u32 i, delay_us;
607*4882a593Smuzhiyun 	struct device *dev = &imx323->client->dev;
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	ret = clk_set_rate(imx323->xvclk, IMX323_XVCLK_FREQ);
610*4882a593Smuzhiyun 	if (ret < 0) {
611*4882a593Smuzhiyun 		dev_err(dev, "Failed to set xvclk rate (%d)\n",
612*4882a593Smuzhiyun 			IMX323_XVCLK_FREQ);
613*4882a593Smuzhiyun 		return ret;
614*4882a593Smuzhiyun 	}
615*4882a593Smuzhiyun 	if (clk_get_rate(imx323->xvclk) != IMX323_XVCLK_FREQ)
616*4882a593Smuzhiyun 		dev_warn(dev, "xvclk mismatched, modes are based on %d\n",
617*4882a593Smuzhiyun 			IMX323_XVCLK_FREQ);
618*4882a593Smuzhiyun 	ret = clk_prepare_enable(imx323->xvclk);
619*4882a593Smuzhiyun 	if (ret < 0) {
620*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable xvclk\n");
621*4882a593Smuzhiyun 		return ret;
622*4882a593Smuzhiyun 	}
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	if (!IS_ERR(imx323->reset_gpio))
625*4882a593Smuzhiyun 		gpiod_set_value_cansleep(imx323->reset_gpio, 0);
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	for (i = 0; i < IMX323_NUM_SUPPLIES; i++)
628*4882a593Smuzhiyun 		regulator_set_voltage(imx323->supplies[i].consumer,
629*4882a593Smuzhiyun 			imx323_regulator[i].val,
630*4882a593Smuzhiyun 			imx323_regulator[i].val);
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 	ret = regulator_bulk_enable(IMX323_NUM_SUPPLIES, imx323->supplies);
633*4882a593Smuzhiyun 	if (ret < 0) {
634*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable regulators\n");
635*4882a593Smuzhiyun 		goto disable_clk;
636*4882a593Smuzhiyun 	}
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 	if (!IS_ERR(imx323->reset_gpio))
639*4882a593Smuzhiyun 		gpiod_set_value_cansleep(imx323->reset_gpio, 1);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	if (!IS_ERR(imx323->pwdn_gpio))
642*4882a593Smuzhiyun 		gpiod_set_value_cansleep(imx323->pwdn_gpio, 1);
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 	/* 8192 cycles prior to first SCCB transaction */
645*4882a593Smuzhiyun 	delay_us = imx323_cal_delay(8192);
646*4882a593Smuzhiyun 	usleep_range(delay_us, delay_us * 2);
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	return 0;
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun disable_clk:
651*4882a593Smuzhiyun 	clk_disable_unprepare(imx323->xvclk);
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	return ret;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun 
__imx323_power_off(struct imx323 * imx323)656*4882a593Smuzhiyun static void __imx323_power_off(struct imx323 *imx323)
657*4882a593Smuzhiyun {
658*4882a593Smuzhiyun 	if (!IS_ERR(imx323->pwdn_gpio))
659*4882a593Smuzhiyun 		gpiod_set_value_cansleep(imx323->pwdn_gpio, 0);
660*4882a593Smuzhiyun 	clk_disable_unprepare(imx323->xvclk);
661*4882a593Smuzhiyun 	if (!IS_ERR(imx323->reset_gpio))
662*4882a593Smuzhiyun 		gpiod_set_value_cansleep(imx323->reset_gpio, 0);
663*4882a593Smuzhiyun 	regulator_bulk_disable(IMX323_NUM_SUPPLIES, imx323->supplies);
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun 
imx323_runtime_resume(struct device * dev)666*4882a593Smuzhiyun static int imx323_runtime_resume(struct device *dev)
667*4882a593Smuzhiyun {
668*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
669*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
670*4882a593Smuzhiyun 	struct imx323 *imx323 = to_imx323(sd);
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun 	return __imx323_power_on(imx323);
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun 
imx323_runtime_suspend(struct device * dev)675*4882a593Smuzhiyun static int imx323_runtime_suspend(struct device *dev)
676*4882a593Smuzhiyun {
677*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
678*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
679*4882a593Smuzhiyun 	struct imx323 *imx323 = to_imx323(sd);
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun 	__imx323_power_off(imx323);
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	return 0;
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
imx323_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)687*4882a593Smuzhiyun static int imx323_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
688*4882a593Smuzhiyun {
689*4882a593Smuzhiyun 	struct imx323 *imx323 = to_imx323(sd);
690*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *try_fmt =
691*4882a593Smuzhiyun 				v4l2_subdev_get_try_format(sd, fh->pad, 0);
692*4882a593Smuzhiyun 	const struct imx323_mode *def_mode = &supported_modes[0];
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	mutex_lock(&imx323->mutex);
695*4882a593Smuzhiyun 	/* Initialize try_fmt */
696*4882a593Smuzhiyun 	try_fmt->width = def_mode->width;
697*4882a593Smuzhiyun 	try_fmt->height = def_mode->height;
698*4882a593Smuzhiyun 	try_fmt->code = PIX_FORMAT;
699*4882a593Smuzhiyun 	try_fmt->field = V4L2_FIELD_NONE;
700*4882a593Smuzhiyun 	mutex_unlock(&imx323->mutex);
701*4882a593Smuzhiyun 	/* No crop or compose */
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	return 0;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun #endif
706*4882a593Smuzhiyun 
imx323_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)707*4882a593Smuzhiyun static int imx323_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
708*4882a593Smuzhiyun 				struct v4l2_mbus_config *config)
709*4882a593Smuzhiyun {
710*4882a593Smuzhiyun 	config->type = V4L2_MBUS_BT656;
711*4882a593Smuzhiyun 	config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
712*4882a593Smuzhiyun 			V4L2_MBUS_VSYNC_ACTIVE_HIGH |
713*4882a593Smuzhiyun 			V4L2_MBUS_PCLK_SAMPLE_FALLING;
714*4882a593Smuzhiyun 	return 0;
715*4882a593Smuzhiyun }
716*4882a593Smuzhiyun 
imx323_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)717*4882a593Smuzhiyun static int imx323_enum_frame_interval(struct v4l2_subdev *sd,
718*4882a593Smuzhiyun 				       struct v4l2_subdev_pad_config *cfg,
719*4882a593Smuzhiyun 				       struct v4l2_subdev_frame_interval_enum *fie)
720*4882a593Smuzhiyun {
721*4882a593Smuzhiyun 	if (fie->index >= ARRAY_SIZE(supported_modes))
722*4882a593Smuzhiyun 		return -EINVAL;
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	fie->code = PIX_FORMAT;
725*4882a593Smuzhiyun 	fie->width = supported_modes[fie->index].width;
726*4882a593Smuzhiyun 	fie->height = supported_modes[fie->index].height;
727*4882a593Smuzhiyun 	fie->interval = supported_modes[fie->index].max_fps;
728*4882a593Smuzhiyun 	return 0;
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun static const struct dev_pm_ops imx323_pm_ops = {
732*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(imx323_runtime_suspend,
733*4882a593Smuzhiyun 			   imx323_runtime_resume, NULL)
734*4882a593Smuzhiyun };
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
737*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops imx323_internal_ops = {
738*4882a593Smuzhiyun 	.open = imx323_open,
739*4882a593Smuzhiyun };
740*4882a593Smuzhiyun #endif
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops imx323_core_ops = {
743*4882a593Smuzhiyun 	.s_power = imx323_s_power,
744*4882a593Smuzhiyun 	.ioctl = imx323_ioctl,
745*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
746*4882a593Smuzhiyun 	.compat_ioctl32 = imx323_compat_ioctl32,
747*4882a593Smuzhiyun #endif
748*4882a593Smuzhiyun };
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops imx323_video_ops = {
751*4882a593Smuzhiyun 	.s_stream = imx323_s_stream,
752*4882a593Smuzhiyun 	.g_frame_interval = imx323_g_frame_interval,
753*4882a593Smuzhiyun };
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops imx323_pad_ops = {
756*4882a593Smuzhiyun 	.enum_mbus_code = imx323_enum_mbus_code,
757*4882a593Smuzhiyun 	.enum_frame_size = imx323_enum_frame_sizes,
758*4882a593Smuzhiyun 	.enum_frame_interval = imx323_enum_frame_interval,
759*4882a593Smuzhiyun 	.get_fmt = imx323_get_fmt,
760*4882a593Smuzhiyun 	.set_fmt = imx323_set_fmt,
761*4882a593Smuzhiyun 	.get_mbus_config = imx323_g_mbus_config,
762*4882a593Smuzhiyun };
763*4882a593Smuzhiyun 
764*4882a593Smuzhiyun static const struct v4l2_subdev_ops imx323_subdev_ops = {
765*4882a593Smuzhiyun 	.core	= &imx323_core_ops,
766*4882a593Smuzhiyun 	.video	= &imx323_video_ops,
767*4882a593Smuzhiyun 	.pad	= &imx323_pad_ops,
768*4882a593Smuzhiyun };
769*4882a593Smuzhiyun 
imx323_set_ctrl(struct v4l2_ctrl * ctrl)770*4882a593Smuzhiyun static int imx323_set_ctrl(struct v4l2_ctrl *ctrl)
771*4882a593Smuzhiyun {
772*4882a593Smuzhiyun 	struct imx323 *imx323 = container_of(ctrl->handler,
773*4882a593Smuzhiyun 					     struct imx323, ctrl_handler);
774*4882a593Smuzhiyun 	struct i2c_client *client = imx323->client;
775*4882a593Smuzhiyun 	int ret = 0;
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun 	if (!pm_runtime_get_if_in_use(&client->dev))
778*4882a593Smuzhiyun 		return 0;
779*4882a593Smuzhiyun 
780*4882a593Smuzhiyun 	switch (ctrl->id) {
781*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE:
782*4882a593Smuzhiyun 		ret = imx323_write_reg(imx323->client, IMX323_REG_EXPOSURE,
783*4882a593Smuzhiyun 				       IMX323_REG_VALUE_16BIT, ctrl->val);
784*4882a593Smuzhiyun 		break;
785*4882a593Smuzhiyun 	case V4L2_CID_ANALOGUE_GAIN:
786*4882a593Smuzhiyun 		ret = imx323_write_reg(imx323->client, IMX323_REG_ANALOG_GAIN,
787*4882a593Smuzhiyun 				       IMX323_REG_VALUE_08BIT, ctrl->val);
788*4882a593Smuzhiyun 		break;
789*4882a593Smuzhiyun 	case V4L2_CID_VBLANK:
790*4882a593Smuzhiyun 		ret = imx323_write_reg(imx323->client, IMX323_REG_VTS,
791*4882a593Smuzhiyun 				       IMX323_REG_VALUE_16BIT,
792*4882a593Smuzhiyun 				       ctrl->val + imx323->cur_mode->height);
793*4882a593Smuzhiyun 		break;
794*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN:
795*4882a593Smuzhiyun 		ret = imx323_enable_test_pattern(imx323, ctrl->val);
796*4882a593Smuzhiyun 		break;
797*4882a593Smuzhiyun 	default:
798*4882a593Smuzhiyun 		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
799*4882a593Smuzhiyun 			 __func__, ctrl->id, ctrl->val);
800*4882a593Smuzhiyun 		break;
801*4882a593Smuzhiyun 	}
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun 	pm_runtime_put(&client->dev);
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 	return ret;
806*4882a593Smuzhiyun }
807*4882a593Smuzhiyun 
808*4882a593Smuzhiyun static const struct v4l2_ctrl_ops imx323_ctrl_ops = {
809*4882a593Smuzhiyun 	.s_ctrl = imx323_set_ctrl,
810*4882a593Smuzhiyun };
811*4882a593Smuzhiyun 
imx323_initialize_controls(struct imx323 * imx323)812*4882a593Smuzhiyun static int imx323_initialize_controls(struct imx323 *imx323)
813*4882a593Smuzhiyun {
814*4882a593Smuzhiyun 	const struct imx323_mode *mode;
815*4882a593Smuzhiyun 	struct v4l2_ctrl_handler *handler;
816*4882a593Smuzhiyun 	s64 exposure_max, vblank_def;
817*4882a593Smuzhiyun 	u32 h_blank;
818*4882a593Smuzhiyun 	int ret;
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	handler = &imx323->ctrl_handler;
821*4882a593Smuzhiyun 	mode = imx323->cur_mode;
822*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_init(handler, 8);
823*4882a593Smuzhiyun 	if (ret)
824*4882a593Smuzhiyun 		return ret;
825*4882a593Smuzhiyun 	handler->lock = &imx323->mutex;
826*4882a593Smuzhiyun 
827*4882a593Smuzhiyun 	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
828*4882a593Smuzhiyun 			  0, IMX323_PIXEL_RATE, 1, IMX323_PIXEL_RATE);
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun 	h_blank = mode->hts_def - mode->width;
831*4882a593Smuzhiyun 	imx323->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
832*4882a593Smuzhiyun 				h_blank, h_blank, 1, h_blank);
833*4882a593Smuzhiyun 	if (imx323->hblank)
834*4882a593Smuzhiyun 		imx323->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun 	vblank_def = mode->vts_def - mode->height;
837*4882a593Smuzhiyun 	imx323->vblank = v4l2_ctrl_new_std(handler, &imx323_ctrl_ops,
838*4882a593Smuzhiyun 				V4L2_CID_VBLANK, vblank_def,
839*4882a593Smuzhiyun 				IMX323_VTS_MAX - mode->height,
840*4882a593Smuzhiyun 				1, vblank_def);
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun 	exposure_max = mode->vts_def - 1;
843*4882a593Smuzhiyun 	imx323->exposure = v4l2_ctrl_new_std(handler, &imx323_ctrl_ops,
844*4882a593Smuzhiyun 				V4L2_CID_EXPOSURE, IMX323_EXPOSURE_MIN,
845*4882a593Smuzhiyun 				exposure_max, IMX323_EXPOSURE_STEP,
846*4882a593Smuzhiyun 				mode->exp_def);
847*4882a593Smuzhiyun 
848*4882a593Smuzhiyun 	imx323->anal_gain = v4l2_ctrl_new_std(handler, &imx323_ctrl_ops,
849*4882a593Smuzhiyun 				V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
850*4882a593Smuzhiyun 				ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
851*4882a593Smuzhiyun 				ANALOG_GAIN_DEFAULT);
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun 	imx323->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
854*4882a593Smuzhiyun 				&imx323_ctrl_ops, V4L2_CID_TEST_PATTERN,
855*4882a593Smuzhiyun 				ARRAY_SIZE(imx323_test_pattern_menu) - 1,
856*4882a593Smuzhiyun 				0, 0, imx323_test_pattern_menu);
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun 	if (handler->error) {
859*4882a593Smuzhiyun 		ret = handler->error;
860*4882a593Smuzhiyun 		dev_err(&imx323->client->dev,
861*4882a593Smuzhiyun 			"Failed to init controls(%d)\n", ret);
862*4882a593Smuzhiyun 		goto err_free_handler;
863*4882a593Smuzhiyun 	}
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun 	imx323->subdev.ctrl_handler = handler;
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 	return 0;
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun err_free_handler:
870*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(handler);
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun 	return ret;
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun 
imx323_check_sensor_id(struct imx323 * imx323,struct i2c_client * client)875*4882a593Smuzhiyun static int imx323_check_sensor_id(struct imx323 *imx323,
876*4882a593Smuzhiyun 				  struct i2c_client *client)
877*4882a593Smuzhiyun {
878*4882a593Smuzhiyun 	struct device *dev = &imx323->client->dev;
879*4882a593Smuzhiyun 	u32 id = 0;
880*4882a593Smuzhiyun 	int ret;
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	ret = imx323_read_reg(client, IMX323_REG_CHIP_ID,
883*4882a593Smuzhiyun 			      IMX323_REG_VALUE_08BIT, &id);
884*4882a593Smuzhiyun 	if (id != CHIP_ID) {
885*4882a593Smuzhiyun 		dev_err(dev, "Unexpected sensor id(%x), ret(%d)\n", id, ret);
886*4882a593Smuzhiyun 		return -ENODEV;
887*4882a593Smuzhiyun 	}
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	dev_info(dev, "Detected IMX323 sensor\n");
890*4882a593Smuzhiyun 
891*4882a593Smuzhiyun 	return 0;
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun 
imx323_configure_regulators(struct imx323 * imx323)894*4882a593Smuzhiyun static int imx323_configure_regulators(struct imx323 *imx323)
895*4882a593Smuzhiyun {
896*4882a593Smuzhiyun 	u32 i;
897*4882a593Smuzhiyun 
898*4882a593Smuzhiyun 	for (i = 0; i < IMX323_NUM_SUPPLIES; i++)
899*4882a593Smuzhiyun 		imx323->supplies[i].supply =
900*4882a593Smuzhiyun 			imx323_regulator[i].name;
901*4882a593Smuzhiyun 
902*4882a593Smuzhiyun 	return devm_regulator_bulk_get(&imx323->client->dev,
903*4882a593Smuzhiyun 				       IMX323_NUM_SUPPLIES,
904*4882a593Smuzhiyun 				       imx323->supplies);
905*4882a593Smuzhiyun }
906*4882a593Smuzhiyun 
imx323_probe(struct i2c_client * client,const struct i2c_device_id * id)907*4882a593Smuzhiyun static int imx323_probe(struct i2c_client *client,
908*4882a593Smuzhiyun 			const struct i2c_device_id *id)
909*4882a593Smuzhiyun {
910*4882a593Smuzhiyun 	struct device *dev = &client->dev;
911*4882a593Smuzhiyun 	struct device_node *node = dev->of_node;
912*4882a593Smuzhiyun 	struct imx323 *imx323;
913*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
914*4882a593Smuzhiyun 	char facing[2];
915*4882a593Smuzhiyun 	int ret;
916*4882a593Smuzhiyun 
917*4882a593Smuzhiyun 	dev_info(dev, "driver version: %02x.%02x.%02x",
918*4882a593Smuzhiyun 		DRIVER_VERSION >> 16,
919*4882a593Smuzhiyun 		(DRIVER_VERSION & 0xff00) >> 8,
920*4882a593Smuzhiyun 		DRIVER_VERSION & 0x00ff);
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun 	imx323 = devm_kzalloc(dev, sizeof(*imx323), GFP_KERNEL);
923*4882a593Smuzhiyun 	if (!imx323)
924*4882a593Smuzhiyun 		return -ENOMEM;
925*4882a593Smuzhiyun 
926*4882a593Smuzhiyun 	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
927*4882a593Smuzhiyun 				   &imx323->module_index);
928*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
929*4882a593Smuzhiyun 				       &imx323->module_facing);
930*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
931*4882a593Smuzhiyun 				       &imx323->module_name);
932*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
933*4882a593Smuzhiyun 				       &imx323->len_name);
934*4882a593Smuzhiyun 	if (ret) {
935*4882a593Smuzhiyun 		dev_err(dev, "could not get module information!\n");
936*4882a593Smuzhiyun 		return -EINVAL;
937*4882a593Smuzhiyun 	}
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun 	imx323->client = client;
940*4882a593Smuzhiyun 	imx323->cur_mode = &supported_modes[0];
941*4882a593Smuzhiyun 
942*4882a593Smuzhiyun 	imx323->xvclk = devm_clk_get(dev, "xvclk");
943*4882a593Smuzhiyun 	if (IS_ERR(imx323->xvclk)) {
944*4882a593Smuzhiyun 		dev_err(dev, "Failed to get xvclk\n");
945*4882a593Smuzhiyun 		return -EINVAL;
946*4882a593Smuzhiyun 	}
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun 	imx323->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
949*4882a593Smuzhiyun 	if (IS_ERR(imx323->reset_gpio))
950*4882a593Smuzhiyun 		dev_warn(dev, "Failed to get reset-gpios\n");
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 	imx323->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
953*4882a593Smuzhiyun 	if (IS_ERR(imx323->pwdn_gpio))
954*4882a593Smuzhiyun 		dev_warn(dev, "Failed to get pwdn-gpios\n");
955*4882a593Smuzhiyun 
956*4882a593Smuzhiyun 	ret = imx323_configure_regulators(imx323);
957*4882a593Smuzhiyun 	if (ret) {
958*4882a593Smuzhiyun 		dev_err(dev, "Failed to get power regulators\n");
959*4882a593Smuzhiyun 		return ret;
960*4882a593Smuzhiyun 	}
961*4882a593Smuzhiyun 
962*4882a593Smuzhiyun 	mutex_init(&imx323->mutex);
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 	sd = &imx323->subdev;
965*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &imx323_subdev_ops);
966*4882a593Smuzhiyun 	ret = imx323_initialize_controls(imx323);
967*4882a593Smuzhiyun 	if (ret)
968*4882a593Smuzhiyun 		goto err_destroy_mutex;
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun 	ret = __imx323_power_on(imx323);
971*4882a593Smuzhiyun 	if (ret)
972*4882a593Smuzhiyun 		goto err_free_handler;
973*4882a593Smuzhiyun 
974*4882a593Smuzhiyun 	ret = imx323_check_sensor_id(imx323, client);
975*4882a593Smuzhiyun 	if (ret)
976*4882a593Smuzhiyun 		goto err_power_off;
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
979*4882a593Smuzhiyun 	sd->internal_ops = &imx323_internal_ops;
980*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
981*4882a593Smuzhiyun 		     V4L2_SUBDEV_FL_HAS_EVENTS;
982*4882a593Smuzhiyun #endif
983*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
984*4882a593Smuzhiyun 	imx323->pad.flags = MEDIA_PAD_FL_SOURCE;
985*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
986*4882a593Smuzhiyun 	ret = media_entity_pads_init(&sd->entity, 1, &imx323->pad);
987*4882a593Smuzhiyun 	if (ret < 0)
988*4882a593Smuzhiyun 		goto err_power_off;
989*4882a593Smuzhiyun #endif
990*4882a593Smuzhiyun 
991*4882a593Smuzhiyun 	memset(facing, 0, sizeof(facing));
992*4882a593Smuzhiyun 	if (strcmp(imx323->module_facing, "back") == 0)
993*4882a593Smuzhiyun 		facing[0] = 'b';
994*4882a593Smuzhiyun 	else
995*4882a593Smuzhiyun 		facing[0] = 'f';
996*4882a593Smuzhiyun 
997*4882a593Smuzhiyun 	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
998*4882a593Smuzhiyun 		 imx323->module_index, facing,
999*4882a593Smuzhiyun 		 IMX323_NAME, dev_name(sd->dev));
1000*4882a593Smuzhiyun 	ret = v4l2_async_register_subdev_sensor_common(sd);
1001*4882a593Smuzhiyun 	if (ret) {
1002*4882a593Smuzhiyun 		dev_err(dev, "v4l2 async register subdev failed\n");
1003*4882a593Smuzhiyun 		goto err_clean_entity;
1004*4882a593Smuzhiyun 	}
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun 	pm_runtime_set_active(dev);
1007*4882a593Smuzhiyun 	pm_runtime_enable(dev);
1008*4882a593Smuzhiyun 	pm_runtime_idle(dev);
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	return 0;
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun err_clean_entity:
1013*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1014*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1015*4882a593Smuzhiyun #endif
1016*4882a593Smuzhiyun err_power_off:
1017*4882a593Smuzhiyun 	__imx323_power_off(imx323);
1018*4882a593Smuzhiyun err_free_handler:
1019*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&imx323->ctrl_handler);
1020*4882a593Smuzhiyun err_destroy_mutex:
1021*4882a593Smuzhiyun 	mutex_destroy(&imx323->mutex);
1022*4882a593Smuzhiyun 
1023*4882a593Smuzhiyun 	return ret;
1024*4882a593Smuzhiyun }
1025*4882a593Smuzhiyun 
imx323_remove(struct i2c_client * client)1026*4882a593Smuzhiyun static int imx323_remove(struct i2c_client *client)
1027*4882a593Smuzhiyun {
1028*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1029*4882a593Smuzhiyun 	struct imx323 *imx323 = to_imx323(sd);
1030*4882a593Smuzhiyun 
1031*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(sd);
1032*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1033*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1034*4882a593Smuzhiyun #endif
1035*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&imx323->ctrl_handler);
1036*4882a593Smuzhiyun 	mutex_destroy(&imx323->mutex);
1037*4882a593Smuzhiyun 
1038*4882a593Smuzhiyun 	pm_runtime_disable(&client->dev);
1039*4882a593Smuzhiyun 	if (!pm_runtime_status_suspended(&client->dev))
1040*4882a593Smuzhiyun 		__imx323_power_off(imx323);
1041*4882a593Smuzhiyun 	pm_runtime_set_suspended(&client->dev);
1042*4882a593Smuzhiyun 
1043*4882a593Smuzhiyun 	return 0;
1044*4882a593Smuzhiyun }
1045*4882a593Smuzhiyun 
1046*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1047*4882a593Smuzhiyun static const struct of_device_id imx323_of_match[] = {
1048*4882a593Smuzhiyun 	{ .compatible = "sony,imx323" },
1049*4882a593Smuzhiyun 	{},
1050*4882a593Smuzhiyun };
1051*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, imx323_of_match);
1052*4882a593Smuzhiyun #endif
1053*4882a593Smuzhiyun 
1054*4882a593Smuzhiyun static const struct i2c_device_id imx323_match_id[] = {
1055*4882a593Smuzhiyun 	{ "sony,imx323", 0 },
1056*4882a593Smuzhiyun 	{ },
1057*4882a593Smuzhiyun };
1058*4882a593Smuzhiyun 
1059*4882a593Smuzhiyun static struct i2c_driver imx323_i2c_driver = {
1060*4882a593Smuzhiyun 	.driver = {
1061*4882a593Smuzhiyun 		.name = IMX323_NAME,
1062*4882a593Smuzhiyun 		.pm = &imx323_pm_ops,
1063*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(imx323_of_match),
1064*4882a593Smuzhiyun 	},
1065*4882a593Smuzhiyun 	.probe		= &imx323_probe,
1066*4882a593Smuzhiyun 	.remove		= &imx323_remove,
1067*4882a593Smuzhiyun 	.id_table	= imx323_match_id,
1068*4882a593Smuzhiyun };
1069*4882a593Smuzhiyun 
sensor_mod_init(void)1070*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1071*4882a593Smuzhiyun {
1072*4882a593Smuzhiyun 	return i2c_add_driver(&imx323_i2c_driver);
1073*4882a593Smuzhiyun }
1074*4882a593Smuzhiyun 
sensor_mod_exit(void)1075*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1076*4882a593Smuzhiyun {
1077*4882a593Smuzhiyun 	i2c_del_driver(&imx323_i2c_driver);
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun 
1080*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1081*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun MODULE_DESCRIPTION("Sony imx323 sensor driver");
1084*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1085