xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/imx274.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * imx274.c - IMX274 CMOS Image Sensor driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2017, Leopard Imaging, Inc.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Leon Luo <leonl@leopardimaging.com>
8*4882a593Smuzhiyun  * Edwin Zou <edwinz@leopardimaging.com>
9*4882a593Smuzhiyun  * Luca Ceresoli <luca@lucaceresoli.net>
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/clk.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/gpio.h>
15*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/init.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/of_gpio.h>
21*4882a593Smuzhiyun #include <linux/regmap.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun #include <linux/v4l2-mediabus.h>
24*4882a593Smuzhiyun #include <linux/videodev2.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
27*4882a593Smuzhiyun #include <media/v4l2-device.h>
28*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun  * See "SHR, SVR Setting" in datasheet
32*4882a593Smuzhiyun  */
33*4882a593Smuzhiyun #define IMX274_DEFAULT_FRAME_LENGTH		(4550)
34*4882a593Smuzhiyun #define IMX274_MAX_FRAME_LENGTH			(0x000fffff)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun  * See "Frame Rate Adjustment" in datasheet
38*4882a593Smuzhiyun  */
39*4882a593Smuzhiyun #define IMX274_PIXCLK_CONST1			(72000000)
40*4882a593Smuzhiyun #define IMX274_PIXCLK_CONST2			(1000000)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun  * The input gain is shifted by IMX274_GAIN_SHIFT to get
44*4882a593Smuzhiyun  * decimal number. The real gain is
45*4882a593Smuzhiyun  * (float)input_gain_value / (1 << IMX274_GAIN_SHIFT)
46*4882a593Smuzhiyun  */
47*4882a593Smuzhiyun #define IMX274_GAIN_SHIFT			(8)
48*4882a593Smuzhiyun #define IMX274_GAIN_SHIFT_MASK			((1 << IMX274_GAIN_SHIFT) - 1)
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun  * See "Analog Gain" and "Digital Gain" in datasheet
52*4882a593Smuzhiyun  * min gain is 1X
53*4882a593Smuzhiyun  * max gain is calculated based on IMX274_GAIN_REG_MAX
54*4882a593Smuzhiyun  */
55*4882a593Smuzhiyun #define IMX274_GAIN_REG_MAX			(1957)
56*4882a593Smuzhiyun #define IMX274_MIN_GAIN				(0x01 << IMX274_GAIN_SHIFT)
57*4882a593Smuzhiyun #define IMX274_MAX_ANALOG_GAIN			((2048 << IMX274_GAIN_SHIFT)\
58*4882a593Smuzhiyun 					/ (2048 - IMX274_GAIN_REG_MAX))
59*4882a593Smuzhiyun #define IMX274_MAX_DIGITAL_GAIN			(8)
60*4882a593Smuzhiyun #define IMX274_DEF_GAIN				(20 << IMX274_GAIN_SHIFT)
61*4882a593Smuzhiyun #define IMX274_GAIN_CONST			(2048) /* for gain formula */
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun  * 1 line time in us = (HMAX / 72), minimal is 4 lines
65*4882a593Smuzhiyun  */
66*4882a593Smuzhiyun #define IMX274_MIN_EXPOSURE_TIME		(4 * 260 / 72)
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #define IMX274_DEFAULT_BINNING			IMX274_BINNING_OFF
69*4882a593Smuzhiyun #define IMX274_MAX_WIDTH			(3840)
70*4882a593Smuzhiyun #define IMX274_MAX_HEIGHT			(2160)
71*4882a593Smuzhiyun #define IMX274_MAX_FRAME_RATE			(120)
72*4882a593Smuzhiyun #define IMX274_MIN_FRAME_RATE			(5)
73*4882a593Smuzhiyun #define IMX274_DEF_FRAME_RATE			(60)
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun  * register SHR is limited to (SVR value + 1) x VMAX value - 4
77*4882a593Smuzhiyun  */
78*4882a593Smuzhiyun #define IMX274_SHR_LIMIT_CONST			(4)
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun  * Min and max sensor reset delay (microseconds)
82*4882a593Smuzhiyun  */
83*4882a593Smuzhiyun #define IMX274_RESET_DELAY1			(2000)
84*4882a593Smuzhiyun #define IMX274_RESET_DELAY2			(2200)
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /*
87*4882a593Smuzhiyun  * shift and mask constants
88*4882a593Smuzhiyun  */
89*4882a593Smuzhiyun #define IMX274_SHIFT_8_BITS			(8)
90*4882a593Smuzhiyun #define IMX274_SHIFT_16_BITS			(16)
91*4882a593Smuzhiyun #define IMX274_MASK_LSB_2_BITS			(0x03)
92*4882a593Smuzhiyun #define IMX274_MASK_LSB_3_BITS			(0x07)
93*4882a593Smuzhiyun #define IMX274_MASK_LSB_4_BITS			(0x0f)
94*4882a593Smuzhiyun #define IMX274_MASK_LSB_8_BITS			(0x00ff)
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun #define DRIVER_NAME "IMX274"
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /*
99*4882a593Smuzhiyun  * IMX274 register definitions
100*4882a593Smuzhiyun  */
101*4882a593Smuzhiyun #define IMX274_SHR_REG_MSB			0x300D /* SHR */
102*4882a593Smuzhiyun #define IMX274_SHR_REG_LSB			0x300C /* SHR */
103*4882a593Smuzhiyun #define IMX274_SVR_REG_MSB			0x300F /* SVR */
104*4882a593Smuzhiyun #define IMX274_SVR_REG_LSB			0x300E /* SVR */
105*4882a593Smuzhiyun #define IMX274_HTRIM_EN_REG			0x3037
106*4882a593Smuzhiyun #define IMX274_HTRIM_START_REG_LSB		0x3038
107*4882a593Smuzhiyun #define IMX274_HTRIM_START_REG_MSB		0x3039
108*4882a593Smuzhiyun #define IMX274_HTRIM_END_REG_LSB		0x303A
109*4882a593Smuzhiyun #define IMX274_HTRIM_END_REG_MSB		0x303B
110*4882a593Smuzhiyun #define IMX274_VWIDCUTEN_REG			0x30DD
111*4882a593Smuzhiyun #define IMX274_VWIDCUT_REG_LSB			0x30DE
112*4882a593Smuzhiyun #define IMX274_VWIDCUT_REG_MSB			0x30DF
113*4882a593Smuzhiyun #define IMX274_VWINPOS_REG_LSB			0x30E0
114*4882a593Smuzhiyun #define IMX274_VWINPOS_REG_MSB			0x30E1
115*4882a593Smuzhiyun #define IMX274_WRITE_VSIZE_REG_LSB		0x3130
116*4882a593Smuzhiyun #define IMX274_WRITE_VSIZE_REG_MSB		0x3131
117*4882a593Smuzhiyun #define IMX274_Y_OUT_SIZE_REG_LSB		0x3132
118*4882a593Smuzhiyun #define IMX274_Y_OUT_SIZE_REG_MSB		0x3133
119*4882a593Smuzhiyun #define IMX274_VMAX_REG_1			0x30FA /* VMAX, MSB */
120*4882a593Smuzhiyun #define IMX274_VMAX_REG_2			0x30F9 /* VMAX */
121*4882a593Smuzhiyun #define IMX274_VMAX_REG_3			0x30F8 /* VMAX, LSB */
122*4882a593Smuzhiyun #define IMX274_HMAX_REG_MSB			0x30F7 /* HMAX */
123*4882a593Smuzhiyun #define IMX274_HMAX_REG_LSB			0x30F6 /* HMAX */
124*4882a593Smuzhiyun #define IMX274_ANALOG_GAIN_ADDR_LSB		0x300A /* ANALOG GAIN LSB */
125*4882a593Smuzhiyun #define IMX274_ANALOG_GAIN_ADDR_MSB		0x300B /* ANALOG GAIN MSB */
126*4882a593Smuzhiyun #define IMX274_DIGITAL_GAIN_REG			0x3012 /* Digital Gain */
127*4882a593Smuzhiyun #define IMX274_VFLIP_REG			0x301A /* VERTICAL FLIP */
128*4882a593Smuzhiyun #define IMX274_TEST_PATTERN_REG			0x303D /* TEST PATTERN */
129*4882a593Smuzhiyun #define IMX274_STANDBY_REG			0x3000 /* STANDBY */
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun #define IMX274_TABLE_WAIT_MS			0
132*4882a593Smuzhiyun #define IMX274_TABLE_END			1
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun /*
135*4882a593Smuzhiyun  * imx274 I2C operation related structure
136*4882a593Smuzhiyun  */
137*4882a593Smuzhiyun struct reg_8 {
138*4882a593Smuzhiyun 	u16 addr;
139*4882a593Smuzhiyun 	u8 val;
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun static const struct regmap_config imx274_regmap_config = {
143*4882a593Smuzhiyun 	.reg_bits = 16,
144*4882a593Smuzhiyun 	.val_bits = 8,
145*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun enum imx274_binning {
149*4882a593Smuzhiyun 	IMX274_BINNING_OFF,
150*4882a593Smuzhiyun 	IMX274_BINNING_2_1,
151*4882a593Smuzhiyun 	IMX274_BINNING_3_1,
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun /*
155*4882a593Smuzhiyun  * Parameters for each imx274 readout mode.
156*4882a593Smuzhiyun  *
157*4882a593Smuzhiyun  * These are the values to configure the sensor in one of the
158*4882a593Smuzhiyun  * implemented modes.
159*4882a593Smuzhiyun  *
160*4882a593Smuzhiyun  * @init_regs: registers to initialize the mode
161*4882a593Smuzhiyun  * @bin_ratio: downscale factor (e.g. 3 for 3:1 binning)
162*4882a593Smuzhiyun  * @min_frame_len: Minimum frame length for each mode (see "Frame Rate
163*4882a593Smuzhiyun  *                 Adjustment (CSI-2)" in the datasheet)
164*4882a593Smuzhiyun  * @min_SHR: Minimum SHR register value (see "Shutter Setting (CSI-2)" in the
165*4882a593Smuzhiyun  *           datasheet)
166*4882a593Smuzhiyun  * @max_fps: Maximum frames per second
167*4882a593Smuzhiyun  * @nocpiop: Number of clocks per internal offset period (see "Integration Time
168*4882a593Smuzhiyun  *           in Each Readout Drive Mode (CSI-2)" in the datasheet)
169*4882a593Smuzhiyun  */
170*4882a593Smuzhiyun struct imx274_mode {
171*4882a593Smuzhiyun 	const struct reg_8 *init_regs;
172*4882a593Smuzhiyun 	unsigned int bin_ratio;
173*4882a593Smuzhiyun 	int min_frame_len;
174*4882a593Smuzhiyun 	int min_SHR;
175*4882a593Smuzhiyun 	int max_fps;
176*4882a593Smuzhiyun 	int nocpiop;
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun /*
180*4882a593Smuzhiyun  * imx274 test pattern related structure
181*4882a593Smuzhiyun  */
182*4882a593Smuzhiyun enum {
183*4882a593Smuzhiyun 	TEST_PATTERN_DISABLED = 0,
184*4882a593Smuzhiyun 	TEST_PATTERN_ALL_000H,
185*4882a593Smuzhiyun 	TEST_PATTERN_ALL_FFFH,
186*4882a593Smuzhiyun 	TEST_PATTERN_ALL_555H,
187*4882a593Smuzhiyun 	TEST_PATTERN_ALL_AAAH,
188*4882a593Smuzhiyun 	TEST_PATTERN_VSP_5AH, /* VERTICAL STRIPE PATTERN 555H/AAAH */
189*4882a593Smuzhiyun 	TEST_PATTERN_VSP_A5H, /* VERTICAL STRIPE PATTERN AAAH/555H */
190*4882a593Smuzhiyun 	TEST_PATTERN_VSP_05H, /* VERTICAL STRIPE PATTERN 000H/555H */
191*4882a593Smuzhiyun 	TEST_PATTERN_VSP_50H, /* VERTICAL STRIPE PATTERN 555H/000H */
192*4882a593Smuzhiyun 	TEST_PATTERN_VSP_0FH, /* VERTICAL STRIPE PATTERN 000H/FFFH */
193*4882a593Smuzhiyun 	TEST_PATTERN_VSP_F0H, /* VERTICAL STRIPE PATTERN FFFH/000H */
194*4882a593Smuzhiyun 	TEST_PATTERN_H_COLOR_BARS,
195*4882a593Smuzhiyun 	TEST_PATTERN_V_COLOR_BARS,
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun static const char * const tp_qmenu[] = {
199*4882a593Smuzhiyun 	"Disabled",
200*4882a593Smuzhiyun 	"All 000h Pattern",
201*4882a593Smuzhiyun 	"All FFFh Pattern",
202*4882a593Smuzhiyun 	"All 555h Pattern",
203*4882a593Smuzhiyun 	"All AAAh Pattern",
204*4882a593Smuzhiyun 	"Vertical Stripe (555h / AAAh)",
205*4882a593Smuzhiyun 	"Vertical Stripe (AAAh / 555h)",
206*4882a593Smuzhiyun 	"Vertical Stripe (000h / 555h)",
207*4882a593Smuzhiyun 	"Vertical Stripe (555h / 000h)",
208*4882a593Smuzhiyun 	"Vertical Stripe (000h / FFFh)",
209*4882a593Smuzhiyun 	"Vertical Stripe (FFFh / 000h)",
210*4882a593Smuzhiyun 	"Vertical Color Bars",
211*4882a593Smuzhiyun 	"Horizontal Color Bars",
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun /*
215*4882a593Smuzhiyun  * All-pixel scan mode (10-bit)
216*4882a593Smuzhiyun  * imx274 mode1(refer to datasheet) register configuration with
217*4882a593Smuzhiyun  * 3840x2160 resolution, raw10 data and mipi four lane output
218*4882a593Smuzhiyun  */
219*4882a593Smuzhiyun static const struct reg_8 imx274_mode1_3840x2160_raw10[] = {
220*4882a593Smuzhiyun 	{0x3004, 0x01},
221*4882a593Smuzhiyun 	{0x3005, 0x01},
222*4882a593Smuzhiyun 	{0x3006, 0x00},
223*4882a593Smuzhiyun 	{0x3007, 0xa2},
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	{0x3018, 0xA2}, /* output XVS, HVS */
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	{0x306B, 0x05},
228*4882a593Smuzhiyun 	{0x30E2, 0x01},
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	{0x30EE, 0x01},
231*4882a593Smuzhiyun 	{0x3342, 0x0A},
232*4882a593Smuzhiyun 	{0x3343, 0x00},
233*4882a593Smuzhiyun 	{0x3344, 0x16},
234*4882a593Smuzhiyun 	{0x3345, 0x00},
235*4882a593Smuzhiyun 	{0x33A6, 0x01},
236*4882a593Smuzhiyun 	{0x3528, 0x0E},
237*4882a593Smuzhiyun 	{0x3554, 0x1F},
238*4882a593Smuzhiyun 	{0x3555, 0x01},
239*4882a593Smuzhiyun 	{0x3556, 0x01},
240*4882a593Smuzhiyun 	{0x3557, 0x01},
241*4882a593Smuzhiyun 	{0x3558, 0x01},
242*4882a593Smuzhiyun 	{0x3559, 0x00},
243*4882a593Smuzhiyun 	{0x355A, 0x00},
244*4882a593Smuzhiyun 	{0x35BA, 0x0E},
245*4882a593Smuzhiyun 	{0x366A, 0x1B},
246*4882a593Smuzhiyun 	{0x366B, 0x1A},
247*4882a593Smuzhiyun 	{0x366C, 0x19},
248*4882a593Smuzhiyun 	{0x366D, 0x17},
249*4882a593Smuzhiyun 	{0x3A41, 0x08},
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	{IMX274_TABLE_END, 0x00}
252*4882a593Smuzhiyun };
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun /*
255*4882a593Smuzhiyun  * Horizontal/vertical 2/2-line binning
256*4882a593Smuzhiyun  * (Horizontal and vertical weightedbinning, 10-bit)
257*4882a593Smuzhiyun  * imx274 mode3(refer to datasheet) register configuration with
258*4882a593Smuzhiyun  * 1920x1080 resolution, raw10 data and mipi four lane output
259*4882a593Smuzhiyun  */
260*4882a593Smuzhiyun static const struct reg_8 imx274_mode3_1920x1080_raw10[] = {
261*4882a593Smuzhiyun 	{0x3004, 0x02},
262*4882a593Smuzhiyun 	{0x3005, 0x21},
263*4882a593Smuzhiyun 	{0x3006, 0x00},
264*4882a593Smuzhiyun 	{0x3007, 0xb1},
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	{0x3018, 0xA2}, /* output XVS, HVS */
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	{0x306B, 0x05},
269*4882a593Smuzhiyun 	{0x30E2, 0x02},
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	{0x30EE, 0x01},
272*4882a593Smuzhiyun 	{0x3342, 0x0A},
273*4882a593Smuzhiyun 	{0x3343, 0x00},
274*4882a593Smuzhiyun 	{0x3344, 0x1A},
275*4882a593Smuzhiyun 	{0x3345, 0x00},
276*4882a593Smuzhiyun 	{0x33A6, 0x01},
277*4882a593Smuzhiyun 	{0x3528, 0x0E},
278*4882a593Smuzhiyun 	{0x3554, 0x00},
279*4882a593Smuzhiyun 	{0x3555, 0x01},
280*4882a593Smuzhiyun 	{0x3556, 0x01},
281*4882a593Smuzhiyun 	{0x3557, 0x01},
282*4882a593Smuzhiyun 	{0x3558, 0x01},
283*4882a593Smuzhiyun 	{0x3559, 0x00},
284*4882a593Smuzhiyun 	{0x355A, 0x00},
285*4882a593Smuzhiyun 	{0x35BA, 0x0E},
286*4882a593Smuzhiyun 	{0x366A, 0x1B},
287*4882a593Smuzhiyun 	{0x366B, 0x1A},
288*4882a593Smuzhiyun 	{0x366C, 0x19},
289*4882a593Smuzhiyun 	{0x366D, 0x17},
290*4882a593Smuzhiyun 	{0x3A41, 0x08},
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	{IMX274_TABLE_END, 0x00}
293*4882a593Smuzhiyun };
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun /*
296*4882a593Smuzhiyun  * Vertical 2/3 subsampling binning horizontal 3 binning
297*4882a593Smuzhiyun  * imx274 mode5(refer to datasheet) register configuration with
298*4882a593Smuzhiyun  * 1280x720 resolution, raw10 data and mipi four lane output
299*4882a593Smuzhiyun  */
300*4882a593Smuzhiyun static const struct reg_8 imx274_mode5_1280x720_raw10[] = {
301*4882a593Smuzhiyun 	{0x3004, 0x03},
302*4882a593Smuzhiyun 	{0x3005, 0x31},
303*4882a593Smuzhiyun 	{0x3006, 0x00},
304*4882a593Smuzhiyun 	{0x3007, 0xa9},
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	{0x3018, 0xA2}, /* output XVS, HVS */
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	{0x306B, 0x05},
309*4882a593Smuzhiyun 	{0x30E2, 0x03},
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	{0x30EE, 0x01},
312*4882a593Smuzhiyun 	{0x3342, 0x0A},
313*4882a593Smuzhiyun 	{0x3343, 0x00},
314*4882a593Smuzhiyun 	{0x3344, 0x1B},
315*4882a593Smuzhiyun 	{0x3345, 0x00},
316*4882a593Smuzhiyun 	{0x33A6, 0x01},
317*4882a593Smuzhiyun 	{0x3528, 0x0E},
318*4882a593Smuzhiyun 	{0x3554, 0x00},
319*4882a593Smuzhiyun 	{0x3555, 0x01},
320*4882a593Smuzhiyun 	{0x3556, 0x01},
321*4882a593Smuzhiyun 	{0x3557, 0x01},
322*4882a593Smuzhiyun 	{0x3558, 0x01},
323*4882a593Smuzhiyun 	{0x3559, 0x00},
324*4882a593Smuzhiyun 	{0x355A, 0x00},
325*4882a593Smuzhiyun 	{0x35BA, 0x0E},
326*4882a593Smuzhiyun 	{0x366A, 0x1B},
327*4882a593Smuzhiyun 	{0x366B, 0x19},
328*4882a593Smuzhiyun 	{0x366C, 0x17},
329*4882a593Smuzhiyun 	{0x366D, 0x17},
330*4882a593Smuzhiyun 	{0x3A41, 0x04},
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	{IMX274_TABLE_END, 0x00}
333*4882a593Smuzhiyun };
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun /*
336*4882a593Smuzhiyun  * imx274 first step register configuration for
337*4882a593Smuzhiyun  * starting stream
338*4882a593Smuzhiyun  */
339*4882a593Smuzhiyun static const struct reg_8 imx274_start_1[] = {
340*4882a593Smuzhiyun 	{IMX274_STANDBY_REG, 0x12},
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	/* PLRD: clock settings */
343*4882a593Smuzhiyun 	{0x3120, 0xF0},
344*4882a593Smuzhiyun 	{0x3121, 0x00},
345*4882a593Smuzhiyun 	{0x3122, 0x02},
346*4882a593Smuzhiyun 	{0x3129, 0x9C},
347*4882a593Smuzhiyun 	{0x312A, 0x02},
348*4882a593Smuzhiyun 	{0x312D, 0x02},
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	{0x310B, 0x00},
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	/* PLSTMG */
353*4882a593Smuzhiyun 	{0x304C, 0x00}, /* PLSTMG01 */
354*4882a593Smuzhiyun 	{0x304D, 0x03},
355*4882a593Smuzhiyun 	{0x331C, 0x1A},
356*4882a593Smuzhiyun 	{0x331D, 0x00},
357*4882a593Smuzhiyun 	{0x3502, 0x02},
358*4882a593Smuzhiyun 	{0x3529, 0x0E},
359*4882a593Smuzhiyun 	{0x352A, 0x0E},
360*4882a593Smuzhiyun 	{0x352B, 0x0E},
361*4882a593Smuzhiyun 	{0x3538, 0x0E},
362*4882a593Smuzhiyun 	{0x3539, 0x0E},
363*4882a593Smuzhiyun 	{0x3553, 0x00},
364*4882a593Smuzhiyun 	{0x357D, 0x05},
365*4882a593Smuzhiyun 	{0x357F, 0x05},
366*4882a593Smuzhiyun 	{0x3581, 0x04},
367*4882a593Smuzhiyun 	{0x3583, 0x76},
368*4882a593Smuzhiyun 	{0x3587, 0x01},
369*4882a593Smuzhiyun 	{0x35BB, 0x0E},
370*4882a593Smuzhiyun 	{0x35BC, 0x0E},
371*4882a593Smuzhiyun 	{0x35BD, 0x0E},
372*4882a593Smuzhiyun 	{0x35BE, 0x0E},
373*4882a593Smuzhiyun 	{0x35BF, 0x0E},
374*4882a593Smuzhiyun 	{0x366E, 0x00},
375*4882a593Smuzhiyun 	{0x366F, 0x00},
376*4882a593Smuzhiyun 	{0x3670, 0x00},
377*4882a593Smuzhiyun 	{0x3671, 0x00},
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	/* PSMIPI */
380*4882a593Smuzhiyun 	{0x3304, 0x32}, /* PSMIPI1 */
381*4882a593Smuzhiyun 	{0x3305, 0x00},
382*4882a593Smuzhiyun 	{0x3306, 0x32},
383*4882a593Smuzhiyun 	{0x3307, 0x00},
384*4882a593Smuzhiyun 	{0x3590, 0x32},
385*4882a593Smuzhiyun 	{0x3591, 0x00},
386*4882a593Smuzhiyun 	{0x3686, 0x32},
387*4882a593Smuzhiyun 	{0x3687, 0x00},
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	{IMX274_TABLE_END, 0x00}
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun /*
393*4882a593Smuzhiyun  * imx274 second step register configuration for
394*4882a593Smuzhiyun  * starting stream
395*4882a593Smuzhiyun  */
396*4882a593Smuzhiyun static const struct reg_8 imx274_start_2[] = {
397*4882a593Smuzhiyun 	{IMX274_STANDBY_REG, 0x00},
398*4882a593Smuzhiyun 	{0x303E, 0x02}, /* SYS_MODE = 2 */
399*4882a593Smuzhiyun 	{IMX274_TABLE_END, 0x00}
400*4882a593Smuzhiyun };
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun /*
403*4882a593Smuzhiyun  * imx274 third step register configuration for
404*4882a593Smuzhiyun  * starting stream
405*4882a593Smuzhiyun  */
406*4882a593Smuzhiyun static const struct reg_8 imx274_start_3[] = {
407*4882a593Smuzhiyun 	{0x30F4, 0x00},
408*4882a593Smuzhiyun 	{0x3018, 0xA2}, /* XHS VHS OUTPUT */
409*4882a593Smuzhiyun 	{IMX274_TABLE_END, 0x00}
410*4882a593Smuzhiyun };
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun /*
413*4882a593Smuzhiyun  * imx274 register configuration for stopping stream
414*4882a593Smuzhiyun  */
415*4882a593Smuzhiyun static const struct reg_8 imx274_stop[] = {
416*4882a593Smuzhiyun 	{IMX274_STANDBY_REG, 0x01},
417*4882a593Smuzhiyun 	{IMX274_TABLE_END, 0x00}
418*4882a593Smuzhiyun };
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun /*
421*4882a593Smuzhiyun  * imx274 disable test pattern register configuration
422*4882a593Smuzhiyun  */
423*4882a593Smuzhiyun static const struct reg_8 imx274_tp_disabled[] = {
424*4882a593Smuzhiyun 	{0x303C, 0x00},
425*4882a593Smuzhiyun 	{0x377F, 0x00},
426*4882a593Smuzhiyun 	{0x3781, 0x00},
427*4882a593Smuzhiyun 	{0x370B, 0x00},
428*4882a593Smuzhiyun 	{IMX274_TABLE_END, 0x00}
429*4882a593Smuzhiyun };
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun /*
432*4882a593Smuzhiyun  * imx274 test pattern register configuration
433*4882a593Smuzhiyun  * reg 0x303D defines the test pattern modes
434*4882a593Smuzhiyun  */
435*4882a593Smuzhiyun static const struct reg_8 imx274_tp_regs[] = {
436*4882a593Smuzhiyun 	{0x303C, 0x11},
437*4882a593Smuzhiyun 	{0x370E, 0x01},
438*4882a593Smuzhiyun 	{0x377F, 0x01},
439*4882a593Smuzhiyun 	{0x3781, 0x01},
440*4882a593Smuzhiyun 	{0x370B, 0x11},
441*4882a593Smuzhiyun 	{IMX274_TABLE_END, 0x00}
442*4882a593Smuzhiyun };
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun /* nocpiop happens to be the same number for the implemented modes */
445*4882a593Smuzhiyun static const struct imx274_mode imx274_modes[] = {
446*4882a593Smuzhiyun 	{
447*4882a593Smuzhiyun 		/* mode 1, 4K */
448*4882a593Smuzhiyun 		.bin_ratio = 1,
449*4882a593Smuzhiyun 		.init_regs = imx274_mode1_3840x2160_raw10,
450*4882a593Smuzhiyun 		.min_frame_len = 4550,
451*4882a593Smuzhiyun 		.min_SHR = 12,
452*4882a593Smuzhiyun 		.max_fps = 60,
453*4882a593Smuzhiyun 		.nocpiop = 112,
454*4882a593Smuzhiyun 	},
455*4882a593Smuzhiyun 	{
456*4882a593Smuzhiyun 		/* mode 3, 1080p */
457*4882a593Smuzhiyun 		.bin_ratio = 2,
458*4882a593Smuzhiyun 		.init_regs = imx274_mode3_1920x1080_raw10,
459*4882a593Smuzhiyun 		.min_frame_len = 2310,
460*4882a593Smuzhiyun 		.min_SHR = 8,
461*4882a593Smuzhiyun 		.max_fps = 120,
462*4882a593Smuzhiyun 		.nocpiop = 112,
463*4882a593Smuzhiyun 	},
464*4882a593Smuzhiyun 	{
465*4882a593Smuzhiyun 		/* mode 5, 720p */
466*4882a593Smuzhiyun 		.bin_ratio = 3,
467*4882a593Smuzhiyun 		.init_regs = imx274_mode5_1280x720_raw10,
468*4882a593Smuzhiyun 		.min_frame_len = 2310,
469*4882a593Smuzhiyun 		.min_SHR = 8,
470*4882a593Smuzhiyun 		.max_fps = 120,
471*4882a593Smuzhiyun 		.nocpiop = 112,
472*4882a593Smuzhiyun 	},
473*4882a593Smuzhiyun };
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun /*
476*4882a593Smuzhiyun  * struct imx274_ctrls - imx274 ctrl structure
477*4882a593Smuzhiyun  * @handler: V4L2 ctrl handler structure
478*4882a593Smuzhiyun  * @exposure: Pointer to expsure ctrl structure
479*4882a593Smuzhiyun  * @gain: Pointer to gain ctrl structure
480*4882a593Smuzhiyun  * @vflip: Pointer to vflip ctrl structure
481*4882a593Smuzhiyun  * @test_pattern: Pointer to test pattern ctrl structure
482*4882a593Smuzhiyun  */
483*4882a593Smuzhiyun struct imx274_ctrls {
484*4882a593Smuzhiyun 	struct v4l2_ctrl_handler handler;
485*4882a593Smuzhiyun 	struct v4l2_ctrl *exposure;
486*4882a593Smuzhiyun 	struct v4l2_ctrl *gain;
487*4882a593Smuzhiyun 	struct v4l2_ctrl *vflip;
488*4882a593Smuzhiyun 	struct v4l2_ctrl *test_pattern;
489*4882a593Smuzhiyun };
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun /*
492*4882a593Smuzhiyun  * struct stim274 - imx274 device structure
493*4882a593Smuzhiyun  * @sd: V4L2 subdevice structure
494*4882a593Smuzhiyun  * @pad: Media pad structure
495*4882a593Smuzhiyun  * @client: Pointer to I2C client
496*4882a593Smuzhiyun  * @ctrls: imx274 control structure
497*4882a593Smuzhiyun  * @crop: rect to be captured
498*4882a593Smuzhiyun  * @compose: compose rect, i.e. output resolution
499*4882a593Smuzhiyun  * @format: V4L2 media bus frame format structure
500*4882a593Smuzhiyun  *          (width and height are in sync with the compose rect)
501*4882a593Smuzhiyun  * @frame_rate: V4L2 frame rate structure
502*4882a593Smuzhiyun  * @regmap: Pointer to regmap structure
503*4882a593Smuzhiyun  * @reset_gpio: Pointer to reset gpio
504*4882a593Smuzhiyun  * @lock: Mutex structure
505*4882a593Smuzhiyun  * @mode: Parameters for the selected readout mode
506*4882a593Smuzhiyun  */
507*4882a593Smuzhiyun struct stimx274 {
508*4882a593Smuzhiyun 	struct v4l2_subdev sd;
509*4882a593Smuzhiyun 	struct media_pad pad;
510*4882a593Smuzhiyun 	struct i2c_client *client;
511*4882a593Smuzhiyun 	struct imx274_ctrls ctrls;
512*4882a593Smuzhiyun 	struct v4l2_rect crop;
513*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt format;
514*4882a593Smuzhiyun 	struct v4l2_fract frame_interval;
515*4882a593Smuzhiyun 	struct regmap *regmap;
516*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
517*4882a593Smuzhiyun 	struct mutex lock; /* mutex lock for operations */
518*4882a593Smuzhiyun 	const struct imx274_mode *mode;
519*4882a593Smuzhiyun };
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun #define IMX274_ROUND(dim, step, flags)			\
522*4882a593Smuzhiyun 	((flags) & V4L2_SEL_FLAG_GE			\
523*4882a593Smuzhiyun 	 ? roundup((dim), (step))			\
524*4882a593Smuzhiyun 	 : ((flags) & V4L2_SEL_FLAG_LE			\
525*4882a593Smuzhiyun 	    ? rounddown((dim), (step))			\
526*4882a593Smuzhiyun 	    : rounddown((dim) + (step) / 2, (step))))
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun /*
529*4882a593Smuzhiyun  * Function declaration
530*4882a593Smuzhiyun  */
531*4882a593Smuzhiyun static int imx274_set_gain(struct stimx274 *priv, struct v4l2_ctrl *ctrl);
532*4882a593Smuzhiyun static int imx274_set_exposure(struct stimx274 *priv, int val);
533*4882a593Smuzhiyun static int imx274_set_vflip(struct stimx274 *priv, int val);
534*4882a593Smuzhiyun static int imx274_set_test_pattern(struct stimx274 *priv, int val);
535*4882a593Smuzhiyun static int imx274_set_frame_interval(struct stimx274 *priv,
536*4882a593Smuzhiyun 				     struct v4l2_fract frame_interval);
537*4882a593Smuzhiyun 
msleep_range(unsigned int delay_base)538*4882a593Smuzhiyun static inline void msleep_range(unsigned int delay_base)
539*4882a593Smuzhiyun {
540*4882a593Smuzhiyun 	usleep_range(delay_base * 1000, delay_base * 1000 + 500);
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun /*
544*4882a593Smuzhiyun  * v4l2_ctrl and v4l2_subdev related operations
545*4882a593Smuzhiyun  */
ctrl_to_sd(struct v4l2_ctrl * ctrl)546*4882a593Smuzhiyun static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
547*4882a593Smuzhiyun {
548*4882a593Smuzhiyun 	return &container_of(ctrl->handler,
549*4882a593Smuzhiyun 			     struct stimx274, ctrls.handler)->sd;
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun 
to_imx274(struct v4l2_subdev * sd)552*4882a593Smuzhiyun static inline struct stimx274 *to_imx274(struct v4l2_subdev *sd)
553*4882a593Smuzhiyun {
554*4882a593Smuzhiyun 	return container_of(sd, struct stimx274, sd);
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun /*
558*4882a593Smuzhiyun  * Writing a register table
559*4882a593Smuzhiyun  *
560*4882a593Smuzhiyun  * @priv: Pointer to device
561*4882a593Smuzhiyun  * @table: Table containing register values (with optional delays)
562*4882a593Smuzhiyun  *
563*4882a593Smuzhiyun  * This is used to write register table into sensor's reg map.
564*4882a593Smuzhiyun  *
565*4882a593Smuzhiyun  * Return: 0 on success, errors otherwise
566*4882a593Smuzhiyun  */
imx274_write_table(struct stimx274 * priv,const struct reg_8 table[])567*4882a593Smuzhiyun static int imx274_write_table(struct stimx274 *priv, const struct reg_8 table[])
568*4882a593Smuzhiyun {
569*4882a593Smuzhiyun 	struct regmap *regmap = priv->regmap;
570*4882a593Smuzhiyun 	int err = 0;
571*4882a593Smuzhiyun 	const struct reg_8 *next;
572*4882a593Smuzhiyun 	u8 val;
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun 	int range_start = -1;
575*4882a593Smuzhiyun 	int range_count = 0;
576*4882a593Smuzhiyun 	u8 range_vals[16];
577*4882a593Smuzhiyun 	int max_range_vals = ARRAY_SIZE(range_vals);
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	for (next = table;; next++) {
580*4882a593Smuzhiyun 		if ((next->addr != range_start + range_count) ||
581*4882a593Smuzhiyun 		    (next->addr == IMX274_TABLE_END) ||
582*4882a593Smuzhiyun 		    (next->addr == IMX274_TABLE_WAIT_MS) ||
583*4882a593Smuzhiyun 		    (range_count == max_range_vals)) {
584*4882a593Smuzhiyun 			if (range_count == 1)
585*4882a593Smuzhiyun 				err = regmap_write(regmap,
586*4882a593Smuzhiyun 						   range_start, range_vals[0]);
587*4882a593Smuzhiyun 			else if (range_count > 1)
588*4882a593Smuzhiyun 				err = regmap_bulk_write(regmap, range_start,
589*4882a593Smuzhiyun 							&range_vals[0],
590*4882a593Smuzhiyun 							range_count);
591*4882a593Smuzhiyun 			else
592*4882a593Smuzhiyun 				err = 0;
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 			if (err)
595*4882a593Smuzhiyun 				return err;
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 			range_start = -1;
598*4882a593Smuzhiyun 			range_count = 0;
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun 			/* Handle special address values */
601*4882a593Smuzhiyun 			if (next->addr == IMX274_TABLE_END)
602*4882a593Smuzhiyun 				break;
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 			if (next->addr == IMX274_TABLE_WAIT_MS) {
605*4882a593Smuzhiyun 				msleep_range(next->val);
606*4882a593Smuzhiyun 				continue;
607*4882a593Smuzhiyun 			}
608*4882a593Smuzhiyun 		}
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 		val = next->val;
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 		if (range_start == -1)
613*4882a593Smuzhiyun 			range_start = next->addr;
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 		range_vals[range_count++] = val;
616*4882a593Smuzhiyun 	}
617*4882a593Smuzhiyun 	return 0;
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun 
imx274_write_reg(struct stimx274 * priv,u16 addr,u8 val)620*4882a593Smuzhiyun static inline int imx274_write_reg(struct stimx274 *priv, u16 addr, u8 val)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun 	int err;
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	err = regmap_write(priv->regmap, addr, val);
625*4882a593Smuzhiyun 	if (err)
626*4882a593Smuzhiyun 		dev_err(&priv->client->dev,
627*4882a593Smuzhiyun 			"%s : i2c write failed, %x = %x\n", __func__,
628*4882a593Smuzhiyun 			addr, val);
629*4882a593Smuzhiyun 	else
630*4882a593Smuzhiyun 		dev_dbg(&priv->client->dev,
631*4882a593Smuzhiyun 			"%s : addr 0x%x, val=0x%x\n", __func__,
632*4882a593Smuzhiyun 			addr, val);
633*4882a593Smuzhiyun 	return err;
634*4882a593Smuzhiyun }
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun /**
637*4882a593Smuzhiyun  * Read a multibyte register.
638*4882a593Smuzhiyun  *
639*4882a593Smuzhiyun  * Uses a bulk read where possible.
640*4882a593Smuzhiyun  *
641*4882a593Smuzhiyun  * @priv: Pointer to device structure
642*4882a593Smuzhiyun  * @addr: Address of the LSB register.  Other registers must be
643*4882a593Smuzhiyun  *        consecutive, least-to-most significant.
644*4882a593Smuzhiyun  * @val: Pointer to store the register value (cpu endianness)
645*4882a593Smuzhiyun  * @nbytes: Number of bytes to read (range: [1..3]).
646*4882a593Smuzhiyun  *          Other bytes are zet to 0.
647*4882a593Smuzhiyun  *
648*4882a593Smuzhiyun  * Return: 0 on success, errors otherwise
649*4882a593Smuzhiyun  */
imx274_read_mbreg(struct stimx274 * priv,u16 addr,u32 * val,size_t nbytes)650*4882a593Smuzhiyun static int imx274_read_mbreg(struct stimx274 *priv, u16 addr, u32 *val,
651*4882a593Smuzhiyun 			     size_t nbytes)
652*4882a593Smuzhiyun {
653*4882a593Smuzhiyun 	__le32 val_le = 0;
654*4882a593Smuzhiyun 	int err;
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 	err = regmap_bulk_read(priv->regmap, addr, &val_le, nbytes);
657*4882a593Smuzhiyun 	if (err) {
658*4882a593Smuzhiyun 		dev_err(&priv->client->dev,
659*4882a593Smuzhiyun 			"%s : i2c bulk read failed, %x (%zu bytes)\n",
660*4882a593Smuzhiyun 			__func__, addr, nbytes);
661*4882a593Smuzhiyun 	} else {
662*4882a593Smuzhiyun 		*val = le32_to_cpu(val_le);
663*4882a593Smuzhiyun 		dev_dbg(&priv->client->dev,
664*4882a593Smuzhiyun 			"%s : addr 0x%x, val=0x%x (%zu bytes)\n",
665*4882a593Smuzhiyun 			__func__, addr, *val, nbytes);
666*4882a593Smuzhiyun 	}
667*4882a593Smuzhiyun 
668*4882a593Smuzhiyun 	return err;
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun /**
672*4882a593Smuzhiyun  * Write a multibyte register.
673*4882a593Smuzhiyun  *
674*4882a593Smuzhiyun  * Uses a bulk write where possible.
675*4882a593Smuzhiyun  *
676*4882a593Smuzhiyun  * @priv: Pointer to device structure
677*4882a593Smuzhiyun  * @addr: Address of the LSB register.  Other registers must be
678*4882a593Smuzhiyun  *        consecutive, least-to-most significant.
679*4882a593Smuzhiyun  * @val: Value to be written to the register (cpu endianness)
680*4882a593Smuzhiyun  * @nbytes: Number of bytes to write (range: [1..3])
681*4882a593Smuzhiyun  */
imx274_write_mbreg(struct stimx274 * priv,u16 addr,u32 val,size_t nbytes)682*4882a593Smuzhiyun static int imx274_write_mbreg(struct stimx274 *priv, u16 addr, u32 val,
683*4882a593Smuzhiyun 			      size_t nbytes)
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun 	__le32 val_le = cpu_to_le32(val);
686*4882a593Smuzhiyun 	int err;
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	err = regmap_bulk_write(priv->regmap, addr, &val_le, nbytes);
689*4882a593Smuzhiyun 	if (err)
690*4882a593Smuzhiyun 		dev_err(&priv->client->dev,
691*4882a593Smuzhiyun 			"%s : i2c bulk write failed, %x = %x (%zu bytes)\n",
692*4882a593Smuzhiyun 			__func__, addr, val, nbytes);
693*4882a593Smuzhiyun 	else
694*4882a593Smuzhiyun 		dev_dbg(&priv->client->dev,
695*4882a593Smuzhiyun 			"%s : addr 0x%x, val=0x%x (%zu bytes)\n",
696*4882a593Smuzhiyun 			__func__, addr, val, nbytes);
697*4882a593Smuzhiyun 	return err;
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun /*
701*4882a593Smuzhiyun  * Set mode registers to start stream.
702*4882a593Smuzhiyun  * @priv: Pointer to device structure
703*4882a593Smuzhiyun  *
704*4882a593Smuzhiyun  * Return: 0 on success, errors otherwise
705*4882a593Smuzhiyun  */
imx274_mode_regs(struct stimx274 * priv)706*4882a593Smuzhiyun static int imx274_mode_regs(struct stimx274 *priv)
707*4882a593Smuzhiyun {
708*4882a593Smuzhiyun 	int err = 0;
709*4882a593Smuzhiyun 
710*4882a593Smuzhiyun 	err = imx274_write_table(priv, imx274_start_1);
711*4882a593Smuzhiyun 	if (err)
712*4882a593Smuzhiyun 		return err;
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	err = imx274_write_table(priv, priv->mode->init_regs);
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun 	return err;
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun /*
720*4882a593Smuzhiyun  * imx274_start_stream - Function for starting stream per mode index
721*4882a593Smuzhiyun  * @priv: Pointer to device structure
722*4882a593Smuzhiyun  *
723*4882a593Smuzhiyun  * Return: 0 on success, errors otherwise
724*4882a593Smuzhiyun  */
imx274_start_stream(struct stimx274 * priv)725*4882a593Smuzhiyun static int imx274_start_stream(struct stimx274 *priv)
726*4882a593Smuzhiyun {
727*4882a593Smuzhiyun 	int err = 0;
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	/*
730*4882a593Smuzhiyun 	 * Refer to "Standby Cancel Sequence when using CSI-2" in
731*4882a593Smuzhiyun 	 * imx274 datasheet, it should wait 10ms or more here.
732*4882a593Smuzhiyun 	 * give it 1 extra ms for margin
733*4882a593Smuzhiyun 	 */
734*4882a593Smuzhiyun 	msleep_range(11);
735*4882a593Smuzhiyun 	err = imx274_write_table(priv, imx274_start_2);
736*4882a593Smuzhiyun 	if (err)
737*4882a593Smuzhiyun 		return err;
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun 	/*
740*4882a593Smuzhiyun 	 * Refer to "Standby Cancel Sequence when using CSI-2" in
741*4882a593Smuzhiyun 	 * imx274 datasheet, it should wait 7ms or more here.
742*4882a593Smuzhiyun 	 * give it 1 extra ms for margin
743*4882a593Smuzhiyun 	 */
744*4882a593Smuzhiyun 	msleep_range(8);
745*4882a593Smuzhiyun 	err = imx274_write_table(priv, imx274_start_3);
746*4882a593Smuzhiyun 	if (err)
747*4882a593Smuzhiyun 		return err;
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun 	return 0;
750*4882a593Smuzhiyun }
751*4882a593Smuzhiyun 
752*4882a593Smuzhiyun /*
753*4882a593Smuzhiyun  * imx274_reset - Function called to reset the sensor
754*4882a593Smuzhiyun  * @priv: Pointer to device structure
755*4882a593Smuzhiyun  * @rst: Input value for determining the sensor's end state after reset
756*4882a593Smuzhiyun  *
757*4882a593Smuzhiyun  * Set the senor in reset and then
758*4882a593Smuzhiyun  * if rst = 0, keep it in reset;
759*4882a593Smuzhiyun  * if rst = 1, bring it out of reset.
760*4882a593Smuzhiyun  *
761*4882a593Smuzhiyun  */
imx274_reset(struct stimx274 * priv,int rst)762*4882a593Smuzhiyun static void imx274_reset(struct stimx274 *priv, int rst)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun 	gpiod_set_value_cansleep(priv->reset_gpio, 0);
765*4882a593Smuzhiyun 	usleep_range(IMX274_RESET_DELAY1, IMX274_RESET_DELAY2);
766*4882a593Smuzhiyun 	gpiod_set_value_cansleep(priv->reset_gpio, !!rst);
767*4882a593Smuzhiyun 	usleep_range(IMX274_RESET_DELAY1, IMX274_RESET_DELAY2);
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun /**
771*4882a593Smuzhiyun  * imx274_s_ctrl - This is used to set the imx274 V4L2 controls
772*4882a593Smuzhiyun  * @ctrl: V4L2 control to be set
773*4882a593Smuzhiyun  *
774*4882a593Smuzhiyun  * This function is used to set the V4L2 controls for the imx274 sensor.
775*4882a593Smuzhiyun  *
776*4882a593Smuzhiyun  * Return: 0 on success, errors otherwise
777*4882a593Smuzhiyun  */
imx274_s_ctrl(struct v4l2_ctrl * ctrl)778*4882a593Smuzhiyun static int imx274_s_ctrl(struct v4l2_ctrl *ctrl)
779*4882a593Smuzhiyun {
780*4882a593Smuzhiyun 	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
781*4882a593Smuzhiyun 	struct stimx274 *imx274 = to_imx274(sd);
782*4882a593Smuzhiyun 	int ret = -EINVAL;
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun 	dev_dbg(&imx274->client->dev,
785*4882a593Smuzhiyun 		"%s : s_ctrl: %s, value: %d\n", __func__,
786*4882a593Smuzhiyun 		ctrl->name, ctrl->val);
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun 	switch (ctrl->id) {
789*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE:
790*4882a593Smuzhiyun 		dev_dbg(&imx274->client->dev,
791*4882a593Smuzhiyun 			"%s : set V4L2_CID_EXPOSURE\n", __func__);
792*4882a593Smuzhiyun 		ret = imx274_set_exposure(imx274, ctrl->val);
793*4882a593Smuzhiyun 		break;
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 	case V4L2_CID_GAIN:
796*4882a593Smuzhiyun 		dev_dbg(&imx274->client->dev,
797*4882a593Smuzhiyun 			"%s : set V4L2_CID_GAIN\n", __func__);
798*4882a593Smuzhiyun 		ret = imx274_set_gain(imx274, ctrl);
799*4882a593Smuzhiyun 		break;
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 	case V4L2_CID_VFLIP:
802*4882a593Smuzhiyun 		dev_dbg(&imx274->client->dev,
803*4882a593Smuzhiyun 			"%s : set V4L2_CID_VFLIP\n", __func__);
804*4882a593Smuzhiyun 		ret = imx274_set_vflip(imx274, ctrl->val);
805*4882a593Smuzhiyun 		break;
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN:
808*4882a593Smuzhiyun 		dev_dbg(&imx274->client->dev,
809*4882a593Smuzhiyun 			"%s : set V4L2_CID_TEST_PATTERN\n", __func__);
810*4882a593Smuzhiyun 		ret = imx274_set_test_pattern(imx274, ctrl->val);
811*4882a593Smuzhiyun 		break;
812*4882a593Smuzhiyun 	}
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 	return ret;
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun 
imx274_binning_goodness(struct stimx274 * imx274,int w,int ask_w,int h,int ask_h,u32 flags)817*4882a593Smuzhiyun static int imx274_binning_goodness(struct stimx274 *imx274,
818*4882a593Smuzhiyun 				   int w, int ask_w,
819*4882a593Smuzhiyun 				   int h, int ask_h, u32 flags)
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun 	struct device *dev = &imx274->client->dev;
822*4882a593Smuzhiyun 	const int goodness = 100000;
823*4882a593Smuzhiyun 	int val = 0;
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun 	if (flags & V4L2_SEL_FLAG_GE) {
826*4882a593Smuzhiyun 		if (w < ask_w)
827*4882a593Smuzhiyun 			val -= goodness;
828*4882a593Smuzhiyun 		if (h < ask_h)
829*4882a593Smuzhiyun 			val -= goodness;
830*4882a593Smuzhiyun 	}
831*4882a593Smuzhiyun 
832*4882a593Smuzhiyun 	if (flags & V4L2_SEL_FLAG_LE) {
833*4882a593Smuzhiyun 		if (w > ask_w)
834*4882a593Smuzhiyun 			val -= goodness;
835*4882a593Smuzhiyun 		if (h > ask_h)
836*4882a593Smuzhiyun 			val -= goodness;
837*4882a593Smuzhiyun 	}
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun 	val -= abs(w - ask_w);
840*4882a593Smuzhiyun 	val -= abs(h - ask_h);
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun 	dev_dbg(dev, "%s: ask %dx%d, size %dx%d, goodness %d\n",
843*4882a593Smuzhiyun 		__func__, ask_w, ask_h, w, h, val);
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun 	return val;
846*4882a593Smuzhiyun }
847*4882a593Smuzhiyun 
848*4882a593Smuzhiyun /**
849*4882a593Smuzhiyun  * Helper function to change binning and set both compose and format.
850*4882a593Smuzhiyun  *
851*4882a593Smuzhiyun  * We have two entry points to change binning: set_fmt and
852*4882a593Smuzhiyun  * set_selection(COMPOSE). Both have to compute the new output size
853*4882a593Smuzhiyun  * and set it in both the compose rect and the frame format size. We
854*4882a593Smuzhiyun  * also need to do the same things after setting cropping to restore
855*4882a593Smuzhiyun  * 1:1 binning.
856*4882a593Smuzhiyun  *
857*4882a593Smuzhiyun  * This function contains the common code for these three cases, it
858*4882a593Smuzhiyun  * has many arguments in order to accommodate the needs of all of
859*4882a593Smuzhiyun  * them.
860*4882a593Smuzhiyun  *
861*4882a593Smuzhiyun  * Must be called with imx274->lock locked.
862*4882a593Smuzhiyun  *
863*4882a593Smuzhiyun  * @imx274: The device object
864*4882a593Smuzhiyun  * @cfg:    The pad config we are editing for TRY requests
865*4882a593Smuzhiyun  * @which:  V4L2_SUBDEV_FORMAT_ACTIVE or V4L2_SUBDEV_FORMAT_TRY from the caller
866*4882a593Smuzhiyun  * @width:  Input-output parameter: set to the desired width before
867*4882a593Smuzhiyun  *          the call, contains the chosen value after returning successfully
868*4882a593Smuzhiyun  * @height: Input-output parameter for height (see @width)
869*4882a593Smuzhiyun  * @flags:  Selection flags from struct v4l2_subdev_selection, or 0 if not
870*4882a593Smuzhiyun  *          available (when called from set_fmt)
871*4882a593Smuzhiyun  */
__imx274_change_compose(struct stimx274 * imx274,struct v4l2_subdev_pad_config * cfg,u32 which,u32 * width,u32 * height,u32 flags)872*4882a593Smuzhiyun static int __imx274_change_compose(struct stimx274 *imx274,
873*4882a593Smuzhiyun 				   struct v4l2_subdev_pad_config *cfg,
874*4882a593Smuzhiyun 				   u32 which,
875*4882a593Smuzhiyun 				   u32 *width,
876*4882a593Smuzhiyun 				   u32 *height,
877*4882a593Smuzhiyun 				   u32 flags)
878*4882a593Smuzhiyun {
879*4882a593Smuzhiyun 	struct device *dev = &imx274->client->dev;
880*4882a593Smuzhiyun 	const struct v4l2_rect *cur_crop;
881*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *tgt_fmt;
882*4882a593Smuzhiyun 	unsigned int i;
883*4882a593Smuzhiyun 	const struct imx274_mode *best_mode = &imx274_modes[0];
884*4882a593Smuzhiyun 	int best_goodness = INT_MIN;
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun 	if (which == V4L2_SUBDEV_FORMAT_TRY) {
887*4882a593Smuzhiyun 		cur_crop = &cfg->try_crop;
888*4882a593Smuzhiyun 		tgt_fmt = &cfg->try_fmt;
889*4882a593Smuzhiyun 	} else {
890*4882a593Smuzhiyun 		cur_crop = &imx274->crop;
891*4882a593Smuzhiyun 		tgt_fmt = &imx274->format;
892*4882a593Smuzhiyun 	}
893*4882a593Smuzhiyun 
894*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(imx274_modes); i++) {
895*4882a593Smuzhiyun 		unsigned int ratio = imx274_modes[i].bin_ratio;
896*4882a593Smuzhiyun 
897*4882a593Smuzhiyun 		int goodness = imx274_binning_goodness(
898*4882a593Smuzhiyun 			imx274,
899*4882a593Smuzhiyun 			cur_crop->width / ratio, *width,
900*4882a593Smuzhiyun 			cur_crop->height / ratio, *height,
901*4882a593Smuzhiyun 			flags);
902*4882a593Smuzhiyun 
903*4882a593Smuzhiyun 		if (goodness >= best_goodness) {
904*4882a593Smuzhiyun 			best_goodness = goodness;
905*4882a593Smuzhiyun 			best_mode = &imx274_modes[i];
906*4882a593Smuzhiyun 		}
907*4882a593Smuzhiyun 	}
908*4882a593Smuzhiyun 
909*4882a593Smuzhiyun 	*width = cur_crop->width / best_mode->bin_ratio;
910*4882a593Smuzhiyun 	*height = cur_crop->height / best_mode->bin_ratio;
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 	if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
913*4882a593Smuzhiyun 		imx274->mode = best_mode;
914*4882a593Smuzhiyun 
915*4882a593Smuzhiyun 	dev_dbg(dev, "%s: selected %u:1 binning\n",
916*4882a593Smuzhiyun 		__func__, best_mode->bin_ratio);
917*4882a593Smuzhiyun 
918*4882a593Smuzhiyun 	tgt_fmt->width = *width;
919*4882a593Smuzhiyun 	tgt_fmt->height = *height;
920*4882a593Smuzhiyun 	tgt_fmt->field = V4L2_FIELD_NONE;
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun 	return 0;
923*4882a593Smuzhiyun }
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun /**
926*4882a593Smuzhiyun  * imx274_get_fmt - Get the pad format
927*4882a593Smuzhiyun  * @sd: Pointer to V4L2 Sub device structure
928*4882a593Smuzhiyun  * @cfg: Pointer to sub device pad information structure
929*4882a593Smuzhiyun  * @fmt: Pointer to pad level media bus format
930*4882a593Smuzhiyun  *
931*4882a593Smuzhiyun  * This function is used to get the pad format information.
932*4882a593Smuzhiyun  *
933*4882a593Smuzhiyun  * Return: 0 on success
934*4882a593Smuzhiyun  */
imx274_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)935*4882a593Smuzhiyun static int imx274_get_fmt(struct v4l2_subdev *sd,
936*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
937*4882a593Smuzhiyun 			  struct v4l2_subdev_format *fmt)
938*4882a593Smuzhiyun {
939*4882a593Smuzhiyun 	struct stimx274 *imx274 = to_imx274(sd);
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 	mutex_lock(&imx274->lock);
942*4882a593Smuzhiyun 	fmt->format = imx274->format;
943*4882a593Smuzhiyun 	mutex_unlock(&imx274->lock);
944*4882a593Smuzhiyun 	return 0;
945*4882a593Smuzhiyun }
946*4882a593Smuzhiyun 
947*4882a593Smuzhiyun /**
948*4882a593Smuzhiyun  * imx274_set_fmt - This is used to set the pad format
949*4882a593Smuzhiyun  * @sd: Pointer to V4L2 Sub device structure
950*4882a593Smuzhiyun  * @cfg: Pointer to sub device pad information structure
951*4882a593Smuzhiyun  * @format: Pointer to pad level media bus format
952*4882a593Smuzhiyun  *
953*4882a593Smuzhiyun  * This function is used to set the pad format.
954*4882a593Smuzhiyun  *
955*4882a593Smuzhiyun  * Return: 0 on success
956*4882a593Smuzhiyun  */
imx274_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)957*4882a593Smuzhiyun static int imx274_set_fmt(struct v4l2_subdev *sd,
958*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
959*4882a593Smuzhiyun 			  struct v4l2_subdev_format *format)
960*4882a593Smuzhiyun {
961*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *fmt = &format->format;
962*4882a593Smuzhiyun 	struct stimx274 *imx274 = to_imx274(sd);
963*4882a593Smuzhiyun 	int err = 0;
964*4882a593Smuzhiyun 
965*4882a593Smuzhiyun 	mutex_lock(&imx274->lock);
966*4882a593Smuzhiyun 
967*4882a593Smuzhiyun 	err = __imx274_change_compose(imx274, cfg, format->which,
968*4882a593Smuzhiyun 				      &fmt->width, &fmt->height, 0);
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun 	if (err)
971*4882a593Smuzhiyun 		goto out;
972*4882a593Smuzhiyun 
973*4882a593Smuzhiyun 	/*
974*4882a593Smuzhiyun 	 * __imx274_change_compose already set width and height in the
975*4882a593Smuzhiyun 	 * applicable format, but we need to keep all other format
976*4882a593Smuzhiyun 	 * values, so do a full copy here
977*4882a593Smuzhiyun 	 */
978*4882a593Smuzhiyun 	fmt->field = V4L2_FIELD_NONE;
979*4882a593Smuzhiyun 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
980*4882a593Smuzhiyun 		cfg->try_fmt = *fmt;
981*4882a593Smuzhiyun 	else
982*4882a593Smuzhiyun 		imx274->format = *fmt;
983*4882a593Smuzhiyun 
984*4882a593Smuzhiyun out:
985*4882a593Smuzhiyun 	mutex_unlock(&imx274->lock);
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 	return err;
988*4882a593Smuzhiyun }
989*4882a593Smuzhiyun 
imx274_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)990*4882a593Smuzhiyun static int imx274_get_selection(struct v4l2_subdev *sd,
991*4882a593Smuzhiyun 				struct v4l2_subdev_pad_config *cfg,
992*4882a593Smuzhiyun 				struct v4l2_subdev_selection *sel)
993*4882a593Smuzhiyun {
994*4882a593Smuzhiyun 	struct stimx274 *imx274 = to_imx274(sd);
995*4882a593Smuzhiyun 	const struct v4l2_rect *src_crop;
996*4882a593Smuzhiyun 	const struct v4l2_mbus_framefmt *src_fmt;
997*4882a593Smuzhiyun 	int ret = 0;
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun 	if (sel->pad != 0)
1000*4882a593Smuzhiyun 		return -EINVAL;
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 	if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1003*4882a593Smuzhiyun 		sel->r.left = 0;
1004*4882a593Smuzhiyun 		sel->r.top = 0;
1005*4882a593Smuzhiyun 		sel->r.width = IMX274_MAX_WIDTH;
1006*4882a593Smuzhiyun 		sel->r.height = IMX274_MAX_HEIGHT;
1007*4882a593Smuzhiyun 		return 0;
1008*4882a593Smuzhiyun 	}
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1011*4882a593Smuzhiyun 		src_crop = &cfg->try_crop;
1012*4882a593Smuzhiyun 		src_fmt = &cfg->try_fmt;
1013*4882a593Smuzhiyun 	} else {
1014*4882a593Smuzhiyun 		src_crop = &imx274->crop;
1015*4882a593Smuzhiyun 		src_fmt = &imx274->format;
1016*4882a593Smuzhiyun 	}
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun 	mutex_lock(&imx274->lock);
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun 	switch (sel->target) {
1021*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP:
1022*4882a593Smuzhiyun 		sel->r = *src_crop;
1023*4882a593Smuzhiyun 		break;
1024*4882a593Smuzhiyun 	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1025*4882a593Smuzhiyun 		sel->r.top = 0;
1026*4882a593Smuzhiyun 		sel->r.left = 0;
1027*4882a593Smuzhiyun 		sel->r.width = src_crop->width;
1028*4882a593Smuzhiyun 		sel->r.height = src_crop->height;
1029*4882a593Smuzhiyun 		break;
1030*4882a593Smuzhiyun 	case V4L2_SEL_TGT_COMPOSE:
1031*4882a593Smuzhiyun 		sel->r.top = 0;
1032*4882a593Smuzhiyun 		sel->r.left = 0;
1033*4882a593Smuzhiyun 		sel->r.width = src_fmt->width;
1034*4882a593Smuzhiyun 		sel->r.height = src_fmt->height;
1035*4882a593Smuzhiyun 		break;
1036*4882a593Smuzhiyun 	default:
1037*4882a593Smuzhiyun 		ret = -EINVAL;
1038*4882a593Smuzhiyun 	}
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun 	mutex_unlock(&imx274->lock);
1041*4882a593Smuzhiyun 
1042*4882a593Smuzhiyun 	return ret;
1043*4882a593Smuzhiyun }
1044*4882a593Smuzhiyun 
imx274_set_selection_crop(struct stimx274 * imx274,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1045*4882a593Smuzhiyun static int imx274_set_selection_crop(struct stimx274 *imx274,
1046*4882a593Smuzhiyun 				     struct v4l2_subdev_pad_config *cfg,
1047*4882a593Smuzhiyun 				     struct v4l2_subdev_selection *sel)
1048*4882a593Smuzhiyun {
1049*4882a593Smuzhiyun 	struct v4l2_rect *tgt_crop;
1050*4882a593Smuzhiyun 	struct v4l2_rect new_crop;
1051*4882a593Smuzhiyun 	bool size_changed;
1052*4882a593Smuzhiyun 
1053*4882a593Smuzhiyun 	/*
1054*4882a593Smuzhiyun 	 * h_step could be 12 or 24 depending on the binning. But we
1055*4882a593Smuzhiyun 	 * won't know the binning until we choose the mode later in
1056*4882a593Smuzhiyun 	 * __imx274_change_compose(). Thus let's be safe and use the
1057*4882a593Smuzhiyun 	 * most conservative value in all cases.
1058*4882a593Smuzhiyun 	 */
1059*4882a593Smuzhiyun 	const u32 h_step = 24;
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	new_crop.width = min_t(u32,
1062*4882a593Smuzhiyun 			       IMX274_ROUND(sel->r.width, h_step, sel->flags),
1063*4882a593Smuzhiyun 			       IMX274_MAX_WIDTH);
1064*4882a593Smuzhiyun 
1065*4882a593Smuzhiyun 	/* Constraint: HTRIMMING_END - HTRIMMING_START >= 144 */
1066*4882a593Smuzhiyun 	if (new_crop.width < 144)
1067*4882a593Smuzhiyun 		new_crop.width = 144;
1068*4882a593Smuzhiyun 
1069*4882a593Smuzhiyun 	new_crop.left = min_t(u32,
1070*4882a593Smuzhiyun 			      IMX274_ROUND(sel->r.left, h_step, 0),
1071*4882a593Smuzhiyun 			      IMX274_MAX_WIDTH - new_crop.width);
1072*4882a593Smuzhiyun 
1073*4882a593Smuzhiyun 	new_crop.height = min_t(u32,
1074*4882a593Smuzhiyun 				IMX274_ROUND(sel->r.height, 2, sel->flags),
1075*4882a593Smuzhiyun 				IMX274_MAX_HEIGHT);
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 	new_crop.top = min_t(u32, IMX274_ROUND(sel->r.top, 2, 0),
1078*4882a593Smuzhiyun 			     IMX274_MAX_HEIGHT - new_crop.height);
1079*4882a593Smuzhiyun 
1080*4882a593Smuzhiyun 	sel->r = new_crop;
1081*4882a593Smuzhiyun 
1082*4882a593Smuzhiyun 	if (sel->which == V4L2_SUBDEV_FORMAT_TRY)
1083*4882a593Smuzhiyun 		tgt_crop = &cfg->try_crop;
1084*4882a593Smuzhiyun 	else
1085*4882a593Smuzhiyun 		tgt_crop = &imx274->crop;
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun 	mutex_lock(&imx274->lock);
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun 	size_changed = (new_crop.width != tgt_crop->width ||
1090*4882a593Smuzhiyun 			new_crop.height != tgt_crop->height);
1091*4882a593Smuzhiyun 
1092*4882a593Smuzhiyun 	/* __imx274_change_compose needs the new size in *tgt_crop */
1093*4882a593Smuzhiyun 	*tgt_crop = new_crop;
1094*4882a593Smuzhiyun 
1095*4882a593Smuzhiyun 	/* if crop size changed then reset the output image size */
1096*4882a593Smuzhiyun 	if (size_changed)
1097*4882a593Smuzhiyun 		__imx274_change_compose(imx274, cfg, sel->which,
1098*4882a593Smuzhiyun 					&new_crop.width, &new_crop.height,
1099*4882a593Smuzhiyun 					sel->flags);
1100*4882a593Smuzhiyun 
1101*4882a593Smuzhiyun 	mutex_unlock(&imx274->lock);
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun 	return 0;
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun 
imx274_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1106*4882a593Smuzhiyun static int imx274_set_selection(struct v4l2_subdev *sd,
1107*4882a593Smuzhiyun 				struct v4l2_subdev_pad_config *cfg,
1108*4882a593Smuzhiyun 				struct v4l2_subdev_selection *sel)
1109*4882a593Smuzhiyun {
1110*4882a593Smuzhiyun 	struct stimx274 *imx274 = to_imx274(sd);
1111*4882a593Smuzhiyun 
1112*4882a593Smuzhiyun 	if (sel->pad != 0)
1113*4882a593Smuzhiyun 		return -EINVAL;
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun 	if (sel->target == V4L2_SEL_TGT_CROP)
1116*4882a593Smuzhiyun 		return imx274_set_selection_crop(imx274, cfg, sel);
1117*4882a593Smuzhiyun 
1118*4882a593Smuzhiyun 	if (sel->target == V4L2_SEL_TGT_COMPOSE) {
1119*4882a593Smuzhiyun 		int err;
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 		mutex_lock(&imx274->lock);
1122*4882a593Smuzhiyun 		err =  __imx274_change_compose(imx274, cfg, sel->which,
1123*4882a593Smuzhiyun 					       &sel->r.width, &sel->r.height,
1124*4882a593Smuzhiyun 					       sel->flags);
1125*4882a593Smuzhiyun 		mutex_unlock(&imx274->lock);
1126*4882a593Smuzhiyun 
1127*4882a593Smuzhiyun 		/*
1128*4882a593Smuzhiyun 		 * __imx274_change_compose already set width and
1129*4882a593Smuzhiyun 		 * height in set->r, we still need to set top-left
1130*4882a593Smuzhiyun 		 */
1131*4882a593Smuzhiyun 		if (!err) {
1132*4882a593Smuzhiyun 			sel->r.top = 0;
1133*4882a593Smuzhiyun 			sel->r.left = 0;
1134*4882a593Smuzhiyun 		}
1135*4882a593Smuzhiyun 
1136*4882a593Smuzhiyun 		return err;
1137*4882a593Smuzhiyun 	}
1138*4882a593Smuzhiyun 
1139*4882a593Smuzhiyun 	return -EINVAL;
1140*4882a593Smuzhiyun }
1141*4882a593Smuzhiyun 
imx274_apply_trimming(struct stimx274 * imx274)1142*4882a593Smuzhiyun static int imx274_apply_trimming(struct stimx274 *imx274)
1143*4882a593Smuzhiyun {
1144*4882a593Smuzhiyun 	u32 h_start;
1145*4882a593Smuzhiyun 	u32 h_end;
1146*4882a593Smuzhiyun 	u32 hmax;
1147*4882a593Smuzhiyun 	u32 v_cut;
1148*4882a593Smuzhiyun 	s32 v_pos;
1149*4882a593Smuzhiyun 	u32 write_v_size;
1150*4882a593Smuzhiyun 	u32 y_out_size;
1151*4882a593Smuzhiyun 	int err;
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun 	h_start = imx274->crop.left + 12;
1154*4882a593Smuzhiyun 	h_end = h_start + imx274->crop.width;
1155*4882a593Smuzhiyun 
1156*4882a593Smuzhiyun 	/* Use the minimum allowed value of HMAX */
1157*4882a593Smuzhiyun 	/* Note: except in mode 1, (width / 16 + 23) is always < hmax_min */
1158*4882a593Smuzhiyun 	/* Note: 260 is the minimum HMAX in all implemented modes */
1159*4882a593Smuzhiyun 	hmax = max_t(u32, 260, (imx274->crop.width) / 16 + 23);
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun 	/* invert v_pos if VFLIP */
1162*4882a593Smuzhiyun 	v_pos = imx274->ctrls.vflip->cur.val ?
1163*4882a593Smuzhiyun 		(-imx274->crop.top / 2) : (imx274->crop.top / 2);
1164*4882a593Smuzhiyun 	v_cut = (IMX274_MAX_HEIGHT - imx274->crop.height) / 2;
1165*4882a593Smuzhiyun 	write_v_size = imx274->crop.height + 22;
1166*4882a593Smuzhiyun 	y_out_size   = imx274->crop.height + 14;
1167*4882a593Smuzhiyun 
1168*4882a593Smuzhiyun 	err = imx274_write_mbreg(imx274, IMX274_HMAX_REG_LSB, hmax, 2);
1169*4882a593Smuzhiyun 	if (!err)
1170*4882a593Smuzhiyun 		err = imx274_write_mbreg(imx274, IMX274_HTRIM_EN_REG, 1, 1);
1171*4882a593Smuzhiyun 	if (!err)
1172*4882a593Smuzhiyun 		err = imx274_write_mbreg(imx274, IMX274_HTRIM_START_REG_LSB,
1173*4882a593Smuzhiyun 					 h_start, 2);
1174*4882a593Smuzhiyun 	if (!err)
1175*4882a593Smuzhiyun 		err = imx274_write_mbreg(imx274, IMX274_HTRIM_END_REG_LSB,
1176*4882a593Smuzhiyun 					 h_end, 2);
1177*4882a593Smuzhiyun 	if (!err)
1178*4882a593Smuzhiyun 		err = imx274_write_mbreg(imx274, IMX274_VWIDCUTEN_REG, 1, 1);
1179*4882a593Smuzhiyun 	if (!err)
1180*4882a593Smuzhiyun 		err = imx274_write_mbreg(imx274, IMX274_VWIDCUT_REG_LSB,
1181*4882a593Smuzhiyun 					 v_cut, 2);
1182*4882a593Smuzhiyun 	if (!err)
1183*4882a593Smuzhiyun 		err = imx274_write_mbreg(imx274, IMX274_VWINPOS_REG_LSB,
1184*4882a593Smuzhiyun 					 v_pos, 2);
1185*4882a593Smuzhiyun 	if (!err)
1186*4882a593Smuzhiyun 		err = imx274_write_mbreg(imx274, IMX274_WRITE_VSIZE_REG_LSB,
1187*4882a593Smuzhiyun 					 write_v_size, 2);
1188*4882a593Smuzhiyun 	if (!err)
1189*4882a593Smuzhiyun 		err = imx274_write_mbreg(imx274, IMX274_Y_OUT_SIZE_REG_LSB,
1190*4882a593Smuzhiyun 					 y_out_size, 2);
1191*4882a593Smuzhiyun 
1192*4882a593Smuzhiyun 	return err;
1193*4882a593Smuzhiyun }
1194*4882a593Smuzhiyun 
1195*4882a593Smuzhiyun /**
1196*4882a593Smuzhiyun  * imx274_g_frame_interval - Get the frame interval
1197*4882a593Smuzhiyun  * @sd: Pointer to V4L2 Sub device structure
1198*4882a593Smuzhiyun  * @fi: Pointer to V4l2 Sub device frame interval structure
1199*4882a593Smuzhiyun  *
1200*4882a593Smuzhiyun  * This function is used to get the frame interval.
1201*4882a593Smuzhiyun  *
1202*4882a593Smuzhiyun  * Return: 0 on success
1203*4882a593Smuzhiyun  */
imx274_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1204*4882a593Smuzhiyun static int imx274_g_frame_interval(struct v4l2_subdev *sd,
1205*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_interval *fi)
1206*4882a593Smuzhiyun {
1207*4882a593Smuzhiyun 	struct stimx274 *imx274 = to_imx274(sd);
1208*4882a593Smuzhiyun 
1209*4882a593Smuzhiyun 	fi->interval = imx274->frame_interval;
1210*4882a593Smuzhiyun 	dev_dbg(&imx274->client->dev, "%s frame rate = %d / %d\n",
1211*4882a593Smuzhiyun 		__func__, imx274->frame_interval.numerator,
1212*4882a593Smuzhiyun 		imx274->frame_interval.denominator);
1213*4882a593Smuzhiyun 
1214*4882a593Smuzhiyun 	return 0;
1215*4882a593Smuzhiyun }
1216*4882a593Smuzhiyun 
1217*4882a593Smuzhiyun /**
1218*4882a593Smuzhiyun  * imx274_s_frame_interval - Set the frame interval
1219*4882a593Smuzhiyun  * @sd: Pointer to V4L2 Sub device structure
1220*4882a593Smuzhiyun  * @fi: Pointer to V4l2 Sub device frame interval structure
1221*4882a593Smuzhiyun  *
1222*4882a593Smuzhiyun  * This function is used to set the frame intervavl.
1223*4882a593Smuzhiyun  *
1224*4882a593Smuzhiyun  * Return: 0 on success
1225*4882a593Smuzhiyun  */
imx274_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1226*4882a593Smuzhiyun static int imx274_s_frame_interval(struct v4l2_subdev *sd,
1227*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_interval *fi)
1228*4882a593Smuzhiyun {
1229*4882a593Smuzhiyun 	struct stimx274 *imx274 = to_imx274(sd);
1230*4882a593Smuzhiyun 	struct v4l2_ctrl *ctrl = imx274->ctrls.exposure;
1231*4882a593Smuzhiyun 	int min, max, def;
1232*4882a593Smuzhiyun 	int ret;
1233*4882a593Smuzhiyun 
1234*4882a593Smuzhiyun 	mutex_lock(&imx274->lock);
1235*4882a593Smuzhiyun 	ret = imx274_set_frame_interval(imx274, fi->interval);
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	if (!ret) {
1238*4882a593Smuzhiyun 		fi->interval = imx274->frame_interval;
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun 		/*
1241*4882a593Smuzhiyun 		 * exposure time range is decided by frame interval
1242*4882a593Smuzhiyun 		 * need to update it after frame interval changes
1243*4882a593Smuzhiyun 		 */
1244*4882a593Smuzhiyun 		min = IMX274_MIN_EXPOSURE_TIME;
1245*4882a593Smuzhiyun 		max = fi->interval.numerator * 1000000
1246*4882a593Smuzhiyun 			/ fi->interval.denominator;
1247*4882a593Smuzhiyun 		def = max;
1248*4882a593Smuzhiyun 		if (__v4l2_ctrl_modify_range(ctrl, min, max, 1, def)) {
1249*4882a593Smuzhiyun 			dev_err(&imx274->client->dev,
1250*4882a593Smuzhiyun 				"Exposure ctrl range update failed\n");
1251*4882a593Smuzhiyun 			goto unlock;
1252*4882a593Smuzhiyun 		}
1253*4882a593Smuzhiyun 
1254*4882a593Smuzhiyun 		/* update exposure time accordingly */
1255*4882a593Smuzhiyun 		imx274_set_exposure(imx274, ctrl->val);
1256*4882a593Smuzhiyun 
1257*4882a593Smuzhiyun 		dev_dbg(&imx274->client->dev, "set frame interval to %uus\n",
1258*4882a593Smuzhiyun 			fi->interval.numerator * 1000000
1259*4882a593Smuzhiyun 			/ fi->interval.denominator);
1260*4882a593Smuzhiyun 	}
1261*4882a593Smuzhiyun 
1262*4882a593Smuzhiyun unlock:
1263*4882a593Smuzhiyun 	mutex_unlock(&imx274->lock);
1264*4882a593Smuzhiyun 
1265*4882a593Smuzhiyun 	return ret;
1266*4882a593Smuzhiyun }
1267*4882a593Smuzhiyun 
1268*4882a593Smuzhiyun /**
1269*4882a593Smuzhiyun  * imx274_load_default - load default control values
1270*4882a593Smuzhiyun  * @priv: Pointer to device structure
1271*4882a593Smuzhiyun  *
1272*4882a593Smuzhiyun  * Return: 0 on success, errors otherwise
1273*4882a593Smuzhiyun  */
imx274_load_default(struct stimx274 * priv)1274*4882a593Smuzhiyun static int imx274_load_default(struct stimx274 *priv)
1275*4882a593Smuzhiyun {
1276*4882a593Smuzhiyun 	int ret;
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 	/* load default control values */
1279*4882a593Smuzhiyun 	priv->frame_interval.numerator = 1;
1280*4882a593Smuzhiyun 	priv->frame_interval.denominator = IMX274_DEF_FRAME_RATE;
1281*4882a593Smuzhiyun 	priv->ctrls.exposure->val = 1000000 / IMX274_DEF_FRAME_RATE;
1282*4882a593Smuzhiyun 	priv->ctrls.gain->val = IMX274_DEF_GAIN;
1283*4882a593Smuzhiyun 	priv->ctrls.vflip->val = 0;
1284*4882a593Smuzhiyun 	priv->ctrls.test_pattern->val = TEST_PATTERN_DISABLED;
1285*4882a593Smuzhiyun 
1286*4882a593Smuzhiyun 	/* update frame rate */
1287*4882a593Smuzhiyun 	ret = imx274_set_frame_interval(priv,
1288*4882a593Smuzhiyun 					priv->frame_interval);
1289*4882a593Smuzhiyun 	if (ret)
1290*4882a593Smuzhiyun 		return ret;
1291*4882a593Smuzhiyun 
1292*4882a593Smuzhiyun 	/* update exposure time */
1293*4882a593Smuzhiyun 	ret = v4l2_ctrl_s_ctrl(priv->ctrls.exposure, priv->ctrls.exposure->val);
1294*4882a593Smuzhiyun 	if (ret)
1295*4882a593Smuzhiyun 		return ret;
1296*4882a593Smuzhiyun 
1297*4882a593Smuzhiyun 	/* update gain */
1298*4882a593Smuzhiyun 	ret = v4l2_ctrl_s_ctrl(priv->ctrls.gain, priv->ctrls.gain->val);
1299*4882a593Smuzhiyun 	if (ret)
1300*4882a593Smuzhiyun 		return ret;
1301*4882a593Smuzhiyun 
1302*4882a593Smuzhiyun 	/* update vflip */
1303*4882a593Smuzhiyun 	ret = v4l2_ctrl_s_ctrl(priv->ctrls.vflip, priv->ctrls.vflip->val);
1304*4882a593Smuzhiyun 	if (ret)
1305*4882a593Smuzhiyun 		return ret;
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun 	return 0;
1308*4882a593Smuzhiyun }
1309*4882a593Smuzhiyun 
1310*4882a593Smuzhiyun /**
1311*4882a593Smuzhiyun  * imx274_s_stream - It is used to start/stop the streaming.
1312*4882a593Smuzhiyun  * @sd: V4L2 Sub device
1313*4882a593Smuzhiyun  * @on: Flag (True / False)
1314*4882a593Smuzhiyun  *
1315*4882a593Smuzhiyun  * This function controls the start or stop of streaming for the
1316*4882a593Smuzhiyun  * imx274 sensor.
1317*4882a593Smuzhiyun  *
1318*4882a593Smuzhiyun  * Return: 0 on success, errors otherwise
1319*4882a593Smuzhiyun  */
imx274_s_stream(struct v4l2_subdev * sd,int on)1320*4882a593Smuzhiyun static int imx274_s_stream(struct v4l2_subdev *sd, int on)
1321*4882a593Smuzhiyun {
1322*4882a593Smuzhiyun 	struct stimx274 *imx274 = to_imx274(sd);
1323*4882a593Smuzhiyun 	int ret = 0;
1324*4882a593Smuzhiyun 
1325*4882a593Smuzhiyun 	dev_dbg(&imx274->client->dev, "%s : %s, mode index = %td\n", __func__,
1326*4882a593Smuzhiyun 		on ? "Stream Start" : "Stream Stop",
1327*4882a593Smuzhiyun 		imx274->mode - &imx274_modes[0]);
1328*4882a593Smuzhiyun 
1329*4882a593Smuzhiyun 	mutex_lock(&imx274->lock);
1330*4882a593Smuzhiyun 
1331*4882a593Smuzhiyun 	if (on) {
1332*4882a593Smuzhiyun 		/* load mode registers */
1333*4882a593Smuzhiyun 		ret = imx274_mode_regs(imx274);
1334*4882a593Smuzhiyun 		if (ret)
1335*4882a593Smuzhiyun 			goto fail;
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun 		ret = imx274_apply_trimming(imx274);
1338*4882a593Smuzhiyun 		if (ret)
1339*4882a593Smuzhiyun 			goto fail;
1340*4882a593Smuzhiyun 
1341*4882a593Smuzhiyun 		/*
1342*4882a593Smuzhiyun 		 * update frame rate & expsoure. if the last mode is different,
1343*4882a593Smuzhiyun 		 * HMAX could be changed. As the result, frame rate & exposure
1344*4882a593Smuzhiyun 		 * are changed.
1345*4882a593Smuzhiyun 		 * gain is not affected.
1346*4882a593Smuzhiyun 		 */
1347*4882a593Smuzhiyun 		ret = imx274_set_frame_interval(imx274,
1348*4882a593Smuzhiyun 						imx274->frame_interval);
1349*4882a593Smuzhiyun 		if (ret)
1350*4882a593Smuzhiyun 			goto fail;
1351*4882a593Smuzhiyun 
1352*4882a593Smuzhiyun 		/* update exposure time */
1353*4882a593Smuzhiyun 		ret = __v4l2_ctrl_s_ctrl(imx274->ctrls.exposure,
1354*4882a593Smuzhiyun 					 imx274->ctrls.exposure->val);
1355*4882a593Smuzhiyun 		if (ret)
1356*4882a593Smuzhiyun 			goto fail;
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun 		/* start stream */
1359*4882a593Smuzhiyun 		ret = imx274_start_stream(imx274);
1360*4882a593Smuzhiyun 		if (ret)
1361*4882a593Smuzhiyun 			goto fail;
1362*4882a593Smuzhiyun 	} else {
1363*4882a593Smuzhiyun 		/* stop stream */
1364*4882a593Smuzhiyun 		ret = imx274_write_table(imx274, imx274_stop);
1365*4882a593Smuzhiyun 		if (ret)
1366*4882a593Smuzhiyun 			goto fail;
1367*4882a593Smuzhiyun 	}
1368*4882a593Smuzhiyun 
1369*4882a593Smuzhiyun 	mutex_unlock(&imx274->lock);
1370*4882a593Smuzhiyun 	dev_dbg(&imx274->client->dev, "%s : Done\n", __func__);
1371*4882a593Smuzhiyun 	return 0;
1372*4882a593Smuzhiyun 
1373*4882a593Smuzhiyun fail:
1374*4882a593Smuzhiyun 	mutex_unlock(&imx274->lock);
1375*4882a593Smuzhiyun 	dev_err(&imx274->client->dev, "s_stream failed\n");
1376*4882a593Smuzhiyun 	return ret;
1377*4882a593Smuzhiyun }
1378*4882a593Smuzhiyun 
1379*4882a593Smuzhiyun /*
1380*4882a593Smuzhiyun  * imx274_get_frame_length - Function for obtaining current frame length
1381*4882a593Smuzhiyun  * @priv: Pointer to device structure
1382*4882a593Smuzhiyun  * @val: Pointer to obainted value
1383*4882a593Smuzhiyun  *
1384*4882a593Smuzhiyun  * frame_length = vmax x (svr + 1), in unit of hmax.
1385*4882a593Smuzhiyun  *
1386*4882a593Smuzhiyun  * Return: 0 on success
1387*4882a593Smuzhiyun  */
imx274_get_frame_length(struct stimx274 * priv,u32 * val)1388*4882a593Smuzhiyun static int imx274_get_frame_length(struct stimx274 *priv, u32 *val)
1389*4882a593Smuzhiyun {
1390*4882a593Smuzhiyun 	int err;
1391*4882a593Smuzhiyun 	u32 svr;
1392*4882a593Smuzhiyun 	u32 vmax;
1393*4882a593Smuzhiyun 
1394*4882a593Smuzhiyun 	err = imx274_read_mbreg(priv, IMX274_SVR_REG_LSB, &svr, 2);
1395*4882a593Smuzhiyun 	if (err)
1396*4882a593Smuzhiyun 		goto fail;
1397*4882a593Smuzhiyun 
1398*4882a593Smuzhiyun 	err = imx274_read_mbreg(priv, IMX274_VMAX_REG_3, &vmax, 3);
1399*4882a593Smuzhiyun 	if (err)
1400*4882a593Smuzhiyun 		goto fail;
1401*4882a593Smuzhiyun 
1402*4882a593Smuzhiyun 	*val = vmax * (svr + 1);
1403*4882a593Smuzhiyun 
1404*4882a593Smuzhiyun 	return 0;
1405*4882a593Smuzhiyun 
1406*4882a593Smuzhiyun fail:
1407*4882a593Smuzhiyun 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
1408*4882a593Smuzhiyun 	return err;
1409*4882a593Smuzhiyun }
1410*4882a593Smuzhiyun 
imx274_clamp_coarse_time(struct stimx274 * priv,u32 * val,u32 * frame_length)1411*4882a593Smuzhiyun static int imx274_clamp_coarse_time(struct stimx274 *priv, u32 *val,
1412*4882a593Smuzhiyun 				    u32 *frame_length)
1413*4882a593Smuzhiyun {
1414*4882a593Smuzhiyun 	int err;
1415*4882a593Smuzhiyun 
1416*4882a593Smuzhiyun 	err = imx274_get_frame_length(priv, frame_length);
1417*4882a593Smuzhiyun 	if (err)
1418*4882a593Smuzhiyun 		return err;
1419*4882a593Smuzhiyun 
1420*4882a593Smuzhiyun 	if (*frame_length < priv->mode->min_frame_len)
1421*4882a593Smuzhiyun 		*frame_length =  priv->mode->min_frame_len;
1422*4882a593Smuzhiyun 
1423*4882a593Smuzhiyun 	*val = *frame_length - *val; /* convert to raw shr */
1424*4882a593Smuzhiyun 	if (*val > *frame_length - IMX274_SHR_LIMIT_CONST)
1425*4882a593Smuzhiyun 		*val = *frame_length - IMX274_SHR_LIMIT_CONST;
1426*4882a593Smuzhiyun 	else if (*val < priv->mode->min_SHR)
1427*4882a593Smuzhiyun 		*val = priv->mode->min_SHR;
1428*4882a593Smuzhiyun 
1429*4882a593Smuzhiyun 	return 0;
1430*4882a593Smuzhiyun }
1431*4882a593Smuzhiyun 
1432*4882a593Smuzhiyun /*
1433*4882a593Smuzhiyun  * imx274_set_digital gain - Function called when setting digital gain
1434*4882a593Smuzhiyun  * @priv: Pointer to device structure
1435*4882a593Smuzhiyun  * @dgain: Value of digital gain.
1436*4882a593Smuzhiyun  *
1437*4882a593Smuzhiyun  * Digital gain has only 4 steps: 1x, 2x, 4x, and 8x
1438*4882a593Smuzhiyun  *
1439*4882a593Smuzhiyun  * Return: 0 on success
1440*4882a593Smuzhiyun  */
imx274_set_digital_gain(struct stimx274 * priv,u32 dgain)1441*4882a593Smuzhiyun static int imx274_set_digital_gain(struct stimx274 *priv, u32 dgain)
1442*4882a593Smuzhiyun {
1443*4882a593Smuzhiyun 	u8 reg_val;
1444*4882a593Smuzhiyun 
1445*4882a593Smuzhiyun 	reg_val = ffs(dgain);
1446*4882a593Smuzhiyun 
1447*4882a593Smuzhiyun 	if (reg_val)
1448*4882a593Smuzhiyun 		reg_val--;
1449*4882a593Smuzhiyun 
1450*4882a593Smuzhiyun 	reg_val = clamp(reg_val, (u8)0, (u8)3);
1451*4882a593Smuzhiyun 
1452*4882a593Smuzhiyun 	return imx274_write_reg(priv, IMX274_DIGITAL_GAIN_REG,
1453*4882a593Smuzhiyun 				reg_val & IMX274_MASK_LSB_4_BITS);
1454*4882a593Smuzhiyun }
1455*4882a593Smuzhiyun 
1456*4882a593Smuzhiyun /*
1457*4882a593Smuzhiyun  * imx274_set_gain - Function called when setting gain
1458*4882a593Smuzhiyun  * @priv: Pointer to device structure
1459*4882a593Smuzhiyun  * @val: Value of gain. the real value = val << IMX274_GAIN_SHIFT;
1460*4882a593Smuzhiyun  * @ctrl: v4l2 control pointer
1461*4882a593Smuzhiyun  *
1462*4882a593Smuzhiyun  * Set the gain based on input value.
1463*4882a593Smuzhiyun  * The caller should hold the mutex lock imx274->lock if necessary
1464*4882a593Smuzhiyun  *
1465*4882a593Smuzhiyun  * Return: 0 on success
1466*4882a593Smuzhiyun  */
imx274_set_gain(struct stimx274 * priv,struct v4l2_ctrl * ctrl)1467*4882a593Smuzhiyun static int imx274_set_gain(struct stimx274 *priv, struct v4l2_ctrl *ctrl)
1468*4882a593Smuzhiyun {
1469*4882a593Smuzhiyun 	int err;
1470*4882a593Smuzhiyun 	u32 gain, analog_gain, digital_gain, gain_reg;
1471*4882a593Smuzhiyun 
1472*4882a593Smuzhiyun 	gain = (u32)(ctrl->val);
1473*4882a593Smuzhiyun 
1474*4882a593Smuzhiyun 	dev_dbg(&priv->client->dev,
1475*4882a593Smuzhiyun 		"%s : input gain = %d.%d\n", __func__,
1476*4882a593Smuzhiyun 		gain >> IMX274_GAIN_SHIFT,
1477*4882a593Smuzhiyun 		((gain & IMX274_GAIN_SHIFT_MASK) * 100) >> IMX274_GAIN_SHIFT);
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	if (gain > IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN)
1480*4882a593Smuzhiyun 		gain = IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN;
1481*4882a593Smuzhiyun 	else if (gain < IMX274_MIN_GAIN)
1482*4882a593Smuzhiyun 		gain = IMX274_MIN_GAIN;
1483*4882a593Smuzhiyun 
1484*4882a593Smuzhiyun 	if (gain <= IMX274_MAX_ANALOG_GAIN)
1485*4882a593Smuzhiyun 		digital_gain = 1;
1486*4882a593Smuzhiyun 	else if (gain <= IMX274_MAX_ANALOG_GAIN * 2)
1487*4882a593Smuzhiyun 		digital_gain = 2;
1488*4882a593Smuzhiyun 	else if (gain <= IMX274_MAX_ANALOG_GAIN * 4)
1489*4882a593Smuzhiyun 		digital_gain = 4;
1490*4882a593Smuzhiyun 	else
1491*4882a593Smuzhiyun 		digital_gain = IMX274_MAX_DIGITAL_GAIN;
1492*4882a593Smuzhiyun 
1493*4882a593Smuzhiyun 	analog_gain = gain / digital_gain;
1494*4882a593Smuzhiyun 
1495*4882a593Smuzhiyun 	dev_dbg(&priv->client->dev,
1496*4882a593Smuzhiyun 		"%s : digital gain = %d, analog gain = %d.%d\n",
1497*4882a593Smuzhiyun 		__func__, digital_gain, analog_gain >> IMX274_GAIN_SHIFT,
1498*4882a593Smuzhiyun 		((analog_gain & IMX274_GAIN_SHIFT_MASK) * 100)
1499*4882a593Smuzhiyun 		>> IMX274_GAIN_SHIFT);
1500*4882a593Smuzhiyun 
1501*4882a593Smuzhiyun 	err = imx274_set_digital_gain(priv, digital_gain);
1502*4882a593Smuzhiyun 	if (err)
1503*4882a593Smuzhiyun 		goto fail;
1504*4882a593Smuzhiyun 
1505*4882a593Smuzhiyun 	/* convert to register value, refer to imx274 datasheet */
1506*4882a593Smuzhiyun 	gain_reg = (u32)IMX274_GAIN_CONST -
1507*4882a593Smuzhiyun 		(IMX274_GAIN_CONST << IMX274_GAIN_SHIFT) / analog_gain;
1508*4882a593Smuzhiyun 	if (gain_reg > IMX274_GAIN_REG_MAX)
1509*4882a593Smuzhiyun 		gain_reg = IMX274_GAIN_REG_MAX;
1510*4882a593Smuzhiyun 
1511*4882a593Smuzhiyun 	err = imx274_write_mbreg(priv, IMX274_ANALOG_GAIN_ADDR_LSB, gain_reg,
1512*4882a593Smuzhiyun 				 2);
1513*4882a593Smuzhiyun 	if (err)
1514*4882a593Smuzhiyun 		goto fail;
1515*4882a593Smuzhiyun 
1516*4882a593Smuzhiyun 	if (IMX274_GAIN_CONST - gain_reg == 0) {
1517*4882a593Smuzhiyun 		err = -EINVAL;
1518*4882a593Smuzhiyun 		goto fail;
1519*4882a593Smuzhiyun 	}
1520*4882a593Smuzhiyun 
1521*4882a593Smuzhiyun 	/* convert register value back to gain value */
1522*4882a593Smuzhiyun 	ctrl->val = (IMX274_GAIN_CONST << IMX274_GAIN_SHIFT)
1523*4882a593Smuzhiyun 			/ (IMX274_GAIN_CONST - gain_reg) * digital_gain;
1524*4882a593Smuzhiyun 
1525*4882a593Smuzhiyun 	dev_dbg(&priv->client->dev,
1526*4882a593Smuzhiyun 		"%s : GAIN control success, gain_reg = %d, new gain = %d\n",
1527*4882a593Smuzhiyun 		__func__, gain_reg, ctrl->val);
1528*4882a593Smuzhiyun 
1529*4882a593Smuzhiyun 	return 0;
1530*4882a593Smuzhiyun 
1531*4882a593Smuzhiyun fail:
1532*4882a593Smuzhiyun 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
1533*4882a593Smuzhiyun 	return err;
1534*4882a593Smuzhiyun }
1535*4882a593Smuzhiyun 
1536*4882a593Smuzhiyun /*
1537*4882a593Smuzhiyun  * imx274_set_coarse_time - Function called when setting SHR value
1538*4882a593Smuzhiyun  * @priv: Pointer to device structure
1539*4882a593Smuzhiyun  * @val: Value for exposure time in number of line_length, or [HMAX]
1540*4882a593Smuzhiyun  *
1541*4882a593Smuzhiyun  * Set SHR value based on input value.
1542*4882a593Smuzhiyun  *
1543*4882a593Smuzhiyun  * Return: 0 on success
1544*4882a593Smuzhiyun  */
imx274_set_coarse_time(struct stimx274 * priv,u32 * val)1545*4882a593Smuzhiyun static int imx274_set_coarse_time(struct stimx274 *priv, u32 *val)
1546*4882a593Smuzhiyun {
1547*4882a593Smuzhiyun 	int err;
1548*4882a593Smuzhiyun 	u32 coarse_time, frame_length;
1549*4882a593Smuzhiyun 
1550*4882a593Smuzhiyun 	coarse_time = *val;
1551*4882a593Smuzhiyun 
1552*4882a593Smuzhiyun 	/* convert exposure_time to appropriate SHR value */
1553*4882a593Smuzhiyun 	err = imx274_clamp_coarse_time(priv, &coarse_time, &frame_length);
1554*4882a593Smuzhiyun 	if (err)
1555*4882a593Smuzhiyun 		goto fail;
1556*4882a593Smuzhiyun 
1557*4882a593Smuzhiyun 	err = imx274_write_mbreg(priv, IMX274_SHR_REG_LSB, coarse_time, 2);
1558*4882a593Smuzhiyun 	if (err)
1559*4882a593Smuzhiyun 		goto fail;
1560*4882a593Smuzhiyun 
1561*4882a593Smuzhiyun 	*val = frame_length - coarse_time;
1562*4882a593Smuzhiyun 	return 0;
1563*4882a593Smuzhiyun 
1564*4882a593Smuzhiyun fail:
1565*4882a593Smuzhiyun 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
1566*4882a593Smuzhiyun 	return err;
1567*4882a593Smuzhiyun }
1568*4882a593Smuzhiyun 
1569*4882a593Smuzhiyun /*
1570*4882a593Smuzhiyun  * imx274_set_exposure - Function called when setting exposure time
1571*4882a593Smuzhiyun  * @priv: Pointer to device structure
1572*4882a593Smuzhiyun  * @val: Variable for exposure time, in the unit of micro-second
1573*4882a593Smuzhiyun  *
1574*4882a593Smuzhiyun  * Set exposure time based on input value.
1575*4882a593Smuzhiyun  * The caller should hold the mutex lock imx274->lock if necessary
1576*4882a593Smuzhiyun  *
1577*4882a593Smuzhiyun  * Return: 0 on success
1578*4882a593Smuzhiyun  */
imx274_set_exposure(struct stimx274 * priv,int val)1579*4882a593Smuzhiyun static int imx274_set_exposure(struct stimx274 *priv, int val)
1580*4882a593Smuzhiyun {
1581*4882a593Smuzhiyun 	int err;
1582*4882a593Smuzhiyun 	u32 hmax;
1583*4882a593Smuzhiyun 	u32 coarse_time; /* exposure time in unit of line (HMAX)*/
1584*4882a593Smuzhiyun 
1585*4882a593Smuzhiyun 	dev_dbg(&priv->client->dev,
1586*4882a593Smuzhiyun 		"%s : EXPOSURE control input = %d\n", __func__, val);
1587*4882a593Smuzhiyun 
1588*4882a593Smuzhiyun 	/* step 1: convert input exposure_time (val) into number of 1[HMAX] */
1589*4882a593Smuzhiyun 
1590*4882a593Smuzhiyun 	err = imx274_read_mbreg(priv, IMX274_HMAX_REG_LSB, &hmax, 2);
1591*4882a593Smuzhiyun 	if (err)
1592*4882a593Smuzhiyun 		goto fail;
1593*4882a593Smuzhiyun 
1594*4882a593Smuzhiyun 	if (hmax == 0) {
1595*4882a593Smuzhiyun 		err = -EINVAL;
1596*4882a593Smuzhiyun 		goto fail;
1597*4882a593Smuzhiyun 	}
1598*4882a593Smuzhiyun 
1599*4882a593Smuzhiyun 	coarse_time = (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2 * val
1600*4882a593Smuzhiyun 			- priv->mode->nocpiop) / hmax;
1601*4882a593Smuzhiyun 
1602*4882a593Smuzhiyun 	/* step 2: convert exposure_time into SHR value */
1603*4882a593Smuzhiyun 
1604*4882a593Smuzhiyun 	/* set SHR */
1605*4882a593Smuzhiyun 	err = imx274_set_coarse_time(priv, &coarse_time);
1606*4882a593Smuzhiyun 	if (err)
1607*4882a593Smuzhiyun 		goto fail;
1608*4882a593Smuzhiyun 
1609*4882a593Smuzhiyun 	priv->ctrls.exposure->val =
1610*4882a593Smuzhiyun 			(coarse_time * hmax + priv->mode->nocpiop)
1611*4882a593Smuzhiyun 			/ (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2);
1612*4882a593Smuzhiyun 
1613*4882a593Smuzhiyun 	dev_dbg(&priv->client->dev,
1614*4882a593Smuzhiyun 		"%s : EXPOSURE control success\n", __func__);
1615*4882a593Smuzhiyun 	return 0;
1616*4882a593Smuzhiyun 
1617*4882a593Smuzhiyun fail:
1618*4882a593Smuzhiyun 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
1619*4882a593Smuzhiyun 
1620*4882a593Smuzhiyun 	return err;
1621*4882a593Smuzhiyun }
1622*4882a593Smuzhiyun 
1623*4882a593Smuzhiyun /*
1624*4882a593Smuzhiyun  * imx274_set_vflip - Function called when setting vertical flip
1625*4882a593Smuzhiyun  * @priv: Pointer to device structure
1626*4882a593Smuzhiyun  * @val: Value for vflip setting
1627*4882a593Smuzhiyun  *
1628*4882a593Smuzhiyun  * Set vertical flip based on input value.
1629*4882a593Smuzhiyun  * val = 0: normal, no vertical flip
1630*4882a593Smuzhiyun  * val = 1: vertical flip enabled
1631*4882a593Smuzhiyun  * The caller should hold the mutex lock imx274->lock if necessary
1632*4882a593Smuzhiyun  *
1633*4882a593Smuzhiyun  * Return: 0 on success
1634*4882a593Smuzhiyun  */
imx274_set_vflip(struct stimx274 * priv,int val)1635*4882a593Smuzhiyun static int imx274_set_vflip(struct stimx274 *priv, int val)
1636*4882a593Smuzhiyun {
1637*4882a593Smuzhiyun 	int err;
1638*4882a593Smuzhiyun 
1639*4882a593Smuzhiyun 	err = imx274_write_reg(priv, IMX274_VFLIP_REG, val);
1640*4882a593Smuzhiyun 	if (err) {
1641*4882a593Smuzhiyun 		dev_err(&priv->client->dev, "VFLIP control error\n");
1642*4882a593Smuzhiyun 		return err;
1643*4882a593Smuzhiyun 	}
1644*4882a593Smuzhiyun 
1645*4882a593Smuzhiyun 	dev_dbg(&priv->client->dev,
1646*4882a593Smuzhiyun 		"%s : VFLIP control success\n", __func__);
1647*4882a593Smuzhiyun 
1648*4882a593Smuzhiyun 	return 0;
1649*4882a593Smuzhiyun }
1650*4882a593Smuzhiyun 
1651*4882a593Smuzhiyun /*
1652*4882a593Smuzhiyun  * imx274_set_test_pattern - Function called when setting test pattern
1653*4882a593Smuzhiyun  * @priv: Pointer to device structure
1654*4882a593Smuzhiyun  * @val: Variable for test pattern
1655*4882a593Smuzhiyun  *
1656*4882a593Smuzhiyun  * Set to different test patterns based on input value.
1657*4882a593Smuzhiyun  *
1658*4882a593Smuzhiyun  * Return: 0 on success
1659*4882a593Smuzhiyun  */
imx274_set_test_pattern(struct stimx274 * priv,int val)1660*4882a593Smuzhiyun static int imx274_set_test_pattern(struct stimx274 *priv, int val)
1661*4882a593Smuzhiyun {
1662*4882a593Smuzhiyun 	int err = 0;
1663*4882a593Smuzhiyun 
1664*4882a593Smuzhiyun 	if (val == TEST_PATTERN_DISABLED) {
1665*4882a593Smuzhiyun 		err = imx274_write_table(priv, imx274_tp_disabled);
1666*4882a593Smuzhiyun 	} else if (val <= TEST_PATTERN_V_COLOR_BARS) {
1667*4882a593Smuzhiyun 		err = imx274_write_reg(priv, IMX274_TEST_PATTERN_REG, val - 1);
1668*4882a593Smuzhiyun 		if (!err)
1669*4882a593Smuzhiyun 			err = imx274_write_table(priv, imx274_tp_regs);
1670*4882a593Smuzhiyun 	} else {
1671*4882a593Smuzhiyun 		err = -EINVAL;
1672*4882a593Smuzhiyun 	}
1673*4882a593Smuzhiyun 
1674*4882a593Smuzhiyun 	if (!err)
1675*4882a593Smuzhiyun 		dev_dbg(&priv->client->dev,
1676*4882a593Smuzhiyun 			"%s : TEST PATTERN control success\n", __func__);
1677*4882a593Smuzhiyun 	else
1678*4882a593Smuzhiyun 		dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
1679*4882a593Smuzhiyun 
1680*4882a593Smuzhiyun 	return err;
1681*4882a593Smuzhiyun }
1682*4882a593Smuzhiyun 
1683*4882a593Smuzhiyun /*
1684*4882a593Smuzhiyun  * imx274_set_frame_length - Function called when setting frame length
1685*4882a593Smuzhiyun  * @priv: Pointer to device structure
1686*4882a593Smuzhiyun  * @val: Variable for frame length (= VMAX, i.e. vertical drive period length)
1687*4882a593Smuzhiyun  *
1688*4882a593Smuzhiyun  * Set frame length based on input value.
1689*4882a593Smuzhiyun  *
1690*4882a593Smuzhiyun  * Return: 0 on success
1691*4882a593Smuzhiyun  */
imx274_set_frame_length(struct stimx274 * priv,u32 val)1692*4882a593Smuzhiyun static int imx274_set_frame_length(struct stimx274 *priv, u32 val)
1693*4882a593Smuzhiyun {
1694*4882a593Smuzhiyun 	int err;
1695*4882a593Smuzhiyun 	u32 frame_length;
1696*4882a593Smuzhiyun 
1697*4882a593Smuzhiyun 	dev_dbg(&priv->client->dev, "%s : input length = %d\n",
1698*4882a593Smuzhiyun 		__func__, val);
1699*4882a593Smuzhiyun 
1700*4882a593Smuzhiyun 	frame_length = (u32)val;
1701*4882a593Smuzhiyun 
1702*4882a593Smuzhiyun 	err = imx274_write_mbreg(priv, IMX274_VMAX_REG_3, frame_length, 3);
1703*4882a593Smuzhiyun 	if (err)
1704*4882a593Smuzhiyun 		goto fail;
1705*4882a593Smuzhiyun 
1706*4882a593Smuzhiyun 	return 0;
1707*4882a593Smuzhiyun 
1708*4882a593Smuzhiyun fail:
1709*4882a593Smuzhiyun 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
1710*4882a593Smuzhiyun 	return err;
1711*4882a593Smuzhiyun }
1712*4882a593Smuzhiyun 
1713*4882a593Smuzhiyun /*
1714*4882a593Smuzhiyun  * imx274_set_frame_interval - Function called when setting frame interval
1715*4882a593Smuzhiyun  * @priv: Pointer to device structure
1716*4882a593Smuzhiyun  * @frame_interval: Variable for frame interval
1717*4882a593Smuzhiyun  *
1718*4882a593Smuzhiyun  * Change frame interval by updating VMAX value
1719*4882a593Smuzhiyun  * The caller should hold the mutex lock imx274->lock if necessary
1720*4882a593Smuzhiyun  *
1721*4882a593Smuzhiyun  * Return: 0 on success
1722*4882a593Smuzhiyun  */
imx274_set_frame_interval(struct stimx274 * priv,struct v4l2_fract frame_interval)1723*4882a593Smuzhiyun static int imx274_set_frame_interval(struct stimx274 *priv,
1724*4882a593Smuzhiyun 				     struct v4l2_fract frame_interval)
1725*4882a593Smuzhiyun {
1726*4882a593Smuzhiyun 	int err;
1727*4882a593Smuzhiyun 	u32 frame_length, req_frame_rate;
1728*4882a593Smuzhiyun 	u32 svr;
1729*4882a593Smuzhiyun 	u32 hmax;
1730*4882a593Smuzhiyun 
1731*4882a593Smuzhiyun 	dev_dbg(&priv->client->dev, "%s: input frame interval = %d / %d",
1732*4882a593Smuzhiyun 		__func__, frame_interval.numerator,
1733*4882a593Smuzhiyun 		frame_interval.denominator);
1734*4882a593Smuzhiyun 
1735*4882a593Smuzhiyun 	if (frame_interval.numerator == 0 || frame_interval.denominator == 0) {
1736*4882a593Smuzhiyun 		frame_interval.denominator = IMX274_DEF_FRAME_RATE;
1737*4882a593Smuzhiyun 		frame_interval.numerator = 1;
1738*4882a593Smuzhiyun 	}
1739*4882a593Smuzhiyun 
1740*4882a593Smuzhiyun 	req_frame_rate = (u32)(frame_interval.denominator
1741*4882a593Smuzhiyun 				/ frame_interval.numerator);
1742*4882a593Smuzhiyun 
1743*4882a593Smuzhiyun 	/* boundary check */
1744*4882a593Smuzhiyun 	if (req_frame_rate > priv->mode->max_fps) {
1745*4882a593Smuzhiyun 		frame_interval.numerator = 1;
1746*4882a593Smuzhiyun 		frame_interval.denominator = priv->mode->max_fps;
1747*4882a593Smuzhiyun 	} else if (req_frame_rate < IMX274_MIN_FRAME_RATE) {
1748*4882a593Smuzhiyun 		frame_interval.numerator = 1;
1749*4882a593Smuzhiyun 		frame_interval.denominator = IMX274_MIN_FRAME_RATE;
1750*4882a593Smuzhiyun 	}
1751*4882a593Smuzhiyun 
1752*4882a593Smuzhiyun 	/*
1753*4882a593Smuzhiyun 	 * VMAX = 1/frame_rate x 72M / (SVR+1) / HMAX
1754*4882a593Smuzhiyun 	 * frame_length (i.e. VMAX) = (frame_interval) x 72M /(SVR+1) / HMAX
1755*4882a593Smuzhiyun 	 */
1756*4882a593Smuzhiyun 
1757*4882a593Smuzhiyun 	err = imx274_read_mbreg(priv, IMX274_SVR_REG_LSB, &svr, 2);
1758*4882a593Smuzhiyun 	if (err)
1759*4882a593Smuzhiyun 		goto fail;
1760*4882a593Smuzhiyun 
1761*4882a593Smuzhiyun 	dev_dbg(&priv->client->dev,
1762*4882a593Smuzhiyun 		"%s : register SVR = %d\n", __func__, svr);
1763*4882a593Smuzhiyun 
1764*4882a593Smuzhiyun 	err = imx274_read_mbreg(priv, IMX274_HMAX_REG_LSB, &hmax, 2);
1765*4882a593Smuzhiyun 	if (err)
1766*4882a593Smuzhiyun 		goto fail;
1767*4882a593Smuzhiyun 
1768*4882a593Smuzhiyun 	dev_dbg(&priv->client->dev,
1769*4882a593Smuzhiyun 		"%s : register HMAX = %d\n", __func__, hmax);
1770*4882a593Smuzhiyun 
1771*4882a593Smuzhiyun 	if (hmax == 0 || frame_interval.denominator == 0) {
1772*4882a593Smuzhiyun 		err = -EINVAL;
1773*4882a593Smuzhiyun 		goto fail;
1774*4882a593Smuzhiyun 	}
1775*4882a593Smuzhiyun 
1776*4882a593Smuzhiyun 	frame_length = IMX274_PIXCLK_CONST1 / (svr + 1) / hmax
1777*4882a593Smuzhiyun 					* frame_interval.numerator
1778*4882a593Smuzhiyun 					/ frame_interval.denominator;
1779*4882a593Smuzhiyun 
1780*4882a593Smuzhiyun 	err = imx274_set_frame_length(priv, frame_length);
1781*4882a593Smuzhiyun 	if (err)
1782*4882a593Smuzhiyun 		goto fail;
1783*4882a593Smuzhiyun 
1784*4882a593Smuzhiyun 	priv->frame_interval = frame_interval;
1785*4882a593Smuzhiyun 	return 0;
1786*4882a593Smuzhiyun 
1787*4882a593Smuzhiyun fail:
1788*4882a593Smuzhiyun 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
1789*4882a593Smuzhiyun 	return err;
1790*4882a593Smuzhiyun }
1791*4882a593Smuzhiyun 
1792*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops imx274_pad_ops = {
1793*4882a593Smuzhiyun 	.get_fmt = imx274_get_fmt,
1794*4882a593Smuzhiyun 	.set_fmt = imx274_set_fmt,
1795*4882a593Smuzhiyun 	.get_selection = imx274_get_selection,
1796*4882a593Smuzhiyun 	.set_selection = imx274_set_selection,
1797*4882a593Smuzhiyun };
1798*4882a593Smuzhiyun 
1799*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops imx274_video_ops = {
1800*4882a593Smuzhiyun 	.g_frame_interval = imx274_g_frame_interval,
1801*4882a593Smuzhiyun 	.s_frame_interval = imx274_s_frame_interval,
1802*4882a593Smuzhiyun 	.s_stream = imx274_s_stream,
1803*4882a593Smuzhiyun };
1804*4882a593Smuzhiyun 
1805*4882a593Smuzhiyun static const struct v4l2_subdev_ops imx274_subdev_ops = {
1806*4882a593Smuzhiyun 	.pad = &imx274_pad_ops,
1807*4882a593Smuzhiyun 	.video = &imx274_video_ops,
1808*4882a593Smuzhiyun };
1809*4882a593Smuzhiyun 
1810*4882a593Smuzhiyun static const struct v4l2_ctrl_ops imx274_ctrl_ops = {
1811*4882a593Smuzhiyun 	.s_ctrl	= imx274_s_ctrl,
1812*4882a593Smuzhiyun };
1813*4882a593Smuzhiyun 
1814*4882a593Smuzhiyun static const struct of_device_id imx274_of_id_table[] = {
1815*4882a593Smuzhiyun 	{ .compatible = "sony,imx274" },
1816*4882a593Smuzhiyun 	{ }
1817*4882a593Smuzhiyun };
1818*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, imx274_of_id_table);
1819*4882a593Smuzhiyun 
1820*4882a593Smuzhiyun static const struct i2c_device_id imx274_id[] = {
1821*4882a593Smuzhiyun 	{ "IMX274", 0 },
1822*4882a593Smuzhiyun 	{ }
1823*4882a593Smuzhiyun };
1824*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, imx274_id);
1825*4882a593Smuzhiyun 
imx274_probe(struct i2c_client * client)1826*4882a593Smuzhiyun static int imx274_probe(struct i2c_client *client)
1827*4882a593Smuzhiyun {
1828*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
1829*4882a593Smuzhiyun 	struct stimx274 *imx274;
1830*4882a593Smuzhiyun 	int ret;
1831*4882a593Smuzhiyun 
1832*4882a593Smuzhiyun 	/* initialize imx274 */
1833*4882a593Smuzhiyun 	imx274 = devm_kzalloc(&client->dev, sizeof(*imx274), GFP_KERNEL);
1834*4882a593Smuzhiyun 	if (!imx274)
1835*4882a593Smuzhiyun 		return -ENOMEM;
1836*4882a593Smuzhiyun 
1837*4882a593Smuzhiyun 	mutex_init(&imx274->lock);
1838*4882a593Smuzhiyun 
1839*4882a593Smuzhiyun 	/* initialize format */
1840*4882a593Smuzhiyun 	imx274->mode = &imx274_modes[IMX274_DEFAULT_BINNING];
1841*4882a593Smuzhiyun 	imx274->crop.width = IMX274_MAX_WIDTH;
1842*4882a593Smuzhiyun 	imx274->crop.height = IMX274_MAX_HEIGHT;
1843*4882a593Smuzhiyun 	imx274->format.width = imx274->crop.width / imx274->mode->bin_ratio;
1844*4882a593Smuzhiyun 	imx274->format.height = imx274->crop.height / imx274->mode->bin_ratio;
1845*4882a593Smuzhiyun 	imx274->format.field = V4L2_FIELD_NONE;
1846*4882a593Smuzhiyun 	imx274->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
1847*4882a593Smuzhiyun 	imx274->format.colorspace = V4L2_COLORSPACE_SRGB;
1848*4882a593Smuzhiyun 	imx274->frame_interval.numerator = 1;
1849*4882a593Smuzhiyun 	imx274->frame_interval.denominator = IMX274_DEF_FRAME_RATE;
1850*4882a593Smuzhiyun 
1851*4882a593Smuzhiyun 	/* initialize regmap */
1852*4882a593Smuzhiyun 	imx274->regmap = devm_regmap_init_i2c(client, &imx274_regmap_config);
1853*4882a593Smuzhiyun 	if (IS_ERR(imx274->regmap)) {
1854*4882a593Smuzhiyun 		dev_err(&client->dev,
1855*4882a593Smuzhiyun 			"regmap init failed: %ld\n", PTR_ERR(imx274->regmap));
1856*4882a593Smuzhiyun 		ret = -ENODEV;
1857*4882a593Smuzhiyun 		goto err_regmap;
1858*4882a593Smuzhiyun 	}
1859*4882a593Smuzhiyun 
1860*4882a593Smuzhiyun 	/* initialize subdevice */
1861*4882a593Smuzhiyun 	imx274->client = client;
1862*4882a593Smuzhiyun 	sd = &imx274->sd;
1863*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &imx274_subdev_ops);
1864*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1865*4882a593Smuzhiyun 
1866*4882a593Smuzhiyun 	/* initialize subdev media pad */
1867*4882a593Smuzhiyun 	imx274->pad.flags = MEDIA_PAD_FL_SOURCE;
1868*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1869*4882a593Smuzhiyun 	ret = media_entity_pads_init(&sd->entity, 1, &imx274->pad);
1870*4882a593Smuzhiyun 	if (ret < 0) {
1871*4882a593Smuzhiyun 		dev_err(&client->dev,
1872*4882a593Smuzhiyun 			"%s : media entity init Failed %d\n", __func__, ret);
1873*4882a593Smuzhiyun 		goto err_regmap;
1874*4882a593Smuzhiyun 	}
1875*4882a593Smuzhiyun 
1876*4882a593Smuzhiyun 	/* initialize sensor reset gpio */
1877*4882a593Smuzhiyun 	imx274->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1878*4882a593Smuzhiyun 						     GPIOD_OUT_HIGH);
1879*4882a593Smuzhiyun 	if (IS_ERR(imx274->reset_gpio)) {
1880*4882a593Smuzhiyun 		if (PTR_ERR(imx274->reset_gpio) != -EPROBE_DEFER)
1881*4882a593Smuzhiyun 			dev_err(&client->dev, "Reset GPIO not setup in DT");
1882*4882a593Smuzhiyun 		ret = PTR_ERR(imx274->reset_gpio);
1883*4882a593Smuzhiyun 		goto err_me;
1884*4882a593Smuzhiyun 	}
1885*4882a593Smuzhiyun 
1886*4882a593Smuzhiyun 	/* pull sensor out of reset */
1887*4882a593Smuzhiyun 	imx274_reset(imx274, 1);
1888*4882a593Smuzhiyun 
1889*4882a593Smuzhiyun 	/* initialize controls */
1890*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_init(&imx274->ctrls.handler, 4);
1891*4882a593Smuzhiyun 	if (ret < 0) {
1892*4882a593Smuzhiyun 		dev_err(&client->dev,
1893*4882a593Smuzhiyun 			"%s : ctrl handler init Failed\n", __func__);
1894*4882a593Smuzhiyun 		goto err_me;
1895*4882a593Smuzhiyun 	}
1896*4882a593Smuzhiyun 
1897*4882a593Smuzhiyun 	imx274->ctrls.handler.lock = &imx274->lock;
1898*4882a593Smuzhiyun 
1899*4882a593Smuzhiyun 	/* add new controls */
1900*4882a593Smuzhiyun 	imx274->ctrls.test_pattern = v4l2_ctrl_new_std_menu_items(
1901*4882a593Smuzhiyun 		&imx274->ctrls.handler, &imx274_ctrl_ops,
1902*4882a593Smuzhiyun 		V4L2_CID_TEST_PATTERN,
1903*4882a593Smuzhiyun 		ARRAY_SIZE(tp_qmenu) - 1, 0, 0, tp_qmenu);
1904*4882a593Smuzhiyun 
1905*4882a593Smuzhiyun 	imx274->ctrls.gain = v4l2_ctrl_new_std(
1906*4882a593Smuzhiyun 		&imx274->ctrls.handler,
1907*4882a593Smuzhiyun 		&imx274_ctrl_ops,
1908*4882a593Smuzhiyun 		V4L2_CID_GAIN, IMX274_MIN_GAIN,
1909*4882a593Smuzhiyun 		IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN, 1,
1910*4882a593Smuzhiyun 		IMX274_DEF_GAIN);
1911*4882a593Smuzhiyun 
1912*4882a593Smuzhiyun 	imx274->ctrls.exposure = v4l2_ctrl_new_std(
1913*4882a593Smuzhiyun 		&imx274->ctrls.handler,
1914*4882a593Smuzhiyun 		&imx274_ctrl_ops,
1915*4882a593Smuzhiyun 		V4L2_CID_EXPOSURE, IMX274_MIN_EXPOSURE_TIME,
1916*4882a593Smuzhiyun 		1000000 / IMX274_DEF_FRAME_RATE, 1,
1917*4882a593Smuzhiyun 		IMX274_MIN_EXPOSURE_TIME);
1918*4882a593Smuzhiyun 
1919*4882a593Smuzhiyun 	imx274->ctrls.vflip = v4l2_ctrl_new_std(
1920*4882a593Smuzhiyun 		&imx274->ctrls.handler,
1921*4882a593Smuzhiyun 		&imx274_ctrl_ops,
1922*4882a593Smuzhiyun 		V4L2_CID_VFLIP, 0, 1, 1, 0);
1923*4882a593Smuzhiyun 
1924*4882a593Smuzhiyun 	imx274->sd.ctrl_handler = &imx274->ctrls.handler;
1925*4882a593Smuzhiyun 	if (imx274->ctrls.handler.error) {
1926*4882a593Smuzhiyun 		ret = imx274->ctrls.handler.error;
1927*4882a593Smuzhiyun 		goto err_ctrls;
1928*4882a593Smuzhiyun 	}
1929*4882a593Smuzhiyun 
1930*4882a593Smuzhiyun 	/* setup default controls */
1931*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_setup(&imx274->ctrls.handler);
1932*4882a593Smuzhiyun 	if (ret) {
1933*4882a593Smuzhiyun 		dev_err(&client->dev,
1934*4882a593Smuzhiyun 			"Error %d setup default controls\n", ret);
1935*4882a593Smuzhiyun 		goto err_ctrls;
1936*4882a593Smuzhiyun 	}
1937*4882a593Smuzhiyun 
1938*4882a593Smuzhiyun 	/* load default control values */
1939*4882a593Smuzhiyun 	ret = imx274_load_default(imx274);
1940*4882a593Smuzhiyun 	if (ret) {
1941*4882a593Smuzhiyun 		dev_err(&client->dev,
1942*4882a593Smuzhiyun 			"%s : imx274_load_default failed %d\n",
1943*4882a593Smuzhiyun 			__func__, ret);
1944*4882a593Smuzhiyun 		goto err_ctrls;
1945*4882a593Smuzhiyun 	}
1946*4882a593Smuzhiyun 
1947*4882a593Smuzhiyun 	/* register subdevice */
1948*4882a593Smuzhiyun 	ret = v4l2_async_register_subdev(sd);
1949*4882a593Smuzhiyun 	if (ret < 0) {
1950*4882a593Smuzhiyun 		dev_err(&client->dev,
1951*4882a593Smuzhiyun 			"%s : v4l2_async_register_subdev failed %d\n",
1952*4882a593Smuzhiyun 			__func__, ret);
1953*4882a593Smuzhiyun 		goto err_ctrls;
1954*4882a593Smuzhiyun 	}
1955*4882a593Smuzhiyun 
1956*4882a593Smuzhiyun 	dev_info(&client->dev, "imx274 : imx274 probe success !\n");
1957*4882a593Smuzhiyun 	return 0;
1958*4882a593Smuzhiyun 
1959*4882a593Smuzhiyun err_ctrls:
1960*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&imx274->ctrls.handler);
1961*4882a593Smuzhiyun err_me:
1962*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1963*4882a593Smuzhiyun err_regmap:
1964*4882a593Smuzhiyun 	mutex_destroy(&imx274->lock);
1965*4882a593Smuzhiyun 	return ret;
1966*4882a593Smuzhiyun }
1967*4882a593Smuzhiyun 
imx274_remove(struct i2c_client * client)1968*4882a593Smuzhiyun static int imx274_remove(struct i2c_client *client)
1969*4882a593Smuzhiyun {
1970*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1971*4882a593Smuzhiyun 	struct stimx274 *imx274 = to_imx274(sd);
1972*4882a593Smuzhiyun 
1973*4882a593Smuzhiyun 	/* stop stream */
1974*4882a593Smuzhiyun 	imx274_write_table(imx274, imx274_stop);
1975*4882a593Smuzhiyun 
1976*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(sd);
1977*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&imx274->ctrls.handler);
1978*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1979*4882a593Smuzhiyun 	mutex_destroy(&imx274->lock);
1980*4882a593Smuzhiyun 	return 0;
1981*4882a593Smuzhiyun }
1982*4882a593Smuzhiyun 
1983*4882a593Smuzhiyun static struct i2c_driver imx274_i2c_driver = {
1984*4882a593Smuzhiyun 	.driver = {
1985*4882a593Smuzhiyun 		.name	= DRIVER_NAME,
1986*4882a593Smuzhiyun 		.of_match_table	= imx274_of_id_table,
1987*4882a593Smuzhiyun 	},
1988*4882a593Smuzhiyun 	.probe_new	= imx274_probe,
1989*4882a593Smuzhiyun 	.remove		= imx274_remove,
1990*4882a593Smuzhiyun 	.id_table	= imx274_id,
1991*4882a593Smuzhiyun };
1992*4882a593Smuzhiyun 
1993*4882a593Smuzhiyun module_i2c_driver(imx274_i2c_driver);
1994*4882a593Smuzhiyun 
1995*4882a593Smuzhiyun MODULE_AUTHOR("Leon Luo <leonl@leopardimaging.com>");
1996*4882a593Smuzhiyun MODULE_DESCRIPTION("IMX274 CMOS Image Sensor driver");
1997*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1998