xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/imx219.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * A V4L2 driver for Sony IMX219 cameras.
4*4882a593Smuzhiyun  * Copyright (C) 2019, Raspberry Pi (Trading) Ltd
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Based on Sony imx258 camera driver
7*4882a593Smuzhiyun  * Copyright (C) 2018 Intel Corporation
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * DT / fwnode changes, and regulator / GPIO control taken from imx214 driver
10*4882a593Smuzhiyun  * Copyright 2018 Qtechnology A/S
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * Flip handling taken from the Sony IMX319 driver.
13*4882a593Smuzhiyun  * Copyright (C) 2018 Intel Corporation
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/clk.h>
18*4882a593Smuzhiyun #include <linux/delay.h>
19*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
20*4882a593Smuzhiyun #include <linux/i2c.h>
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun #include <linux/pm_runtime.h>
23*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
24*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
25*4882a593Smuzhiyun #include <media/v4l2-device.h>
26*4882a593Smuzhiyun #include <media/v4l2-event.h>
27*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
28*4882a593Smuzhiyun #include <media/v4l2-mediabus.h>
29*4882a593Smuzhiyun #include <asm/unaligned.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define IMX219_REG_VALUE_08BIT		1
32*4882a593Smuzhiyun #define IMX219_REG_VALUE_16BIT		2
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define IMX219_REG_MODE_SELECT		0x0100
35*4882a593Smuzhiyun #define IMX219_MODE_STANDBY		0x00
36*4882a593Smuzhiyun #define IMX219_MODE_STREAMING		0x01
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Chip ID */
39*4882a593Smuzhiyun #define IMX219_REG_CHIP_ID		0x0000
40*4882a593Smuzhiyun #define IMX219_CHIP_ID			0x0219
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* External clock frequency is 24.0M */
43*4882a593Smuzhiyun #define IMX219_XCLK_FREQ		24000000
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* Pixel rate is fixed at 182.4M for all the modes */
46*4882a593Smuzhiyun #define IMX219_PIXEL_RATE		182400000
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define IMX219_DEFAULT_LINK_FREQ	456000000
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /* V_TIMING internal */
51*4882a593Smuzhiyun #define IMX219_REG_VTS			0x0160
52*4882a593Smuzhiyun #define IMX219_VTS_15FPS		0x0dc6
53*4882a593Smuzhiyun #define IMX219_VTS_30FPS_1080P		0x06e3
54*4882a593Smuzhiyun #define IMX219_VTS_30FPS_BINNED		0x06e3
55*4882a593Smuzhiyun #define IMX219_VTS_30FPS_640x480	0x06e3
56*4882a593Smuzhiyun #define IMX219_VTS_MAX			0xffff
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define IMX219_VBLANK_MIN		4
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /*Frame Length Line*/
61*4882a593Smuzhiyun #define IMX219_FLL_MIN			0x08a6
62*4882a593Smuzhiyun #define IMX219_FLL_MAX			0xffff
63*4882a593Smuzhiyun #define IMX219_FLL_STEP			1
64*4882a593Smuzhiyun #define IMX219_FLL_DEFAULT		0x0c98
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /* HBLANK control - read only */
67*4882a593Smuzhiyun #define IMX219_PPL_DEFAULT		3448
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /* Exposure control */
70*4882a593Smuzhiyun #define IMX219_REG_EXPOSURE		0x015a
71*4882a593Smuzhiyun #define IMX219_EXPOSURE_MIN		4
72*4882a593Smuzhiyun #define IMX219_EXPOSURE_STEP		1
73*4882a593Smuzhiyun #define IMX219_EXPOSURE_DEFAULT		0x640
74*4882a593Smuzhiyun #define IMX219_EXPOSURE_MAX		65535
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* Analog gain control */
77*4882a593Smuzhiyun #define IMX219_REG_ANALOG_GAIN		0x0157
78*4882a593Smuzhiyun #define IMX219_ANA_GAIN_MIN		0
79*4882a593Smuzhiyun #define IMX219_ANA_GAIN_MAX		232
80*4882a593Smuzhiyun #define IMX219_ANA_GAIN_STEP		1
81*4882a593Smuzhiyun #define IMX219_ANA_GAIN_DEFAULT		0x0
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /* Digital gain control */
84*4882a593Smuzhiyun #define IMX219_REG_DIGITAL_GAIN		0x0158
85*4882a593Smuzhiyun #define IMX219_DGTL_GAIN_MIN		0x0100
86*4882a593Smuzhiyun #define IMX219_DGTL_GAIN_MAX		0x0fff
87*4882a593Smuzhiyun #define IMX219_DGTL_GAIN_DEFAULT	0x0100
88*4882a593Smuzhiyun #define IMX219_DGTL_GAIN_STEP		1
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #define IMX219_REG_ORIENTATION		0x0172
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /* Test Pattern Control */
93*4882a593Smuzhiyun #define IMX219_REG_TEST_PATTERN		0x0600
94*4882a593Smuzhiyun #define IMX219_TEST_PATTERN_DISABLE	0
95*4882a593Smuzhiyun #define IMX219_TEST_PATTERN_SOLID_COLOR	1
96*4882a593Smuzhiyun #define IMX219_TEST_PATTERN_COLOR_BARS	2
97*4882a593Smuzhiyun #define IMX219_TEST_PATTERN_GREY_COLOR	3
98*4882a593Smuzhiyun #define IMX219_TEST_PATTERN_PN9		4
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /* Test pattern colour components */
101*4882a593Smuzhiyun #define IMX219_REG_TESTP_RED		0x0602
102*4882a593Smuzhiyun #define IMX219_REG_TESTP_GREENR		0x0604
103*4882a593Smuzhiyun #define IMX219_REG_TESTP_BLUE		0x0606
104*4882a593Smuzhiyun #define IMX219_REG_TESTP_GREENB		0x0608
105*4882a593Smuzhiyun #define IMX219_TESTP_COLOUR_MIN		0
106*4882a593Smuzhiyun #define IMX219_TESTP_COLOUR_MAX		0x03ff
107*4882a593Smuzhiyun #define IMX219_TESTP_COLOUR_STEP	1
108*4882a593Smuzhiyun #define IMX219_TESTP_RED_DEFAULT	IMX219_TESTP_COLOUR_MAX
109*4882a593Smuzhiyun #define IMX219_TESTP_GREENR_DEFAULT	0
110*4882a593Smuzhiyun #define IMX219_TESTP_BLUE_DEFAULT	0
111*4882a593Smuzhiyun #define IMX219_TESTP_GREENB_DEFAULT	0
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /* IMX219 native and active pixel array size. */
114*4882a593Smuzhiyun #define IMX219_NATIVE_WIDTH		3296U
115*4882a593Smuzhiyun #define IMX219_NATIVE_HEIGHT		2480U
116*4882a593Smuzhiyun #define IMX219_PIXEL_ARRAY_LEFT		8U
117*4882a593Smuzhiyun #define IMX219_PIXEL_ARRAY_TOP		8U
118*4882a593Smuzhiyun #define IMX219_PIXEL_ARRAY_WIDTH	3280U
119*4882a593Smuzhiyun #define IMX219_PIXEL_ARRAY_HEIGHT	2464U
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun struct imx219_reg {
122*4882a593Smuzhiyun 	u16 address;
123*4882a593Smuzhiyun 	u8 val;
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun struct imx219_reg_list {
127*4882a593Smuzhiyun 	unsigned int num_of_regs;
128*4882a593Smuzhiyun 	const struct imx219_reg *regs;
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /* Mode : resolution and related config&values */
132*4882a593Smuzhiyun struct imx219_mode {
133*4882a593Smuzhiyun 	/* Frame width */
134*4882a593Smuzhiyun 	unsigned int width;
135*4882a593Smuzhiyun 	/* Frame height */
136*4882a593Smuzhiyun 	unsigned int height;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	/* Analog crop rectangle. */
139*4882a593Smuzhiyun 	struct v4l2_rect crop;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/* V-timing */
142*4882a593Smuzhiyun 	unsigned int vts_def;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	/* Default register values */
145*4882a593Smuzhiyun 	struct imx219_reg_list reg_list;
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun /*
149*4882a593Smuzhiyun  * Register sets lifted off the i2C interface from the Raspberry Pi firmware
150*4882a593Smuzhiyun  * driver.
151*4882a593Smuzhiyun  * 3280x2464 = mode 2, 1920x1080 = mode 1, 1640x1232 = mode 4, 640x480 = mode 7.
152*4882a593Smuzhiyun  */
153*4882a593Smuzhiyun static const struct imx219_reg mode_3280x2464_regs[] = {
154*4882a593Smuzhiyun 	{0x0100, 0x00},
155*4882a593Smuzhiyun 	{0x30eb, 0x0c},
156*4882a593Smuzhiyun 	{0x30eb, 0x05},
157*4882a593Smuzhiyun 	{0x300a, 0xff},
158*4882a593Smuzhiyun 	{0x300b, 0xff},
159*4882a593Smuzhiyun 	{0x30eb, 0x05},
160*4882a593Smuzhiyun 	{0x30eb, 0x09},
161*4882a593Smuzhiyun 	{0x0114, 0x01},
162*4882a593Smuzhiyun 	{0x0128, 0x00},
163*4882a593Smuzhiyun 	{0x012a, 0x18},
164*4882a593Smuzhiyun 	{0x012b, 0x00},
165*4882a593Smuzhiyun 	{0x0164, 0x00},
166*4882a593Smuzhiyun 	{0x0165, 0x00},
167*4882a593Smuzhiyun 	{0x0166, 0x0c},
168*4882a593Smuzhiyun 	{0x0167, 0xcf},
169*4882a593Smuzhiyun 	{0x0168, 0x00},
170*4882a593Smuzhiyun 	{0x0169, 0x00},
171*4882a593Smuzhiyun 	{0x016a, 0x09},
172*4882a593Smuzhiyun 	{0x016b, 0x9f},
173*4882a593Smuzhiyun 	{0x016c, 0x0c},
174*4882a593Smuzhiyun 	{0x016d, 0xd0},
175*4882a593Smuzhiyun 	{0x016e, 0x09},
176*4882a593Smuzhiyun 	{0x016f, 0xa0},
177*4882a593Smuzhiyun 	{0x0170, 0x01},
178*4882a593Smuzhiyun 	{0x0171, 0x01},
179*4882a593Smuzhiyun 	{0x0174, 0x00},
180*4882a593Smuzhiyun 	{0x0175, 0x00},
181*4882a593Smuzhiyun 	{0x0301, 0x05},
182*4882a593Smuzhiyun 	{0x0303, 0x01},
183*4882a593Smuzhiyun 	{0x0304, 0x03},
184*4882a593Smuzhiyun 	{0x0305, 0x03},
185*4882a593Smuzhiyun 	{0x0306, 0x00},
186*4882a593Smuzhiyun 	{0x0307, 0x39},
187*4882a593Smuzhiyun 	{0x030b, 0x01},
188*4882a593Smuzhiyun 	{0x030c, 0x00},
189*4882a593Smuzhiyun 	{0x030d, 0x72},
190*4882a593Smuzhiyun 	{0x0624, 0x0c},
191*4882a593Smuzhiyun 	{0x0625, 0xd0},
192*4882a593Smuzhiyun 	{0x0626, 0x09},
193*4882a593Smuzhiyun 	{0x0627, 0xa0},
194*4882a593Smuzhiyun 	{0x455e, 0x00},
195*4882a593Smuzhiyun 	{0x471e, 0x4b},
196*4882a593Smuzhiyun 	{0x4767, 0x0f},
197*4882a593Smuzhiyun 	{0x4750, 0x14},
198*4882a593Smuzhiyun 	{0x4540, 0x00},
199*4882a593Smuzhiyun 	{0x47b4, 0x14},
200*4882a593Smuzhiyun 	{0x4713, 0x30},
201*4882a593Smuzhiyun 	{0x478b, 0x10},
202*4882a593Smuzhiyun 	{0x478f, 0x10},
203*4882a593Smuzhiyun 	{0x4793, 0x10},
204*4882a593Smuzhiyun 	{0x4797, 0x0e},
205*4882a593Smuzhiyun 	{0x479b, 0x0e},
206*4882a593Smuzhiyun 	{0x0162, 0x0d},
207*4882a593Smuzhiyun 	{0x0163, 0x78},
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun static const struct imx219_reg mode_1920_1080_regs[] = {
211*4882a593Smuzhiyun 	{0x0100, 0x00},
212*4882a593Smuzhiyun 	{0x30eb, 0x05},
213*4882a593Smuzhiyun 	{0x30eb, 0x0c},
214*4882a593Smuzhiyun 	{0x300a, 0xff},
215*4882a593Smuzhiyun 	{0x300b, 0xff},
216*4882a593Smuzhiyun 	{0x30eb, 0x05},
217*4882a593Smuzhiyun 	{0x30eb, 0x09},
218*4882a593Smuzhiyun 	{0x0114, 0x01},
219*4882a593Smuzhiyun 	{0x0128, 0x00},
220*4882a593Smuzhiyun 	{0x012a, 0x18},
221*4882a593Smuzhiyun 	{0x012b, 0x00},
222*4882a593Smuzhiyun 	{0x0162, 0x0d},
223*4882a593Smuzhiyun 	{0x0163, 0x78},
224*4882a593Smuzhiyun 	{0x0164, 0x02},
225*4882a593Smuzhiyun 	{0x0165, 0xa8},
226*4882a593Smuzhiyun 	{0x0166, 0x0a},
227*4882a593Smuzhiyun 	{0x0167, 0x27},
228*4882a593Smuzhiyun 	{0x0168, 0x02},
229*4882a593Smuzhiyun 	{0x0169, 0xb4},
230*4882a593Smuzhiyun 	{0x016a, 0x06},
231*4882a593Smuzhiyun 	{0x016b, 0xeb},
232*4882a593Smuzhiyun 	{0x016c, 0x07},
233*4882a593Smuzhiyun 	{0x016d, 0x80},
234*4882a593Smuzhiyun 	{0x016e, 0x04},
235*4882a593Smuzhiyun 	{0x016f, 0x38},
236*4882a593Smuzhiyun 	{0x0170, 0x01},
237*4882a593Smuzhiyun 	{0x0171, 0x01},
238*4882a593Smuzhiyun 	{0x0174, 0x00},
239*4882a593Smuzhiyun 	{0x0175, 0x00},
240*4882a593Smuzhiyun 	{0x0301, 0x05},
241*4882a593Smuzhiyun 	{0x0303, 0x01},
242*4882a593Smuzhiyun 	{0x0304, 0x03},
243*4882a593Smuzhiyun 	{0x0305, 0x03},
244*4882a593Smuzhiyun 	{0x0306, 0x00},
245*4882a593Smuzhiyun 	{0x0307, 0x39},
246*4882a593Smuzhiyun 	{0x030b, 0x01},
247*4882a593Smuzhiyun 	{0x030c, 0x00},
248*4882a593Smuzhiyun 	{0x030d, 0x72},
249*4882a593Smuzhiyun 	{0x0624, 0x07},
250*4882a593Smuzhiyun 	{0x0625, 0x80},
251*4882a593Smuzhiyun 	{0x0626, 0x04},
252*4882a593Smuzhiyun 	{0x0627, 0x38},
253*4882a593Smuzhiyun 	{0x455e, 0x00},
254*4882a593Smuzhiyun 	{0x471e, 0x4b},
255*4882a593Smuzhiyun 	{0x4767, 0x0f},
256*4882a593Smuzhiyun 	{0x4750, 0x14},
257*4882a593Smuzhiyun 	{0x4540, 0x00},
258*4882a593Smuzhiyun 	{0x47b4, 0x14},
259*4882a593Smuzhiyun 	{0x4713, 0x30},
260*4882a593Smuzhiyun 	{0x478b, 0x10},
261*4882a593Smuzhiyun 	{0x478f, 0x10},
262*4882a593Smuzhiyun 	{0x4793, 0x10},
263*4882a593Smuzhiyun 	{0x4797, 0x0e},
264*4882a593Smuzhiyun 	{0x479b, 0x0e},
265*4882a593Smuzhiyun 	{0x0162, 0x0d},
266*4882a593Smuzhiyun 	{0x0163, 0x78},
267*4882a593Smuzhiyun };
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun static const struct imx219_reg mode_1640_1232_regs[] = {
270*4882a593Smuzhiyun 	{0x0100, 0x00},
271*4882a593Smuzhiyun 	{0x30eb, 0x0c},
272*4882a593Smuzhiyun 	{0x30eb, 0x05},
273*4882a593Smuzhiyun 	{0x300a, 0xff},
274*4882a593Smuzhiyun 	{0x300b, 0xff},
275*4882a593Smuzhiyun 	{0x30eb, 0x05},
276*4882a593Smuzhiyun 	{0x30eb, 0x09},
277*4882a593Smuzhiyun 	{0x0114, 0x01},
278*4882a593Smuzhiyun 	{0x0128, 0x00},
279*4882a593Smuzhiyun 	{0x012a, 0x18},
280*4882a593Smuzhiyun 	{0x012b, 0x00},
281*4882a593Smuzhiyun 	{0x0164, 0x00},
282*4882a593Smuzhiyun 	{0x0165, 0x00},
283*4882a593Smuzhiyun 	{0x0166, 0x0c},
284*4882a593Smuzhiyun 	{0x0167, 0xcf},
285*4882a593Smuzhiyun 	{0x0168, 0x00},
286*4882a593Smuzhiyun 	{0x0169, 0x00},
287*4882a593Smuzhiyun 	{0x016a, 0x09},
288*4882a593Smuzhiyun 	{0x016b, 0x9f},
289*4882a593Smuzhiyun 	{0x016c, 0x06},
290*4882a593Smuzhiyun 	{0x016d, 0x68},
291*4882a593Smuzhiyun 	{0x016e, 0x04},
292*4882a593Smuzhiyun 	{0x016f, 0xd0},
293*4882a593Smuzhiyun 	{0x0170, 0x01},
294*4882a593Smuzhiyun 	{0x0171, 0x01},
295*4882a593Smuzhiyun 	{0x0174, 0x01},
296*4882a593Smuzhiyun 	{0x0175, 0x01},
297*4882a593Smuzhiyun 	{0x0301, 0x05},
298*4882a593Smuzhiyun 	{0x0303, 0x01},
299*4882a593Smuzhiyun 	{0x0304, 0x03},
300*4882a593Smuzhiyun 	{0x0305, 0x03},
301*4882a593Smuzhiyun 	{0x0306, 0x00},
302*4882a593Smuzhiyun 	{0x0307, 0x39},
303*4882a593Smuzhiyun 	{0x030b, 0x01},
304*4882a593Smuzhiyun 	{0x030c, 0x00},
305*4882a593Smuzhiyun 	{0x030d, 0x72},
306*4882a593Smuzhiyun 	{0x0624, 0x06},
307*4882a593Smuzhiyun 	{0x0625, 0x68},
308*4882a593Smuzhiyun 	{0x0626, 0x04},
309*4882a593Smuzhiyun 	{0x0627, 0xd0},
310*4882a593Smuzhiyun 	{0x455e, 0x00},
311*4882a593Smuzhiyun 	{0x471e, 0x4b},
312*4882a593Smuzhiyun 	{0x4767, 0x0f},
313*4882a593Smuzhiyun 	{0x4750, 0x14},
314*4882a593Smuzhiyun 	{0x4540, 0x00},
315*4882a593Smuzhiyun 	{0x47b4, 0x14},
316*4882a593Smuzhiyun 	{0x4713, 0x30},
317*4882a593Smuzhiyun 	{0x478b, 0x10},
318*4882a593Smuzhiyun 	{0x478f, 0x10},
319*4882a593Smuzhiyun 	{0x4793, 0x10},
320*4882a593Smuzhiyun 	{0x4797, 0x0e},
321*4882a593Smuzhiyun 	{0x479b, 0x0e},
322*4882a593Smuzhiyun 	{0x0162, 0x0d},
323*4882a593Smuzhiyun 	{0x0163, 0x78},
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun static const struct imx219_reg mode_640_480_regs[] = {
327*4882a593Smuzhiyun 	{0x0100, 0x00},
328*4882a593Smuzhiyun 	{0x30eb, 0x05},
329*4882a593Smuzhiyun 	{0x30eb, 0x0c},
330*4882a593Smuzhiyun 	{0x300a, 0xff},
331*4882a593Smuzhiyun 	{0x300b, 0xff},
332*4882a593Smuzhiyun 	{0x30eb, 0x05},
333*4882a593Smuzhiyun 	{0x30eb, 0x09},
334*4882a593Smuzhiyun 	{0x0114, 0x01},
335*4882a593Smuzhiyun 	{0x0128, 0x00},
336*4882a593Smuzhiyun 	{0x012a, 0x18},
337*4882a593Smuzhiyun 	{0x012b, 0x00},
338*4882a593Smuzhiyun 	{0x0162, 0x0d},
339*4882a593Smuzhiyun 	{0x0163, 0x78},
340*4882a593Smuzhiyun 	{0x0164, 0x03},
341*4882a593Smuzhiyun 	{0x0165, 0xe8},
342*4882a593Smuzhiyun 	{0x0166, 0x08},
343*4882a593Smuzhiyun 	{0x0167, 0xe7},
344*4882a593Smuzhiyun 	{0x0168, 0x02},
345*4882a593Smuzhiyun 	{0x0169, 0xf0},
346*4882a593Smuzhiyun 	{0x016a, 0x06},
347*4882a593Smuzhiyun 	{0x016b, 0xaf},
348*4882a593Smuzhiyun 	{0x016c, 0x02},
349*4882a593Smuzhiyun 	{0x016d, 0x80},
350*4882a593Smuzhiyun 	{0x016e, 0x01},
351*4882a593Smuzhiyun 	{0x016f, 0xe0},
352*4882a593Smuzhiyun 	{0x0170, 0x01},
353*4882a593Smuzhiyun 	{0x0171, 0x01},
354*4882a593Smuzhiyun 	{0x0174, 0x03},
355*4882a593Smuzhiyun 	{0x0175, 0x03},
356*4882a593Smuzhiyun 	{0x0301, 0x05},
357*4882a593Smuzhiyun 	{0x0303, 0x01},
358*4882a593Smuzhiyun 	{0x0304, 0x03},
359*4882a593Smuzhiyun 	{0x0305, 0x03},
360*4882a593Smuzhiyun 	{0x0306, 0x00},
361*4882a593Smuzhiyun 	{0x0307, 0x39},
362*4882a593Smuzhiyun 	{0x030b, 0x01},
363*4882a593Smuzhiyun 	{0x030c, 0x00},
364*4882a593Smuzhiyun 	{0x030d, 0x72},
365*4882a593Smuzhiyun 	{0x0624, 0x06},
366*4882a593Smuzhiyun 	{0x0625, 0x68},
367*4882a593Smuzhiyun 	{0x0626, 0x04},
368*4882a593Smuzhiyun 	{0x0627, 0xd0},
369*4882a593Smuzhiyun 	{0x455e, 0x00},
370*4882a593Smuzhiyun 	{0x471e, 0x4b},
371*4882a593Smuzhiyun 	{0x4767, 0x0f},
372*4882a593Smuzhiyun 	{0x4750, 0x14},
373*4882a593Smuzhiyun 	{0x4540, 0x00},
374*4882a593Smuzhiyun 	{0x47b4, 0x14},
375*4882a593Smuzhiyun 	{0x4713, 0x30},
376*4882a593Smuzhiyun 	{0x478b, 0x10},
377*4882a593Smuzhiyun 	{0x478f, 0x10},
378*4882a593Smuzhiyun 	{0x4793, 0x10},
379*4882a593Smuzhiyun 	{0x4797, 0x0e},
380*4882a593Smuzhiyun 	{0x479b, 0x0e},
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun static const struct imx219_reg raw8_framefmt_regs[] = {
384*4882a593Smuzhiyun 	{0x018c, 0x08},
385*4882a593Smuzhiyun 	{0x018d, 0x08},
386*4882a593Smuzhiyun 	{0x0309, 0x08},
387*4882a593Smuzhiyun };
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun static const struct imx219_reg raw10_framefmt_regs[] = {
390*4882a593Smuzhiyun 	{0x018c, 0x0a},
391*4882a593Smuzhiyun 	{0x018d, 0x0a},
392*4882a593Smuzhiyun 	{0x0309, 0x0a},
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun static const char * const imx219_test_pattern_menu[] = {
396*4882a593Smuzhiyun 	"Disabled",
397*4882a593Smuzhiyun 	"Color Bars",
398*4882a593Smuzhiyun 	"Solid Color",
399*4882a593Smuzhiyun 	"Grey Color Bars",
400*4882a593Smuzhiyun 	"PN9"
401*4882a593Smuzhiyun };
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun static const int imx219_test_pattern_val[] = {
404*4882a593Smuzhiyun 	IMX219_TEST_PATTERN_DISABLE,
405*4882a593Smuzhiyun 	IMX219_TEST_PATTERN_COLOR_BARS,
406*4882a593Smuzhiyun 	IMX219_TEST_PATTERN_SOLID_COLOR,
407*4882a593Smuzhiyun 	IMX219_TEST_PATTERN_GREY_COLOR,
408*4882a593Smuzhiyun 	IMX219_TEST_PATTERN_PN9,
409*4882a593Smuzhiyun };
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun /* regulator supplies */
412*4882a593Smuzhiyun static const char * const imx219_supply_name[] = {
413*4882a593Smuzhiyun 	/* Supplies can be enabled in any order */
414*4882a593Smuzhiyun 	"VANA",  /* Analog (2.8V) supply */
415*4882a593Smuzhiyun 	"VDIG",  /* Digital Core (1.8V) supply */
416*4882a593Smuzhiyun 	"VDDL",  /* IF (1.2V) supply */
417*4882a593Smuzhiyun };
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun #define IMX219_NUM_SUPPLIES ARRAY_SIZE(imx219_supply_name)
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun /*
422*4882a593Smuzhiyun  * The supported formats.
423*4882a593Smuzhiyun  * This table MUST contain 4 entries per format, to cover the various flip
424*4882a593Smuzhiyun  * combinations in the order
425*4882a593Smuzhiyun  * - no flip
426*4882a593Smuzhiyun  * - h flip
427*4882a593Smuzhiyun  * - v flip
428*4882a593Smuzhiyun  * - h&v flips
429*4882a593Smuzhiyun  */
430*4882a593Smuzhiyun static const u32 codes[] = {
431*4882a593Smuzhiyun 	MEDIA_BUS_FMT_SRGGB10_1X10,
432*4882a593Smuzhiyun 	MEDIA_BUS_FMT_SGRBG10_1X10,
433*4882a593Smuzhiyun 	MEDIA_BUS_FMT_SGBRG10_1X10,
434*4882a593Smuzhiyun 	MEDIA_BUS_FMT_SBGGR10_1X10,
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	MEDIA_BUS_FMT_SRGGB8_1X8,
437*4882a593Smuzhiyun 	MEDIA_BUS_FMT_SGRBG8_1X8,
438*4882a593Smuzhiyun 	MEDIA_BUS_FMT_SGBRG8_1X8,
439*4882a593Smuzhiyun 	MEDIA_BUS_FMT_SBGGR8_1X8,
440*4882a593Smuzhiyun };
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun /*
443*4882a593Smuzhiyun  * Initialisation delay between XCLR low->high and the moment when the sensor
444*4882a593Smuzhiyun  * can start capture (i.e. can leave software stanby) must be not less than:
445*4882a593Smuzhiyun  *   t4 + max(t5, t6 + <time to initialize the sensor register over I2C>)
446*4882a593Smuzhiyun  * where
447*4882a593Smuzhiyun  *   t4 is fixed, and is max 200uS,
448*4882a593Smuzhiyun  *   t5 is fixed, and is 6000uS,
449*4882a593Smuzhiyun  *   t6 depends on the sensor external clock, and is max 32000 clock periods.
450*4882a593Smuzhiyun  * As per sensor datasheet, the external clock must be from 6MHz to 27MHz.
451*4882a593Smuzhiyun  * So for any acceptable external clock t6 is always within the range of
452*4882a593Smuzhiyun  * 1185 to 5333 uS, and is always less than t5.
453*4882a593Smuzhiyun  * For this reason this is always safe to wait (t4 + t5) = 6200 uS, then
454*4882a593Smuzhiyun  * initialize the sensor over I2C, and then exit the software standby.
455*4882a593Smuzhiyun  *
456*4882a593Smuzhiyun  * This start-up time can be optimized a bit more, if we start the writes
457*4882a593Smuzhiyun  * over I2C after (t4+t6), but before (t4+t5) expires. But then sensor
458*4882a593Smuzhiyun  * initialization over I2C may complete before (t4+t5) expires, and we must
459*4882a593Smuzhiyun  * ensure that capture is not started before (t4+t5).
460*4882a593Smuzhiyun  *
461*4882a593Smuzhiyun  * This delay doesn't account for the power supply startup time. If needed,
462*4882a593Smuzhiyun  * this should be taken care of via the regulator framework. E.g. in the
463*4882a593Smuzhiyun  * case of DT for regulator-fixed one should define the startup-delay-us
464*4882a593Smuzhiyun  * property.
465*4882a593Smuzhiyun  */
466*4882a593Smuzhiyun #define IMX219_XCLR_MIN_DELAY_US	6200
467*4882a593Smuzhiyun #define IMX219_XCLR_DELAY_RANGE_US	1000
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun /* Mode configs */
470*4882a593Smuzhiyun static const struct imx219_mode supported_modes[] = {
471*4882a593Smuzhiyun 	{
472*4882a593Smuzhiyun 		/* 8MPix 15fps mode */
473*4882a593Smuzhiyun 		.width = 3280,
474*4882a593Smuzhiyun 		.height = 2464,
475*4882a593Smuzhiyun 		.crop = {
476*4882a593Smuzhiyun 			.left = IMX219_PIXEL_ARRAY_LEFT,
477*4882a593Smuzhiyun 			.top = IMX219_PIXEL_ARRAY_TOP,
478*4882a593Smuzhiyun 			.width = 3280,
479*4882a593Smuzhiyun 			.height = 2464
480*4882a593Smuzhiyun 		},
481*4882a593Smuzhiyun 		.vts_def = IMX219_VTS_15FPS,
482*4882a593Smuzhiyun 		.reg_list = {
483*4882a593Smuzhiyun 			.num_of_regs = ARRAY_SIZE(mode_3280x2464_regs),
484*4882a593Smuzhiyun 			.regs = mode_3280x2464_regs,
485*4882a593Smuzhiyun 		},
486*4882a593Smuzhiyun 	},
487*4882a593Smuzhiyun 	{
488*4882a593Smuzhiyun 		/* 1080P 30fps cropped */
489*4882a593Smuzhiyun 		.width = 1920,
490*4882a593Smuzhiyun 		.height = 1080,
491*4882a593Smuzhiyun 		.crop = {
492*4882a593Smuzhiyun 			.left = 688,
493*4882a593Smuzhiyun 			.top = 700,
494*4882a593Smuzhiyun 			.width = 1920,
495*4882a593Smuzhiyun 			.height = 1080
496*4882a593Smuzhiyun 		},
497*4882a593Smuzhiyun 		.vts_def = IMX219_VTS_30FPS_1080P,
498*4882a593Smuzhiyun 		.reg_list = {
499*4882a593Smuzhiyun 			.num_of_regs = ARRAY_SIZE(mode_1920_1080_regs),
500*4882a593Smuzhiyun 			.regs = mode_1920_1080_regs,
501*4882a593Smuzhiyun 		},
502*4882a593Smuzhiyun 	},
503*4882a593Smuzhiyun 	{
504*4882a593Smuzhiyun 		/* 2x2 binned 30fps mode */
505*4882a593Smuzhiyun 		.width = 1640,
506*4882a593Smuzhiyun 		.height = 1232,
507*4882a593Smuzhiyun 		.crop = {
508*4882a593Smuzhiyun 			.left = IMX219_PIXEL_ARRAY_LEFT,
509*4882a593Smuzhiyun 			.top = IMX219_PIXEL_ARRAY_TOP,
510*4882a593Smuzhiyun 			.width = 3280,
511*4882a593Smuzhiyun 			.height = 2464
512*4882a593Smuzhiyun 		},
513*4882a593Smuzhiyun 		.vts_def = IMX219_VTS_30FPS_BINNED,
514*4882a593Smuzhiyun 		.reg_list = {
515*4882a593Smuzhiyun 			.num_of_regs = ARRAY_SIZE(mode_1640_1232_regs),
516*4882a593Smuzhiyun 			.regs = mode_1640_1232_regs,
517*4882a593Smuzhiyun 		},
518*4882a593Smuzhiyun 	},
519*4882a593Smuzhiyun 	{
520*4882a593Smuzhiyun 		/* 640x480 30fps mode */
521*4882a593Smuzhiyun 		.width = 640,
522*4882a593Smuzhiyun 		.height = 480,
523*4882a593Smuzhiyun 		.crop = {
524*4882a593Smuzhiyun 			.left = 1008,
525*4882a593Smuzhiyun 			.top = 760,
526*4882a593Smuzhiyun 			.width = 1280,
527*4882a593Smuzhiyun 			.height = 960
528*4882a593Smuzhiyun 		},
529*4882a593Smuzhiyun 		.vts_def = IMX219_VTS_30FPS_640x480,
530*4882a593Smuzhiyun 		.reg_list = {
531*4882a593Smuzhiyun 			.num_of_regs = ARRAY_SIZE(mode_640_480_regs),
532*4882a593Smuzhiyun 			.regs = mode_640_480_regs,
533*4882a593Smuzhiyun 		},
534*4882a593Smuzhiyun 	},
535*4882a593Smuzhiyun };
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun struct imx219 {
538*4882a593Smuzhiyun 	struct v4l2_subdev sd;
539*4882a593Smuzhiyun 	struct media_pad pad;
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt fmt;
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	struct clk *xclk; /* system clock to IMX219 */
544*4882a593Smuzhiyun 	u32 xclk_freq;
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
547*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[IMX219_NUM_SUPPLIES];
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	struct v4l2_ctrl_handler ctrl_handler;
550*4882a593Smuzhiyun 	/* V4L2 Controls */
551*4882a593Smuzhiyun 	struct v4l2_ctrl *pixel_rate;
552*4882a593Smuzhiyun 	struct v4l2_ctrl *exposure;
553*4882a593Smuzhiyun 	struct v4l2_ctrl *vflip;
554*4882a593Smuzhiyun 	struct v4l2_ctrl *hflip;
555*4882a593Smuzhiyun 	struct v4l2_ctrl *vblank;
556*4882a593Smuzhiyun 	struct v4l2_ctrl *hblank;
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	/* Current mode */
559*4882a593Smuzhiyun 	const struct imx219_mode *mode;
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	/*
562*4882a593Smuzhiyun 	 * Mutex for serialized access:
563*4882a593Smuzhiyun 	 * Protect sensor module set pad format and start/stop streaming safely.
564*4882a593Smuzhiyun 	 */
565*4882a593Smuzhiyun 	struct mutex mutex;
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	/* Streaming on/off */
568*4882a593Smuzhiyun 	bool streaming;
569*4882a593Smuzhiyun };
570*4882a593Smuzhiyun 
to_imx219(struct v4l2_subdev * _sd)571*4882a593Smuzhiyun static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd)
572*4882a593Smuzhiyun {
573*4882a593Smuzhiyun 	return container_of(_sd, struct imx219, sd);
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun /* Read registers up to 2 at a time */
imx219_read_reg(struct imx219 * imx219,u16 reg,u32 len,u32 * val)577*4882a593Smuzhiyun static int imx219_read_reg(struct imx219 *imx219, u16 reg, u32 len, u32 *val)
578*4882a593Smuzhiyun {
579*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
580*4882a593Smuzhiyun 	struct i2c_msg msgs[2];
581*4882a593Smuzhiyun 	u8 addr_buf[2] = { reg >> 8, reg & 0xff };
582*4882a593Smuzhiyun 	u8 data_buf[4] = { 0, };
583*4882a593Smuzhiyun 	int ret;
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	if (len > 4)
586*4882a593Smuzhiyun 		return -EINVAL;
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	/* Write register address */
589*4882a593Smuzhiyun 	msgs[0].addr = client->addr;
590*4882a593Smuzhiyun 	msgs[0].flags = 0;
591*4882a593Smuzhiyun 	msgs[0].len = ARRAY_SIZE(addr_buf);
592*4882a593Smuzhiyun 	msgs[0].buf = addr_buf;
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	/* Read data from register */
595*4882a593Smuzhiyun 	msgs[1].addr = client->addr;
596*4882a593Smuzhiyun 	msgs[1].flags = I2C_M_RD;
597*4882a593Smuzhiyun 	msgs[1].len = len;
598*4882a593Smuzhiyun 	msgs[1].buf = &data_buf[4 - len];
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
601*4882a593Smuzhiyun 	if (ret != ARRAY_SIZE(msgs))
602*4882a593Smuzhiyun 		return -EIO;
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 	*val = get_unaligned_be32(data_buf);
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	return 0;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun /* Write registers up to 2 at a time */
imx219_write_reg(struct imx219 * imx219,u16 reg,u32 len,u32 val)610*4882a593Smuzhiyun static int imx219_write_reg(struct imx219 *imx219, u16 reg, u32 len, u32 val)
611*4882a593Smuzhiyun {
612*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
613*4882a593Smuzhiyun 	u8 buf[6];
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	if (len > 4)
616*4882a593Smuzhiyun 		return -EINVAL;
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	put_unaligned_be16(reg, buf);
619*4882a593Smuzhiyun 	put_unaligned_be32(val << (8 * (4 - len)), buf + 2);
620*4882a593Smuzhiyun 	if (i2c_master_send(client, buf, len + 2) != len + 2)
621*4882a593Smuzhiyun 		return -EIO;
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	return 0;
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun /* Write a list of registers */
imx219_write_regs(struct imx219 * imx219,const struct imx219_reg * regs,u32 len)627*4882a593Smuzhiyun static int imx219_write_regs(struct imx219 *imx219,
628*4882a593Smuzhiyun 			     const struct imx219_reg *regs, u32 len)
629*4882a593Smuzhiyun {
630*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
631*4882a593Smuzhiyun 	unsigned int i;
632*4882a593Smuzhiyun 	int ret;
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	for (i = 0; i < len; i++) {
635*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, regs[i].address, 1, regs[i].val);
636*4882a593Smuzhiyun 		if (ret) {
637*4882a593Smuzhiyun 			dev_err_ratelimited(&client->dev,
638*4882a593Smuzhiyun 					    "Failed to write reg 0x%4.4x. error = %d\n",
639*4882a593Smuzhiyun 					    regs[i].address, ret);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 			return ret;
642*4882a593Smuzhiyun 		}
643*4882a593Smuzhiyun 	}
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	return 0;
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun /* Get bayer order based on flip setting. */
imx219_get_format_code(struct imx219 * imx219,u32 code)649*4882a593Smuzhiyun static u32 imx219_get_format_code(struct imx219 *imx219, u32 code)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun 	unsigned int i;
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	lockdep_assert_held(&imx219->mutex);
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(codes); i++)
656*4882a593Smuzhiyun 		if (codes[i] == code)
657*4882a593Smuzhiyun 			break;
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	if (i >= ARRAY_SIZE(codes))
660*4882a593Smuzhiyun 		i = 0;
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun 	i = (i & ~3) | (imx219->vflip->val ? 2 : 0) |
663*4882a593Smuzhiyun 	    (imx219->hflip->val ? 1 : 0);
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	return codes[i];
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun 
imx219_set_default_format(struct imx219 * imx219)668*4882a593Smuzhiyun static void imx219_set_default_format(struct imx219 *imx219)
669*4882a593Smuzhiyun {
670*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *fmt;
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun 	fmt = &imx219->fmt;
673*4882a593Smuzhiyun 	fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
674*4882a593Smuzhiyun 	fmt->colorspace = V4L2_COLORSPACE_SRGB;
675*4882a593Smuzhiyun 	fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
676*4882a593Smuzhiyun 	fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
677*4882a593Smuzhiyun 							  fmt->colorspace,
678*4882a593Smuzhiyun 							  fmt->ycbcr_enc);
679*4882a593Smuzhiyun 	fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
680*4882a593Smuzhiyun 	fmt->width = supported_modes[0].width;
681*4882a593Smuzhiyun 	fmt->height = supported_modes[0].height;
682*4882a593Smuzhiyun 	fmt->field = V4L2_FIELD_NONE;
683*4882a593Smuzhiyun }
684*4882a593Smuzhiyun 
imx219_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)685*4882a593Smuzhiyun static int imx219_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
686*4882a593Smuzhiyun {
687*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
688*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *try_fmt =
689*4882a593Smuzhiyun 		v4l2_subdev_get_try_format(sd, fh->pad, 0);
690*4882a593Smuzhiyun 	struct v4l2_rect *try_crop;
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun 	mutex_lock(&imx219->mutex);
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	/* Initialize try_fmt */
695*4882a593Smuzhiyun 	try_fmt->width = supported_modes[0].width;
696*4882a593Smuzhiyun 	try_fmt->height = supported_modes[0].height;
697*4882a593Smuzhiyun 	try_fmt->code = imx219_get_format_code(imx219,
698*4882a593Smuzhiyun 					       MEDIA_BUS_FMT_SRGGB10_1X10);
699*4882a593Smuzhiyun 	try_fmt->field = V4L2_FIELD_NONE;
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun 	/* Initialize try_crop rectangle. */
702*4882a593Smuzhiyun 	try_crop = v4l2_subdev_get_try_crop(sd, fh->pad, 0);
703*4882a593Smuzhiyun 	try_crop->top = IMX219_PIXEL_ARRAY_TOP;
704*4882a593Smuzhiyun 	try_crop->left = IMX219_PIXEL_ARRAY_LEFT;
705*4882a593Smuzhiyun 	try_crop->width = IMX219_PIXEL_ARRAY_WIDTH;
706*4882a593Smuzhiyun 	try_crop->height = IMX219_PIXEL_ARRAY_HEIGHT;
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 	mutex_unlock(&imx219->mutex);
709*4882a593Smuzhiyun 
710*4882a593Smuzhiyun 	return 0;
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun 
imx219_set_ctrl(struct v4l2_ctrl * ctrl)713*4882a593Smuzhiyun static int imx219_set_ctrl(struct v4l2_ctrl *ctrl)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun 	struct imx219 *imx219 =
716*4882a593Smuzhiyun 		container_of(ctrl->handler, struct imx219, ctrl_handler);
717*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
718*4882a593Smuzhiyun 	int ret;
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun 	if (ctrl->id == V4L2_CID_VBLANK) {
721*4882a593Smuzhiyun 		int exposure_max, exposure_def;
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 		/* Update max exposure while meeting expected vblanking */
724*4882a593Smuzhiyun 		exposure_max = imx219->mode->height + ctrl->val - 4;
725*4882a593Smuzhiyun 		exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
726*4882a593Smuzhiyun 			exposure_max : IMX219_EXPOSURE_DEFAULT;
727*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(imx219->exposure,
728*4882a593Smuzhiyun 					 imx219->exposure->minimum,
729*4882a593Smuzhiyun 					 exposure_max, imx219->exposure->step,
730*4882a593Smuzhiyun 					 exposure_def);
731*4882a593Smuzhiyun 	}
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	/*
734*4882a593Smuzhiyun 	 * Applying V4L2 control value only happens
735*4882a593Smuzhiyun 	 * when power is up for streaming
736*4882a593Smuzhiyun 	 */
737*4882a593Smuzhiyun 	if (pm_runtime_get_if_in_use(&client->dev) == 0)
738*4882a593Smuzhiyun 		return 0;
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	switch (ctrl->id) {
741*4882a593Smuzhiyun 	case V4L2_CID_ANALOGUE_GAIN:
742*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, IMX219_REG_ANALOG_GAIN,
743*4882a593Smuzhiyun 				       IMX219_REG_VALUE_08BIT, ctrl->val);
744*4882a593Smuzhiyun 		break;
745*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE:
746*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, IMX219_REG_EXPOSURE,
747*4882a593Smuzhiyun 				       IMX219_REG_VALUE_16BIT, ctrl->val);
748*4882a593Smuzhiyun 		break;
749*4882a593Smuzhiyun 	case V4L2_CID_DIGITAL_GAIN:
750*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, IMX219_REG_DIGITAL_GAIN,
751*4882a593Smuzhiyun 				       IMX219_REG_VALUE_16BIT, ctrl->val);
752*4882a593Smuzhiyun 		break;
753*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN:
754*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, IMX219_REG_TEST_PATTERN,
755*4882a593Smuzhiyun 				       IMX219_REG_VALUE_16BIT,
756*4882a593Smuzhiyun 				       imx219_test_pattern_val[ctrl->val]);
757*4882a593Smuzhiyun 		break;
758*4882a593Smuzhiyun 	case V4L2_CID_HFLIP:
759*4882a593Smuzhiyun 	case V4L2_CID_VFLIP:
760*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, IMX219_REG_ORIENTATION, 1,
761*4882a593Smuzhiyun 				       imx219->hflip->val |
762*4882a593Smuzhiyun 				       imx219->vflip->val << 1);
763*4882a593Smuzhiyun 		break;
764*4882a593Smuzhiyun 	case V4L2_CID_VBLANK:
765*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, IMX219_REG_VTS,
766*4882a593Smuzhiyun 				       IMX219_REG_VALUE_16BIT,
767*4882a593Smuzhiyun 				       imx219->mode->height + ctrl->val);
768*4882a593Smuzhiyun 		break;
769*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN_RED:
770*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, IMX219_REG_TESTP_RED,
771*4882a593Smuzhiyun 				       IMX219_REG_VALUE_16BIT, ctrl->val);
772*4882a593Smuzhiyun 		break;
773*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN_GREENR:
774*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, IMX219_REG_TESTP_GREENR,
775*4882a593Smuzhiyun 				       IMX219_REG_VALUE_16BIT, ctrl->val);
776*4882a593Smuzhiyun 		break;
777*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN_BLUE:
778*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, IMX219_REG_TESTP_BLUE,
779*4882a593Smuzhiyun 				       IMX219_REG_VALUE_16BIT, ctrl->val);
780*4882a593Smuzhiyun 		break;
781*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN_GREENB:
782*4882a593Smuzhiyun 		ret = imx219_write_reg(imx219, IMX219_REG_TESTP_GREENB,
783*4882a593Smuzhiyun 				       IMX219_REG_VALUE_16BIT, ctrl->val);
784*4882a593Smuzhiyun 		break;
785*4882a593Smuzhiyun 	default:
786*4882a593Smuzhiyun 		dev_info(&client->dev,
787*4882a593Smuzhiyun 			 "ctrl(id:0x%x,val:0x%x) is not handled\n",
788*4882a593Smuzhiyun 			 ctrl->id, ctrl->val);
789*4882a593Smuzhiyun 		ret = -EINVAL;
790*4882a593Smuzhiyun 		break;
791*4882a593Smuzhiyun 	}
792*4882a593Smuzhiyun 
793*4882a593Smuzhiyun 	pm_runtime_put(&client->dev);
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 	return ret;
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun static const struct v4l2_ctrl_ops imx219_ctrl_ops = {
799*4882a593Smuzhiyun 	.s_ctrl = imx219_set_ctrl,
800*4882a593Smuzhiyun };
801*4882a593Smuzhiyun 
imx219_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)802*4882a593Smuzhiyun static int imx219_enum_mbus_code(struct v4l2_subdev *sd,
803*4882a593Smuzhiyun 				 struct v4l2_subdev_pad_config *cfg,
804*4882a593Smuzhiyun 				 struct v4l2_subdev_mbus_code_enum *code)
805*4882a593Smuzhiyun {
806*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
807*4882a593Smuzhiyun 
808*4882a593Smuzhiyun 	if (code->index >= (ARRAY_SIZE(codes) / 4))
809*4882a593Smuzhiyun 		return -EINVAL;
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun 	code->code = imx219_get_format_code(imx219, codes[code->index * 4]);
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun 	return 0;
814*4882a593Smuzhiyun }
815*4882a593Smuzhiyun 
imx219_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)816*4882a593Smuzhiyun static int imx219_enum_frame_size(struct v4l2_subdev *sd,
817*4882a593Smuzhiyun 				  struct v4l2_subdev_pad_config *cfg,
818*4882a593Smuzhiyun 				  struct v4l2_subdev_frame_size_enum *fse)
819*4882a593Smuzhiyun {
820*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	if (fse->index >= ARRAY_SIZE(supported_modes))
823*4882a593Smuzhiyun 		return -EINVAL;
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun 	if (fse->code != imx219_get_format_code(imx219, fse->code))
826*4882a593Smuzhiyun 		return -EINVAL;
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun 	fse->min_width = supported_modes[fse->index].width;
829*4882a593Smuzhiyun 	fse->max_width = fse->min_width;
830*4882a593Smuzhiyun 	fse->min_height = supported_modes[fse->index].height;
831*4882a593Smuzhiyun 	fse->max_height = fse->min_height;
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 	return 0;
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun 
imx219_reset_colorspace(struct v4l2_mbus_framefmt * fmt)836*4882a593Smuzhiyun static void imx219_reset_colorspace(struct v4l2_mbus_framefmt *fmt)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun 	fmt->colorspace = V4L2_COLORSPACE_SRGB;
839*4882a593Smuzhiyun 	fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
840*4882a593Smuzhiyun 	fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
841*4882a593Smuzhiyun 							  fmt->colorspace,
842*4882a593Smuzhiyun 							  fmt->ycbcr_enc);
843*4882a593Smuzhiyun 	fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun 
imx219_update_pad_format(struct imx219 * imx219,const struct imx219_mode * mode,struct v4l2_subdev_format * fmt)846*4882a593Smuzhiyun static void imx219_update_pad_format(struct imx219 *imx219,
847*4882a593Smuzhiyun 				     const struct imx219_mode *mode,
848*4882a593Smuzhiyun 				     struct v4l2_subdev_format *fmt)
849*4882a593Smuzhiyun {
850*4882a593Smuzhiyun 	fmt->format.width = mode->width;
851*4882a593Smuzhiyun 	fmt->format.height = mode->height;
852*4882a593Smuzhiyun 	fmt->format.field = V4L2_FIELD_NONE;
853*4882a593Smuzhiyun 	imx219_reset_colorspace(&fmt->format);
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun 
__imx219_get_pad_format(struct imx219 * imx219,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)856*4882a593Smuzhiyun static int __imx219_get_pad_format(struct imx219 *imx219,
857*4882a593Smuzhiyun 				   struct v4l2_subdev_pad_config *cfg,
858*4882a593Smuzhiyun 				   struct v4l2_subdev_format *fmt)
859*4882a593Smuzhiyun {
860*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
861*4882a593Smuzhiyun 		struct v4l2_mbus_framefmt *try_fmt =
862*4882a593Smuzhiyun 			v4l2_subdev_get_try_format(&imx219->sd, cfg, fmt->pad);
863*4882a593Smuzhiyun 		/* update the code which could change due to vflip or hflip: */
864*4882a593Smuzhiyun 		try_fmt->code = imx219_get_format_code(imx219, try_fmt->code);
865*4882a593Smuzhiyun 		fmt->format = *try_fmt;
866*4882a593Smuzhiyun 	} else {
867*4882a593Smuzhiyun 		imx219_update_pad_format(imx219, imx219->mode, fmt);
868*4882a593Smuzhiyun 		fmt->format.code = imx219_get_format_code(imx219,
869*4882a593Smuzhiyun 							  imx219->fmt.code);
870*4882a593Smuzhiyun 	}
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun 	return 0;
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun 
imx219_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)875*4882a593Smuzhiyun static int imx219_get_pad_format(struct v4l2_subdev *sd,
876*4882a593Smuzhiyun 				 struct v4l2_subdev_pad_config *cfg,
877*4882a593Smuzhiyun 				 struct v4l2_subdev_format *fmt)
878*4882a593Smuzhiyun {
879*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
880*4882a593Smuzhiyun 	int ret;
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	mutex_lock(&imx219->mutex);
883*4882a593Smuzhiyun 	ret = __imx219_get_pad_format(imx219, cfg, fmt);
884*4882a593Smuzhiyun 	mutex_unlock(&imx219->mutex);
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun 	return ret;
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun 
imx219_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)889*4882a593Smuzhiyun static int imx219_set_pad_format(struct v4l2_subdev *sd,
890*4882a593Smuzhiyun 				 struct v4l2_subdev_pad_config *cfg,
891*4882a593Smuzhiyun 				 struct v4l2_subdev_format *fmt)
892*4882a593Smuzhiyun {
893*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
894*4882a593Smuzhiyun 	const struct imx219_mode *mode;
895*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *framefmt;
896*4882a593Smuzhiyun 	int exposure_max, exposure_def, hblank;
897*4882a593Smuzhiyun 	unsigned int i;
898*4882a593Smuzhiyun 
899*4882a593Smuzhiyun 	mutex_lock(&imx219->mutex);
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(codes); i++)
902*4882a593Smuzhiyun 		if (codes[i] == fmt->format.code)
903*4882a593Smuzhiyun 			break;
904*4882a593Smuzhiyun 	if (i >= ARRAY_SIZE(codes))
905*4882a593Smuzhiyun 		i = 0;
906*4882a593Smuzhiyun 
907*4882a593Smuzhiyun 	/* Bayer order varies with flips */
908*4882a593Smuzhiyun 	fmt->format.code = imx219_get_format_code(imx219, codes[i]);
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun 	mode = v4l2_find_nearest_size(supported_modes,
911*4882a593Smuzhiyun 				      ARRAY_SIZE(supported_modes),
912*4882a593Smuzhiyun 				      width, height,
913*4882a593Smuzhiyun 				      fmt->format.width, fmt->format.height);
914*4882a593Smuzhiyun 	imx219_update_pad_format(imx219, mode, fmt);
915*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
916*4882a593Smuzhiyun 		framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
917*4882a593Smuzhiyun 		*framefmt = fmt->format;
918*4882a593Smuzhiyun 	} else if (imx219->mode != mode ||
919*4882a593Smuzhiyun 		   imx219->fmt.code != fmt->format.code) {
920*4882a593Smuzhiyun 		imx219->fmt = fmt->format;
921*4882a593Smuzhiyun 		imx219->mode = mode;
922*4882a593Smuzhiyun 		/* Update limits and set FPS to default */
923*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN,
924*4882a593Smuzhiyun 					 IMX219_VTS_MAX - mode->height, 1,
925*4882a593Smuzhiyun 					 mode->vts_def - mode->height);
926*4882a593Smuzhiyun 		__v4l2_ctrl_s_ctrl(imx219->vblank,
927*4882a593Smuzhiyun 				   mode->vts_def - mode->height);
928*4882a593Smuzhiyun 		/* Update max exposure while meeting expected vblanking */
929*4882a593Smuzhiyun 		exposure_max = mode->vts_def - 4;
930*4882a593Smuzhiyun 		exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
931*4882a593Smuzhiyun 			exposure_max : IMX219_EXPOSURE_DEFAULT;
932*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(imx219->exposure,
933*4882a593Smuzhiyun 					 imx219->exposure->minimum,
934*4882a593Smuzhiyun 					 exposure_max, imx219->exposure->step,
935*4882a593Smuzhiyun 					 exposure_def);
936*4882a593Smuzhiyun 		/*
937*4882a593Smuzhiyun 		 * Currently PPL is fixed to IMX219_PPL_DEFAULT, so hblank
938*4882a593Smuzhiyun 		 * depends on mode->width only, and is not changeble in any
939*4882a593Smuzhiyun 		 * way other than changing the mode.
940*4882a593Smuzhiyun 		 */
941*4882a593Smuzhiyun 		hblank = IMX219_PPL_DEFAULT - mode->width;
942*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1,
943*4882a593Smuzhiyun 					 hblank);
944*4882a593Smuzhiyun 	}
945*4882a593Smuzhiyun 
946*4882a593Smuzhiyun 	mutex_unlock(&imx219->mutex);
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun 	return 0;
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun 
imx219_set_framefmt(struct imx219 * imx219)951*4882a593Smuzhiyun static int imx219_set_framefmt(struct imx219 *imx219)
952*4882a593Smuzhiyun {
953*4882a593Smuzhiyun 	switch (imx219->fmt.code) {
954*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SRGGB8_1X8:
955*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SGRBG8_1X8:
956*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SGBRG8_1X8:
957*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SBGGR8_1X8:
958*4882a593Smuzhiyun 		return imx219_write_regs(imx219, raw8_framefmt_regs,
959*4882a593Smuzhiyun 					ARRAY_SIZE(raw8_framefmt_regs));
960*4882a593Smuzhiyun 
961*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SRGGB10_1X10:
962*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SGRBG10_1X10:
963*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SGBRG10_1X10:
964*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SBGGR10_1X10:
965*4882a593Smuzhiyun 		return imx219_write_regs(imx219, raw10_framefmt_regs,
966*4882a593Smuzhiyun 					ARRAY_SIZE(raw10_framefmt_regs));
967*4882a593Smuzhiyun 	}
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun 	return -EINVAL;
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun 
972*4882a593Smuzhiyun static const struct v4l2_rect *
__imx219_get_pad_crop(struct imx219 * imx219,struct v4l2_subdev_pad_config * cfg,unsigned int pad,enum v4l2_subdev_format_whence which)973*4882a593Smuzhiyun __imx219_get_pad_crop(struct imx219 *imx219, struct v4l2_subdev_pad_config *cfg,
974*4882a593Smuzhiyun 		      unsigned int pad, enum v4l2_subdev_format_whence which)
975*4882a593Smuzhiyun {
976*4882a593Smuzhiyun 	switch (which) {
977*4882a593Smuzhiyun 	case V4L2_SUBDEV_FORMAT_TRY:
978*4882a593Smuzhiyun 		return v4l2_subdev_get_try_crop(&imx219->sd, cfg, pad);
979*4882a593Smuzhiyun 	case V4L2_SUBDEV_FORMAT_ACTIVE:
980*4882a593Smuzhiyun 		return &imx219->mode->crop;
981*4882a593Smuzhiyun 	}
982*4882a593Smuzhiyun 
983*4882a593Smuzhiyun 	return NULL;
984*4882a593Smuzhiyun }
985*4882a593Smuzhiyun 
imx219_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)986*4882a593Smuzhiyun static int imx219_get_selection(struct v4l2_subdev *sd,
987*4882a593Smuzhiyun 				struct v4l2_subdev_pad_config *cfg,
988*4882a593Smuzhiyun 				struct v4l2_subdev_selection *sel)
989*4882a593Smuzhiyun {
990*4882a593Smuzhiyun 	switch (sel->target) {
991*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP: {
992*4882a593Smuzhiyun 		struct imx219 *imx219 = to_imx219(sd);
993*4882a593Smuzhiyun 
994*4882a593Smuzhiyun 		mutex_lock(&imx219->mutex);
995*4882a593Smuzhiyun 		sel->r = *__imx219_get_pad_crop(imx219, cfg, sel->pad,
996*4882a593Smuzhiyun 						sel->which);
997*4882a593Smuzhiyun 		mutex_unlock(&imx219->mutex);
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun 		return 0;
1000*4882a593Smuzhiyun 	}
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 	case V4L2_SEL_TGT_NATIVE_SIZE:
1003*4882a593Smuzhiyun 		sel->r.top = 0;
1004*4882a593Smuzhiyun 		sel->r.left = 0;
1005*4882a593Smuzhiyun 		sel->r.width = IMX219_NATIVE_WIDTH;
1006*4882a593Smuzhiyun 		sel->r.height = IMX219_NATIVE_HEIGHT;
1007*4882a593Smuzhiyun 
1008*4882a593Smuzhiyun 		return 0;
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP_DEFAULT:
1011*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP_BOUNDS:
1012*4882a593Smuzhiyun 		sel->r.top = IMX219_PIXEL_ARRAY_TOP;
1013*4882a593Smuzhiyun 		sel->r.left = IMX219_PIXEL_ARRAY_LEFT;
1014*4882a593Smuzhiyun 		sel->r.width = IMX219_PIXEL_ARRAY_WIDTH;
1015*4882a593Smuzhiyun 		sel->r.height = IMX219_PIXEL_ARRAY_HEIGHT;
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun 		return 0;
1018*4882a593Smuzhiyun 	}
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun 	return -EINVAL;
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun 
imx219_start_streaming(struct imx219 * imx219)1023*4882a593Smuzhiyun static int imx219_start_streaming(struct imx219 *imx219)
1024*4882a593Smuzhiyun {
1025*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1026*4882a593Smuzhiyun 	const struct imx219_reg_list *reg_list;
1027*4882a593Smuzhiyun 	int ret;
1028*4882a593Smuzhiyun 
1029*4882a593Smuzhiyun 	ret = pm_runtime_get_sync(&client->dev);
1030*4882a593Smuzhiyun 	if (ret < 0) {
1031*4882a593Smuzhiyun 		pm_runtime_put_noidle(&client->dev);
1032*4882a593Smuzhiyun 		return ret;
1033*4882a593Smuzhiyun 	}
1034*4882a593Smuzhiyun 
1035*4882a593Smuzhiyun 	/* Apply default values of current mode */
1036*4882a593Smuzhiyun 	reg_list = &imx219->mode->reg_list;
1037*4882a593Smuzhiyun 	ret = imx219_write_regs(imx219, reg_list->regs, reg_list->num_of_regs);
1038*4882a593Smuzhiyun 	if (ret) {
1039*4882a593Smuzhiyun 		dev_err(&client->dev, "%s failed to set mode\n", __func__);
1040*4882a593Smuzhiyun 		goto err_rpm_put;
1041*4882a593Smuzhiyun 	}
1042*4882a593Smuzhiyun 
1043*4882a593Smuzhiyun 	ret = imx219_set_framefmt(imx219);
1044*4882a593Smuzhiyun 	if (ret) {
1045*4882a593Smuzhiyun 		dev_err(&client->dev, "%s failed to set frame format: %d\n",
1046*4882a593Smuzhiyun 			__func__, ret);
1047*4882a593Smuzhiyun 		goto err_rpm_put;
1048*4882a593Smuzhiyun 	}
1049*4882a593Smuzhiyun 
1050*4882a593Smuzhiyun 	/* Apply customized values from user */
1051*4882a593Smuzhiyun 	ret =  __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler);
1052*4882a593Smuzhiyun 	if (ret)
1053*4882a593Smuzhiyun 		goto err_rpm_put;
1054*4882a593Smuzhiyun 
1055*4882a593Smuzhiyun 	/* set stream on register */
1056*4882a593Smuzhiyun 	ret = imx219_write_reg(imx219, IMX219_REG_MODE_SELECT,
1057*4882a593Smuzhiyun 			       IMX219_REG_VALUE_08BIT, IMX219_MODE_STREAMING);
1058*4882a593Smuzhiyun 	if (ret)
1059*4882a593Smuzhiyun 		goto err_rpm_put;
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	/* vflip and hflip cannot change during streaming */
1062*4882a593Smuzhiyun 	__v4l2_ctrl_grab(imx219->vflip, true);
1063*4882a593Smuzhiyun 	__v4l2_ctrl_grab(imx219->hflip, true);
1064*4882a593Smuzhiyun 
1065*4882a593Smuzhiyun 	return 0;
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun err_rpm_put:
1068*4882a593Smuzhiyun 	pm_runtime_put(&client->dev);
1069*4882a593Smuzhiyun 	return ret;
1070*4882a593Smuzhiyun }
1071*4882a593Smuzhiyun 
imx219_stop_streaming(struct imx219 * imx219)1072*4882a593Smuzhiyun static void imx219_stop_streaming(struct imx219 *imx219)
1073*4882a593Smuzhiyun {
1074*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1075*4882a593Smuzhiyun 	int ret;
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 	/* set stream off register */
1078*4882a593Smuzhiyun 	ret = imx219_write_reg(imx219, IMX219_REG_MODE_SELECT,
1079*4882a593Smuzhiyun 			       IMX219_REG_VALUE_08BIT, IMX219_MODE_STANDBY);
1080*4882a593Smuzhiyun 	if (ret)
1081*4882a593Smuzhiyun 		dev_err(&client->dev, "%s failed to set stream\n", __func__);
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 	__v4l2_ctrl_grab(imx219->vflip, false);
1084*4882a593Smuzhiyun 	__v4l2_ctrl_grab(imx219->hflip, false);
1085*4882a593Smuzhiyun 
1086*4882a593Smuzhiyun 	pm_runtime_put(&client->dev);
1087*4882a593Smuzhiyun }
1088*4882a593Smuzhiyun 
imx219_set_stream(struct v4l2_subdev * sd,int enable)1089*4882a593Smuzhiyun static int imx219_set_stream(struct v4l2_subdev *sd, int enable)
1090*4882a593Smuzhiyun {
1091*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
1092*4882a593Smuzhiyun 	int ret = 0;
1093*4882a593Smuzhiyun 
1094*4882a593Smuzhiyun 	mutex_lock(&imx219->mutex);
1095*4882a593Smuzhiyun 	if (imx219->streaming == enable) {
1096*4882a593Smuzhiyun 		mutex_unlock(&imx219->mutex);
1097*4882a593Smuzhiyun 		return 0;
1098*4882a593Smuzhiyun 	}
1099*4882a593Smuzhiyun 
1100*4882a593Smuzhiyun 	if (enable) {
1101*4882a593Smuzhiyun 		/*
1102*4882a593Smuzhiyun 		 * Apply default & customized values
1103*4882a593Smuzhiyun 		 * and then start streaming.
1104*4882a593Smuzhiyun 		 */
1105*4882a593Smuzhiyun 		ret = imx219_start_streaming(imx219);
1106*4882a593Smuzhiyun 		if (ret)
1107*4882a593Smuzhiyun 			goto err_unlock;
1108*4882a593Smuzhiyun 	} else {
1109*4882a593Smuzhiyun 		imx219_stop_streaming(imx219);
1110*4882a593Smuzhiyun 	}
1111*4882a593Smuzhiyun 
1112*4882a593Smuzhiyun 	imx219->streaming = enable;
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 	mutex_unlock(&imx219->mutex);
1115*4882a593Smuzhiyun 
1116*4882a593Smuzhiyun 	return ret;
1117*4882a593Smuzhiyun 
1118*4882a593Smuzhiyun err_unlock:
1119*4882a593Smuzhiyun 	mutex_unlock(&imx219->mutex);
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 	return ret;
1122*4882a593Smuzhiyun }
1123*4882a593Smuzhiyun 
1124*4882a593Smuzhiyun /* Power/clock management functions */
imx219_power_on(struct device * dev)1125*4882a593Smuzhiyun static int imx219_power_on(struct device *dev)
1126*4882a593Smuzhiyun {
1127*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1128*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1129*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
1130*4882a593Smuzhiyun 	int ret;
1131*4882a593Smuzhiyun 
1132*4882a593Smuzhiyun 	ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES,
1133*4882a593Smuzhiyun 				    imx219->supplies);
1134*4882a593Smuzhiyun 	if (ret) {
1135*4882a593Smuzhiyun 		dev_err(&client->dev, "%s: failed to enable regulators\n",
1136*4882a593Smuzhiyun 			__func__);
1137*4882a593Smuzhiyun 		return ret;
1138*4882a593Smuzhiyun 	}
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun 	ret = clk_prepare_enable(imx219->xclk);
1141*4882a593Smuzhiyun 	if (ret) {
1142*4882a593Smuzhiyun 		dev_err(&client->dev, "%s: failed to enable clock\n",
1143*4882a593Smuzhiyun 			__func__);
1144*4882a593Smuzhiyun 		goto reg_off;
1145*4882a593Smuzhiyun 	}
1146*4882a593Smuzhiyun 
1147*4882a593Smuzhiyun 	gpiod_set_value_cansleep(imx219->reset_gpio, 1);
1148*4882a593Smuzhiyun 	usleep_range(IMX219_XCLR_MIN_DELAY_US,
1149*4882a593Smuzhiyun 		     IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US);
1150*4882a593Smuzhiyun 
1151*4882a593Smuzhiyun 	return 0;
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun reg_off:
1154*4882a593Smuzhiyun 	regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
1155*4882a593Smuzhiyun 
1156*4882a593Smuzhiyun 	return ret;
1157*4882a593Smuzhiyun }
1158*4882a593Smuzhiyun 
imx219_power_off(struct device * dev)1159*4882a593Smuzhiyun static int imx219_power_off(struct device *dev)
1160*4882a593Smuzhiyun {
1161*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1162*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1163*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
1164*4882a593Smuzhiyun 
1165*4882a593Smuzhiyun 	gpiod_set_value_cansleep(imx219->reset_gpio, 0);
1166*4882a593Smuzhiyun 	regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
1167*4882a593Smuzhiyun 	clk_disable_unprepare(imx219->xclk);
1168*4882a593Smuzhiyun 
1169*4882a593Smuzhiyun 	return 0;
1170*4882a593Smuzhiyun }
1171*4882a593Smuzhiyun 
imx219_suspend(struct device * dev)1172*4882a593Smuzhiyun static int __maybe_unused imx219_suspend(struct device *dev)
1173*4882a593Smuzhiyun {
1174*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1175*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1176*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
1177*4882a593Smuzhiyun 
1178*4882a593Smuzhiyun 	if (imx219->streaming)
1179*4882a593Smuzhiyun 		imx219_stop_streaming(imx219);
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun 	return 0;
1182*4882a593Smuzhiyun }
1183*4882a593Smuzhiyun 
imx219_resume(struct device * dev)1184*4882a593Smuzhiyun static int __maybe_unused imx219_resume(struct device *dev)
1185*4882a593Smuzhiyun {
1186*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1187*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1188*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
1189*4882a593Smuzhiyun 	int ret;
1190*4882a593Smuzhiyun 
1191*4882a593Smuzhiyun 	if (imx219->streaming) {
1192*4882a593Smuzhiyun 		ret = imx219_start_streaming(imx219);
1193*4882a593Smuzhiyun 		if (ret)
1194*4882a593Smuzhiyun 			goto error;
1195*4882a593Smuzhiyun 	}
1196*4882a593Smuzhiyun 
1197*4882a593Smuzhiyun 	return 0;
1198*4882a593Smuzhiyun 
1199*4882a593Smuzhiyun error:
1200*4882a593Smuzhiyun 	imx219_stop_streaming(imx219);
1201*4882a593Smuzhiyun 	imx219->streaming = false;
1202*4882a593Smuzhiyun 
1203*4882a593Smuzhiyun 	return ret;
1204*4882a593Smuzhiyun }
1205*4882a593Smuzhiyun 
imx219_get_regulators(struct imx219 * imx219)1206*4882a593Smuzhiyun static int imx219_get_regulators(struct imx219 *imx219)
1207*4882a593Smuzhiyun {
1208*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1209*4882a593Smuzhiyun 	unsigned int i;
1210*4882a593Smuzhiyun 
1211*4882a593Smuzhiyun 	for (i = 0; i < IMX219_NUM_SUPPLIES; i++)
1212*4882a593Smuzhiyun 		imx219->supplies[i].supply = imx219_supply_name[i];
1213*4882a593Smuzhiyun 
1214*4882a593Smuzhiyun 	return devm_regulator_bulk_get(&client->dev,
1215*4882a593Smuzhiyun 				       IMX219_NUM_SUPPLIES,
1216*4882a593Smuzhiyun 				       imx219->supplies);
1217*4882a593Smuzhiyun }
1218*4882a593Smuzhiyun 
1219*4882a593Smuzhiyun /* Verify chip ID */
imx219_identify_module(struct imx219 * imx219)1220*4882a593Smuzhiyun static int imx219_identify_module(struct imx219 *imx219)
1221*4882a593Smuzhiyun {
1222*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1223*4882a593Smuzhiyun 	int ret;
1224*4882a593Smuzhiyun 	u32 val;
1225*4882a593Smuzhiyun 
1226*4882a593Smuzhiyun 	ret = imx219_read_reg(imx219, IMX219_REG_CHIP_ID,
1227*4882a593Smuzhiyun 			      IMX219_REG_VALUE_16BIT, &val);
1228*4882a593Smuzhiyun 	if (ret) {
1229*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to read chip id %x\n",
1230*4882a593Smuzhiyun 			IMX219_CHIP_ID);
1231*4882a593Smuzhiyun 		return ret;
1232*4882a593Smuzhiyun 	}
1233*4882a593Smuzhiyun 
1234*4882a593Smuzhiyun 	if (val != IMX219_CHIP_ID) {
1235*4882a593Smuzhiyun 		dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1236*4882a593Smuzhiyun 			IMX219_CHIP_ID, val);
1237*4882a593Smuzhiyun 		return -EIO;
1238*4882a593Smuzhiyun 	}
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun 	return 0;
1241*4882a593Smuzhiyun }
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops imx219_core_ops = {
1244*4882a593Smuzhiyun 	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1245*4882a593Smuzhiyun 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
1246*4882a593Smuzhiyun };
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops imx219_video_ops = {
1249*4882a593Smuzhiyun 	.s_stream = imx219_set_stream,
1250*4882a593Smuzhiyun };
1251*4882a593Smuzhiyun 
1252*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops imx219_pad_ops = {
1253*4882a593Smuzhiyun 	.enum_mbus_code = imx219_enum_mbus_code,
1254*4882a593Smuzhiyun 	.get_fmt = imx219_get_pad_format,
1255*4882a593Smuzhiyun 	.set_fmt = imx219_set_pad_format,
1256*4882a593Smuzhiyun 	.get_selection = imx219_get_selection,
1257*4882a593Smuzhiyun 	.enum_frame_size = imx219_enum_frame_size,
1258*4882a593Smuzhiyun };
1259*4882a593Smuzhiyun 
1260*4882a593Smuzhiyun static const struct v4l2_subdev_ops imx219_subdev_ops = {
1261*4882a593Smuzhiyun 	.core = &imx219_core_ops,
1262*4882a593Smuzhiyun 	.video = &imx219_video_ops,
1263*4882a593Smuzhiyun 	.pad = &imx219_pad_ops,
1264*4882a593Smuzhiyun };
1265*4882a593Smuzhiyun 
1266*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops imx219_internal_ops = {
1267*4882a593Smuzhiyun 	.open = imx219_open,
1268*4882a593Smuzhiyun };
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun /* Initialize control handlers */
imx219_init_controls(struct imx219 * imx219)1271*4882a593Smuzhiyun static int imx219_init_controls(struct imx219 *imx219)
1272*4882a593Smuzhiyun {
1273*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1274*4882a593Smuzhiyun 	struct v4l2_ctrl_handler *ctrl_hdlr;
1275*4882a593Smuzhiyun 	unsigned int height = imx219->mode->height;
1276*4882a593Smuzhiyun 	struct v4l2_fwnode_device_properties props;
1277*4882a593Smuzhiyun 	int exposure_max, exposure_def, hblank;
1278*4882a593Smuzhiyun 	int i, ret;
1279*4882a593Smuzhiyun 
1280*4882a593Smuzhiyun 	ctrl_hdlr = &imx219->ctrl_handler;
1281*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_init(ctrl_hdlr, 11);
1282*4882a593Smuzhiyun 	if (ret)
1283*4882a593Smuzhiyun 		return ret;
1284*4882a593Smuzhiyun 
1285*4882a593Smuzhiyun 	mutex_init(&imx219->mutex);
1286*4882a593Smuzhiyun 	ctrl_hdlr->lock = &imx219->mutex;
1287*4882a593Smuzhiyun 
1288*4882a593Smuzhiyun 	/* By default, PIXEL_RATE is read only */
1289*4882a593Smuzhiyun 	imx219->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
1290*4882a593Smuzhiyun 					       V4L2_CID_PIXEL_RATE,
1291*4882a593Smuzhiyun 					       IMX219_PIXEL_RATE,
1292*4882a593Smuzhiyun 					       IMX219_PIXEL_RATE, 1,
1293*4882a593Smuzhiyun 					       IMX219_PIXEL_RATE);
1294*4882a593Smuzhiyun 
1295*4882a593Smuzhiyun 	/* Initial vblank/hblank/exposure parameters based on current mode */
1296*4882a593Smuzhiyun 	imx219->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
1297*4882a593Smuzhiyun 					   V4L2_CID_VBLANK, IMX219_VBLANK_MIN,
1298*4882a593Smuzhiyun 					   IMX219_VTS_MAX - height, 1,
1299*4882a593Smuzhiyun 					   imx219->mode->vts_def - height);
1300*4882a593Smuzhiyun 	hblank = IMX219_PPL_DEFAULT - imx219->mode->width;
1301*4882a593Smuzhiyun 	imx219->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
1302*4882a593Smuzhiyun 					   V4L2_CID_HBLANK, hblank, hblank,
1303*4882a593Smuzhiyun 					   1, hblank);
1304*4882a593Smuzhiyun 	if (imx219->hblank)
1305*4882a593Smuzhiyun 		imx219->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1306*4882a593Smuzhiyun 	exposure_max = imx219->mode->vts_def - 4;
1307*4882a593Smuzhiyun 	exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
1308*4882a593Smuzhiyun 		exposure_max : IMX219_EXPOSURE_DEFAULT;
1309*4882a593Smuzhiyun 	imx219->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
1310*4882a593Smuzhiyun 					     V4L2_CID_EXPOSURE,
1311*4882a593Smuzhiyun 					     IMX219_EXPOSURE_MIN, exposure_max,
1312*4882a593Smuzhiyun 					     IMX219_EXPOSURE_STEP,
1313*4882a593Smuzhiyun 					     exposure_def);
1314*4882a593Smuzhiyun 
1315*4882a593Smuzhiyun 	v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1316*4882a593Smuzhiyun 			  IMX219_ANA_GAIN_MIN, IMX219_ANA_GAIN_MAX,
1317*4882a593Smuzhiyun 			  IMX219_ANA_GAIN_STEP, IMX219_ANA_GAIN_DEFAULT);
1318*4882a593Smuzhiyun 
1319*4882a593Smuzhiyun 	v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1320*4882a593Smuzhiyun 			  IMX219_DGTL_GAIN_MIN, IMX219_DGTL_GAIN_MAX,
1321*4882a593Smuzhiyun 			  IMX219_DGTL_GAIN_STEP, IMX219_DGTL_GAIN_DEFAULT);
1322*4882a593Smuzhiyun 
1323*4882a593Smuzhiyun 	imx219->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
1324*4882a593Smuzhiyun 					  V4L2_CID_HFLIP, 0, 1, 1, 0);
1325*4882a593Smuzhiyun 	if (imx219->hflip)
1326*4882a593Smuzhiyun 		imx219->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
1327*4882a593Smuzhiyun 
1328*4882a593Smuzhiyun 	imx219->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
1329*4882a593Smuzhiyun 					  V4L2_CID_VFLIP, 0, 1, 1, 0);
1330*4882a593Smuzhiyun 	if (imx219->vflip)
1331*4882a593Smuzhiyun 		imx219->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
1332*4882a593Smuzhiyun 
1333*4882a593Smuzhiyun 	v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx219_ctrl_ops,
1334*4882a593Smuzhiyun 				     V4L2_CID_TEST_PATTERN,
1335*4882a593Smuzhiyun 				     ARRAY_SIZE(imx219_test_pattern_menu) - 1,
1336*4882a593Smuzhiyun 				     0, 0, imx219_test_pattern_menu);
1337*4882a593Smuzhiyun 	for (i = 0; i < 4; i++) {
1338*4882a593Smuzhiyun 		/*
1339*4882a593Smuzhiyun 		 * The assumption is that
1340*4882a593Smuzhiyun 		 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1
1341*4882a593Smuzhiyun 		 * V4L2_CID_TEST_PATTERN_BLUE   == V4L2_CID_TEST_PATTERN_RED + 2
1342*4882a593Smuzhiyun 		 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3
1343*4882a593Smuzhiyun 		 */
1344*4882a593Smuzhiyun 		v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
1345*4882a593Smuzhiyun 				  V4L2_CID_TEST_PATTERN_RED + i,
1346*4882a593Smuzhiyun 				  IMX219_TESTP_COLOUR_MIN,
1347*4882a593Smuzhiyun 				  IMX219_TESTP_COLOUR_MAX,
1348*4882a593Smuzhiyun 				  IMX219_TESTP_COLOUR_STEP,
1349*4882a593Smuzhiyun 				  IMX219_TESTP_COLOUR_MAX);
1350*4882a593Smuzhiyun 		/* The "Solid color" pattern is white by default */
1351*4882a593Smuzhiyun 	}
1352*4882a593Smuzhiyun 
1353*4882a593Smuzhiyun 	if (ctrl_hdlr->error) {
1354*4882a593Smuzhiyun 		ret = ctrl_hdlr->error;
1355*4882a593Smuzhiyun 		dev_err(&client->dev, "%s control init failed (%d)\n",
1356*4882a593Smuzhiyun 			__func__, ret);
1357*4882a593Smuzhiyun 		goto error;
1358*4882a593Smuzhiyun 	}
1359*4882a593Smuzhiyun 
1360*4882a593Smuzhiyun 	ret = v4l2_fwnode_device_parse(&client->dev, &props);
1361*4882a593Smuzhiyun 	if (ret)
1362*4882a593Smuzhiyun 		goto error;
1363*4882a593Smuzhiyun 
1364*4882a593Smuzhiyun 	ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx219_ctrl_ops,
1365*4882a593Smuzhiyun 					      &props);
1366*4882a593Smuzhiyun 	if (ret)
1367*4882a593Smuzhiyun 		goto error;
1368*4882a593Smuzhiyun 
1369*4882a593Smuzhiyun 	imx219->sd.ctrl_handler = ctrl_hdlr;
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun 	return 0;
1372*4882a593Smuzhiyun 
1373*4882a593Smuzhiyun error:
1374*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(ctrl_hdlr);
1375*4882a593Smuzhiyun 	mutex_destroy(&imx219->mutex);
1376*4882a593Smuzhiyun 
1377*4882a593Smuzhiyun 	return ret;
1378*4882a593Smuzhiyun }
1379*4882a593Smuzhiyun 
imx219_free_controls(struct imx219 * imx219)1380*4882a593Smuzhiyun static void imx219_free_controls(struct imx219 *imx219)
1381*4882a593Smuzhiyun {
1382*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(imx219->sd.ctrl_handler);
1383*4882a593Smuzhiyun 	mutex_destroy(&imx219->mutex);
1384*4882a593Smuzhiyun }
1385*4882a593Smuzhiyun 
imx219_check_hwcfg(struct device * dev)1386*4882a593Smuzhiyun static int imx219_check_hwcfg(struct device *dev)
1387*4882a593Smuzhiyun {
1388*4882a593Smuzhiyun 	struct fwnode_handle *endpoint;
1389*4882a593Smuzhiyun 	struct v4l2_fwnode_endpoint ep_cfg = {
1390*4882a593Smuzhiyun 		.bus_type = V4L2_MBUS_CSI2_DPHY
1391*4882a593Smuzhiyun 	};
1392*4882a593Smuzhiyun 	int ret = -EINVAL;
1393*4882a593Smuzhiyun 
1394*4882a593Smuzhiyun 	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1395*4882a593Smuzhiyun 	if (!endpoint) {
1396*4882a593Smuzhiyun 		dev_err(dev, "endpoint node not found\n");
1397*4882a593Smuzhiyun 		return -EINVAL;
1398*4882a593Smuzhiyun 	}
1399*4882a593Smuzhiyun 
1400*4882a593Smuzhiyun 	if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg)) {
1401*4882a593Smuzhiyun 		dev_err(dev, "could not parse endpoint\n");
1402*4882a593Smuzhiyun 		goto error_out;
1403*4882a593Smuzhiyun 	}
1404*4882a593Smuzhiyun 
1405*4882a593Smuzhiyun 	/* Check the number of MIPI CSI2 data lanes */
1406*4882a593Smuzhiyun 	if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2) {
1407*4882a593Smuzhiyun 		dev_err(dev, "only 2 data lanes are currently supported\n");
1408*4882a593Smuzhiyun 		goto error_out;
1409*4882a593Smuzhiyun 	}
1410*4882a593Smuzhiyun 
1411*4882a593Smuzhiyun 	/* Check the link frequency set in device tree */
1412*4882a593Smuzhiyun 	if (!ep_cfg.nr_of_link_frequencies) {
1413*4882a593Smuzhiyun 		dev_err(dev, "link-frequency property not found in DT\n");
1414*4882a593Smuzhiyun 		goto error_out;
1415*4882a593Smuzhiyun 	}
1416*4882a593Smuzhiyun 
1417*4882a593Smuzhiyun 	if (ep_cfg.nr_of_link_frequencies != 1 ||
1418*4882a593Smuzhiyun 	    ep_cfg.link_frequencies[0] != IMX219_DEFAULT_LINK_FREQ) {
1419*4882a593Smuzhiyun 		dev_err(dev, "Link frequency not supported: %lld\n",
1420*4882a593Smuzhiyun 			ep_cfg.link_frequencies[0]);
1421*4882a593Smuzhiyun 		goto error_out;
1422*4882a593Smuzhiyun 	}
1423*4882a593Smuzhiyun 
1424*4882a593Smuzhiyun 	ret = 0;
1425*4882a593Smuzhiyun 
1426*4882a593Smuzhiyun error_out:
1427*4882a593Smuzhiyun 	v4l2_fwnode_endpoint_free(&ep_cfg);
1428*4882a593Smuzhiyun 	fwnode_handle_put(endpoint);
1429*4882a593Smuzhiyun 
1430*4882a593Smuzhiyun 	return ret;
1431*4882a593Smuzhiyun }
1432*4882a593Smuzhiyun 
imx219_probe(struct i2c_client * client)1433*4882a593Smuzhiyun static int imx219_probe(struct i2c_client *client)
1434*4882a593Smuzhiyun {
1435*4882a593Smuzhiyun 	struct device *dev = &client->dev;
1436*4882a593Smuzhiyun 	struct imx219 *imx219;
1437*4882a593Smuzhiyun 	int ret;
1438*4882a593Smuzhiyun 
1439*4882a593Smuzhiyun 	imx219 = devm_kzalloc(&client->dev, sizeof(*imx219), GFP_KERNEL);
1440*4882a593Smuzhiyun 	if (!imx219)
1441*4882a593Smuzhiyun 		return -ENOMEM;
1442*4882a593Smuzhiyun 
1443*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(&imx219->sd, client, &imx219_subdev_ops);
1444*4882a593Smuzhiyun 
1445*4882a593Smuzhiyun 	/* Check the hardware configuration in device tree */
1446*4882a593Smuzhiyun 	if (imx219_check_hwcfg(dev))
1447*4882a593Smuzhiyun 		return -EINVAL;
1448*4882a593Smuzhiyun 
1449*4882a593Smuzhiyun 	/* Get system clock (xclk) */
1450*4882a593Smuzhiyun 	imx219->xclk = devm_clk_get(dev, NULL);
1451*4882a593Smuzhiyun 	if (IS_ERR(imx219->xclk)) {
1452*4882a593Smuzhiyun 		dev_err(dev, "failed to get xclk\n");
1453*4882a593Smuzhiyun 		return PTR_ERR(imx219->xclk);
1454*4882a593Smuzhiyun 	}
1455*4882a593Smuzhiyun 
1456*4882a593Smuzhiyun 	imx219->xclk_freq = clk_get_rate(imx219->xclk);
1457*4882a593Smuzhiyun 	if (imx219->xclk_freq != IMX219_XCLK_FREQ) {
1458*4882a593Smuzhiyun 		dev_err(dev, "xclk frequency not supported: %d Hz\n",
1459*4882a593Smuzhiyun 			imx219->xclk_freq);
1460*4882a593Smuzhiyun 		return -EINVAL;
1461*4882a593Smuzhiyun 	}
1462*4882a593Smuzhiyun 
1463*4882a593Smuzhiyun 	ret = imx219_get_regulators(imx219);
1464*4882a593Smuzhiyun 	if (ret) {
1465*4882a593Smuzhiyun 		dev_err(dev, "failed to get regulators\n");
1466*4882a593Smuzhiyun 		return ret;
1467*4882a593Smuzhiyun 	}
1468*4882a593Smuzhiyun 
1469*4882a593Smuzhiyun 	/* Request optional enable pin */
1470*4882a593Smuzhiyun 	imx219->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1471*4882a593Smuzhiyun 						     GPIOD_OUT_HIGH);
1472*4882a593Smuzhiyun 
1473*4882a593Smuzhiyun 	/*
1474*4882a593Smuzhiyun 	 * The sensor must be powered for imx219_identify_module()
1475*4882a593Smuzhiyun 	 * to be able to read the CHIP_ID register
1476*4882a593Smuzhiyun 	 */
1477*4882a593Smuzhiyun 	ret = imx219_power_on(dev);
1478*4882a593Smuzhiyun 	if (ret)
1479*4882a593Smuzhiyun 		return ret;
1480*4882a593Smuzhiyun 
1481*4882a593Smuzhiyun 	ret = imx219_identify_module(imx219);
1482*4882a593Smuzhiyun 	if (ret)
1483*4882a593Smuzhiyun 		goto error_power_off;
1484*4882a593Smuzhiyun 
1485*4882a593Smuzhiyun 	/* Set default mode to max resolution */
1486*4882a593Smuzhiyun 	imx219->mode = &supported_modes[0];
1487*4882a593Smuzhiyun 
1488*4882a593Smuzhiyun 	/* sensor doesn't enter LP-11 state upon power up until and unless
1489*4882a593Smuzhiyun 	 * streaming is started, so upon power up switch the modes to:
1490*4882a593Smuzhiyun 	 * streaming -> standby
1491*4882a593Smuzhiyun 	 */
1492*4882a593Smuzhiyun 	ret = imx219_write_reg(imx219, IMX219_REG_MODE_SELECT,
1493*4882a593Smuzhiyun 			       IMX219_REG_VALUE_08BIT, IMX219_MODE_STREAMING);
1494*4882a593Smuzhiyun 	if (ret < 0)
1495*4882a593Smuzhiyun 		goto error_power_off;
1496*4882a593Smuzhiyun 	usleep_range(100, 110);
1497*4882a593Smuzhiyun 
1498*4882a593Smuzhiyun 	/* put sensor back to standby mode */
1499*4882a593Smuzhiyun 	ret = imx219_write_reg(imx219, IMX219_REG_MODE_SELECT,
1500*4882a593Smuzhiyun 			       IMX219_REG_VALUE_08BIT, IMX219_MODE_STANDBY);
1501*4882a593Smuzhiyun 	if (ret < 0)
1502*4882a593Smuzhiyun 		goto error_power_off;
1503*4882a593Smuzhiyun 	usleep_range(100, 110);
1504*4882a593Smuzhiyun 
1505*4882a593Smuzhiyun 	ret = imx219_init_controls(imx219);
1506*4882a593Smuzhiyun 	if (ret)
1507*4882a593Smuzhiyun 		goto error_power_off;
1508*4882a593Smuzhiyun 
1509*4882a593Smuzhiyun 	/* Initialize subdev */
1510*4882a593Smuzhiyun 	imx219->sd.internal_ops = &imx219_internal_ops;
1511*4882a593Smuzhiyun 	imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1512*4882a593Smuzhiyun 	imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1513*4882a593Smuzhiyun 
1514*4882a593Smuzhiyun 	/* Initialize source pad */
1515*4882a593Smuzhiyun 	imx219->pad.flags = MEDIA_PAD_FL_SOURCE;
1516*4882a593Smuzhiyun 
1517*4882a593Smuzhiyun 	/* Initialize default format */
1518*4882a593Smuzhiyun 	imx219_set_default_format(imx219);
1519*4882a593Smuzhiyun 
1520*4882a593Smuzhiyun 	ret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad);
1521*4882a593Smuzhiyun 	if (ret) {
1522*4882a593Smuzhiyun 		dev_err(dev, "failed to init entity pads: %d\n", ret);
1523*4882a593Smuzhiyun 		goto error_handler_free;
1524*4882a593Smuzhiyun 	}
1525*4882a593Smuzhiyun 
1526*4882a593Smuzhiyun 	ret = v4l2_async_register_subdev_sensor_common(&imx219->sd);
1527*4882a593Smuzhiyun 	if (ret < 0) {
1528*4882a593Smuzhiyun 		dev_err(dev, "failed to register sensor sub-device: %d\n", ret);
1529*4882a593Smuzhiyun 		goto error_media_entity;
1530*4882a593Smuzhiyun 	}
1531*4882a593Smuzhiyun 
1532*4882a593Smuzhiyun 	/* Enable runtime PM and turn off the device */
1533*4882a593Smuzhiyun 	pm_runtime_set_active(dev);
1534*4882a593Smuzhiyun 	pm_runtime_enable(dev);
1535*4882a593Smuzhiyun 	pm_runtime_idle(dev);
1536*4882a593Smuzhiyun 
1537*4882a593Smuzhiyun 	return 0;
1538*4882a593Smuzhiyun 
1539*4882a593Smuzhiyun error_media_entity:
1540*4882a593Smuzhiyun 	media_entity_cleanup(&imx219->sd.entity);
1541*4882a593Smuzhiyun 
1542*4882a593Smuzhiyun error_handler_free:
1543*4882a593Smuzhiyun 	imx219_free_controls(imx219);
1544*4882a593Smuzhiyun 
1545*4882a593Smuzhiyun error_power_off:
1546*4882a593Smuzhiyun 	imx219_power_off(dev);
1547*4882a593Smuzhiyun 
1548*4882a593Smuzhiyun 	return ret;
1549*4882a593Smuzhiyun }
1550*4882a593Smuzhiyun 
imx219_remove(struct i2c_client * client)1551*4882a593Smuzhiyun static int imx219_remove(struct i2c_client *client)
1552*4882a593Smuzhiyun {
1553*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1554*4882a593Smuzhiyun 	struct imx219 *imx219 = to_imx219(sd);
1555*4882a593Smuzhiyun 
1556*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(sd);
1557*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1558*4882a593Smuzhiyun 	imx219_free_controls(imx219);
1559*4882a593Smuzhiyun 
1560*4882a593Smuzhiyun 	pm_runtime_disable(&client->dev);
1561*4882a593Smuzhiyun 	if (!pm_runtime_status_suspended(&client->dev))
1562*4882a593Smuzhiyun 		imx219_power_off(&client->dev);
1563*4882a593Smuzhiyun 	pm_runtime_set_suspended(&client->dev);
1564*4882a593Smuzhiyun 
1565*4882a593Smuzhiyun 	return 0;
1566*4882a593Smuzhiyun }
1567*4882a593Smuzhiyun 
1568*4882a593Smuzhiyun static const struct of_device_id imx219_dt_ids[] = {
1569*4882a593Smuzhiyun 	{ .compatible = "sony,imx219" },
1570*4882a593Smuzhiyun 	{ /* sentinel */ }
1571*4882a593Smuzhiyun };
1572*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, imx219_dt_ids);
1573*4882a593Smuzhiyun 
1574*4882a593Smuzhiyun static const struct dev_pm_ops imx219_pm_ops = {
1575*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(imx219_suspend, imx219_resume)
1576*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(imx219_power_off, imx219_power_on, NULL)
1577*4882a593Smuzhiyun };
1578*4882a593Smuzhiyun 
1579*4882a593Smuzhiyun static struct i2c_driver imx219_i2c_driver = {
1580*4882a593Smuzhiyun 	.driver = {
1581*4882a593Smuzhiyun 		.name = "imx219",
1582*4882a593Smuzhiyun 		.of_match_table	= imx219_dt_ids,
1583*4882a593Smuzhiyun 		.pm = &imx219_pm_ops,
1584*4882a593Smuzhiyun 	},
1585*4882a593Smuzhiyun 	.probe_new = imx219_probe,
1586*4882a593Smuzhiyun 	.remove = imx219_remove,
1587*4882a593Smuzhiyun };
1588*4882a593Smuzhiyun 
1589*4882a593Smuzhiyun module_i2c_driver(imx219_i2c_driver);
1590*4882a593Smuzhiyun 
1591*4882a593Smuzhiyun MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com");
1592*4882a593Smuzhiyun MODULE_DESCRIPTION("Sony IMX219 sensor driver");
1593*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1594