1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc3003 driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 first version
8 */
9
10 //#define DEBUG
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/sysfs.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
22 #include <linux/rk-camera-module.h>
23 #include <linux/rk-preisp.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/pinctrl/consumer.h>
29 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
30
31 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x07)
32
33 #ifndef V4L2_CID_DIGITAL_GAIN
34 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35 #endif
36
37 #define GC3003_LANES 2
38 #define GC3003_BITS_PER_SAMPLE 10
39 #define GC3003_LINK_FREQ_LINEAR 315000000
40
41 #define GC3003_PIXEL_RATE_LINEAR (GC3003_LINK_FREQ_LINEAR * 2 * \
42 GC3003_LANES / GC3003_BITS_PER_SAMPLE)
43 #define GC3003_XVCLK_FREQ 27000000
44
45 #define CHIP_ID 0x3003
46 #define GC3003_REG_CHIP_ID_H 0x03f0
47 #define GC3003_REG_CHIP_ID_L 0x03f1
48
49 #define GC3003_REG_CTRL_MODE 0x023e
50 #define GC3003_MODE_SW_STANDBY 0x00
51 #define GC3003_MODE_STREAMING 0x99
52
53 #define GC3003_REG_EXPOSURE_H 0x0d03
54 #define GC3003_REG_EXPOSURE_L 0x0d04
55 #define GC3003_EXPOSURE_MIN 4
56 #define GC3003_EXPOSURE_STEP 1
57 #define GC3003_VTS_MAX 0x7fff
58
59 #define GC3003_GAIN_MIN 64
60 #define GC3003_GAIN_MAX 0xffff
61 #define GC3003_GAIN_STEP 1
62 #define GC3003_GAIN_DEFAULT 64
63
64 #define GC3003_REG_TEST_PATTERN 0x018c
65 #define GC3003_TEST_PATTERN_ENABLE 0x17
66 #define GC3003_TEST_PATTERN_DISABLE 0x0
67
68 #define GC3003_REG_VTS_H 0x0d41 //0x0d0d
69 #define GC3003_REG_VTS_L 0x0d42 //0x0d0e act w: d05 d06
70
71 #define GC3003_FLIP_MIRROR_REG 0x0015
72 #define GC3003_FLIP_MIRROR_REG_1 0x0d15
73 #define GC3003_MIRROR_BIT_MASK BIT(0)
74 #define GC3003_FLIP_BIT_MASK BIT(3)
75
76 #define REG_NULL 0xFFFF
77
78 #define GC3003_REG_VALUE_08BIT 1
79 #define GC3003_REG_VALUE_16BIT 2
80 #define GC3003_REG_VALUE_24BIT 3
81
82 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
83 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
84 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
85 #define GC3003_NAME "gc3003"
86
87 static const char * const gc3003_supply_names[] = {
88 "dovdd", /* Digital I/O power */
89 "dvdd", /* Digital core power */
90 "avdd", /* Analog power */
91 };
92
93 #define GC3003_NUM_SUPPLIES ARRAY_SIZE(gc3003_supply_names)
94
95 struct regval {
96 u16 addr;
97 u8 val;
98 };
99
100 struct gc3003_mode {
101 u32 bus_fmt;
102 u32 width;
103 u32 height;
104 struct v4l2_fract max_fps;
105 u32 hts_def;
106 u32 vts_def;
107 u32 exp_def;
108 const struct regval *reg_list;
109 const struct regval *stream_on_reg_list;
110 const struct regval *stand_by_reg_list;
111 u32 hdr_mode;
112 u32 vc[PAD_MAX];
113 };
114
115 struct gc3003 {
116 struct i2c_client *client;
117 struct clk *xvclk;
118 struct gpio_desc *reset_gpio;
119 struct gpio_desc *pwdn_gpio;
120 struct gpio_desc *pwren_gpio;
121 struct regulator_bulk_data supplies[GC3003_NUM_SUPPLIES];
122
123 struct pinctrl *pinctrl;
124 struct pinctrl_state *pins_default;
125 struct pinctrl_state *pins_sleep;
126
127 struct v4l2_subdev subdev;
128 struct media_pad pad;
129 struct v4l2_ctrl_handler ctrl_handler;
130 struct v4l2_ctrl *exposure;
131 struct v4l2_ctrl *anal_gain;
132 struct v4l2_ctrl *digi_gain;
133 struct v4l2_ctrl *hblank;
134 struct v4l2_ctrl *vblank;
135 struct v4l2_ctrl *pixel_rate;
136 struct v4l2_ctrl *link_freq;
137 struct v4l2_ctrl *h_flip;
138 struct v4l2_ctrl *v_flip;
139 struct v4l2_ctrl *test_pattern;
140 struct mutex mutex;
141 bool streaming;
142 bool power_on;
143 const struct gc3003_mode *cur_mode;
144 u32 cfg_num;
145 u32 module_index;
146 u32 cur_vts;
147 u32 cur_pixel_rate;
148 u32 cur_link_freq;
149 struct preisp_hdrae_exp_s init_hdrae_exp;
150 const char *module_facing;
151 const char *module_name;
152 const char *len_name;
153 bool has_init_exp;
154 bool is_thunderboot;
155 bool is_first_streamoff;
156 };
157
158 #define to_gc3003(sd) container_of(sd, struct gc3003, subdev)
159
160 /*
161 * Xclk 24Mhz
162 */
163 static const struct regval gc3003_global_regs[] = {
164 {REG_NULL, 0x00},
165 };
166
167 static const u32 reg_val_table_liner[25][6] = {
168 {0x00, 0x00, 0x05, 0x01, 0x01, 0x00},
169 {0x0a, 0x00, 0x06, 0x01, 0x01, 0x0c},
170 {0x00, 0x01, 0x06, 0x01, 0x01, 0x1a},
171 {0x0a, 0x01, 0x08, 0x01, 0x01, 0x2a},
172 {0x20, 0x00, 0x0a, 0x02, 0x02, 0x00},
173 {0x25, 0x00, 0x0a, 0x03, 0x02, 0x18},
174 {0x20, 0x01, 0x0a, 0x04, 0x02, 0x33},
175 {0x25, 0x01, 0x0b, 0x05, 0x03, 0x14},
176 {0x30, 0x00, 0x0b, 0x06, 0x04, 0x00},
177 {0x32, 0x80, 0x0c, 0x09, 0x04, 0x2f},
178 {0x30, 0x01, 0x0c, 0x0c, 0x05, 0x26},
179 {0x32, 0x81, 0x0d, 0x0e, 0x06, 0x29},
180 {0x38, 0x00, 0x0e, 0x10, 0x08, 0x00},
181 {0x39, 0x40, 0x10, 0x12, 0x09, 0x1f},
182 {0x38, 0x01, 0x12, 0x12, 0x0b, 0x0d},
183 {0x39, 0x41, 0x14, 0x14, 0x0d, 0x12},
184 {0x30, 0x08, 0x15, 0x16, 0x10, 0x00},
185 {0x32, 0x88, 0x18, 0x1a, 0x12, 0x3e},
186 {0x30, 0x09, 0x1a, 0x1d, 0x16, 0x1a},
187 {0x32, 0x89, 0x1c, 0x22, 0x1a, 0x23},
188 {0x38, 0x08, 0x1e, 0x26, 0x20, 0x00},
189 {0x39, 0x48, 0x20, 0x2d, 0x25, 0x3b},
190 {0x38, 0x09, 0x22, 0x32, 0x2c, 0x33},
191 {0x39, 0x49, 0x24, 0x3a, 0x35, 0x06},
192 {0x38, 0x0a, 0x26, 0x42, 0x3f, 0x3f},
193 };
194
195 static const u32 gain_level_table[26] = {
196 64,
197 76,
198 90,
199 106,
200 128,
201 152,
202 179,
203 212,
204 256,
205 303,
206 358,
207 425,
208 512,
209 607,
210 716,
211 848,
212 1024,
213 1214,
214 1434,
215 1699,
216 2048,
217 2427,
218 2865,
219 3393,
220 4096,
221 0xffffffff,
222 };
223
224 /*
225 * Xclk 27Mhz
226 * max_framerate 30fps
227 * mipi_datarate per lane 630Mbps, 2lane
228 */
229 static const struct regval gc3003_linear_10_2304x1298_regs[] = {
230 {0x03fe, 0xf0},
231 {0x03fe, 0xf0},
232 {0x03fe, 0xf0},
233 {0x03fe, 0x00},
234 {0x03f3, 0x00},
235 {0x03f5, 0xc0},
236 {0x03f6, 0x06},
237 {0x03f7, 0x01},
238 {0x03f8, 0x46},
239 {0x03f9, 0x13},
240 {0x03fa, 0x00},
241 {0x03e0, 0x16},
242 {0x03e1, 0x0d},
243 {0x03e2, 0x30},
244 {0x03e4, 0x08},
245 {0x03fc, 0xce},
246 {0x0d05, 0x05},
247 {0x0d06, 0x40},
248 {0x0d76, 0x00},
249 {0x0d41, 0x05},
250 {0x0d42, 0x3c},
251 {0x0d0a, 0x02},
252 {0x000c, 0x02},
253 {0x0d0d, 0x05},
254 {0x0d0e, 0x18},
255 {0x000f, 0x09},
256 {0x0010, 0x08},
257 {0x0017, 0x0c},
258 {0x0d53, 0x12},
259 {0x0051, 0x03},
260 {0x0082, 0x01},
261 {0x008c, 0x05},
262 {0x008d, 0xd0},
263 {0x0db7, 0x01},
264 {0x0db0, 0xad},
265 {0x0db1, 0x00},
266 {0x0db2, 0x8c},
267 {0x0db3, 0xf4},
268 {0x0db4, 0x00},
269 {0x0db5, 0x97},
270 {0x0db6, 0x08},
271 {0x0d25, 0xcb},
272 {0x0d4a, 0x04},
273 {0x00d2, 0x70},
274 {0x00d7, 0x19},
275 {0x00d9, 0x1c},
276 {0x00da, 0xc1},
277 {0x0d55, 0x1b},
278 {0x0d92, 0x17},
279 {0x0dc2, 0x30},
280 {0x0d2a, 0x30},
281 {0x0d19, 0x51},
282 {0x0d29, 0x30},
283 {0x0d20, 0x30},
284 {0x0d72, 0x12},
285 {0x0d4e, 0x12},
286 {0x0d43, 0x20},
287 {0x0050, 0x0c},
288 {0x006e, 0x03},
289 {0x0153, 0x50},
290 {0x0192, 0x04},
291 {0x0194, 0x04},
292 {0x0195, 0x05},
293 {0x0196, 0x10},
294 {0x0197, 0x09},
295 {0x0198, 0x00},
296 {0x0077, 0x01},
297 {0x0078, 0x04},
298 {0x0079, 0x65},
299 {0x0067, 0xc0},
300 {0x0054, 0xff},
301 {0x0055, 0x02},
302 {0x0056, 0x00},
303 {0x0057, 0x04},
304 {0x005a, 0xff},
305 {0x005b, 0x07},
306 {0x00d5, 0x03},
307 {0x0102, 0x10},
308 {0x0d4a, 0x04},
309 {0x04e0, 0xff},
310 {0x031e, 0x3e},
311 {0x0159, 0x01},
312 {0x014f, 0x28},
313 {0x0150, 0x40},
314 {0x0026, 0x00},
315 {0x0d26, 0xa0},
316 {0x0414, 0x76},
317 {0x0415, 0x75},
318 {0x0416, 0x75},
319 {0x0417, 0x76},
320 {0x0155, 0x01},
321 {0x0170, 0x3f},
322 {0x0171, 0x3f},
323 {0x0172, 0x3f},
324 {0x0173, 0x3f},
325 {0x0428, 0x0b},
326 {0x0429, 0x0b},
327 {0x042a, 0x0b},
328 {0x042b, 0x0b},
329 {0x042c, 0x0b},
330 {0x042d, 0x0b},
331 {0x042e, 0x0b},
332 {0x042f, 0x0b},
333 {0x0430, 0x05},
334 {0x0431, 0x05},
335 {0x0432, 0x05},
336 {0x0433, 0x05},
337 {0x0434, 0x04},
338 {0x0435, 0x04},
339 {0x0436, 0x04},
340 {0x0437, 0x04},
341 {0x0438, 0x18},
342 {0x0439, 0x18},
343 {0x043a, 0x18},
344 {0x043b, 0x18},
345 {0x043c, 0x1d},
346 {0x043d, 0x20},
347 {0x043e, 0x22},
348 {0x043f, 0x24},
349 {0x0468, 0x04},
350 {0x0469, 0x04},
351 {0x046a, 0x04},
352 {0x046b, 0x04},
353 {0x046c, 0x04},
354 {0x046d, 0x04},
355 {0x046e, 0x04},
356 {0x046f, 0x04},
357 {0x0108, 0xf0},
358 {0x0109, 0x80},
359 {0x0d03, 0x05},
360 {0x0d04, 0x00},
361 {0x007a, 0x60},
362 {0x00d0, 0x00},
363 {0x0080, 0x05},
364 {0x0291, 0x0f},
365 {0x0292, 0xff},
366 {0x0201, 0x27},
367 {0x0202, 0x53},
368 {0x0203, 0x4e},
369 {0x0206, 0x03},
370 {0x0212, 0x0b},
371 {0x0213, 0x40},
372 {0x0215, 0x12},
373 {0x023e, 0x99},
374 {0x03fe, 0x10},
375 {0x0183, 0x09},
376 {0x0187, 0x51},
377 {0x0d22, 0x04},
378 {0x0d21, 0x3C},
379 {0x0d03, 0x01},
380 {0x0d04, 0x28},
381 {0x0d23, 0x0e},
382 {0x03fe, 0x00},
383 {REG_NULL, 0x00},
384 };
385
386 static const struct regval gc3003_linear_10_320x240_regs[] = {
387 {0x03fe, 0xf0},
388 {0x03fe, 0xf0},
389 {0x03fe, 0xf0},
390 {0x03fe, 0x00},
391 {0x03f3, 0x00},
392 {0x03f5, 0xc0},
393 {0x03f6, 0x06},
394 {0x03f7, 0x01},
395 {0x03f8, 0x46},
396 {0x03f9, 0x13},
397 {0x03fa, 0x00},
398 {0x03e0, 0x16},
399 {0x03e1, 0x0d},
400 {0x03e2, 0x30},
401 {0x03e4, 0x08},
402 {0x03fc, 0xce},
403 {0x0d05, 0x05},
404 {0x0d06, 0xdc},
405 {0x0d76, 0x00},
406 {0x0d41, 0x01},
407 {0x0d42, 0x2c},
408 {0x0d0a, 0x02},
409 {0x000c, 0x02},
410 {0x0d0d, 0x00},
411 {0x0d0e, 0xf8},
412 {0x000f, 0x01},
413 {0x0010, 0x48},
414 {0x0017, 0x0c},
415 {0x0d53, 0x12},
416 {0x0051, 0x03},
417 {0x0082, 0x01},
418 {0x0086, 0x20},
419 {0x008a, 0x01},
420 {0x008b, 0x1d},
421 {0x008c, 0x05},
422 {0x008d, 0xd0},
423 {0x0db7, 0x01},
424 {0x0db0, 0x05},
425 {0x0db1, 0x00},
426 {0x0db2, 0x04},
427 {0x0db3, 0x54},
428 {0x0db4, 0x00},
429 {0x0db5, 0x17},
430 {0x0db6, 0x08},
431 {0x0d25, 0xcb},
432 {0x0d4a, 0x04},
433 {0x00d2, 0x70},
434 {0x00d7, 0x19},
435 {0x00d9, 0x10},
436 {0x00da, 0xc1},
437 {0x0d55, 0x1b},
438 {0x0d92, 0x17},
439 {0x0dc2, 0x30},
440 {0x0d2a, 0x30},
441 {0x0d19, 0x51},
442 {0x0d29, 0x30},
443 {0x0d20, 0x30},
444 {0x0d72, 0x12},
445 {0x0d4e, 0x12},
446 {0x0d43, 0x20},
447 {0x0050, 0x0c},
448 {0x006e, 0x03},
449 {0x0153, 0x50},
450 {0x0192, 0x04},
451 {0x0194, 0x04},
452 {0x0195, 0x00},
453 {0x0196, 0xf0},
454 {0x0197, 0x01},
455 {0x0198, 0x40},
456 {0x0077, 0x01},
457 {0x0078, 0x65},
458 {0x0079, 0x04},
459 {0x0067, 0xc0},
460 {0x0054, 0xff},
461 {0x0055, 0x02},
462 {0x0056, 0x00},
463 {0x0057, 0x04},
464 {0x005a, 0xff},
465 {0x005b, 0x07},
466 {0x00d5, 0x03},
467 {0x0102, 0x10},
468 {0x0d4a, 0x04},
469 {0x04e0, 0xff},
470 {0x031e, 0x3e},
471 {0x0159, 0x01},
472 {0x014f, 0x28},
473 {0x0150, 0x40},
474 {0x0026, 0x00},
475 {0x0d26, 0xa0},
476 {0x0414, 0x77},
477 {0x0415, 0x77},
478 {0x0416, 0x77},
479 {0x0417, 0x77},
480 {0x0155, 0x00},
481 {0x0170, 0x3e},
482 {0x0171, 0x3e},
483 {0x0172, 0x3e},
484 {0x0173, 0x3e},
485 {0x0428, 0x0b},
486 {0x0429, 0x0b},
487 {0x042a, 0x0b},
488 {0x042b, 0x0b},
489 {0x042c, 0x0b},
490 {0x042d, 0x0b},
491 {0x042e, 0x0b},
492 {0x042f, 0x0b},
493 {0x0430, 0x05},
494 {0x0431, 0x05},
495 {0x0432, 0x05},
496 {0x0433, 0x05},
497 {0x0434, 0x04},
498 {0x0435, 0x04},
499 {0x0436, 0x04},
500 {0x0437, 0x04},
501 {0x0438, 0x18},
502 {0x0439, 0x18},
503 {0x043a, 0x18},
504 {0x043b, 0x18},
505 {0x043c, 0x1d},
506 {0x043d, 0x20},
507 {0x043e, 0x22},
508 {0x043f, 0x24},
509 {0x0468, 0x04},
510 {0x0469, 0x04},
511 {0x046a, 0x04},
512 {0x046b, 0x04},
513 {0x046c, 0x04},
514 {0x046d, 0x04},
515 {0x046e, 0x04},
516 {0x046f, 0x04},
517 {0x0108, 0xf0},
518 {0x0109, 0x80},
519 {0x0d03, 0x05},
520 {0x0d04, 0x00},
521 {0x007a, 0x60},
522 {0x00d0, 0x00},
523 {0x0080, 0x09},
524 {0x0291, 0x0f},
525 {0x0292, 0xff},
526 {0x0201, 0x27},
527 {0x0202, 0x53},
528 {0x0203, 0x4e},
529 {0x0206, 0x03},
530 {0x0212, 0x0b},
531 {0x0213, 0x40},
532 {0x0215, 0x10},
533 {0x03fe, 0x10},
534 {0x0183, 0x09},
535 {0x0187, 0x51},
536 {0x0d22, 0x01},
537 {0x0d21, 0x2c},
538 {0x0d03, 0x00},
539 {0x0d04, 0x40},
540 {0x0d23, 0x0e},
541 {0x03fe, 0x00},
542 {REG_NULL, 0x00},
543 };
544
545 static const struct regval gc3003_linear_10_1920x528_regs[] = {
546 {0x03fe, 0xf0},
547 {0x03fe, 0xf0},
548 {0x03fe, 0xf0},
549 {0x03fe, 0x00},
550 {0x03f3, 0x00},
551 {0x03f5, 0xc0},
552 {0x03f6, 0x06},
553 {0x03f7, 0x01},
554 {0x03f8, 0x46},
555 {0x03f9, 0x13},
556 {0x03fa, 0x00},
557 {0x03e0, 0x16},
558 {0x03e1, 0x0d},
559 {0x03e2, 0x30},
560 {0x03e4, 0x08},
561 {0x03fc, 0xce},
562 {0x0d05, 0x05},
563 {0x0d06, 0x40},
564 {0x0d76, 0x00},
565 {0x0d41, 0x02},
566 {0x0d42, 0x3c},
567 {0x0d09, 0x01},
568 {0x0d0a, 0x7a},
569 {0x000c, 0x02},
570 {0x0d0d, 0x02},
571 {0x0d0e, 0x10},//528
572 {0x000f, 0x09},
573 {0x0010, 0x08},
574 {0x0017, 0x0c},
575 {0x0d53, 0x12},
576 {0x0051, 0x03},
577 {0x0082, 0x01},
578 {0x0086, 0x20},
579 {0x008a, 0x01},
580 {0x008b, 0x1d},
581 {0x008c, 0x05},
582 {0x008d, 0xd0},
583 {0x0db7, 0x01},
584 {0x0db0, 0x05},
585 {0x0db1, 0x00},
586 {0x0db2, 0x04},
587 {0x0db3, 0x54},
588 {0x0db4, 0x00},
589 {0x0db5, 0x17},
590 {0x0db6, 0x08},
591 {0x0d25, 0xcb},
592 {0x0d4a, 0x04},
593 {0x00d2, 0x70},
594 {0x00d7, 0x19},
595 {0x00d9, 0x10},
596 {0x00da, 0xc1},
597 {0x0d55, 0x1b},
598 {0x0d92, 0x17},
599 {0x0dc2, 0x30},
600 {0x0d2a, 0x30},
601 {0x0d19, 0x51},
602 {0x0d29, 0x30},
603 {0x0d20, 0x30},
604 {0x0d72, 0x12},
605 {0x0d4e, 0x12},
606 {0x0d43, 0x20},
607 {0x0050, 0x0c},
608 {0x006e, 0x03},
609 {0x0153, 0x50},
610 {0x0192, 0x00},
611 {0x0193, 0x00},
612 {0x0194, 0xc0},
613 {0x0195, 0x02},
614 {0x0196, 0x1c},
615 {0x0197, 0x07},
616 {0x0198, 0x80},
617 {0x0077, 0x01},
618 {0x0078, 0x65},
619 {0x0079, 0x04},
620 {0x0067, 0xc0},
621 {0x0054, 0xff},
622 {0x0055, 0x02},
623 {0x0056, 0x00},
624 {0x0057, 0x04},
625 {0x005a, 0xff},
626 {0x005b, 0x07},
627 {0x00d5, 0x03},
628 {0x0102, 0x10},
629 {0x0d4a, 0x04},
630 {0x04e0, 0xff},
631 {0x031e, 0x3e},
632 {0x0159, 0x01},
633 {0x014f, 0x28},
634 {0x0150, 0x40},
635 {0x0026, 0x00},
636 {0x0d26, 0xa0},
637 {0x0414, 0x77},
638 {0x0415, 0x77},
639 {0x0416, 0x77},
640 {0x0417, 0x77},
641 {0x0155, 0x00},
642 {0x0170, 0x3e},
643 {0x0171, 0x3e},
644 {0x0172, 0x3e},
645 {0x0173, 0x3e},
646 {0x0428, 0x0b},
647 {0x0429, 0x0b},
648 {0x042a, 0x0b},
649 {0x042b, 0x0b},
650 {0x042c, 0x0b},
651 {0x042d, 0x0b},
652 {0x042e, 0x0b},
653 {0x042f, 0x0b},
654 {0x0430, 0x05},
655 {0x0431, 0x05},
656 {0x0432, 0x05},
657 {0x0433, 0x05},
658 {0x0434, 0x04},
659 {0x0435, 0x04},
660 {0x0436, 0x04},
661 {0x0437, 0x04},
662 {0x0438, 0x18},
663 {0x0439, 0x18},
664 {0x043a, 0x18},
665 {0x043b, 0x18},
666 {0x043c, 0x1d},
667 {0x043d, 0x20},
668 {0x043e, 0x22},
669 {0x043f, 0x24},
670 {0x0468, 0x04},
671 {0x0469, 0x04},
672 {0x046a, 0x04},
673 {0x046b, 0x04},
674 {0x046c, 0x04},
675 {0x046d, 0x04},
676 {0x046e, 0x04},
677 {0x046f, 0x04},
678 {0x0108, 0xf0},
679 {0x0109, 0x80},
680 {0x0d03, 0x05},
681 {0x0d04, 0x00},
682 {0x007a, 0x60},
683 {0x00d0, 0x00},
684 {0x0080, 0x09},
685 {0x0291, 0x0f},
686 {0x0292, 0xff},
687 {0x0201, 0x27},
688 {0x0202, 0x53},
689 {0x0203, 0x4e},
690 {0x0206, 0x03},
691 {0x0212, 0x0b},
692 {0x0213, 0x40},
693 {0x0215, 0x12},
694 {0x023e, 0x99},
695 {0x03fe, 0x10},
696 {0x0183, 0x09},
697 {0x0187, 0x51},
698 {0x0d22, 0x01},
699 {0x0d21, 0x2c},
700 {0x0d03, 0x01},
701 {0x0d04, 0x00},
702 {0x0d23, 0x0e},
703 {0x03fe, 0x00},
704 {REG_NULL, 0x00},
705 };
706
707 static const struct regval gc3003_stream_on_regs[] = {
708 {0x0201, 0x27},
709 {0x0202, 0x53},
710 {0x0203, 0x4e},
711 {0x0206, 0x03},
712 {0x0212, 0x0b},
713 {0x0213, 0x40},
714 {0x0215, 0x10},
715 {0x023e, 0x99},
716 {0x03fe, 0x00},
717 {REG_NULL, 0x00},
718 };
719
720 static const struct regval gc3003_stand_by_regs[] = {
721 {0x023e, 0x00},
722 {0x03f7, 0x00},
723 {0x03fc, 0x01},
724 {0x03f9, 0x01},
725 {REG_NULL, 0x00},
726 };
727
728 static const struct gc3003_mode supported_modes[] = {
729 {
730 .width = 2304,
731 .height = 1298,
732 .max_fps = {
733 .numerator = 10000,
734 .denominator = 300000,
735 },
736 .exp_def = 0x0500,
737 .hts_def = 0x540 * 2,
738 .vts_def = 0x053c,
739 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
740 .reg_list = gc3003_linear_10_2304x1298_regs,
741 .stream_on_reg_list = gc3003_stream_on_regs,
742 .stand_by_reg_list = gc3003_stand_by_regs,
743 .hdr_mode = NO_HDR,
744 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
745 },
746 {
747 .width = 320,
748 .height = 240,
749 .max_fps = {
750 .numerator = 10000,
751 .denominator = 1200000,
752 },
753 .exp_def = 0x0100,
754 .hts_def = 0x05dc * 2,
755 .vts_def = 0x12c,
756 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
757 .reg_list = gc3003_linear_10_320x240_regs,
758 .stream_on_reg_list = gc3003_stream_on_regs,
759 .stand_by_reg_list = gc3003_stand_by_regs,
760 .hdr_mode = NO_HDR,
761 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
762 },
763 {
764 .width = 1920,
765 .height = 528,
766 .max_fps = {
767 .numerator = 10000,
768 .denominator = 700000,
769 },
770 .exp_def = 0x0100,
771 .hts_def = 0x05dc * 2,
772 .vts_def = 0x23c,
773 .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
774 .reg_list = gc3003_linear_10_1920x528_regs,
775 .stream_on_reg_list = gc3003_stream_on_regs,
776 .stand_by_reg_list = gc3003_stand_by_regs,
777 .hdr_mode = NO_HDR,
778 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
779 },
780 };
781
782 static const s64 link_freq_menu_items[] = {
783 GC3003_LINK_FREQ_LINEAR,
784 };
785
786 static const char * const gc3003_test_pattern_menu[] = {
787 "Disabled",
788 "Vertical Color Bar Type 1",
789 "Vertical Color Bar Type 2",
790 "Vertical Color Bar Type 3",
791 "Vertical Color Bar Type 4"
792 };
793
794 /* Write registers up to 4 at a time */
gc3003_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)795 static int gc3003_write_reg(struct i2c_client *client, u16 reg,
796 u32 len, u32 val)
797 {
798 u32 buf_i, val_i;
799 u8 buf[6];
800 u8 *val_p;
801 __be32 val_be;
802
803 if (len > 4)
804 return -EINVAL;
805
806 buf[0] = reg >> 8;
807 buf[1] = reg & 0xff;
808
809 val_be = cpu_to_be32(val);
810 val_p = (u8 *)&val_be;
811 buf_i = 2;
812 val_i = 4 - len;
813
814 while (val_i < 4)
815 buf[buf_i++] = val_p[val_i++];
816
817 if (i2c_master_send(client, buf, len + 2) != len + 2)
818 return -EIO;
819 return 0;
820 }
821
gc3003_write_array(struct i2c_client * client,const struct regval * regs)822 static int gc3003_write_array(struct i2c_client *client,
823 const struct regval *regs)
824 {
825 u32 i;
826 int ret = 0;
827
828 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
829 ret = gc3003_write_reg(client, regs[i].addr,
830 GC3003_REG_VALUE_08BIT, regs[i].val);
831
832 return ret;
833 }
834
835 /* Read registers up to 4 at a time */
gc3003_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)836 static int gc3003_read_reg(struct i2c_client *client, u16 reg,
837 unsigned int len, u32 *val)
838 {
839 struct i2c_msg msgs[2];
840 u8 *data_be_p;
841 __be32 data_be = 0;
842 __be16 reg_addr_be = cpu_to_be16(reg);
843 int ret;
844
845 if (len > 4 || !len)
846 return -EINVAL;
847
848 data_be_p = (u8 *)&data_be;
849 /* Write register address */
850 msgs[0].addr = client->addr;
851 msgs[0].flags = 0;
852 msgs[0].len = 2;
853 msgs[0].buf = (u8 *)®_addr_be;
854
855 /* Read data from register */
856 msgs[1].addr = client->addr;
857 msgs[1].flags = I2C_M_RD;
858 msgs[1].len = len;
859 msgs[1].buf = &data_be_p[4 - len];
860
861 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
862 if (ret != ARRAY_SIZE(msgs))
863 return -EIO;
864
865 *val = be32_to_cpu(data_be);
866
867 return 0;
868 }
869
gc3003_get_reso_dist(const struct gc3003_mode * mode,struct v4l2_mbus_framefmt * framefmt)870 static int gc3003_get_reso_dist(const struct gc3003_mode *mode,
871 struct v4l2_mbus_framefmt *framefmt)
872 {
873 return abs(mode->width - framefmt->width) +
874 abs(mode->height - framefmt->height);
875 }
876
877 static const struct gc3003_mode *
gc3003_find_best_fit(struct gc3003 * gc3003,struct v4l2_subdev_format * fmt)878 gc3003_find_best_fit(struct gc3003 *gc3003, struct v4l2_subdev_format *fmt)
879 {
880 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
881 int dist;
882 int cur_best_fit = 0;
883 int cur_best_fit_dist = -1;
884 unsigned int i;
885
886 for (i = 0; i < gc3003->cfg_num; i++) {
887 dist = gc3003_get_reso_dist(&supported_modes[i], framefmt);
888 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
889 cur_best_fit_dist = dist;
890 cur_best_fit = i;
891 }
892 }
893
894 return &supported_modes[cur_best_fit];
895 }
896
gc3003_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)897 static int gc3003_set_fmt(struct v4l2_subdev *sd,
898 struct v4l2_subdev_pad_config *cfg,
899 struct v4l2_subdev_format *fmt)
900 {
901 struct gc3003 *gc3003 = to_gc3003(sd);
902 const struct gc3003_mode *mode;
903 s64 h_blank, vblank_def;
904
905 mutex_lock(&gc3003->mutex);
906
907 mode = gc3003_find_best_fit(gc3003, fmt);
908 fmt->format.code = mode->bus_fmt;
909 fmt->format.width = mode->width;
910 fmt->format.height = mode->height;
911 fmt->format.field = V4L2_FIELD_NONE;
912 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
913 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
914 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
915 #else
916 mutex_unlock(&gc3003->mutex);
917 return -ENOTTY;
918 #endif
919 } else {
920 gc3003->cur_mode = mode;
921 h_blank = mode->hts_def - mode->width;
922 __v4l2_ctrl_modify_range(gc3003->hblank, h_blank,
923 h_blank, 1, h_blank);
924 vblank_def = mode->vts_def - mode->height;
925 __v4l2_ctrl_modify_range(gc3003->vblank, vblank_def,
926 GC3003_VTS_MAX - mode->height,
927 1, vblank_def);
928
929 gc3003->cur_link_freq = 0;
930 gc3003->cur_pixel_rate = GC3003_PIXEL_RATE_LINEAR;
931
932 __v4l2_ctrl_s_ctrl_int64(gc3003->pixel_rate,
933 gc3003->cur_pixel_rate);
934 __v4l2_ctrl_s_ctrl(gc3003->link_freq,
935 gc3003->cur_link_freq);
936 gc3003->cur_vts = mode->vts_def;
937 }
938
939 mutex_unlock(&gc3003->mutex);
940
941 return 0;
942 }
943
gc3003_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)944 static int gc3003_get_fmt(struct v4l2_subdev *sd,
945 struct v4l2_subdev_pad_config *cfg,
946 struct v4l2_subdev_format *fmt)
947 {
948 struct gc3003 *gc3003 = to_gc3003(sd);
949 const struct gc3003_mode *mode = gc3003->cur_mode;
950
951 mutex_lock(&gc3003->mutex);
952 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
953 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
954 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
955 #else
956 mutex_unlock(&gc3003->mutex);
957 return -ENOTTY;
958 #endif
959 } else {
960 fmt->format.width = mode->width;
961 fmt->format.height = mode->height;
962 fmt->format.code = mode->bus_fmt;
963 fmt->format.field = V4L2_FIELD_NONE;
964 }
965 mutex_unlock(&gc3003->mutex);
966
967 return 0;
968 }
969
gc3003_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)970 static int gc3003_enum_mbus_code(struct v4l2_subdev *sd,
971 struct v4l2_subdev_pad_config *cfg,
972 struct v4l2_subdev_mbus_code_enum *code)
973 {
974 struct gc3003 *gc3003 = to_gc3003(sd);
975
976 if (code->index != 0)
977 return -EINVAL;
978 code->code = gc3003->cur_mode->bus_fmt;
979
980 return 0;
981 }
982
gc3003_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)983 static int gc3003_enum_frame_sizes(struct v4l2_subdev *sd,
984 struct v4l2_subdev_pad_config *cfg,
985 struct v4l2_subdev_frame_size_enum *fse)
986 {
987 struct gc3003 *gc3003 = to_gc3003(sd);
988
989 if (fse->index >= gc3003->cfg_num)
990 return -EINVAL;
991
992 if (fse->code != supported_modes[0].bus_fmt)
993 return -EINVAL;
994
995 fse->min_width = supported_modes[fse->index].width;
996 fse->max_width = supported_modes[fse->index].width;
997 fse->max_height = supported_modes[fse->index].height;
998 fse->min_height = supported_modes[fse->index].height;
999
1000 return 0;
1001 }
1002
gc3003_enable_test_pattern(struct gc3003 * gc3003,u32 pattern)1003 static int gc3003_enable_test_pattern(struct gc3003 *gc3003, u32 pattern)
1004 {
1005 u32 val;
1006
1007 if (pattern)
1008 val = GC3003_TEST_PATTERN_ENABLE;
1009 else
1010 val = GC3003_TEST_PATTERN_DISABLE;
1011
1012 return gc3003_write_reg(gc3003->client, GC3003_REG_TEST_PATTERN,
1013 GC3003_REG_VALUE_08BIT, val);
1014 }
gc3003_set_gain_reg(struct gc3003 * gc3003,u32 gain)1015 static int gc3003_set_gain_reg(struct gc3003 *gc3003, u32 gain)
1016 {
1017 int i;
1018 int total;
1019 u32 tol_dig_gain = 0;
1020
1021 if (gain < 64)
1022 gain = 64;
1023 total = sizeof(gain_level_table) / sizeof(u32) - 1; // why -1
1024 for (i = 0; i < total; i++) {
1025 if (gain_level_table[i] <= gain &&
1026 gain < gain_level_table[i + 1])
1027 break;
1028 }
1029 tol_dig_gain = gain * 64 / gain_level_table[i];
1030 if (i >= total)
1031 i = total - 1;
1032
1033 gc3003_write_reg(gc3003->client, 0x0d1,
1034 GC3003_REG_VALUE_08BIT, reg_val_table_liner[i][0]);
1035 gc3003_write_reg(gc3003->client, 0x0d0,
1036 GC3003_REG_VALUE_08BIT, reg_val_table_liner[i][1]);
1037 gc3003_write_reg(gc3003->client, 0x080,
1038 GC3003_REG_VALUE_08BIT, reg_val_table_liner[i][2]);
1039 gc3003_write_reg(gc3003->client, 0x155,
1040 GC3003_REG_VALUE_08BIT, reg_val_table_liner[i][3]);
1041 gc3003_write_reg(gc3003->client, 0x0b8,
1042 GC3003_REG_VALUE_08BIT, reg_val_table_liner[i][4]);
1043 gc3003_write_reg(gc3003->client, 0x0b9,
1044 GC3003_REG_VALUE_08BIT, reg_val_table_liner[i][5]);
1045 gc3003_write_reg(gc3003->client, 0x0b1,
1046 GC3003_REG_VALUE_08BIT, (tol_dig_gain >> 6));
1047 gc3003_write_reg(gc3003->client, 0x0b2,
1048 GC3003_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f)<<2));
1049
1050 return 0;
1051 }
gc3003_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1052 static int gc3003_g_frame_interval(struct v4l2_subdev *sd,
1053 struct v4l2_subdev_frame_interval *fi)
1054 {
1055 struct gc3003 *gc3003 = to_gc3003(sd);
1056 const struct gc3003_mode *mode = gc3003->cur_mode;
1057
1058 fi->interval = mode->max_fps;
1059
1060 return 0;
1061 }
1062
gc3003_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1063 static int gc3003_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1064 struct v4l2_mbus_config *config)
1065 {
1066 struct gc3003 *gc3003 = to_gc3003(sd);
1067 const struct gc3003_mode *mode = gc3003->cur_mode;
1068 u32 val = 0;
1069
1070 if (mode->hdr_mode == NO_HDR)
1071 val = 1 << (GC3003_LANES - 1) |
1072 V4L2_MBUS_CSI2_CHANNEL_0 |
1073 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1074
1075 config->type = V4L2_MBUS_CSI2_DPHY;
1076 config->flags = val;
1077
1078 return 0;
1079 }
1080
gc3003_get_module_inf(struct gc3003 * gc3003,struct rkmodule_inf * inf)1081 static void gc3003_get_module_inf(struct gc3003 *gc3003,
1082 struct rkmodule_inf *inf)
1083 {
1084 memset(inf, 0, sizeof(*inf));
1085 strscpy(inf->base.sensor, GC3003_NAME, sizeof(inf->base.sensor));
1086 strscpy(inf->base.module, gc3003->module_name,
1087 sizeof(inf->base.module));
1088 strscpy(inf->base.lens, gc3003->len_name, sizeof(inf->base.lens));
1089 }
1090
gc3003_get_channel_info(struct gc3003 * gc3003,struct rkmodule_channel_info * ch_info)1091 static int gc3003_get_channel_info(struct gc3003 *gc3003, struct rkmodule_channel_info *ch_info)
1092 {
1093 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1094 return -EINVAL;
1095 ch_info->vc = gc3003->cur_mode->vc[ch_info->index];
1096 ch_info->width = gc3003->cur_mode->width;
1097 ch_info->height = gc3003->cur_mode->height;
1098 ch_info->bus_fmt = gc3003->cur_mode->bus_fmt;
1099 return 0;
1100 }
1101
gc3003_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1102 static long gc3003_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1103 {
1104 struct gc3003 *gc3003 = to_gc3003(sd);
1105 struct rkmodule_hdr_cfg *hdr;
1106 u32 i, h, w;
1107 long ret = 0;
1108 u32 stream = 0;
1109 struct rkmodule_channel_info *ch_info;
1110
1111 switch (cmd) {
1112 case RKMODULE_GET_MODULE_INFO:
1113 gc3003_get_module_inf(gc3003, (struct rkmodule_inf *)arg);
1114 break;
1115 case RKMODULE_GET_HDR_CFG:
1116 hdr = (struct rkmodule_hdr_cfg *)arg;
1117 hdr->esp.mode = HDR_NORMAL_VC;
1118 hdr->hdr_mode = gc3003->cur_mode->hdr_mode;
1119 break;
1120 case RKMODULE_SET_HDR_CFG:
1121 hdr = (struct rkmodule_hdr_cfg *)arg;
1122 w = gc3003->cur_mode->width;
1123 h = gc3003->cur_mode->height;
1124 for (i = 0; i < gc3003->cfg_num; i++) {
1125 if (w == supported_modes[i].width &&
1126 h == supported_modes[i].height &&
1127 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1128 gc3003->cur_mode = &supported_modes[i];
1129 break;
1130 }
1131 }
1132 if (i == gc3003->cfg_num) {
1133 dev_err(&gc3003->client->dev,
1134 "not find hdr mode:%d %dx%d config\n",
1135 hdr->hdr_mode, w, h);
1136 ret = -EINVAL;
1137 } else {
1138 w = gc3003->cur_mode->hts_def -
1139 gc3003->cur_mode->width;
1140 h = gc3003->cur_mode->vts_def -
1141 gc3003->cur_mode->height;
1142 __v4l2_ctrl_modify_range(gc3003->hblank, w, w, 1, w);
1143 __v4l2_ctrl_modify_range(gc3003->vblank, h,
1144 GC3003_VTS_MAX -
1145 gc3003->cur_mode->height,
1146 1, h);
1147 gc3003->cur_link_freq = 0;
1148 gc3003->cur_pixel_rate = GC3003_PIXEL_RATE_LINEAR;
1149
1150 __v4l2_ctrl_s_ctrl_int64(gc3003->pixel_rate,
1151 gc3003->cur_pixel_rate);
1152 __v4l2_ctrl_s_ctrl(gc3003->link_freq,
1153 gc3003->cur_link_freq);
1154 gc3003->cur_vts = gc3003->cur_mode->vts_def;
1155 }
1156 break;
1157 case PREISP_CMD_SET_HDRAE_EXP:
1158 break;
1159 case RKMODULE_SET_QUICK_STREAM:
1160
1161 stream = *((u32 *)arg);
1162
1163 if (stream)
1164 ret = gc3003_write_reg(gc3003->client, GC3003_REG_CTRL_MODE,
1165 GC3003_REG_VALUE_08BIT, GC3003_MODE_STREAMING);
1166 else
1167 ret = gc3003_write_reg(gc3003->client, GC3003_REG_CTRL_MODE,
1168 GC3003_REG_VALUE_08BIT, GC3003_MODE_SW_STANDBY);
1169 break;
1170 case RKMODULE_GET_CHANNEL_INFO:
1171 ch_info = (struct rkmodule_channel_info *)arg;
1172 ret = gc3003_get_channel_info(gc3003, ch_info);
1173 break;
1174 default:
1175 ret = -ENOIOCTLCMD;
1176 break;
1177 }
1178
1179 return ret;
1180 }
1181
1182 #ifdef CONFIG_COMPAT
gc3003_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1183 static long gc3003_compat_ioctl32(struct v4l2_subdev *sd,
1184 unsigned int cmd, unsigned long arg)
1185 {
1186 void __user *up = compat_ptr(arg);
1187 struct rkmodule_inf *inf;
1188 struct rkmodule_awb_cfg *cfg;
1189 struct rkmodule_hdr_cfg *hdr;
1190 struct preisp_hdrae_exp_s *hdrae;
1191 long ret;
1192 u32 stream = 0;
1193 struct rkmodule_channel_info *ch_info;
1194
1195 switch (cmd) {
1196 case RKMODULE_GET_MODULE_INFO:
1197 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1198 if (!inf) {
1199 ret = -ENOMEM;
1200 return ret;
1201 }
1202
1203 ret = gc3003_ioctl(sd, cmd, inf);
1204 if (!ret) {
1205 ret = copy_to_user(up, inf, sizeof(*inf));
1206 if (ret)
1207 ret = -EFAULT;
1208 }
1209 kfree(inf);
1210 break;
1211 case RKMODULE_AWB_CFG:
1212 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1213 if (!cfg) {
1214 ret = -ENOMEM;
1215 return ret;
1216 }
1217
1218 ret = copy_from_user(cfg, up, sizeof(*cfg));
1219 if (!ret)
1220 ret = gc3003_ioctl(sd, cmd, cfg);
1221 else
1222 ret = -EFAULT;
1223 kfree(cfg);
1224 break;
1225 case RKMODULE_GET_HDR_CFG:
1226 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1227 if (!hdr) {
1228 ret = -ENOMEM;
1229 return ret;
1230 }
1231
1232 ret = gc3003_ioctl(sd, cmd, hdr);
1233 if (!ret) {
1234 ret = copy_to_user(up, hdr, sizeof(*hdr));
1235 if (ret)
1236 ret = -EFAULT;
1237 }
1238 kfree(hdr);
1239 break;
1240 case RKMODULE_SET_HDR_CFG:
1241 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1242 if (!hdr) {
1243 ret = -ENOMEM;
1244 return ret;
1245 }
1246
1247 ret = copy_from_user(hdr, up, sizeof(*hdr));
1248 if (!ret)
1249 ret = gc3003_ioctl(sd, cmd, hdr);
1250 else
1251 ret = -EFAULT;
1252 kfree(hdr);
1253 break;
1254 case PREISP_CMD_SET_HDRAE_EXP:
1255 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1256 if (!hdrae) {
1257 ret = -ENOMEM;
1258 return ret;
1259 }
1260
1261 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1262 if (!ret)
1263 ret = gc3003_ioctl(sd, cmd, hdrae);
1264 else
1265 ret = -EFAULT;
1266 kfree(hdrae);
1267 break;
1268 case RKMODULE_SET_QUICK_STREAM:
1269 ret = copy_from_user(&stream, up, sizeof(u32));
1270 if (!ret)
1271 ret = gc3003_ioctl(sd, cmd, &stream);
1272 else
1273 ret = -EFAULT;
1274 break;
1275 case RKMODULE_GET_CHANNEL_INFO:
1276 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1277 if (!ch_info) {
1278 ret = -ENOMEM;
1279 return ret;
1280 }
1281
1282 ret = gc3003_ioctl(sd, cmd, ch_info);
1283 if (!ret) {
1284 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1285 if (ret)
1286 ret = -EFAULT;
1287 }
1288 kfree(ch_info);
1289 break;
1290 default:
1291 ret = -ENOIOCTLCMD;
1292 break;
1293 }
1294
1295 return ret;
1296 }
1297 #endif
1298
__gc3003_start_stream(struct gc3003 * gc3003)1299 static int __gc3003_start_stream(struct gc3003 *gc3003)
1300 {
1301 int ret;
1302
1303 if (!gc3003->is_thunderboot) {
1304 ret = gc3003_write_array(gc3003->client, gc3003->cur_mode->reg_list);
1305 if (ret)
1306 return ret;
1307
1308 /* In case these controls are set before streaming */
1309 ret = __v4l2_ctrl_handler_setup(&gc3003->ctrl_handler);
1310 if (ret)
1311 return ret;
1312 if (gc3003->has_init_exp && gc3003->cur_mode->hdr_mode != NO_HDR) {
1313 ret = gc3003_ioctl(&gc3003->subdev, PREISP_CMD_SET_HDRAE_EXP,
1314 &gc3003->init_hdrae_exp);
1315 if (ret) {
1316 dev_err(&gc3003->client->dev,
1317 "init exp fail in hdr mode\n");
1318 return ret;
1319 }
1320 }
1321 }
1322
1323 ret = gc3003_write_array(gc3003->client, gc3003->cur_mode->stream_on_reg_list);
1324
1325 return ret;
1326 }
1327
__gc3003_stop_stream(struct gc3003 * gc3003)1328 static int __gc3003_stop_stream(struct gc3003 *gc3003)
1329 {
1330 int ret;
1331
1332 gc3003->has_init_exp = false;
1333 if (gc3003->is_thunderboot) {
1334 gc3003->is_first_streamoff = true;
1335 pm_runtime_put(&gc3003->client->dev);
1336 }
1337 ret = gc3003_write_array(gc3003->client, gc3003->cur_mode->stand_by_reg_list);
1338
1339 return ret;
1340 }
1341
1342 static int __gc3003_power_on(struct gc3003 *gc3003);
gc3003_s_stream(struct v4l2_subdev * sd,int on)1343 static int gc3003_s_stream(struct v4l2_subdev *sd, int on)
1344 {
1345 struct gc3003 *gc3003 = to_gc3003(sd);
1346 struct i2c_client *client = gc3003->client;
1347 int ret = 0;
1348
1349 mutex_lock(&gc3003->mutex);
1350 on = !!on;
1351 if (on == gc3003->streaming)
1352 goto unlock_and_return;
1353
1354 if (on) {
1355 if (gc3003->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1356 gc3003->is_thunderboot = false;
1357 __gc3003_power_on(gc3003);
1358 }
1359 ret = pm_runtime_get_sync(&client->dev);
1360 if (ret < 0) {
1361 pm_runtime_put_noidle(&client->dev);
1362 goto unlock_and_return;
1363 }
1364
1365 ret = __gc3003_start_stream(gc3003);
1366 if (ret) {
1367 v4l2_err(sd, "start stream failed while write regs\n");
1368 pm_runtime_put(&client->dev);
1369 goto unlock_and_return;
1370 }
1371 } else {
1372 __gc3003_stop_stream(gc3003);
1373 pm_runtime_put(&client->dev);
1374 }
1375
1376 gc3003->streaming = on;
1377
1378 unlock_and_return:
1379 mutex_unlock(&gc3003->mutex);
1380
1381 return ret;
1382 }
1383
gc3003_s_power(struct v4l2_subdev * sd,int on)1384 static int gc3003_s_power(struct v4l2_subdev *sd, int on)
1385 {
1386 struct gc3003 *gc3003 = to_gc3003(sd);
1387 struct i2c_client *client = gc3003->client;
1388 int ret = 0;
1389
1390 mutex_lock(&gc3003->mutex);
1391
1392 /* If the power state is not modified - no work to do. */
1393 if (gc3003->power_on == !!on)
1394 goto unlock_and_return;
1395
1396 if (on) {
1397 ret = pm_runtime_get_sync(&client->dev);
1398 if (ret < 0) {
1399 pm_runtime_put_noidle(&client->dev);
1400 goto unlock_and_return;
1401 }
1402
1403 if (!gc3003->is_thunderboot) {
1404 ret = gc3003_write_array(gc3003->client, gc3003_global_regs);
1405 if (ret) {
1406 v4l2_err(sd, "could not set init registers\n");
1407 pm_runtime_put_noidle(&client->dev);
1408 goto unlock_and_return;
1409 }
1410 }
1411
1412 gc3003->power_on = true;
1413 } else {
1414 pm_runtime_put(&client->dev);
1415 gc3003->power_on = false;
1416 }
1417
1418 unlock_and_return:
1419 mutex_unlock(&gc3003->mutex);
1420
1421 return ret;
1422 }
1423
1424 /* Calculate the delay in us by clock rate and clock cycles */
gc3003_cal_delay(u32 cycles)1425 static inline u32 gc3003_cal_delay(u32 cycles)
1426 {
1427 return DIV_ROUND_UP(cycles, GC3003_XVCLK_FREQ / 1000 / 1000);
1428 }
1429
__gc3003_power_on(struct gc3003 * gc3003)1430 static int __gc3003_power_on(struct gc3003 *gc3003)
1431 {
1432 int ret;
1433 u32 delay_us;
1434 struct device *dev = &gc3003->client->dev;
1435
1436 if (!IS_ERR_OR_NULL(gc3003->pins_default)) {
1437 ret = pinctrl_select_state(gc3003->pinctrl,
1438 gc3003->pins_default);
1439 if (ret < 0)
1440 dev_err(dev, "could not set pins\n");
1441 }
1442 ret = clk_set_rate(gc3003->xvclk, GC3003_XVCLK_FREQ);
1443 if (ret < 0)
1444 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1445 if (clk_get_rate(gc3003->xvclk) != GC3003_XVCLK_FREQ)
1446 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1447 ret = clk_prepare_enable(gc3003->xvclk);
1448 if (ret < 0) {
1449 dev_err(dev, "Failed to enable xvclk\n");
1450 return ret;
1451 }
1452
1453 if (gc3003->is_thunderboot)
1454 return 0;
1455
1456 if (!IS_ERR(gc3003->reset_gpio))
1457 gpiod_set_value_cansleep(gc3003->reset_gpio, 0);
1458
1459 if (!IS_ERR(gc3003->pwdn_gpio))
1460 gpiod_set_value_cansleep(gc3003->pwdn_gpio, 0);
1461
1462 usleep_range(500, 1000);
1463 ret = regulator_bulk_enable(GC3003_NUM_SUPPLIES, gc3003->supplies);
1464
1465 if (ret < 0) {
1466 dev_err(dev, "Failed to enable regulators\n");
1467 goto disable_clk;
1468 }
1469
1470 if (!IS_ERR(gc3003->pwren_gpio))
1471 gpiod_set_value_cansleep(gc3003->pwren_gpio, 1);
1472
1473 usleep_range(1000, 1100);
1474 if (!IS_ERR(gc3003->pwdn_gpio))
1475 gpiod_set_value_cansleep(gc3003->pwdn_gpio, 1);
1476 usleep_range(100, 150);
1477 if (!IS_ERR(gc3003->reset_gpio))
1478 gpiod_set_value_cansleep(gc3003->reset_gpio, 1);
1479
1480 /* 8192 cycles prior to first SCCB transaction */
1481 delay_us = gc3003_cal_delay(8192);
1482 usleep_range(delay_us, delay_us * 2);
1483
1484 return 0;
1485
1486 disable_clk:
1487 clk_disable_unprepare(gc3003->xvclk);
1488
1489 return ret;
1490 }
1491
__gc3003_power_off(struct gc3003 * gc3003)1492 static void __gc3003_power_off(struct gc3003 *gc3003)
1493 {
1494 int ret;
1495 struct device *dev = &gc3003->client->dev;
1496
1497 clk_disable_unprepare(gc3003->xvclk);
1498 if (gc3003->is_thunderboot) {
1499 if (gc3003->is_first_streamoff) {
1500 gc3003->is_thunderboot = false;
1501 gc3003->is_first_streamoff = false;
1502 } else {
1503 return;
1504 }
1505 }
1506
1507 if (!IS_ERR(gc3003->pwdn_gpio))
1508 gpiod_set_value_cansleep(gc3003->pwdn_gpio, 0);
1509 clk_disable_unprepare(gc3003->xvclk);
1510 if (!IS_ERR(gc3003->reset_gpio))
1511 gpiod_set_value_cansleep(gc3003->reset_gpio, 0);
1512 if (!IS_ERR_OR_NULL(gc3003->pins_sleep)) {
1513 ret = pinctrl_select_state(gc3003->pinctrl,
1514 gc3003->pins_sleep);
1515 if (ret < 0)
1516 dev_dbg(dev, "could not set pins\n");
1517 }
1518 regulator_bulk_disable(GC3003_NUM_SUPPLIES, gc3003->supplies);
1519 }
1520
gc3003_runtime_resume(struct device * dev)1521 static int gc3003_runtime_resume(struct device *dev)
1522 {
1523 struct i2c_client *client = to_i2c_client(dev);
1524 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1525 struct gc3003 *gc3003 = to_gc3003(sd);
1526
1527 return __gc3003_power_on(gc3003);
1528 }
1529
gc3003_runtime_suspend(struct device * dev)1530 static int gc3003_runtime_suspend(struct device *dev)
1531 {
1532 struct i2c_client *client = to_i2c_client(dev);
1533 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1534 struct gc3003 *gc3003 = to_gc3003(sd);
1535
1536 __gc3003_power_off(gc3003);
1537
1538 return 0;
1539 }
1540
1541 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc3003_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1542 static int gc3003_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1543 {
1544 struct gc3003 *gc3003 = to_gc3003(sd);
1545 struct v4l2_mbus_framefmt *try_fmt =
1546 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1547 const struct gc3003_mode *def_mode = &supported_modes[0];
1548
1549 mutex_lock(&gc3003->mutex);
1550 /* Initialize try_fmt */
1551 try_fmt->width = def_mode->width;
1552 try_fmt->height = def_mode->height;
1553 try_fmt->code = def_mode->bus_fmt;
1554 try_fmt->field = V4L2_FIELD_NONE;
1555
1556 mutex_unlock(&gc3003->mutex);
1557 /* No crop or compose */
1558
1559 return 0;
1560 }
1561 #endif
1562
gc3003_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1563 static int gc3003_enum_frame_interval(struct v4l2_subdev *sd,
1564 struct v4l2_subdev_pad_config *cfg,
1565 struct v4l2_subdev_frame_interval_enum *fie)
1566 {
1567 struct gc3003 *gc3003 = to_gc3003(sd);
1568
1569 if (fie->index >= gc3003->cfg_num)
1570 return -EINVAL;
1571
1572 fie->code = supported_modes[fie->index].bus_fmt;
1573 fie->width = supported_modes[fie->index].width;
1574 fie->height = supported_modes[fie->index].height;
1575 fie->interval = supported_modes[fie->index].max_fps;
1576 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1577 return 0;
1578 }
1579
1580 #define DST_WIDTH 2304
1581 #define DST_HEIGHT 1296
1582
1583 /*
1584 * The resolution of the driver configuration needs to be exactly
1585 * the same as the current output resolution of the sensor,
1586 * the input width of the isp needs to be 16 aligned,
1587 * the input height of the isp needs to be 8 aligned.
1588 * Can be cropped to standard resolution by this function,
1589 * otherwise it will crop out strange resolution according
1590 * to the alignment rules.
1591 */
gc3003_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1592 static int gc3003_get_selection(struct v4l2_subdev *sd,
1593 struct v4l2_subdev_pad_config *cfg,
1594 struct v4l2_subdev_selection *sel)
1595 {
1596 /*
1597 * From "Pixel Array Image Drawing in All scan mode",
1598 * there are 12 pixel offset on horizontal and vertical.
1599 */
1600 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1601 sel->r.left = 0;
1602 sel->r.width = DST_WIDTH;
1603 sel->r.top = 0;
1604 sel->r.height = DST_HEIGHT;
1605 return 0;
1606 }
1607 return -EINVAL;
1608 }
1609
1610 static const struct dev_pm_ops gc3003_pm_ops = {
1611 SET_RUNTIME_PM_OPS(gc3003_runtime_suspend,
1612 gc3003_runtime_resume, NULL)
1613 };
1614
1615 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1616 static const struct v4l2_subdev_internal_ops gc3003_internal_ops = {
1617 .open = gc3003_open,
1618 };
1619 #endif
1620
1621 static const struct v4l2_subdev_core_ops gc3003_core_ops = {
1622 .s_power = gc3003_s_power,
1623 .ioctl = gc3003_ioctl,
1624 #ifdef CONFIG_COMPAT
1625 .compat_ioctl32 = gc3003_compat_ioctl32,
1626 #endif
1627 };
1628
1629 static const struct v4l2_subdev_video_ops gc3003_video_ops = {
1630 .s_stream = gc3003_s_stream,
1631 .g_frame_interval = gc3003_g_frame_interval,
1632 };
1633
1634 static const struct v4l2_subdev_pad_ops gc3003_pad_ops = {
1635 .enum_mbus_code = gc3003_enum_mbus_code,
1636 .enum_frame_size = gc3003_enum_frame_sizes,
1637 .enum_frame_interval = gc3003_enum_frame_interval,
1638 .get_fmt = gc3003_get_fmt,
1639 .set_fmt = gc3003_set_fmt,
1640 .get_selection = gc3003_get_selection,
1641 .get_mbus_config = gc3003_g_mbus_config,
1642 };
1643
1644 static const struct v4l2_subdev_ops gc3003_subdev_ops = {
1645 .core = &gc3003_core_ops,
1646 .video = &gc3003_video_ops,
1647 .pad = &gc3003_pad_ops,
1648 };
1649
gc3003_set_ctrl(struct v4l2_ctrl * ctrl)1650 static int gc3003_set_ctrl(struct v4l2_ctrl *ctrl)
1651 {
1652 struct gc3003 *gc3003 = container_of(ctrl->handler,
1653 struct gc3003, ctrl_handler);
1654 struct i2c_client *client = gc3003->client;
1655 s64 max;
1656 int ret = 0;
1657 int val = 0;
1658
1659 /*Propagate change of current control to all related controls*/
1660 switch (ctrl->id) {
1661 case V4L2_CID_VBLANK:
1662 /*Update max exposure while meeting expected vblanking*/
1663 max = gc3003->cur_mode->height + ctrl->val - 4;
1664 __v4l2_ctrl_modify_range(gc3003->exposure,
1665 gc3003->exposure->minimum,
1666 max,
1667 gc3003->exposure->step,
1668 gc3003->exposure->default_value);
1669 break;
1670 }
1671
1672 if (!pm_runtime_get_if_in_use(&client->dev))
1673 return 0;
1674
1675 switch (ctrl->id) {
1676 case V4L2_CID_EXPOSURE:
1677 /* 4 least significant bits of expsoure are fractional part */
1678 ret = gc3003_write_reg(gc3003->client, GC3003_REG_EXPOSURE_H,
1679 GC3003_REG_VALUE_08BIT,
1680 ctrl->val >> 8);
1681 ret |= gc3003_write_reg(gc3003->client, GC3003_REG_EXPOSURE_L,
1682 GC3003_REG_VALUE_08BIT,
1683 ctrl->val & 0xff);
1684 break;
1685 case V4L2_CID_ANALOGUE_GAIN:
1686 ret = gc3003_set_gain_reg(gc3003, ctrl->val);
1687 break;
1688 case V4L2_CID_VBLANK:
1689 gc3003->cur_vts = ctrl->val + gc3003->cur_mode->height;
1690 ret = gc3003_write_reg(gc3003->client, GC3003_REG_VTS_H,
1691 GC3003_REG_VALUE_08BIT,
1692 gc3003->cur_vts >> 8);
1693 ret |= gc3003_write_reg(gc3003->client, GC3003_REG_VTS_L,
1694 GC3003_REG_VALUE_08BIT,
1695 gc3003->cur_vts & 0xff);
1696 break;
1697 case V4L2_CID_TEST_PATTERN:
1698 ret = gc3003_enable_test_pattern(gc3003, ctrl->val);
1699 break;
1700 case V4L2_CID_HFLIP:
1701 ret = gc3003_read_reg(gc3003->client, GC3003_FLIP_MIRROR_REG,
1702 GC3003_REG_VALUE_08BIT, &val);
1703 if (ctrl->val)
1704 val |= GC3003_MIRROR_BIT_MASK;
1705 else
1706 val &= ~GC3003_MIRROR_BIT_MASK;
1707 ret |= gc3003_write_reg(gc3003->client, GC3003_FLIP_MIRROR_REG,
1708 GC3003_REG_VALUE_08BIT, val);
1709 break;
1710 case V4L2_CID_VFLIP:
1711 ret = gc3003_read_reg(gc3003->client, GC3003_FLIP_MIRROR_REG,
1712 GC3003_REG_VALUE_08BIT, &val);
1713 if (ctrl->val)
1714 val |= GC3003_FLIP_BIT_MASK;
1715 else
1716 val &= ~GC3003_FLIP_BIT_MASK;
1717 ret |= gc3003_write_reg(gc3003->client, GC3003_FLIP_MIRROR_REG,
1718 GC3003_REG_VALUE_08BIT, val);
1719 break;
1720 default:
1721 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1722 __func__, ctrl->id, ctrl->val);
1723 break;
1724 }
1725
1726 pm_runtime_put(&client->dev);
1727
1728 return ret;
1729 }
1730
1731 static const struct v4l2_ctrl_ops gc3003_ctrl_ops = {
1732 .s_ctrl = gc3003_set_ctrl,
1733 };
1734
gc3003_initialize_controls(struct gc3003 * gc3003)1735 static int gc3003_initialize_controls(struct gc3003 *gc3003)
1736 {
1737 const struct gc3003_mode *mode;
1738 struct v4l2_ctrl_handler *handler;
1739 s64 exposure_max, vblank_def;
1740 u32 h_blank;
1741 int ret;
1742
1743 handler = &gc3003->ctrl_handler;
1744 mode = gc3003->cur_mode;
1745 ret = v4l2_ctrl_handler_init(handler, 9);
1746 if (ret)
1747 return ret;
1748 handler->lock = &gc3003->mutex;
1749
1750 gc3003->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1751 0, 0, link_freq_menu_items);
1752 gc3003->cur_link_freq = 0;
1753 gc3003->cur_pixel_rate = GC3003_PIXEL_RATE_LINEAR;
1754
1755 __v4l2_ctrl_s_ctrl(gc3003->link_freq,
1756 gc3003->cur_link_freq);
1757
1758 gc3003->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1759 0, GC3003_PIXEL_RATE_LINEAR, 1, GC3003_PIXEL_RATE_LINEAR);
1760
1761 h_blank = mode->hts_def - mode->width;
1762 gc3003->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1763 h_blank, h_blank, 1, h_blank);
1764 if (gc3003->hblank)
1765 gc3003->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1766
1767 vblank_def = mode->vts_def - mode->height;
1768 gc3003->cur_vts = mode->vts_def;
1769 gc3003->vblank = v4l2_ctrl_new_std(handler, &gc3003_ctrl_ops,
1770 V4L2_CID_VBLANK, vblank_def,
1771 GC3003_VTS_MAX - mode->height,
1772 1, vblank_def);
1773
1774 exposure_max = mode->vts_def - 4;
1775 gc3003->exposure = v4l2_ctrl_new_std(handler, &gc3003_ctrl_ops,
1776 V4L2_CID_EXPOSURE,
1777 GC3003_EXPOSURE_MIN,
1778 exposure_max,
1779 GC3003_EXPOSURE_STEP,
1780 mode->exp_def);
1781
1782 gc3003->anal_gain = v4l2_ctrl_new_std(handler, &gc3003_ctrl_ops,
1783 V4L2_CID_ANALOGUE_GAIN,
1784 GC3003_GAIN_MIN,
1785 GC3003_GAIN_MAX,
1786 GC3003_GAIN_STEP,
1787 GC3003_GAIN_DEFAULT);
1788
1789 gc3003->test_pattern =
1790 v4l2_ctrl_new_std_menu_items(handler,
1791 &gc3003_ctrl_ops,
1792 V4L2_CID_TEST_PATTERN,
1793 ARRAY_SIZE(gc3003_test_pattern_menu) - 1,
1794 0, 0, gc3003_test_pattern_menu);
1795
1796 gc3003->h_flip = v4l2_ctrl_new_std(handler, &gc3003_ctrl_ops,
1797 V4L2_CID_HFLIP, 0, 1, 1, 0);
1798
1799 gc3003->v_flip = v4l2_ctrl_new_std(handler, &gc3003_ctrl_ops,
1800 V4L2_CID_VFLIP, 0, 1, 1, 0);
1801 if (handler->error) {
1802 ret = handler->error;
1803 dev_err(&gc3003->client->dev,
1804 "Failed to init controls(%d)\n", ret);
1805 goto err_free_handler;
1806 }
1807
1808 gc3003->subdev.ctrl_handler = handler;
1809 gc3003->has_init_exp = false;
1810
1811 return 0;
1812
1813 err_free_handler:
1814 v4l2_ctrl_handler_free(handler);
1815
1816 return ret;
1817 }
1818
gc3003_check_sensor_id(struct gc3003 * gc3003,struct i2c_client * client)1819 static int gc3003_check_sensor_id(struct gc3003 *gc3003,
1820 struct i2c_client *client)
1821 {
1822 struct device *dev = &gc3003->client->dev;
1823 u16 id = 0;
1824 u32 reg_H = 0;
1825 u32 reg_L = 0;
1826 int ret;
1827
1828 if (gc3003->is_thunderboot) {
1829 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
1830 return 0;
1831 }
1832
1833 ret = gc3003_read_reg(client, GC3003_REG_CHIP_ID_H,
1834 GC3003_REG_VALUE_08BIT, ®_H);
1835 ret |= gc3003_read_reg(client, GC3003_REG_CHIP_ID_L,
1836 GC3003_REG_VALUE_08BIT, ®_L);
1837
1838 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
1839 if (!(reg_H == (CHIP_ID >> 8) || reg_L == (CHIP_ID & 0xff))) {
1840 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1841 return -ENODEV;
1842 }
1843 dev_info(dev, "detected gc%04x sensor\n", id);
1844 return 0;
1845 }
1846
gc3003_configure_regulators(struct gc3003 * gc3003)1847 static int gc3003_configure_regulators(struct gc3003 *gc3003)
1848 {
1849 unsigned int i;
1850
1851 for (i = 0; i < GC3003_NUM_SUPPLIES; i++)
1852 gc3003->supplies[i].supply = gc3003_supply_names[i];
1853
1854 return devm_regulator_bulk_get(&gc3003->client->dev,
1855 GC3003_NUM_SUPPLIES,
1856 gc3003->supplies);
1857 }
1858
gc3003_probe(struct i2c_client * client,const struct i2c_device_id * id)1859 static int gc3003_probe(struct i2c_client *client,
1860 const struct i2c_device_id *id)
1861 {
1862 struct device *dev = &client->dev;
1863 struct device_node *node = dev->of_node;
1864 struct gc3003 *gc3003;
1865 struct v4l2_subdev *sd;
1866 char facing[2];
1867 int ret;
1868 u32 i, hdr_mode = 0;
1869
1870 dev_info(dev, "driver version: %02x.%02x.%02x",
1871 DRIVER_VERSION >> 16,
1872 (DRIVER_VERSION & 0xff00) >> 8,
1873 DRIVER_VERSION & 0x00ff);
1874
1875 gc3003 = devm_kzalloc(dev, sizeof(*gc3003), GFP_KERNEL);
1876 if (!gc3003)
1877 return -ENOMEM;
1878
1879 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1880 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1881 &gc3003->module_index);
1882 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1883 &gc3003->module_facing);
1884 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1885 &gc3003->module_name);
1886 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1887 &gc3003->len_name);
1888 if (ret) {
1889 dev_err(dev, "could not get module information!\n");
1890 return -EINVAL;
1891 }
1892
1893 gc3003->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
1894
1895 gc3003->client = client;
1896 gc3003->cfg_num = ARRAY_SIZE(supported_modes);
1897 for (i = 0; i < gc3003->cfg_num; i++) {
1898 if (hdr_mode == supported_modes[i].hdr_mode) {
1899 gc3003->cur_mode = &supported_modes[i];
1900 break;
1901 }
1902 }
1903 if (i == gc3003->cfg_num)
1904 gc3003->cur_mode = &supported_modes[0];
1905
1906 gc3003->xvclk = devm_clk_get(dev, "xvclk");
1907 if (IS_ERR(gc3003->xvclk)) {
1908 dev_err(dev, "Failed to get xvclk\n");
1909 return -EINVAL;
1910 }
1911
1912 gc3003->pwren_gpio = devm_gpiod_get(dev, "pwren", GPIOD_ASIS);
1913 if (IS_ERR(gc3003->pwren_gpio))
1914 dev_warn(dev, "Failed to get pwren-gpios\n");
1915
1916 gc3003->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1917 if (IS_ERR(gc3003->reset_gpio))
1918 dev_warn(dev, "Failed to get reset-gpios\n");
1919
1920 gc3003->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1921 if (IS_ERR(gc3003->pwdn_gpio))
1922 dev_warn(dev, "Failed to get pwdn-gpios\n");
1923
1924 gc3003->pinctrl = devm_pinctrl_get(dev);
1925 if (!IS_ERR(gc3003->pinctrl)) {
1926 gc3003->pins_default =
1927 pinctrl_lookup_state(gc3003->pinctrl,
1928 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1929 if (IS_ERR(gc3003->pins_default))
1930 dev_err(dev, "could not get default pinstate\n");
1931
1932 gc3003->pins_sleep =
1933 pinctrl_lookup_state(gc3003->pinctrl,
1934 OF_CAMERA_PINCTRL_STATE_SLEEP);
1935 if (IS_ERR(gc3003->pins_sleep))
1936 dev_err(dev, "could not get sleep pinstate\n");
1937 } else {
1938 dev_err(dev, "no pinctrl\n");
1939 }
1940
1941 ret = gc3003_configure_regulators(gc3003);
1942 if (ret) {
1943 dev_err(dev, "Failed to get power regulators\n");
1944 return ret;
1945 }
1946
1947 mutex_init(&gc3003->mutex);
1948
1949 sd = &gc3003->subdev;
1950 v4l2_i2c_subdev_init(sd, client, &gc3003_subdev_ops);
1951 ret = gc3003_initialize_controls(gc3003);
1952 if (ret)
1953 goto err_destroy_mutex;
1954
1955 ret = __gc3003_power_on(gc3003);
1956 if (ret)
1957 goto err_free_handler;
1958
1959 usleep_range(3000, 4000);
1960
1961 ret = gc3003_check_sensor_id(gc3003, client);
1962 if (ret)
1963 goto err_power_off;
1964
1965 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1966 sd->internal_ops = &gc3003_internal_ops;
1967 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1968 V4L2_SUBDEV_FL_HAS_EVENTS;
1969 #endif
1970 #if defined(CONFIG_MEDIA_CONTROLLER)
1971 gc3003->pad.flags = MEDIA_PAD_FL_SOURCE;
1972 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1973 ret = media_entity_pads_init(&sd->entity, 1, &gc3003->pad);
1974 if (ret < 0)
1975 goto err_power_off;
1976 #endif
1977
1978 memset(facing, 0, sizeof(facing));
1979 if (strcmp(gc3003->module_facing, "back") == 0)
1980 facing[0] = 'b';
1981 else
1982 facing[0] = 'f';
1983
1984 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1985 gc3003->module_index, facing,
1986 GC3003_NAME, dev_name(sd->dev));
1987 ret = v4l2_async_register_subdev_sensor_common(sd);
1988 if (ret) {
1989 dev_err(dev, "v4l2 async register subdev failed\n");
1990 goto err_clean_entity;
1991 }
1992
1993 pm_runtime_set_active(dev);
1994 pm_runtime_enable(dev);
1995 if (gc3003->is_thunderboot)
1996 pm_runtime_get_sync(dev);
1997 else
1998 pm_runtime_idle(dev);
1999
2000 return 0;
2001
2002 err_clean_entity:
2003 #if defined(CONFIG_MEDIA_CONTROLLER)
2004 media_entity_cleanup(&sd->entity);
2005 #endif
2006 err_power_off:
2007 __gc3003_power_off(gc3003);
2008 err_free_handler:
2009 v4l2_ctrl_handler_free(&gc3003->ctrl_handler);
2010 err_destroy_mutex:
2011 mutex_destroy(&gc3003->mutex);
2012
2013 return ret;
2014 }
2015
gc3003_remove(struct i2c_client * client)2016 static int gc3003_remove(struct i2c_client *client)
2017 {
2018 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2019 struct gc3003 *gc3003 = to_gc3003(sd);
2020
2021 v4l2_async_unregister_subdev(sd);
2022 #if defined(CONFIG_MEDIA_CONTROLLER)
2023 media_entity_cleanup(&sd->entity);
2024 #endif
2025 v4l2_ctrl_handler_free(&gc3003->ctrl_handler);
2026 mutex_destroy(&gc3003->mutex);
2027
2028 pm_runtime_disable(&client->dev);
2029 if (!pm_runtime_status_suspended(&client->dev))
2030 __gc3003_power_off(gc3003);
2031 pm_runtime_set_suspended(&client->dev);
2032
2033 return 0;
2034 }
2035
2036 #if IS_ENABLED(CONFIG_OF)
2037 static const struct of_device_id gc3003_of_match[] = {
2038 { .compatible = "galaxycore,gc3003" },
2039 {},
2040 };
2041 MODULE_DEVICE_TABLE(of, gc3003_of_match);
2042 #endif
2043
2044 static const struct i2c_device_id gc3003_match_id[] = {
2045 { "galaxycore,gc3003", 0 },
2046 { },
2047 };
2048
2049 static struct i2c_driver gc3003_i2c_driver = {
2050 .driver = {
2051 .name = GC3003_NAME,
2052 .pm = &gc3003_pm_ops,
2053 .of_match_table = of_match_ptr(gc3003_of_match),
2054 },
2055 .probe = &gc3003_probe,
2056 .remove = &gc3003_remove,
2057 .id_table = gc3003_match_id,
2058 };
2059
sensor_mod_init(void)2060 static int __init sensor_mod_init(void)
2061 {
2062 return i2c_add_driver(&gc3003_i2c_driver);
2063 }
2064
sensor_mod_exit(void)2065 static void __exit sensor_mod_exit(void)
2066 {
2067 i2c_del_driver(&gc3003_i2c_driver);
2068 }
2069
2070 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
2071 subsys_initcall(sensor_mod_init);
2072 #else
2073 device_initcall_sync(sensor_mod_init);
2074 #endif
2075 module_exit(sensor_mod_exit);
2076
2077 MODULE_DESCRIPTION("galaxycore gc3003 sensor driver");
2078 MODULE_LICENSE("GPL");
2079