1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc08a3 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 init first version.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/of.h>
18 #include <linux/of_graph.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/sysfs.h>
21 #include <linux/version.h>
22 #include <linux/rk-camera-module.h>
23 #include <media/media-entity.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-device.h>
27 #include <media/v4l2-event.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-image-sizes.h>
30 #include <media/v4l2-mediabus.h>
31 #include <media/v4l2-subdev.h>
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/slab.h>
34
35 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
36
37 #ifndef V4L2_CID_DIGITAL_GAIN
38 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
39 #endif
40
41 #define GC08A3_REG_VALUE_08BIT 1
42 #define GC08A3_REG_VALUE_16BIT 2
43 #define GC08A3_REG_VALUE_24BIT 3
44
45 #define GC08A3_LANES 4
46 #define GC08A3_BITS_PER_SAMPLE 10
47 #define GC08A3_MIPI_FREQ_150MHZ 150000000U
48 #define GC08A3_MIPI_FREQ_350MHZ 350000000U
49 #define GC08A3_MIPI_FREQ_700MHZ 700000000U
50
51 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
52 #define GC08A3_PIXEL_RATE 288000000
53 #define GC08A3_XVCLK_FREQ 24000000
54
55 #define CHIP_ID 0x08a3
56 #define GC08A3_REG_CHIP_ID_H 0x03f0
57 #define GC08A3_REG_CHIP_ID_L 0x03f1
58
59 #define GC08A3_REG_CTRL_MODE 0x0100
60 #define GC08A3_MODE_SW_STANDBY 0x00
61 #define GC08A3_MODE_STREAMING 0x01
62
63 #define GC08A3_REG_EXPOSURE_H 0x0202
64 #define GC08A3_REG_EXPOSURE_L 0x0203
65 #define GC08A3_FETCH_HIGH_BYTE(VAL) (((VAL) >> 8) & 0xFF) /* 4 Bits */
66 #define GC08A3_FETCH_LOW_BYTE(VAL) ((VAL) & 0xFF) /* 8 Bits */
67 #define GC08A3_EXPOSURE_MIN 4
68 #define GC08A3_EXPOSURE_STEP 1
69 #define GC08A3_VTS_MAX 0xfffe
70
71 #define GC08A3_REG_GAIN_H 0x0204
72 #define GC08A3_REG_GAIN_L 0x0205
73
74 #define GC08A3_AGAIN_MIN 0x400
75 #define GC08A3_AGAIN_MAX 0x4000
76 #define GC08A3_AGAIN_STEP 1
77 #define GC08A3_AGAIN_DEFAULT 0x800
78
79 #define GC08A3_REG_VTS_H 0x0340
80 #define GC08A3_REG_VTS_L 0x0341
81
82 #define REG_NULL 0xFFFF
83
84 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
85 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
86
87 #define GC08A3_NAME "gc08a3"
88 #define GC08A3_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
89
90 static const char * const gc08a3_supply_names[] = {
91 "avdd", /* Analog power */
92 "dovdd", /* Digital I/O power */
93 "dvdd", /* Digital core power */
94 };
95
96 #define GC08A3_NUM_SUPPLIES ARRAY_SIZE(gc08a3_supply_names)
97
98 struct gc08a3_id_name {
99 u32 id;
100 char name[RKMODULE_NAME_LEN];
101 };
102
103 struct regval {
104 u16 addr;
105 u8 val;
106 };
107
108 struct gc08a3_mode {
109 u32 width;
110 u32 height;
111 struct v4l2_fract max_fps;
112 u32 hts_def;
113 u32 vts_def;
114 u32 exp_def;
115 const struct regval *reg_list;
116 const struct regval *global_reg_list;
117 u32 mipi_freq_idx;
118 u32 vc[PAD_MAX];
119 };
120
121 struct gc08a3 {
122 struct i2c_client *client;
123 struct clk *xvclk;
124 struct gpio_desc *power_gpio;
125 struct gpio_desc *reset_gpio;
126 struct gpio_desc *pwdn_gpio;
127 struct regulator_bulk_data supplies[GC08A3_NUM_SUPPLIES];
128 struct pinctrl *pinctrl;
129 struct pinctrl_state *pins_default;
130 struct pinctrl_state *pins_sleep;
131 struct v4l2_subdev subdev;
132 struct media_pad pad;
133 struct v4l2_ctrl_handler ctrl_handler;
134 struct v4l2_ctrl *exposure;
135 struct v4l2_ctrl *anal_gain;
136 struct v4l2_ctrl *digi_gain;
137 struct v4l2_ctrl *hblank;
138 struct v4l2_ctrl *vblank;
139 struct v4l2_ctrl *link_freq;
140 struct mutex mutex;
141 bool streaming;
142 unsigned int lane_num;
143 unsigned int cfg_num;
144 unsigned int pixel_rate;
145 bool power_on;
146 const struct gc08a3_mode *cur_mode;
147 const struct gc08a3_mode *support_modes;
148 u32 module_index;
149 const char *module_facing;
150 const char *module_name;
151 const char *len_name;
152 struct rkmodule_inf module_inf;
153 struct rkmodule_awb_cfg awb_cfg;
154 };
155
156 #define to_gc08a3(sd) container_of(sd, struct gc08a3, subdev)
157
158 #undef GC08A3_MIRROR_NORMAL
159 #undef GC08A3_MIRROR_H
160 #undef GC08A3_MIRROR_V
161 #undef GC08A3_MIRROR_HV
162
163 /* SENSOR MIRROR FLIP INFO */
164 #define GC08A3_MIRROR_NORMAL 0
165 #define GC08A3_MIRROR_H 1
166 #define GC08A3_MIRROR_V 0
167 #define GC08A3_MIRROR_HV 0
168
169 #if GC08A3_MIRROR_NORMAL
170 #define GC08A3_MIRROR 0x00
171 #define FULL_STARTY 0x06
172 #define FULL_STARTX 0x08
173 #define BINNING_STARTY 0x03
174 #define BINNING_STARTX 0x03
175 #elif GC08A3_MIRROR_H
176 #define GC08A3_MIRROR 0x01
177 #define FULL_STARTY 0x06
178 #define FULL_STARTX 0x09
179 #define BINNING_STARTY 0x03
180 #define BINNING_STARTX 0x04
181 #elif GC08A3_MIRROR_V
182 #define GC08A3_MIRROR 0x02
183 #define FULL_STARTY 0x07
184 #define FULL_STARTX 0x08
185 #define BINNING_STARTY 0x04
186 #define BINNING_STARTX 0x03
187 #elif GC08A3_MIRROR_HV
188 #define GC08A3_MIRROR 0x03
189 #define FULL_STARTY 0x07
190 #define FULL_STARTX 0x09
191 #define BINNING_STARTY 0x04
192 #define BINNING_STARTX 0x04
193 #else
194 #define GC08A3_MIRROR 0x00
195 #define FULL_STARTY 0x06
196 #define FULL_STARTX 0x08
197 #define BINNING_STARTY 0x03
198 #define BINNING_STARTX 0x03
199 #endif
200
201 /*
202 * Xclk 24Mhz
203 */
204 static const struct regval gc08a3_global_regs_4lane[] = {
205 /*system*/
206 {0x031c, 0x60},
207 {0x0337, 0x04},
208 {0x0335, 0x51},
209 {0x0336, 0x70},
210 {0x0383, 0xbb},
211 {0x031a, 0x00},
212 {0x0321, 0x10},
213 {0x0327, 0x03},
214 {0x0325, 0x40},
215 {0x0326, 0x23},
216 {0x0314, 0x11},
217 {0x0315, 0xd6},
218 {0x0316, 0x01},
219 {0x0334, 0x40},
220 {0x0324, 0x42},
221 {0x031c, 0x00},
222 {0x031c, 0x9f},
223 {0x039a, 0x13},
224 {0x0084, 0x30},
225 {0x02b3, 0x08},
226 {0x0057, 0x0c},
227 {0x05c3, 0x50},
228 {0x0311, 0x90},
229 {0x05a0, 0x02},
230 {0x0074, 0x0a},
231 {0x0059, 0x11},
232 {0x0070, 0x05},
233 {0x0101, GC08A3_MIRROR},
234
235 /*analog*/
236 {0x0344, 0x00},
237 {0x0345, 0x06},
238 {0x0346, 0x00},
239 {0x0347, 0x04},
240 {0x0348, 0x0c},
241 {0x0349, 0xd0},
242 {0x034a, 0x09},
243 {0x034b, 0x9c},
244 {0x0202, 0x09},
245 {0x0203, 0x04},
246 {0x0340, 0x09},
247 {0x0341, 0xf4},
248 {0x0342, 0x07},
249 {0x0343, 0x1c},
250 {0x0219, 0x05},
251 {0x0226, 0x00},
252 {0x0227, 0x28},
253 {0x0e0a, 0x00},
254 {0x0e0b, 0x00},
255 {0x0e24, 0x04},
256 {0x0e25, 0x04},
257 {0x0e26, 0x00},
258 {0x0e27, 0x10},
259 {0x0e01, 0x74},
260 {0x0e03, 0x47},
261 {0x0e04, 0x33},
262 {0x0e05, 0x44},
263 {0x0e06, 0x44},
264 {0x0e0c, 0x1e},
265 {0x0e17, 0x3a},
266 {0x0e18, 0x3c},
267 {0x0e19, 0x40},
268 {0x0e1a, 0x42},
269 {0x0e28, 0x21},
270 {0x0e2b, 0x68},
271 {0x0e2c, 0x0d},
272 {0x0e2d, 0x08},
273 {0x0e34, 0xf4},
274 {0x0e35, 0x44},
275 {0x0e36, 0x07},
276 {0x0e38, 0x49},
277 {0x0210, 0x13},
278 {0x0218, 0x00},
279 {0x0241, 0x88},
280 {0x0e32, 0x00},
281 {0x0e33, 0x18},
282 {0x0e42, 0x03},
283 {0x0e43, 0x80},
284 {0x0e44, 0x04},
285 {0x0e45, 0x00},
286 {0x0e4f, 0x04},
287 {0x057a, 0x20},
288 {0x0381, 0x7c},
289 {0x0382, 0x9b},
290 {0x0384, 0xfb},
291 {0x0389, 0x38},
292 {0x038a, 0x03},
293 {0x0390, 0x6a},
294 {0x0391, 0x0b},
295 {0x0392, 0x60},
296 {0x0393, 0xc1},
297 {0x0396, 0xff},
298 {0x0398, 0x62},
299
300 /*cisctl reset*/
301 {0x031c, 0x80},
302 {0x03fe, 0x10},
303 {0x03fe, 0x00},
304 {0x031c, 0x9f},
305 {0x03fe, 0x00},
306 {0x03fe, 0x00},
307 {0x03fe, 0x00},
308 {0x03fe, 0x00},
309 {0x031c, 0x80},
310 {0x03fe, 0x10},
311 {0x03fe, 0x00},
312 {0x031c, 0x9f},
313 {0x0360, 0x01},
314 {0x0360, 0x00},
315 {0x0316, 0x09},
316 {0x0a67, 0x80},
317 {0x0313, 0x00},
318 {0x0a53, 0x0e},
319 {0x0a65, 0x17},
320 {0x0a68, 0xa1},
321 {0x0a58, 0x00},
322 {0x0ace, 0x0c},
323 {0x00a4, 0x00},
324 {0x00a5, 0x01},
325 {0x00a7, 0x09},
326 {0x00a8, 0x9c},
327 {0x00a9, 0x0c},
328 {0x00aa, 0xd0},
329 {0x0a8a, 0x00},
330 {0x0a8b, 0xe0},
331 {0x0a8c, 0x13},
332 {0x0a8d, 0xe8},
333 {0x0a90, 0x0a},
334 {0x0a91, 0x10},
335 {0x0a92, 0xf8},
336 {0x0a71, 0xf2},
337 {0x0a72, 0x12},
338 {0x0a73, 0x64},
339 {0x0a75, 0x41},
340 {0x0a70, 0x07},
341 {0x0313, 0x80},
342
343 /*ISP*/
344 {0x00a0, 0x01},
345 {0x0080, 0xd2},
346 {0x0081, 0x3f},
347 {0x0087, 0x51},
348 {0x0089, 0x03},
349 {0x009b, 0x40},
350 {0x05a0, 0x82},
351 {0x05ac, 0x00},
352 {0x05ad, 0x01},
353 {0x05ae, 0x00},
354 {0x0800, 0x0a},
355 {0x0801, 0x14},
356 {0x0802, 0x28},
357 {0x0803, 0x34},
358 {0x0804, 0x0e},
359 {0x0805, 0x33},
360 {0x0806, 0x03},
361 {0x0807, 0x8a},
362 {0x0808, 0x50},
363 {0x0809, 0x00},
364 {0x080a, 0x34},
365 {0x080b, 0x03},
366 {0x080c, 0x26},
367 {0x080d, 0x03},
368 {0x080e, 0x18},
369 {0x080f, 0x03},
370 {0x0810, 0x10},
371 {0x0811, 0x03},
372 {0x0812, 0x00},
373 {0x0813, 0x00},
374 {0x0814, 0x01},
375 {0x0815, 0x00},
376 {0x0816, 0x01},
377 {0x0817, 0x00},
378 {0x0818, 0x00},
379 {0x0819, 0x0a},
380 {0x081a, 0x01},
381 {0x081b, 0x6c},
382 {0x081c, 0x00},
383 {0x081d, 0x0b},
384 {0x081e, 0x02},
385 {0x081f, 0x00},
386 {0x0820, 0x00},
387 {0x0821, 0x0c},
388 {0x0822, 0x02},
389 {0x0823, 0xd9},
390 {0x0824, 0x00},
391 {0x0825, 0x0d},
392 {0x0826, 0x03},
393 {0x0827, 0xf0},
394 {0x0828, 0x00},
395 {0x0829, 0x0e},
396 {0x082a, 0x05},
397 {0x082b, 0x94},
398 {0x082c, 0x09},
399 {0x082d, 0x6e},
400 {0x082e, 0x07},
401 {0x082f, 0xe6},
402 {0x0830, 0x10},
403 {0x0831, 0x0e},
404 {0x0832, 0x0b},
405 {0x0833, 0x2c},
406 {0x0834, 0x14},
407 {0x0835, 0xae},
408 {0x0836, 0x0f},
409 {0x0837, 0xc4},
410 {0x0838, 0x18},
411 {0x0839, 0x0e},
412 {0x05ac, 0x01},
413 {0x059a, 0x00},
414 {0x059b, 0x00},
415 {0x059c, 0x01},
416 {0x0598, 0x00},
417 {0x0597, 0x14},
418 {0x05ab, 0x09},
419 {0x05a4, 0x02},
420 {0x05a3, 0x05},
421 {0x05a0, 0xc2},
422 {0x0207, 0xc4},
423
424 /*GAIN*/
425 {0x0208, 0x01},
426 {0x0209, 0x72},
427 {0x0204, 0x04},
428 {0x0205, 0x00},
429
430 {0x0040, 0x22},
431 {0x0041, 0x20},
432 {0x0043, 0x10},
433 {0x0044, 0x00},
434 {0x0046, 0x08},
435 {0x0047, 0xf0},
436 {0x0048, 0x0f},
437 {0x004b, 0x0f},
438 {0x004c, 0x00},
439 {0x0050, 0x5c},
440 {0x0051, 0x44},
441 {0x005b, 0x03},
442 {0x00c0, 0x00},
443 {0x00c1, 0x80},
444 {0x00c2, 0x31},
445 {0x00c3, 0x00},
446 {0x0460, 0x04},
447 {0x0462, 0x08},
448 {0x0464, 0x0e},
449 {0x0466, 0x0a},
450 {0x0468, 0x12},
451 {0x046a, 0x12},
452 {0x046c, 0x10},
453 {0x046e, 0x0c},
454 {0x0461, 0x03},
455 {0x0463, 0x03},
456 {0x0465, 0x03},
457 {0x0467, 0x03},
458 {0x0469, 0x04},
459 {0x046b, 0x04},
460 {0x046d, 0x04},
461 {0x046f, 0x04},
462 {0x0470, 0x04},
463 {0x0472, 0x10},
464 {0x0474, 0x26},
465 {0x0476, 0x38},
466 {0x0478, 0x20},
467 {0x047a, 0x30},
468 {0x047c, 0x38},
469 {0x047e, 0x60},
470 {0x0471, 0x05},
471 {0x0473, 0x05},
472 {0x0475, 0x05},
473 {0x0477, 0x05},
474 {0x0479, 0x04},
475 {0x047b, 0x04},
476 {0x047d, 0x04},
477 {0x047f, 0x04},
478
479 {REG_NULL, 0x00},
480 };
481
482 /*
483 * Xclk 24Mhz
484 * max_framerate 30fps
485 * mipi_datarate per lane 700Mbps
486 */
487 static const struct regval gc08a3_3264x2448_regs_4lane[] = {
488 /*system*/
489 {0x031c, 0x60},
490 {0x0337, 0x04},
491 {0x0335, 0x51},
492 {0x0336, 0x70},
493 {0x0383, 0xbb},
494 {0x031a, 0x00},
495 {0x0321, 0x10},
496 {0x0327, 0x03},
497 {0x0325, 0x40},
498 {0x0326, 0x23},
499 {0x0314, 0x11},
500 {0x0315, 0xd6},
501 {0x0316, 0x01},
502 {0x0334, 0x40},
503 {0x0324, 0x42},
504 {0x031c, 0x00},
505 {0x031c, 0x9f},
506 {0x0344, 0x00},
507 {0x0345, 0x06},
508 {0x0346, 0x00},
509 {0x0347, 0x04},
510 {0x0348, 0x0c},
511 {0x0349, 0xd0},
512 {0x034a, 0x09},
513 {0x034b, 0x9c},
514 {0x0202, 0x09},
515 {0x0203, 0x04},
516 {0x0340, 0x09},
517 {0x0341, 0xf4},
518 {0x0342, 0x07},
519 {0x0343, 0x1c},
520 {0x0226, 0x00},
521 {0x0227, 0x28},
522 {0x0e38, 0x49},
523 {0x0210, 0x13},
524 {0x0218, 0x00},
525 {0x0241, 0x88},
526 {0x0392, 0x60},
527
528 /*ISP*/
529 {0x031c, 0x80},
530 {0x03fe, 0x10},
531 {0x03fe, 0x00},
532 {0x031c, 0x9f},
533 {0x03fe, 0x00},
534 {0x03fe, 0x00},
535 {0x03fe, 0x00},
536 {0x03fe, 0x00},
537 {0x031c, 0x80},
538 {0x03fe, 0x10},
539 {0x03fe, 0x00},
540 {0x031c, 0x9f},
541 {0x00a2, 0x00},
542 {0x00a3, 0x00},
543 {0x00ab, 0x00},
544 {0x00ac, 0x00},
545 {0x05a0, 0x82},
546 {0x05ac, 0x00},
547 {0x05ad, 0x01},
548 {0x05ae, 0x00},
549 {0x0800, 0x0a},
550 {0x0801, 0x14},
551 {0x0802, 0x28},
552 {0x0803, 0x34},
553 {0x0804, 0x0e},
554 {0x0805, 0x33},
555 {0x0806, 0x03},
556 {0x0807, 0x8a},
557 {0x0808, 0x50},
558 {0x0809, 0x00},
559 {0x080a, 0x34},
560 {0x080b, 0x03},
561 {0x080c, 0x26},
562 {0x080d, 0x03},
563 {0x080e, 0x18},
564 {0x080f, 0x03},
565 {0x0810, 0x10},
566 {0x0811, 0x03},
567 {0x0812, 0x00},
568 {0x0813, 0x00},
569 {0x0814, 0x01},
570 {0x0815, 0x00},
571 {0x0816, 0x01},
572 {0x0817, 0x00},
573 {0x0818, 0x00},
574 {0x0819, 0x0a},
575 {0x081a, 0x01},
576 {0x081b, 0x6c},
577 {0x081c, 0x00},
578 {0x081d, 0x0b},
579 {0x081e, 0x02},
580 {0x081f, 0x00},
581 {0x0820, 0x00},
582 {0x0821, 0x0c},
583 {0x0822, 0x02},
584 {0x0823, 0xd9},
585 {0x0824, 0x00},
586 {0x0825, 0x0d},
587 {0x0826, 0x03},
588 {0x0827, 0xf0},
589 {0x0828, 0x00},
590 {0x0829, 0x0e},
591 {0x082a, 0x05},
592 {0x082b, 0x94},
593 {0x082c, 0x09},
594 {0x082d, 0x6e},
595 {0x082e, 0x07},
596 {0x082f, 0xe6},
597 {0x0830, 0x10},
598 {0x0831, 0x0e},
599 {0x0832, 0x0b},
600 {0x0833, 0x2c},
601 {0x0834, 0x14},
602 {0x0835, 0xae},
603 {0x0836, 0x0f},
604 {0x0837, 0xc4},
605 {0x0838, 0x18},
606 {0x0839, 0x0e},
607 {0x05ac, 0x01},
608 {0x059a, 0x00},
609 {0x059b, 0x00},
610 {0x059c, 0x01},
611 {0x0598, 0x00},
612 {0x0597, 0x14},
613 {0x05ab, 0x09},
614 {0x05a4, 0x02},
615 {0x05a3, 0x05},
616 {0x05a0, 0xc2},
617 {0x0207, 0xc4},
618
619 /*GAIN*/
620 {0x0204, 0x04},
621 {0x0205, 0x00},
622 {0x0050, 0x5c},
623 {0x0051, 0x44},
624
625 /*out window*/
626 {0x009a, 0x00},
627 {0x0351, 0x00},
628 {0x0352, FULL_STARTY},
629 {0x0353, 0x00},
630 {0x0354, FULL_STARTX},
631 {0x034c, 0x0c},
632 {0x034d, 0xc0},
633 {0x034e, 0x09},
634 {0x034f, 0x90},
635
636 /*MIPI*/
637 {0x0114, 0x03},
638 {0x0180, 0x67},
639 {0x0181, 0xf0},
640 {0x0185, 0x01},
641 {0x0115, 0x30},
642 {0x011b, 0x12},
643 {0x011c, 0x12},
644 {0x0121, 0x06},
645 {0x0122, 0x06},
646 {0x0123, 0x15},
647 {0x0124, 0x01},
648 {0x0125, 0x0b},
649 {0x0126, 0x08},
650 {0x0129, 0x06},
651 {0x012a, 0x08},
652 {0x012b, 0x08},
653
654 {0x0a73, 0x60},
655 {0x0a70, 0x11},
656 {0x0313, 0x80},
657 {0x0aff, 0x00},
658 {0x0aff, 0x00},
659 {0x0aff, 0x00},
660 {0x0aff, 0x00},
661 {0x0aff, 0x00},
662 {0x0aff, 0x00},
663 {0x0aff, 0x00},
664 {0x0aff, 0x00},
665 {0x0a70, 0x00},
666 {0x00a4, 0x80},
667 {0x0316, 0x01},
668 {0x0a67, 0x00},
669 {0x0084, 0x10},
670 {0x0102, 0x09},
671
672 {REG_NULL, 0x00},
673 };
674
675 /*
676 * Xclk 24Mhz
677 * max_framerate 30fps
678 * mipi_datarate per lane 350Mbps
679 */
680 static const struct regval gc08a3_1280x720_regs_4lane[] = {
681 /*system*/
682 {0x031c, 0x60},
683 {0x0337, 0x04},
684 {0x0335, 0x55},
685 {0x0336, 0x5d},
686 {0x0383, 0x9b},
687 {0x031a, 0x00},
688 {0x0321, 0x10},
689 {0x0327, 0x03},
690 {0x0325, 0x40},
691 {0x0326, 0x23},
692 {0x0314, 0x11},
693 {0x0315, 0xd6},
694 {0x0316, 0x01},
695 {0x0334, 0x40},
696 {0x0324, 0x42},
697 {0x031c, 0x00},
698 {0x031c, 0x9f},
699 {0x0344, 0x01},
700 {0x0345, 0x66},
701 {0x0346, 0x01},
702 {0x0347, 0xfc},
703 {0x0348, 0x0a},
704 {0x0349, 0x10},
705 {0x034a, 0x05},
706 {0x034b, 0xac},
707 {0x0202, 0x03},
708 {0x0203, 0x00},
709 {0x0340, 0x09},
710 {0x0341, 0xf4},
711 {0x0342, 0x07},
712 {0x0343, 0x1c},
713 {0x0226, 0x00},
714 {0x0227, 0x56},
715 {0x0e38, 0x49},
716 {0x0210, 0x53},
717 {0x0218, 0x80},
718 {0x0241, 0x8c},
719 {0x0392, 0x3b},
720 /*ISP*/
721 {0x031c, 0x80},
722 {0x03fe, 0x10},
723 {0x03fe, 0x00},
724 {0x031c, 0x9f},
725 {0x03fe, 0x00},
726 {0x03fe, 0x00},
727 {0x03fe, 0x00},
728 {0x03fe, 0x00},
729 {0x031c, 0x80},
730 {0x03fe, 0x10},
731 {0x03fe, 0x00},
732 {0x031c, 0x9f},
733 {0x00a2, 0xf8},
734 {0x00a3, 0x01},
735 {0x00ab, 0x60},
736 {0x00ac, 0x01},
737 {0x05a0, 0x82},
738 {0x05ac, 0x00},
739 {0x05ad, 0x01},
740 {0x05ae, 0x00},
741 {0x0800, 0x0a},
742 {0x0801, 0x14},
743 {0x0802, 0x28},
744 {0x0803, 0x34},
745 {0x0804, 0x0e},
746 {0x0805, 0x33},
747 {0x0806, 0x03},
748 {0x0807, 0x8a},
749 {0x0808, 0x50},
750 {0x0809, 0x00},
751 {0x080a, 0x34},
752 {0x080b, 0x03},
753 {0x080c, 0x26},
754 {0x080d, 0x03},
755 {0x080e, 0x18},
756 {0x080f, 0x03},
757 {0x0810, 0x10},
758 {0x0811, 0x03},
759 {0x0812, 0x00},
760 {0x0813, 0x00},
761 {0x0814, 0x01},
762 {0x0815, 0x00},
763 {0x0816, 0x01},
764 {0x0817, 0x00},
765 {0x0818, 0x00},
766 {0x0819, 0x0a},
767 {0x081a, 0x01},
768 {0x081b, 0x6c},
769 {0x081c, 0x00},
770 {0x081d, 0x0b},
771 {0x081e, 0x02},
772 {0x081f, 0x00},
773 {0x0820, 0x00},
774 {0x0821, 0x0c},
775 {0x0822, 0x02},
776 {0x0823, 0xd9},
777 {0x0824, 0x00},
778 {0x0825, 0x0d},
779 {0x0826, 0x03},
780 {0x0827, 0xf0},
781 {0x0828, 0x00},
782 {0x0829, 0x0e},
783 {0x082a, 0x05},
784 {0x082b, 0x94},
785 {0x082c, 0x09},
786 {0x082d, 0x6e},
787 {0x082e, 0x07},
788 {0x082f, 0xe6},
789 {0x0830, 0x10},
790 {0x0831, 0x0e},
791 {0x0832, 0x0b},
792 {0x0833, 0x2c},
793 {0x0834, 0x14},
794 {0x0835, 0xae},
795 {0x0836, 0x0f},
796 {0x0837, 0xc4},
797 {0x0838, 0x18},
798 {0x0839, 0x0e},
799 {0x05ac, 0x01},
800 {0x059a, 0x00},
801 {0x059b, 0x00},
802 {0x059c, 0x01},
803 {0x0598, 0x00},
804 {0x0597, 0x14},
805 {0x05ab, 0x09},
806 {0x05a4, 0x02},
807 {0x05a3, 0x05},
808 {0x05a0, 0xc2},
809 {0x0207, 0xc4},
810 /*GAIN*/
811 {0x0204, 0x04},
812 {0x0205, 0x00},
813 {0x0050, 0x48},
814 {0x0051, 0x30},
815 /*out window*/
816 {0x009a, 0x00},
817 {0x0351, 0x00},
818 {0x0352, BINNING_STARTY},
819 {0x0353, 0x00},
820 {0x0354, BINNING_STARTX},
821 {0x034c, 0x05},
822 {0x034d, 0x00},
823 {0x034e, 0x02},
824 {0x034f, 0xd0},
825 /*MIPI*/
826 {0x0114, 0x03},
827 {0x0180, 0x67},
828 {0x0181, 0xf0},
829 {0x0185, 0x01},
830 {0x0115, 0x30},
831 {0x011b, 0x12},
832 {0x011c, 0x12},
833 {0x0121, 0x01},
834 {0x0122, 0x02},
835 {0x0123, 0x07},
836 {0x0124, 0x00},
837 {0x0125, 0x07},
838 {0x0126, 0x04},
839 {0x0129, 0x02},
840 {0x012a, 0x01},
841 {0x012b, 0x04},
842 {0x0a73, 0x60},
843 {0x0a70, 0x11},
844 {0x0313, 0x80},
845 {0x0aff, 0x00},
846 {0x0aff, 0x00},
847 {0x0aff, 0x00},
848 {0x0aff, 0x00},
849 {0x0aff, 0x00},
850 {0x0aff, 0x00},
851 {0x0aff, 0x00},
852 {0x0aff, 0x00},
853 {0x0a70, 0x00},
854 {0x00a4, 0x80},
855 {0x0316, 0x01},
856 {0x0a67, 0x00},
857 {0x0084, 0x10},
858 {0x0102, 0x09},
859 {REG_NULL, 0x00},
860 };
861
862 /*
863 * Xclk 24Mhz
864 * max_framerate 30fps
865 * mipi_datarate per lane 350Mbps
866 */
867 static const struct regval gc08a3_1280x800_regs_4lane[] = {
868 /*system*/
869 {0x031c, 0x60},
870 {0x0337, 0x04},
871 {0x0335, 0x55},
872 {0x0336, 0x5d},
873 {0x0383, 0x9b},
874 {0x031a, 0x00},
875 {0x0321, 0x10},
876 {0x0327, 0x03},
877 {0x0325, 0x40},
878 {0x0326, 0x23},
879 {0x0314, 0x11},
880 {0x0315, 0xd6},
881 {0x0316, 0x01},
882 {0x0334, 0x40},
883 {0x0324, 0x42},
884 {0x031c, 0x00},
885 {0x031c, 0x9f},
886 {0x0344, 0x01},
887 {0x0345, 0x66},
888 {0x0346, 0x01},
889 {0x0347, 0xaa},
890 {0x0348, 0x0a},
891 {0x0349, 0x10},
892 {0x034a, 0x06},
893 {0x034b, 0x50},
894
895 {0x0202, 0x03},
896 {0x0203, 0x00},
897 {0x0340, 0x09},
898 {0x0341, 0xf4},
899 {0x0342, 0x07},
900 {0x0343, 0x1c},
901 {0x0226, 0x00},
902 {0x0227, 0x56},
903 {0x0e38, 0x49},
904 {0x0210, 0x53},
905 {0x0218, 0x80},
906 {0x0241, 0x8c},
907 {0x0392, 0x3b},
908 /*ISP*/
909 {0x031c, 0x80},
910 {0x03fe, 0x10},
911 {0x03fe, 0x00},
912 {0x031c, 0x9f},
913 {0x03fe, 0x00},
914 {0x03fe, 0x00},
915 {0x03fe, 0x00},
916 {0x03fe, 0x00},
917 {0x031c, 0x80},
918 {0x03fe, 0x10},
919 {0x03fe, 0x00},
920 {0x031c, 0x9f},
921 {0x00a2, 0xf8},
922 {0x00a3, 0x01},
923 {0x00ab, 0x60},
924 {0x00ac, 0x01},
925 {0x05a0, 0x82},
926 {0x05ac, 0x00},
927 {0x05ad, 0x01},
928 {0x05ae, 0x00},
929 {0x0800, 0x0a},
930 {0x0801, 0x14},
931 {0x0802, 0x28},
932 {0x0803, 0x34},
933 {0x0804, 0x0e},
934 {0x0805, 0x33},
935 {0x0806, 0x03},
936 {0x0807, 0x8a},
937 {0x0808, 0x50},
938 {0x0809, 0x00},
939 {0x080a, 0x34},
940 {0x080b, 0x03},
941 {0x080c, 0x26},
942 {0x080d, 0x03},
943 {0x080e, 0x18},
944 {0x080f, 0x03},
945 {0x0810, 0x10},
946 {0x0811, 0x03},
947 {0x0812, 0x00},
948 {0x0813, 0x00},
949 {0x0814, 0x01},
950 {0x0815, 0x00},
951 {0x0816, 0x01},
952 {0x0817, 0x00},
953 {0x0818, 0x00},
954 {0x0819, 0x0a},
955 {0x081a, 0x01},
956 {0x081b, 0x6c},
957 {0x081c, 0x00},
958 {0x081d, 0x0b},
959 {0x081e, 0x02},
960 {0x081f, 0x00},
961 {0x0820, 0x00},
962 {0x0821, 0x0c},
963 {0x0822, 0x02},
964 {0x0823, 0xd9},
965 {0x0824, 0x00},
966 {0x0825, 0x0d},
967 {0x0826, 0x03},
968 {0x0827, 0xf0},
969 {0x0828, 0x00},
970 {0x0829, 0x0e},
971 {0x082a, 0x05},
972 {0x082b, 0x94},
973 {0x082c, 0x09},
974 {0x082d, 0x6e},
975 {0x082e, 0x07},
976 {0x082f, 0xe6},
977 {0x0830, 0x10},
978 {0x0831, 0x0e},
979 {0x0832, 0x0b},
980 {0x0833, 0x2c},
981 {0x0834, 0x14},
982 {0x0835, 0xae},
983 {0x0836, 0x0f},
984 {0x0837, 0xc4},
985 {0x0838, 0x18},
986 {0x0839, 0x0e},
987 {0x05ac, 0x01},
988 {0x059a, 0x00},
989 {0x059b, 0x00},
990 {0x059c, 0x01},
991 {0x0598, 0x00},
992 {0x0597, 0x14},
993 {0x05ab, 0x09},
994 {0x05a4, 0x02},
995 {0x05a3, 0x05},
996 {0x05a0, 0xc2},
997 {0x0207, 0xc4},
998 /*GAIN*/
999 {0x0204, 0x04},
1000 {0x0205, 0x00},
1001 {0x0050, 0x48},
1002 {0x0051, 0x30},
1003 /*out window*/
1004 {0x009a, 0x00},
1005 {0x0351, 0x00},
1006 {0x0352, BINNING_STARTY},
1007 {0x0353, 0x00},
1008 {0x0354, BINNING_STARTX},
1009 {0x034c, 0x05},
1010 {0x034d, 0x00},
1011 {0x034e, 0x03},
1012 {0x034f, 0x20},
1013 /*MIPI*/
1014 {0x0114, 0x03},
1015 {0x0180, 0x67},
1016 {0x0181, 0xf0},
1017 {0x0185, 0x01},
1018 {0x0115, 0x30},
1019 {0x011b, 0x12},
1020 {0x011c, 0x12},
1021 {0x0121, 0x01},
1022 {0x0122, 0x02},
1023 {0x0123, 0x07},
1024 {0x0124, 0x00},
1025 {0x0125, 0x07},
1026 {0x0126, 0x04},
1027 {0x0129, 0x02},
1028 {0x012a, 0x01},
1029 {0x012b, 0x04},
1030 {0x0a73, 0x60},
1031 {0x0a70, 0x11},
1032 {0x0313, 0x80},
1033 {0x0aff, 0x00},
1034 {0x0aff, 0x00},
1035 {0x0aff, 0x00},
1036 {0x0aff, 0x00},
1037 {0x0aff, 0x00},
1038 {0x0aff, 0x00},
1039 {0x0aff, 0x00},
1040 {0x0aff, 0x00},
1041 {0x0a70, 0x00},
1042 {0x00a4, 0x80},
1043 {0x0316, 0x01},
1044 {0x0a67, 0x00},
1045 {0x0084, 0x10},
1046 {0x0102, 0x09},
1047 {REG_NULL, 0x00},
1048 };
1049
1050 static const struct gc08a3_mode supported_modes_4lane[] = {
1051 {
1052 .width = 3264,
1053 .height = 2448,
1054 .max_fps = {
1055 .numerator = 10000,
1056 .denominator = 300000,
1057 },
1058 .exp_def = 0x0900,
1059 .hts_def = 0x0568 * 4,
1060 .vts_def = 0x0a04,
1061 .reg_list = gc08a3_3264x2448_regs_4lane,
1062 .global_reg_list = gc08a3_global_regs_4lane,
1063 .mipi_freq_idx = 1,
1064 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1065 },
1066 {
1067 .width = 1280,
1068 .height = 800,
1069 .max_fps = {
1070 .numerator = 10000,
1071 .denominator = 300000,
1072 },
1073 .exp_def = 0x0900,
1074 .hts_def = 0x0568 * 4,
1075 .vts_def = 0x0a04,
1076 .reg_list = gc08a3_1280x800_regs_4lane,
1077 .global_reg_list = gc08a3_global_regs_4lane,
1078 .mipi_freq_idx = 0,
1079 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1080 },
1081 {
1082 .width = 1280,
1083 .height = 720,
1084 .max_fps = {
1085 .numerator = 10000,
1086 .denominator = 300000,
1087 },
1088 .exp_def = 0x0900,
1089 .hts_def = 0x0568 * 4,
1090 .vts_def = 0x0a04,
1091 .reg_list = gc08a3_1280x720_regs_4lane,
1092 .global_reg_list = gc08a3_global_regs_4lane,
1093 .mipi_freq_idx = 0,
1094 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1095 },
1096 };
1097
1098 static const s64 link_freq_menu_items[] = {
1099 GC08A3_MIPI_FREQ_150MHZ,
1100 GC08A3_MIPI_FREQ_350MHZ,
1101 GC08A3_MIPI_FREQ_700MHZ
1102 };
1103
gc08a3_write_reg(struct i2c_client * client,u16 reg,u8 val)1104 static int gc08a3_write_reg(struct i2c_client *client, u16 reg, u8 val)
1105 {
1106 struct i2c_msg msg;
1107 u8 buf[3];
1108 int ret;
1109
1110 buf[0] = reg >> 8;
1111 buf[1] = reg & 0xff;
1112 buf[2] = val;
1113
1114 msg.addr = client->addr;
1115 msg.flags = client->flags;
1116 msg.buf = buf;
1117 msg.len = sizeof(buf);
1118
1119 ret = i2c_transfer(client->adapter, &msg, 1);
1120 if (ret >= 0)
1121 return 0;
1122
1123 dev_err(&client->dev,
1124 "gc08a3 write reg(0x%x val:0x%x) failed !\n", reg, val);
1125
1126 return ret;
1127 }
1128
gc08a3_write_array(struct i2c_client * client,const struct regval * regs)1129 static int gc08a3_write_array(struct i2c_client *client,
1130 const struct regval *regs)
1131 {
1132 u32 i = 0;
1133 int ret = 0;
1134
1135 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
1136 ret = gc08a3_write_reg(client, regs[i].addr, regs[i].val);
1137
1138 return ret;
1139 }
1140
1141 /* Read registers up to 4 at a time */
gc08a3_read_reg(struct i2c_client * client,u16 reg,u8 * val)1142 static int gc08a3_read_reg(struct i2c_client *client, u16 reg, u8 *val)
1143 {
1144 struct i2c_msg msg[2];
1145 u8 buf[2];
1146 int ret;
1147
1148 buf[0] = reg >> 8;
1149 buf[1] = reg & 0xff;
1150
1151 msg[0].addr = client->addr;
1152 msg[0].flags = client->flags;
1153 msg[0].buf = buf;
1154 msg[0].len = sizeof(buf);
1155
1156 msg[1].addr = client->addr;
1157 msg[1].flags = client->flags | I2C_M_RD;
1158 msg[1].buf = buf;
1159 msg[1].len = 1;
1160
1161 ret = i2c_transfer(client->adapter, msg, 2);
1162 if (ret >= 0) {
1163 *val = buf[0];
1164 return 0;
1165 }
1166
1167 dev_err(&client->dev,
1168 "gc08a3 read reg:0x%x failed !\n", reg);
1169
1170 return ret;
1171 }
1172
gc08a3_get_reso_dist(const struct gc08a3_mode * mode,struct v4l2_mbus_framefmt * framefmt)1173 static int gc08a3_get_reso_dist(const struct gc08a3_mode *mode,
1174 struct v4l2_mbus_framefmt *framefmt)
1175 {
1176 return abs(mode->width - framefmt->width) +
1177 abs(mode->height - framefmt->height);
1178 }
1179
1180 static const struct gc08a3_mode *
gc08a3_find_best_fit(struct gc08a3 * gc08a3,struct v4l2_subdev_format * fmt)1181 gc08a3_find_best_fit(struct gc08a3 *gc08a3,
1182 struct v4l2_subdev_format *fmt)
1183 {
1184 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1185 int dist;
1186 int cur_best_fit = 0;
1187 int cur_best_fit_dist = -1;
1188 unsigned int i;
1189
1190 for (i = 0; i < gc08a3->cfg_num; i++) {
1191 dist = gc08a3_get_reso_dist(&gc08a3->support_modes[i], framefmt);
1192 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1193 cur_best_fit_dist = dist;
1194 cur_best_fit = i;
1195 }
1196 }
1197
1198 return &gc08a3->support_modes[cur_best_fit];
1199 }
1200
gc08a3_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1201 static int gc08a3_set_fmt(struct v4l2_subdev *sd,
1202 struct v4l2_subdev_pad_config *cfg,
1203 struct v4l2_subdev_format *fmt)
1204 {
1205 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1206 const struct gc08a3_mode *mode;
1207 s64 h_blank, vblank_def;
1208
1209 mutex_lock(&gc08a3->mutex);
1210
1211 mode = gc08a3_find_best_fit(gc08a3, fmt);
1212 fmt->format.code = GC08A3_MEDIA_BUS_FMT;
1213 fmt->format.width = mode->width;
1214 fmt->format.height = mode->height;
1215 fmt->format.field = V4L2_FIELD_NONE;
1216 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1217 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1218 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1219 #else
1220 mutex_unlock(&gc08a3->mutex);
1221 return -ENOTTY;
1222 #endif
1223 } else {
1224 gc08a3->cur_mode = mode;
1225 h_blank = mode->hts_def - mode->width;
1226 __v4l2_ctrl_modify_range(gc08a3->hblank, h_blank,
1227 h_blank, 1, h_blank);
1228 vblank_def = mode->vts_def - mode->height;
1229 __v4l2_ctrl_modify_range(gc08a3->vblank, vblank_def,
1230 GC08A3_VTS_MAX - mode->height,
1231 1, vblank_def);
1232 __v4l2_ctrl_s_ctrl(gc08a3->link_freq,
1233 mode->mipi_freq_idx);
1234 }
1235 dev_info(&gc08a3->client->dev, "%s: mode->mipi_freq_idx(%d)",
1236 __func__, mode->mipi_freq_idx);
1237
1238 mutex_unlock(&gc08a3->mutex);
1239
1240 return 0;
1241 }
1242
gc08a3_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1243 static int gc08a3_get_fmt(struct v4l2_subdev *sd,
1244 struct v4l2_subdev_pad_config *cfg,
1245 struct v4l2_subdev_format *fmt)
1246 {
1247 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1248 const struct gc08a3_mode *mode = gc08a3->cur_mode;
1249
1250 mutex_lock(&gc08a3->mutex);
1251 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1252 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1253 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1254 #else
1255 mutex_unlock(&gc08a3->mutex);
1256 return -ENOTTY;
1257 #endif
1258 } else {
1259 fmt->format.width = mode->width;
1260 fmt->format.height = mode->height;
1261 fmt->format.code = GC08A3_MEDIA_BUS_FMT;
1262 fmt->format.field = V4L2_FIELD_NONE;
1263 }
1264 mutex_unlock(&gc08a3->mutex);
1265
1266 return 0;
1267 }
1268
gc08a3_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1269 static int gc08a3_enum_mbus_code(struct v4l2_subdev *sd,
1270 struct v4l2_subdev_pad_config *cfg,
1271 struct v4l2_subdev_mbus_code_enum *code)
1272 {
1273 if (code->index != 0)
1274 return -EINVAL;
1275 code->code = GC08A3_MEDIA_BUS_FMT;
1276
1277 return 0;
1278 }
1279
gc08a3_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1280 static int gc08a3_enum_frame_sizes(struct v4l2_subdev *sd,
1281 struct v4l2_subdev_pad_config *cfg,
1282 struct v4l2_subdev_frame_size_enum *fse)
1283 {
1284 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1285
1286 if (fse->index >= gc08a3->cfg_num)
1287 return -EINVAL;
1288
1289 if (fse->code != GC08A3_MEDIA_BUS_FMT)
1290 return -EINVAL;
1291
1292 fse->min_width = gc08a3->support_modes[fse->index].width;
1293 fse->max_width = gc08a3->support_modes[fse->index].width;
1294 fse->max_height = gc08a3->support_modes[fse->index].height;
1295 fse->min_height = gc08a3->support_modes[fse->index].height;
1296
1297 return 0;
1298 }
1299
gc08a3_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1300 static int gc08a3_g_frame_interval(struct v4l2_subdev *sd,
1301 struct v4l2_subdev_frame_interval *fi)
1302 {
1303 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1304 const struct gc08a3_mode *mode = gc08a3->cur_mode;
1305
1306 fi->interval = mode->max_fps;
1307
1308 return 0;
1309 }
1310
gc08a3_get_module_inf(struct gc08a3 * gc08a3,struct rkmodule_inf * inf)1311 static void gc08a3_get_module_inf(struct gc08a3 *gc08a3,
1312 struct rkmodule_inf *inf)
1313 {
1314 strscpy(inf->base.sensor,
1315 GC08A3_NAME,
1316 sizeof(inf->base.sensor));
1317 strscpy(inf->base.module,
1318 gc08a3->module_name,
1319 sizeof(inf->base.module));
1320 strscpy(inf->base.lens,
1321 gc08a3->len_name,
1322 sizeof(inf->base.lens));
1323 }
1324
gc08a3_set_module_inf(struct gc08a3 * gc08a3,struct rkmodule_awb_cfg * cfg)1325 static void gc08a3_set_module_inf(struct gc08a3 *gc08a3,
1326 struct rkmodule_awb_cfg *cfg)
1327 {
1328 mutex_lock(&gc08a3->mutex);
1329 memcpy(&gc08a3->awb_cfg, cfg, sizeof(*cfg));
1330 mutex_unlock(&gc08a3->mutex);
1331 }
1332
gc08a3_get_channel_info(struct gc08a3 * gc08a3,struct rkmodule_channel_info * ch_info)1333 static int gc08a3_get_channel_info(struct gc08a3 *gc08a3, struct rkmodule_channel_info *ch_info)
1334 {
1335 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1336 return -EINVAL;
1337 ch_info->vc = gc08a3->cur_mode->vc[ch_info->index];
1338 ch_info->width = gc08a3->cur_mode->width;
1339 ch_info->height = gc08a3->cur_mode->height;
1340 ch_info->bus_fmt = GC08A3_MEDIA_BUS_FMT;
1341 return 0;
1342 }
1343
gc08a3_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1344 static long gc08a3_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1345 {
1346 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1347 long ret = 0;
1348 u32 stream = 0;
1349 struct rkmodule_channel_info *ch_info;
1350
1351 switch (cmd) {
1352 case RKMODULE_GET_MODULE_INFO:
1353 gc08a3_get_module_inf(gc08a3, (struct rkmodule_inf *)arg);
1354 break;
1355 case RKMODULE_AWB_CFG:
1356 gc08a3_set_module_inf(gc08a3, (struct rkmodule_awb_cfg *)arg);
1357 break;
1358 case RKMODULE_SET_QUICK_STREAM:
1359
1360 stream = *((u32 *)arg);
1361
1362 if (stream) {
1363 ret |= gc08a3_write_reg(gc08a3->client,
1364 GC08A3_REG_CTRL_MODE,
1365 GC08A3_MODE_STREAMING);
1366 } else {
1367 ret |= gc08a3_write_reg(gc08a3->client,
1368 GC08A3_REG_CTRL_MODE,
1369 GC08A3_MODE_SW_STANDBY);
1370 }
1371 break;
1372 case RKMODULE_GET_CHANNEL_INFO:
1373 ch_info = (struct rkmodule_channel_info *)arg;
1374 ret = gc08a3_get_channel_info(gc08a3, ch_info);
1375 break;
1376 default:
1377 ret = -ENOTTY;
1378 break;
1379 }
1380
1381 return ret;
1382 }
1383
1384 #ifdef CONFIG_COMPAT
gc08a3_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1385 static long gc08a3_compat_ioctl32(struct v4l2_subdev *sd,
1386 unsigned int cmd, unsigned long arg)
1387 {
1388 void __user *up = compat_ptr(arg);
1389 struct rkmodule_inf *inf;
1390 struct rkmodule_awb_cfg *cfg;
1391 long ret = 0;
1392 u32 stream = 0;
1393 struct rkmodule_channel_info *ch_info;
1394
1395 switch (cmd) {
1396 case RKMODULE_GET_MODULE_INFO:
1397 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1398 if (!inf) {
1399 ret = -ENOMEM;
1400 return ret;
1401 }
1402
1403 ret = gc08a3_ioctl(sd, cmd, inf);
1404 if (!ret) {
1405 ret = copy_to_user(up, inf, sizeof(*inf));
1406 if (ret)
1407 ret = -EFAULT;
1408 }
1409 kfree(inf);
1410 break;
1411 case RKMODULE_AWB_CFG:
1412 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1413 if (!cfg) {
1414 ret = -ENOMEM;
1415 return ret;
1416 }
1417
1418 ret = copy_from_user(cfg, up, sizeof(*cfg));
1419 if (!ret)
1420 ret = gc08a3_ioctl(sd, cmd, cfg);
1421 else
1422 ret = -EFAULT;
1423 kfree(cfg);
1424 break;
1425 case RKMODULE_SET_QUICK_STREAM:
1426 ret = copy_from_user(&stream, up, sizeof(u32));
1427 if (!ret)
1428 ret = gc08a3_ioctl(sd, cmd, &stream);
1429 else
1430 ret = -EFAULT;
1431 break;
1432 case RKMODULE_GET_CHANNEL_INFO:
1433 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1434 if (!ch_info) {
1435 ret = -ENOMEM;
1436 return ret;
1437 }
1438
1439 ret = gc08a3_ioctl(sd, cmd, ch_info);
1440 if (!ret) {
1441 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1442 if (ret)
1443 ret = -EFAULT;
1444 }
1445 kfree(ch_info);
1446 break;
1447 default:
1448 ret = -ENOTTY;
1449 break;
1450 }
1451
1452 return ret;
1453 }
1454 #endif
1455
__gc08a3_start_stream(struct gc08a3 * gc08a3)1456 static int __gc08a3_start_stream(struct gc08a3 *gc08a3)
1457 {
1458 int ret;
1459
1460 ret = gc08a3_write_array(gc08a3->client, gc08a3->cur_mode->reg_list);
1461 if (ret)
1462 return ret;
1463
1464 /* In case these controls are set before streaming */
1465 mutex_unlock(&gc08a3->mutex);
1466 ret = v4l2_ctrl_handler_setup(&gc08a3->ctrl_handler);
1467 mutex_lock(&gc08a3->mutex);
1468 ret |= gc08a3_write_reg(gc08a3->client,
1469 GC08A3_REG_CTRL_MODE,
1470 GC08A3_MODE_STREAMING);
1471 return ret;
1472 }
1473
__gc08a3_stop_stream(struct gc08a3 * gc08a3)1474 static int __gc08a3_stop_stream(struct gc08a3 *gc08a3)
1475 {
1476 int ret;
1477
1478 ret = gc08a3_write_reg(gc08a3->client,
1479 GC08A3_REG_CTRL_MODE,
1480 GC08A3_MODE_SW_STANDBY);
1481
1482 return ret;
1483 }
1484
gc08a3_s_stream(struct v4l2_subdev * sd,int on)1485 static int gc08a3_s_stream(struct v4l2_subdev *sd, int on)
1486 {
1487 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1488 struct i2c_client *client = gc08a3->client;
1489 int ret = 0;
1490
1491 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1492 gc08a3->cur_mode->width,
1493 gc08a3->cur_mode->height,
1494 DIV_ROUND_CLOSEST(gc08a3->cur_mode->max_fps.denominator,
1495 gc08a3->cur_mode->max_fps.numerator));
1496
1497 mutex_lock(&gc08a3->mutex);
1498 on = !!on;
1499 if (on == gc08a3->streaming)
1500 goto unlock_and_return;
1501
1502 if (on) {
1503 ret = pm_runtime_get_sync(&client->dev);
1504 if (ret < 0) {
1505 pm_runtime_put_noidle(&client->dev);
1506 goto unlock_and_return;
1507 }
1508
1509 ret = __gc08a3_start_stream(gc08a3);
1510 if (ret) {
1511 v4l2_err(sd, "start stream failed while write regs\n");
1512 pm_runtime_put(&client->dev);
1513 goto unlock_and_return;
1514 }
1515 } else {
1516 __gc08a3_stop_stream(gc08a3);
1517 pm_runtime_put(&client->dev);
1518 }
1519
1520 gc08a3->streaming = on;
1521
1522 unlock_and_return:
1523 mutex_unlock(&gc08a3->mutex);
1524
1525 return ret;
1526 }
1527
gc08a3_s_power(struct v4l2_subdev * sd,int on)1528 static int gc08a3_s_power(struct v4l2_subdev *sd, int on)
1529 {
1530 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1531 struct i2c_client *client = gc08a3->client;
1532 int ret = 0;
1533
1534 dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
1535 mutex_lock(&gc08a3->mutex);
1536
1537 /* If the power state is not modified - no work to do. */
1538 if (gc08a3->power_on == !!on)
1539 goto unlock_and_return;
1540
1541 if (on) {
1542 ret = pm_runtime_get_sync(&client->dev);
1543 if (ret < 0) {
1544 pm_runtime_put_noidle(&client->dev);
1545 goto unlock_and_return;
1546 }
1547
1548 ret = gc08a3_write_array(gc08a3->client, gc08a3->cur_mode->global_reg_list);
1549 if (ret) {
1550 v4l2_err(sd, "could not set init registers\n");
1551 pm_runtime_put_noidle(&client->dev);
1552 goto unlock_and_return;
1553 }
1554
1555 gc08a3->power_on = true;
1556 } else {
1557 pm_runtime_put(&client->dev);
1558 gc08a3->power_on = false;
1559 }
1560
1561 unlock_and_return:
1562 mutex_unlock(&gc08a3->mutex);
1563
1564 return ret;
1565 }
1566
1567 /* Calculate the delay in us by clock rate and clock cycles */
gc08a3_cal_delay(u32 cycles)1568 static inline u32 gc08a3_cal_delay(u32 cycles)
1569 {
1570 return DIV_ROUND_UP(cycles, GC08A3_XVCLK_FREQ / 1000 / 1000);
1571 }
1572
__gc08a3_power_on(struct gc08a3 * gc08a3)1573 static int __gc08a3_power_on(struct gc08a3 *gc08a3)
1574 {
1575 int ret;
1576 u32 delay_us;
1577 struct device *dev = &gc08a3->client->dev;
1578
1579 if (!IS_ERR(gc08a3->power_gpio))
1580 gpiod_set_value_cansleep(gc08a3->power_gpio, 1);
1581
1582 usleep_range(1000, 2000);
1583
1584 if (!IS_ERR_OR_NULL(gc08a3->pins_default)) {
1585 ret = pinctrl_select_state(gc08a3->pinctrl,
1586 gc08a3->pins_default);
1587 if (ret < 0)
1588 dev_err(dev, "could not set pins\n");
1589 }
1590 ret = clk_set_rate(gc08a3->xvclk, GC08A3_XVCLK_FREQ);
1591 if (ret < 0)
1592 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1593 if (clk_get_rate(gc08a3->xvclk) != GC08A3_XVCLK_FREQ)
1594 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1595 ret = clk_prepare_enable(gc08a3->xvclk);
1596 if (ret < 0) {
1597 dev_err(dev, "Failed to enable xvclk\n");
1598 return ret;
1599 }
1600 if (!IS_ERR(gc08a3->reset_gpio))
1601 gpiod_set_value_cansleep(gc08a3->reset_gpio, 0);
1602
1603 ret = regulator_bulk_enable(GC08A3_NUM_SUPPLIES, gc08a3->supplies);
1604 if (ret < 0) {
1605 dev_err(dev, "Failed to enable regulators\n");
1606 goto disable_clk;
1607 }
1608
1609 usleep_range(1000, 1100);
1610 if (!IS_ERR(gc08a3->reset_gpio))
1611 gpiod_set_value_cansleep(gc08a3->reset_gpio, 1);
1612
1613 usleep_range(500, 1000);
1614 if (!IS_ERR(gc08a3->pwdn_gpio))
1615 gpiod_set_value_cansleep(gc08a3->pwdn_gpio, 1);
1616
1617 /* 8192 cycles prior to first SCCB transaction */
1618 delay_us = gc08a3_cal_delay(8192);
1619 usleep_range(delay_us, delay_us * 2);
1620
1621 return 0;
1622
1623 disable_clk:
1624 clk_disable_unprepare(gc08a3->xvclk);
1625
1626 return ret;
1627 }
1628
__gc08a3_power_off(struct gc08a3 * gc08a3)1629 static void __gc08a3_power_off(struct gc08a3 *gc08a3)
1630 {
1631 int ret;
1632
1633 if (!IS_ERR(gc08a3->pwdn_gpio))
1634 gpiod_set_value_cansleep(gc08a3->pwdn_gpio, 0);
1635 clk_disable_unprepare(gc08a3->xvclk);
1636 if (!IS_ERR(gc08a3->reset_gpio))
1637 gpiod_set_value_cansleep(gc08a3->reset_gpio, 0);
1638 if (!IS_ERR_OR_NULL(gc08a3->pins_sleep)) {
1639 ret = pinctrl_select_state(gc08a3->pinctrl,
1640 gc08a3->pins_sleep);
1641 if (ret < 0)
1642 dev_dbg(&gc08a3->client->dev, "could not set pins\n");
1643 }
1644 if (!IS_ERR(gc08a3->power_gpio))
1645 gpiod_set_value_cansleep(gc08a3->power_gpio, 0);
1646
1647 regulator_bulk_disable(GC08A3_NUM_SUPPLIES, gc08a3->supplies);
1648 }
1649
gc08a3_runtime_resume(struct device * dev)1650 static int gc08a3_runtime_resume(struct device *dev)
1651 {
1652 struct i2c_client *client = to_i2c_client(dev);
1653 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1654 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1655
1656 return __gc08a3_power_on(gc08a3);
1657 }
1658
gc08a3_runtime_suspend(struct device * dev)1659 static int gc08a3_runtime_suspend(struct device *dev)
1660 {
1661 struct i2c_client *client = to_i2c_client(dev);
1662 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1663 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1664
1665 __gc08a3_power_off(gc08a3);
1666
1667 return 0;
1668 }
1669
1670 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc08a3_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1671 static int gc08a3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1672 {
1673 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1674 struct v4l2_mbus_framefmt *try_fmt =
1675 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1676 const struct gc08a3_mode *def_mode = &gc08a3->support_modes[0];
1677
1678 mutex_lock(&gc08a3->mutex);
1679 /* Initialize try_fmt */
1680 try_fmt->width = def_mode->width;
1681 try_fmt->height = def_mode->height;
1682 try_fmt->code = GC08A3_MEDIA_BUS_FMT;
1683 try_fmt->field = V4L2_FIELD_NONE;
1684
1685 mutex_unlock(&gc08a3->mutex);
1686 /* No crop or compose */
1687
1688 return 0;
1689 }
1690 #endif
1691
gc08a3_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1692 static int gc08a3_enum_frame_interval(struct v4l2_subdev *sd,
1693 struct v4l2_subdev_pad_config *cfg,
1694 struct v4l2_subdev_frame_interval_enum *fie)
1695 {
1696 struct gc08a3 *gc08a3 = to_gc08a3(sd);
1697
1698 if (fie->index >= gc08a3->cfg_num)
1699 return -EINVAL;
1700
1701 fie->code = GC08A3_MEDIA_BUS_FMT;
1702 fie->width = gc08a3->support_modes[fie->index].width;
1703 fie->height = gc08a3->support_modes[fie->index].height;
1704 fie->interval = gc08a3->support_modes[fie->index].max_fps;
1705 return 0;
1706 }
1707
gc08a3_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1708 static int gc08a3_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1709 struct v4l2_mbus_config *config)
1710 {
1711 struct gc08a3 *sensor = to_gc08a3(sd);
1712 struct device *dev = &sensor->client->dev;
1713
1714 dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
1715
1716 if (2 == sensor->lane_num) {
1717 config->type = V4L2_MBUS_CSI2_DPHY;
1718 config->flags = V4L2_MBUS_CSI2_2_LANE |
1719 V4L2_MBUS_CSI2_CHANNEL_0 |
1720 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1721 } else if (4 == sensor->lane_num) {
1722 config->type = V4L2_MBUS_CSI2_DPHY;
1723 config->flags = V4L2_MBUS_CSI2_4_LANE |
1724 V4L2_MBUS_CSI2_CHANNEL_0 |
1725 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1726 } else {
1727 dev_err(&sensor->client->dev,
1728 "unsupported lane_num(%d)\n", sensor->lane_num);
1729 }
1730 return 0;
1731 }
1732
1733 static const struct dev_pm_ops gc08a3_pm_ops = {
1734 SET_RUNTIME_PM_OPS(gc08a3_runtime_suspend,
1735 gc08a3_runtime_resume, NULL)
1736 };
1737
1738 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1739 static const struct v4l2_subdev_internal_ops gc08a3_internal_ops = {
1740 .open = gc08a3_open,
1741 };
1742 #endif
1743
1744 static const struct v4l2_subdev_core_ops gc08a3_core_ops = {
1745 .s_power = gc08a3_s_power,
1746 .ioctl = gc08a3_ioctl,
1747 #ifdef CONFIG_COMPAT
1748 .compat_ioctl32 = gc08a3_compat_ioctl32,
1749 #endif
1750 };
1751
1752 static const struct v4l2_subdev_video_ops gc08a3_video_ops = {
1753 .s_stream = gc08a3_s_stream,
1754 .g_frame_interval = gc08a3_g_frame_interval,
1755 };
1756
1757 static const struct v4l2_subdev_pad_ops gc08a3_pad_ops = {
1758 .enum_mbus_code = gc08a3_enum_mbus_code,
1759 .enum_frame_size = gc08a3_enum_frame_sizes,
1760 .enum_frame_interval = gc08a3_enum_frame_interval,
1761 .get_fmt = gc08a3_get_fmt,
1762 .set_fmt = gc08a3_set_fmt,
1763 .get_mbus_config = gc08a3_g_mbus_config,
1764 };
1765
1766 static const struct v4l2_subdev_ops gc08a3_subdev_ops = {
1767 .core = &gc08a3_core_ops,
1768 .video = &gc08a3_video_ops,
1769 .pad = &gc08a3_pad_ops,
1770 };
1771
gc08a3_set_exposure_reg(struct gc08a3 * gc08a3,u32 exposure)1772 static int gc08a3_set_exposure_reg(struct gc08a3 *gc08a3, u32 exposure)
1773 {
1774 int ret = 0;
1775 u32 cal_shutter = 0;
1776
1777 cal_shutter = exposure >> 1;
1778 cal_shutter = cal_shutter << 1;
1779
1780 ret |= gc08a3_write_reg(gc08a3->client,
1781 GC08A3_REG_EXPOSURE_H,
1782 GC08A3_FETCH_HIGH_BYTE(cal_shutter));
1783 ret |= gc08a3_write_reg(gc08a3->client,
1784 GC08A3_REG_EXPOSURE_L,
1785 GC08A3_FETCH_LOW_BYTE(cal_shutter));
1786 return ret;
1787 }
1788
gc08a3_set_gain_reg(struct gc08a3 * gc08a3,u32 a_gain)1789 static int gc08a3_set_gain_reg(struct gc08a3 *gc08a3, u32 a_gain)
1790 {
1791 int ret = 0;
1792 u32 temp_gain;
1793
1794 if (a_gain < GC08A3_AGAIN_MIN)
1795 temp_gain = GC08A3_AGAIN_MIN;
1796 else if (a_gain > GC08A3_AGAIN_MAX)
1797 temp_gain = GC08A3_AGAIN_MAX;
1798 else
1799 temp_gain = a_gain;
1800
1801 ret |= gc08a3_write_reg(gc08a3->client,
1802 GC08A3_REG_GAIN_H,
1803 GC08A3_FETCH_HIGH_BYTE(temp_gain));
1804 /* gain effect when 0x0205 is written */
1805 ret |= gc08a3_write_reg(gc08a3->client,
1806 GC08A3_REG_GAIN_L,
1807 GC08A3_FETCH_LOW_BYTE(temp_gain));
1808
1809 return ret;
1810 }
1811
gc08a3_set_ctrl(struct v4l2_ctrl * ctrl)1812 static int gc08a3_set_ctrl(struct v4l2_ctrl *ctrl)
1813 {
1814 struct gc08a3 *gc08a3 = container_of(ctrl->handler,
1815 struct gc08a3, ctrl_handler);
1816 struct i2c_client *client = gc08a3->client;
1817 s64 max;
1818 int ret = 0;
1819
1820 /* Propagate change of current control to all related controls */
1821 switch (ctrl->id) {
1822 case V4L2_CID_VBLANK:
1823 /* Update max exposure while meeting expected vblanking */
1824 max = gc08a3->cur_mode->height + ctrl->val - 16;
1825 __v4l2_ctrl_modify_range(gc08a3->exposure,
1826 gc08a3->exposure->minimum, max,
1827 gc08a3->exposure->step,
1828 gc08a3->exposure->default_value);
1829 break;
1830 }
1831
1832 if (!pm_runtime_get_if_in_use(&client->dev))
1833 return 0;
1834
1835 switch (ctrl->id) {
1836 case V4L2_CID_EXPOSURE:
1837 /* 4 least significant bits of expsoure are fractional part */
1838 dev_info(&client->dev, "set exposure value 0x%x\n", ctrl->val);
1839 ret = gc08a3_set_exposure_reg(gc08a3, ctrl->val);
1840 break;
1841 case V4L2_CID_ANALOGUE_GAIN:
1842 dev_info(&client->dev, "set analog gain value 0x%x\n", ctrl->val);
1843 ret = gc08a3_set_gain_reg(gc08a3, ctrl->val);
1844 break;
1845 case V4L2_CID_VBLANK:
1846 dev_info(&client->dev, "set vb value 0x%x\n", ctrl->val);
1847 ret = gc08a3_write_reg(gc08a3->client,
1848 GC08A3_REG_VTS_H,
1849 (ctrl->val + gc08a3->cur_mode->height)
1850 >> 8);
1851 ret |= gc08a3_write_reg(gc08a3->client,
1852 GC08A3_REG_VTS_L,
1853 (ctrl->val + gc08a3->cur_mode->height)
1854 & 0xff);
1855 break;
1856 default:
1857 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1858 __func__, ctrl->id, ctrl->val);
1859 break;
1860 }
1861
1862 pm_runtime_put(&client->dev);
1863
1864 return ret;
1865 }
1866
1867 static const struct v4l2_ctrl_ops gc08a3_ctrl_ops = {
1868 .s_ctrl = gc08a3_set_ctrl,
1869 };
1870
gc08a3_initialize_controls(struct gc08a3 * gc08a3)1871 static int gc08a3_initialize_controls(struct gc08a3 *gc08a3)
1872 {
1873 const struct gc08a3_mode *mode;
1874 struct v4l2_ctrl_handler *handler;
1875 s64 exposure_max, vblank_def;
1876 u32 h_blank;
1877 int ret;
1878
1879 handler = &gc08a3->ctrl_handler;
1880 mode = gc08a3->cur_mode;
1881 ret = v4l2_ctrl_handler_init(handler, 8);
1882 if (ret)
1883 return ret;
1884 handler->lock = &gc08a3->mutex;
1885
1886 gc08a3->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1887 V4L2_CID_LINK_FREQ, 2, 0,
1888 link_freq_menu_items);
1889
1890 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1891 0, gc08a3->pixel_rate, 1, gc08a3->pixel_rate);
1892
1893 __v4l2_ctrl_s_ctrl(gc08a3->link_freq,
1894 mode->mipi_freq_idx);
1895
1896 h_blank = mode->hts_def - mode->width;
1897 gc08a3->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1898 h_blank, h_blank, 1, h_blank);
1899 if (gc08a3->hblank)
1900 gc08a3->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1901
1902 vblank_def = mode->vts_def - mode->height;
1903 gc08a3->vblank = v4l2_ctrl_new_std(handler, &gc08a3_ctrl_ops,
1904 V4L2_CID_VBLANK, vblank_def,
1905 GC08A3_VTS_MAX - mode->height,
1906 1, vblank_def);
1907
1908 exposure_max = mode->vts_def - 4;
1909 gc08a3->exposure = v4l2_ctrl_new_std(handler, &gc08a3_ctrl_ops,
1910 V4L2_CID_EXPOSURE, GC08A3_EXPOSURE_MIN,
1911 exposure_max, GC08A3_EXPOSURE_STEP,
1912 mode->exp_def);
1913
1914 gc08a3->anal_gain = v4l2_ctrl_new_std(handler, &gc08a3_ctrl_ops,
1915 V4L2_CID_ANALOGUE_GAIN, GC08A3_AGAIN_MIN,
1916 GC08A3_AGAIN_MAX, GC08A3_AGAIN_STEP,
1917 GC08A3_AGAIN_DEFAULT);
1918
1919 if (handler->error) {
1920 ret = handler->error;
1921 dev_err(&gc08a3->client->dev,
1922 "Failed to init controls(%d)\n", ret);
1923 goto err_free_handler;
1924 }
1925
1926 gc08a3->subdev.ctrl_handler = handler;
1927
1928 return 0;
1929
1930 err_free_handler:
1931 v4l2_ctrl_handler_free(handler);
1932
1933 return ret;
1934 }
1935
gc08a3_check_sensor_id(struct gc08a3 * gc08a3,struct i2c_client * client)1936 static int gc08a3_check_sensor_id(struct gc08a3 *gc08a3,
1937 struct i2c_client *client)
1938 {
1939 struct device *dev = &gc08a3->client->dev;
1940 u32 id = 0;
1941 u8 reg_H = 0;
1942 u8 reg_L = 0;
1943 int ret;
1944
1945 ret = gc08a3_read_reg(client, GC08A3_REG_CHIP_ID_H, ®_H);
1946 ret |= gc08a3_read_reg(client, GC08A3_REG_CHIP_ID_L, ®_L);
1947 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
1948 if (id != CHIP_ID) {
1949 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1950 return -ENODEV;
1951 }
1952 dev_info(dev, "detected gc%04x sensor\n", id);
1953 return ret;
1954 }
1955
gc08a3_configure_regulators(struct gc08a3 * gc08a3)1956 static int gc08a3_configure_regulators(struct gc08a3 *gc08a3)
1957 {
1958 unsigned int i;
1959
1960 for (i = 0; i < GC08A3_NUM_SUPPLIES; i++)
1961 gc08a3->supplies[i].supply = gc08a3_supply_names[i];
1962
1963 return devm_regulator_bulk_get(&gc08a3->client->dev,
1964 GC08A3_NUM_SUPPLIES,
1965 gc08a3->supplies);
1966 }
1967
gc08a3_parse_of(struct gc08a3 * gc08a3)1968 static int gc08a3_parse_of(struct gc08a3 *gc08a3)
1969 {
1970 struct device *dev = &gc08a3->client->dev;
1971 struct device_node *endpoint;
1972 struct fwnode_handle *fwnode;
1973 int rval;
1974 unsigned int fps;
1975
1976 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1977 if (!endpoint) {
1978 dev_err(dev, "Failed to get endpoint\n");
1979 return -EINVAL;
1980 }
1981 fwnode = of_fwnode_handle(endpoint);
1982 rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
1983 if (rval <= 0) {
1984 dev_warn(dev, " Get mipi lane num failed!\n");
1985 return -1;
1986 }
1987
1988 gc08a3->lane_num = rval;
1989 if (4 == gc08a3->lane_num) {
1990 gc08a3->cur_mode = &supported_modes_4lane[0];
1991 gc08a3->support_modes = supported_modes_4lane;
1992 gc08a3->cfg_num = ARRAY_SIZE(supported_modes_4lane);
1993 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1994 fps = DIV_ROUND_CLOSEST(gc08a3->cur_mode->max_fps.denominator,
1995 gc08a3->cur_mode->max_fps.numerator);
1996 gc08a3->pixel_rate = gc08a3->cur_mode->vts_def *
1997 gc08a3->cur_mode->hts_def * fps;
1998
1999 dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
2000 gc08a3->lane_num, gc08a3->pixel_rate);
2001 } else if (2 == gc08a3->lane_num) {
2002 /* TODO*/
2003 dev_err(dev, "unsupported lane_num(%d)\n", gc08a3->lane_num);
2004 return -1;
2005 }
2006
2007 return 0;
2008 }
2009
gc08a3_probe(struct i2c_client * client,const struct i2c_device_id * id)2010 static int gc08a3_probe(struct i2c_client *client,
2011 const struct i2c_device_id *id)
2012 {
2013 struct device *dev = &client->dev;
2014 struct device_node *node = dev->of_node;
2015 struct gc08a3 *gc08a3;
2016 struct v4l2_subdev *sd;
2017 char facing[2];
2018 int ret;
2019
2020 dev_info(dev, "driver version: %02x.%02x.%02x",
2021 DRIVER_VERSION >> 16,
2022 (DRIVER_VERSION & 0xff00) >> 8,
2023 DRIVER_VERSION & 0x00ff);
2024
2025 gc08a3 = devm_kzalloc(dev, sizeof(*gc08a3), GFP_KERNEL);
2026 if (!gc08a3)
2027 return -ENOMEM;
2028
2029 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2030 &gc08a3->module_index);
2031 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2032 &gc08a3->module_facing);
2033 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2034 &gc08a3->module_name);
2035 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2036 &gc08a3->len_name);
2037 if (ret) {
2038 dev_err(dev, "could not get module information!\n");
2039 return -EINVAL;
2040 }
2041 gc08a3->client = client;
2042
2043 gc08a3->xvclk = devm_clk_get(dev, "xvclk");
2044 if (IS_ERR(gc08a3->xvclk)) {
2045 dev_err(dev, "Failed to get xvclk\n");
2046 return -EINVAL;
2047 }
2048
2049 gc08a3->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
2050 if (IS_ERR(gc08a3->power_gpio))
2051 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
2052 gc08a3->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2053 if (IS_ERR(gc08a3->reset_gpio))
2054 dev_warn(dev, "Failed to get reset-gpios\n");
2055
2056 gc08a3->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
2057 if (IS_ERR(gc08a3->pwdn_gpio))
2058 dev_warn(dev, "Failed to get pwdn-gpios\n");
2059
2060 ret = gc08a3_configure_regulators(gc08a3);
2061 if (ret) {
2062 dev_err(dev, "Failed to get power regulators\n");
2063 return ret;
2064 }
2065
2066 ret = gc08a3_parse_of(gc08a3);
2067 if (ret != 0)
2068 return -EINVAL;
2069
2070 gc08a3->pinctrl = devm_pinctrl_get(dev);
2071 if (!IS_ERR(gc08a3->pinctrl)) {
2072 gc08a3->pins_default =
2073 pinctrl_lookup_state(gc08a3->pinctrl,
2074 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2075 if (IS_ERR(gc08a3->pins_default))
2076 dev_err(dev, "could not get default pinstate\n");
2077
2078 gc08a3->pins_sleep =
2079 pinctrl_lookup_state(gc08a3->pinctrl,
2080 OF_CAMERA_PINCTRL_STATE_SLEEP);
2081 if (IS_ERR(gc08a3->pins_sleep))
2082 dev_err(dev, "could not get sleep pinstate\n");
2083 }
2084
2085 mutex_init(&gc08a3->mutex);
2086
2087 sd = &gc08a3->subdev;
2088 v4l2_i2c_subdev_init(sd, client, &gc08a3_subdev_ops);
2089 ret = gc08a3_initialize_controls(gc08a3);
2090 if (ret)
2091 goto err_destroy_mutex;
2092
2093 ret = __gc08a3_power_on(gc08a3);
2094 if (ret)
2095 goto err_free_handler;
2096
2097 ret = gc08a3_check_sensor_id(gc08a3, client);
2098 if (ret)
2099 goto err_power_off;
2100
2101 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2102 sd->internal_ops = &gc08a3_internal_ops;
2103 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2104 V4L2_SUBDEV_FL_HAS_EVENTS;
2105 #endif
2106 #if defined(CONFIG_MEDIA_CONTROLLER)
2107 gc08a3->pad.flags = MEDIA_PAD_FL_SOURCE;
2108 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2109 ret = media_entity_pads_init(&sd->entity, 1, &gc08a3->pad);
2110 if (ret < 0)
2111 goto err_power_off;
2112 #endif
2113
2114 memset(facing, 0, sizeof(facing));
2115 if (strcmp(gc08a3->module_facing, "back") == 0)
2116 facing[0] = 'b';
2117 else
2118 facing[0] = 'f';
2119
2120 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2121 gc08a3->module_index, facing,
2122 GC08A3_NAME, dev_name(sd->dev));
2123 ret = v4l2_async_register_subdev_sensor_common(sd);
2124 if (ret) {
2125 dev_err(dev, "v4l2 async register subdev failed\n");
2126 goto err_clean_entity;
2127 }
2128
2129 pm_runtime_set_active(dev);
2130 pm_runtime_enable(dev);
2131 pm_runtime_idle(dev);
2132
2133 return 0;
2134
2135 err_clean_entity:
2136 #if defined(CONFIG_MEDIA_CONTROLLER)
2137 media_entity_cleanup(&sd->entity);
2138 #endif
2139 err_power_off:
2140 __gc08a3_power_off(gc08a3);
2141 err_free_handler:
2142 v4l2_ctrl_handler_free(&gc08a3->ctrl_handler);
2143 err_destroy_mutex:
2144 mutex_destroy(&gc08a3->mutex);
2145
2146 return ret;
2147 }
2148
gc08a3_remove(struct i2c_client * client)2149 static int gc08a3_remove(struct i2c_client *client)
2150 {
2151 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2152 struct gc08a3 *gc08a3 = to_gc08a3(sd);
2153
2154 v4l2_async_unregister_subdev(sd);
2155 #if defined(CONFIG_MEDIA_CONTROLLER)
2156 media_entity_cleanup(&sd->entity);
2157 #endif
2158 v4l2_ctrl_handler_free(&gc08a3->ctrl_handler);
2159 mutex_destroy(&gc08a3->mutex);
2160
2161 pm_runtime_disable(&client->dev);
2162 if (!pm_runtime_status_suspended(&client->dev))
2163 __gc08a3_power_off(gc08a3);
2164 pm_runtime_set_suspended(&client->dev);
2165
2166 return 0;
2167 }
2168
2169 #if IS_ENABLED(CONFIG_OF)
2170 static const struct of_device_id gc08a3_of_match[] = {
2171 { .compatible = "galaxycore,gc08a3" },
2172 {},
2173 };
2174 MODULE_DEVICE_TABLE(of, gc08a3_of_match);
2175 #endif
2176
2177 static const struct i2c_device_id gc08a3_match_id[] = {
2178 { "galaxycore,gc08a3", 0},
2179 { },
2180 };
2181
2182 static struct i2c_driver gc08a3_i2c_driver = {
2183 .driver = {
2184 .name = GC08A3_NAME,
2185 .pm = &gc08a3_pm_ops,
2186 .of_match_table = of_match_ptr(gc08a3_of_match),
2187 },
2188 .probe = &gc08a3_probe,
2189 .remove = &gc08a3_remove,
2190 .id_table = gc08a3_match_id,
2191 };
2192
sensor_mod_init(void)2193 static int __init sensor_mod_init(void)
2194 {
2195 return i2c_add_driver(&gc08a3_i2c_driver);
2196 }
2197
sensor_mod_exit(void)2198 static void __exit sensor_mod_exit(void)
2199 {
2200 i2c_del_driver(&gc08a3_i2c_driver);
2201 }
2202
2203 device_initcall_sync(sensor_mod_init);
2204 module_exit(sensor_mod_exit);
2205
2206 MODULE_DESCRIPTION("GalaxyCore gc08a3 sensor driver");
2207 MODULE_LICENSE("GPL v2");
2208