1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * et8ek8_reg.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2008 Nokia Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Contact: Sakari Ailus <sakari.ailus@iki.fi> 8*4882a593Smuzhiyun * Tuukka Toivonen <tuukkat76@gmail.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef ET8EK8REGS_H 12*4882a593Smuzhiyun #define ET8EK8REGS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/i2c.h> 15*4882a593Smuzhiyun #include <linux/types.h> 16*4882a593Smuzhiyun #include <linux/videodev2.h> 17*4882a593Smuzhiyun #include <linux/v4l2-subdev.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct v4l2_mbus_framefmt; 20*4882a593Smuzhiyun struct v4l2_subdev_pad_mbus_code_enum; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct et8ek8_mode { 23*4882a593Smuzhiyun /* Physical sensor resolution and current image window */ 24*4882a593Smuzhiyun u16 sensor_width; 25*4882a593Smuzhiyun u16 sensor_height; 26*4882a593Smuzhiyun u16 sensor_window_origin_x; 27*4882a593Smuzhiyun u16 sensor_window_origin_y; 28*4882a593Smuzhiyun u16 sensor_window_width; 29*4882a593Smuzhiyun u16 sensor_window_height; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Image data coming from sensor (after scaling) */ 32*4882a593Smuzhiyun u16 width; 33*4882a593Smuzhiyun u16 height; 34*4882a593Smuzhiyun u16 window_origin_x; 35*4882a593Smuzhiyun u16 window_origin_y; 36*4882a593Smuzhiyun u16 window_width; 37*4882a593Smuzhiyun u16 window_height; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun u32 pixel_clock; /* in Hz */ 40*4882a593Smuzhiyun u32 ext_clock; /* in Hz */ 41*4882a593Smuzhiyun struct v4l2_fract timeperframe; 42*4882a593Smuzhiyun u32 max_exp; /* Maximum exposure value */ 43*4882a593Smuzhiyun u32 bus_format; /* MEDIA_BUS_FMT_ */ 44*4882a593Smuzhiyun u32 sensitivity; /* 16.16 fixed point */ 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define ET8EK8_REG_8BIT 1 48*4882a593Smuzhiyun #define ET8EK8_REG_16BIT 2 49*4882a593Smuzhiyun #define ET8EK8_REG_DELAY 100 50*4882a593Smuzhiyun #define ET8EK8_REG_TERM 0xff 51*4882a593Smuzhiyun struct et8ek8_reg { 52*4882a593Smuzhiyun u16 type; 53*4882a593Smuzhiyun u16 reg; /* 16-bit offset */ 54*4882a593Smuzhiyun u32 val; /* 8/16/32-bit value */ 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Possible struct smia_reglist types. */ 58*4882a593Smuzhiyun #define ET8EK8_REGLIST_STANDBY 0 59*4882a593Smuzhiyun #define ET8EK8_REGLIST_POWERON 1 60*4882a593Smuzhiyun #define ET8EK8_REGLIST_RESUME 2 61*4882a593Smuzhiyun #define ET8EK8_REGLIST_STREAMON 3 62*4882a593Smuzhiyun #define ET8EK8_REGLIST_STREAMOFF 4 63*4882a593Smuzhiyun #define ET8EK8_REGLIST_DISABLED 5 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define ET8EK8_REGLIST_MODE 10 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define ET8EK8_REGLIST_LSC_ENABLE 100 68*4882a593Smuzhiyun #define ET8EK8_REGLIST_LSC_DISABLE 101 69*4882a593Smuzhiyun #define ET8EK8_REGLIST_ANR_ENABLE 102 70*4882a593Smuzhiyun #define ET8EK8_REGLIST_ANR_DISABLE 103 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun struct et8ek8_reglist { 73*4882a593Smuzhiyun u32 type; 74*4882a593Smuzhiyun struct et8ek8_mode mode; 75*4882a593Smuzhiyun struct et8ek8_reg regs[]; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define ET8EK8_MAX_LEN 32 79*4882a593Smuzhiyun struct et8ek8_meta_reglist { 80*4882a593Smuzhiyun char version[ET8EK8_MAX_LEN]; 81*4882a593Smuzhiyun union { 82*4882a593Smuzhiyun struct et8ek8_reglist *ptr; 83*4882a593Smuzhiyun } reglist[]; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun extern struct et8ek8_meta_reglist meta_reglist; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif /* ET8EK8REGS */ 89