xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/et8ek8/et8ek8_mode.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * et8ek8_mode.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2008 Nokia Corporation
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Contact: Sakari Ailus <sakari.ailus@iki.fi>
8*4882a593Smuzhiyun  *          Tuukka Toivonen <tuukkat76@gmail.com>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include "et8ek8_reg.h"
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun  * Stingray sensor mode settings for Scooby
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun /* Mode1_poweron_Mode2_16VGA_2592x1968_12.07fps */
18*4882a593Smuzhiyun static struct et8ek8_reglist mode1_poweron_mode2_16vga_2592x1968_12_07fps = {
19*4882a593Smuzhiyun /* (without the +1)
20*4882a593Smuzhiyun  * SPCK       = 80 MHz
21*4882a593Smuzhiyun  * CCP2       = 640 MHz
22*4882a593Smuzhiyun  * VCO        = 640 MHz
23*4882a593Smuzhiyun  * VCOUNT     = 84 (2016)
24*4882a593Smuzhiyun  * HCOUNT     = 137 (3288)
25*4882a593Smuzhiyun  * CKREF_DIV  = 2
26*4882a593Smuzhiyun  * CKVAR_DIV  = 200
27*4882a593Smuzhiyun  * VCO_DIV    = 0
28*4882a593Smuzhiyun  * SPCK_DIV   = 7
29*4882a593Smuzhiyun  * MRCK_DIV   = 7
30*4882a593Smuzhiyun  * LVDSCK_DIV = 0
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun 	.type = ET8EK8_REGLIST_POWERON,
33*4882a593Smuzhiyun 	.mode = {
34*4882a593Smuzhiyun 		.sensor_width = 2592,
35*4882a593Smuzhiyun 		.sensor_height = 1968,
36*4882a593Smuzhiyun 		.sensor_window_origin_x = 0,
37*4882a593Smuzhiyun 		.sensor_window_origin_y = 0,
38*4882a593Smuzhiyun 		.sensor_window_width = 2592,
39*4882a593Smuzhiyun 		.sensor_window_height = 1968,
40*4882a593Smuzhiyun 		.width = 3288,
41*4882a593Smuzhiyun 		.height = 2016,
42*4882a593Smuzhiyun 		.window_origin_x = 0,
43*4882a593Smuzhiyun 		.window_origin_y = 0,
44*4882a593Smuzhiyun 		.window_width = 2592,
45*4882a593Smuzhiyun 		.window_height = 1968,
46*4882a593Smuzhiyun 		.pixel_clock = 80000000,
47*4882a593Smuzhiyun 		.ext_clock = 9600000,
48*4882a593Smuzhiyun 		.timeperframe = {
49*4882a593Smuzhiyun 			.numerator = 100,
50*4882a593Smuzhiyun 			.denominator = 1207
51*4882a593Smuzhiyun 		},
52*4882a593Smuzhiyun 		.max_exp = 2012,
53*4882a593Smuzhiyun 		/* .max_gain = 0, */
54*4882a593Smuzhiyun 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
55*4882a593Smuzhiyun 		.sensitivity = 65536
56*4882a593Smuzhiyun 	},
57*4882a593Smuzhiyun 	.regs = {
58*4882a593Smuzhiyun 		/* Need to set firstly */
59*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x126C, 0xCC },
60*4882a593Smuzhiyun 		/* Strobe and Data of CCP2 delay are minimized. */
61*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1269, 0x00 },
62*4882a593Smuzhiyun 		/* Refined value of Min H_COUNT  */
63*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
64*4882a593Smuzhiyun 		/* Frequency of SPCK setting (SPCK=MRCK) */
65*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
66*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1241, 0x94 },
67*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1242, 0x02 },
68*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x124B, 0x00 },
69*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1255, 0xFF },
70*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1256, 0x9F },
71*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1258, 0x00 },
72*4882a593Smuzhiyun 		/* From parallel out to serial out */
73*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 },
74*4882a593Smuzhiyun 		/* From w/ embedded data to w/o embedded data */
75*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x125E, 0xC0 },
76*4882a593Smuzhiyun 		/* CCP2 out is from STOP to ACTIVE */
77*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1263, 0x98 },
78*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1268, 0xC6 },
79*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1434, 0x00 },
80*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1163, 0x44 },
81*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1166, 0x29 },
82*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1140, 0x02 },
83*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1011, 0x24 },
84*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1151, 0x80 },
85*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1152, 0x23 },
86*4882a593Smuzhiyun 		/* Initial setting for improvement2 of lower frequency noise */
87*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1014, 0x05 },
88*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1033, 0x06 },
89*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1034, 0x79 },
90*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1423, 0x3F },
91*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1424, 0x3F },
92*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1426, 0x00 },
93*4882a593Smuzhiyun 		/* Switch of Preset-White-balance (0d:disable / 1d:enable) */
94*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1439, 0x00 },
95*4882a593Smuzhiyun 		/* Switch of blemish correction (0d:disable / 1d:enable) */
96*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x161F, 0x60 },
97*4882a593Smuzhiyun 		/* Switch of auto noise correction (0d:disable / 1d:enable) */
98*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1634, 0x00 },
99*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1646, 0x00 },
100*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1648, 0x00 },
101*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x113E, 0x01 },
102*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x113F, 0x22 },
103*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
104*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
105*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
106*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
107*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121B, 0x64 },
108*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121D, 0x64 },
109*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
110*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
111*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
112*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
113*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
114*4882a593Smuzhiyun 		{ ET8EK8_REG_TERM, 0, 0}
115*4882a593Smuzhiyun 	}
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun /* Mode1_16VGA_2592x1968_13.12fps_DPCM10-8 */
119*4882a593Smuzhiyun static struct et8ek8_reglist mode1_16vga_2592x1968_13_12fps_dpcm10_8 = {
120*4882a593Smuzhiyun /* (without the +1)
121*4882a593Smuzhiyun  * SPCK       = 80 MHz
122*4882a593Smuzhiyun  * CCP2       = 560 MHz
123*4882a593Smuzhiyun  * VCO        = 560 MHz
124*4882a593Smuzhiyun  * VCOUNT     = 84 (2016)
125*4882a593Smuzhiyun  * HCOUNT     = 128 (3072)
126*4882a593Smuzhiyun  * CKREF_DIV  = 2
127*4882a593Smuzhiyun  * CKVAR_DIV  = 175
128*4882a593Smuzhiyun  * VCO_DIV    = 0
129*4882a593Smuzhiyun  * SPCK_DIV   = 6
130*4882a593Smuzhiyun  * MRCK_DIV   = 7
131*4882a593Smuzhiyun  * LVDSCK_DIV = 0
132*4882a593Smuzhiyun  */
133*4882a593Smuzhiyun 	.type = ET8EK8_REGLIST_MODE,
134*4882a593Smuzhiyun 	.mode = {
135*4882a593Smuzhiyun 		.sensor_width = 2592,
136*4882a593Smuzhiyun 		.sensor_height = 1968,
137*4882a593Smuzhiyun 		.sensor_window_origin_x = 0,
138*4882a593Smuzhiyun 		.sensor_window_origin_y = 0,
139*4882a593Smuzhiyun 		.sensor_window_width = 2592,
140*4882a593Smuzhiyun 		.sensor_window_height = 1968,
141*4882a593Smuzhiyun 		.width = 3072,
142*4882a593Smuzhiyun 		.height = 2016,
143*4882a593Smuzhiyun 		.window_origin_x = 0,
144*4882a593Smuzhiyun 		.window_origin_y = 0,
145*4882a593Smuzhiyun 		.window_width = 2592,
146*4882a593Smuzhiyun 		.window_height = 1968,
147*4882a593Smuzhiyun 		.pixel_clock = 80000000,
148*4882a593Smuzhiyun 		.ext_clock = 9600000,
149*4882a593Smuzhiyun 		.timeperframe = {
150*4882a593Smuzhiyun 			.numerator = 100,
151*4882a593Smuzhiyun 			.denominator = 1292
152*4882a593Smuzhiyun 		},
153*4882a593Smuzhiyun 		.max_exp = 2012,
154*4882a593Smuzhiyun 		/* .max_gain = 0, */
155*4882a593Smuzhiyun 		.bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
156*4882a593Smuzhiyun 		.sensitivity = 65536
157*4882a593Smuzhiyun 	},
158*4882a593Smuzhiyun 	.regs = {
159*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1239, 0x57 },
160*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1238, 0x82 },
161*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
162*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123A, 0x06 },
163*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121B, 0x64 },
164*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121D, 0x64 },
165*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
166*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1220, 0x80 }, /* <-changed to v14 7E->80 */
167*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
168*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
169*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x125D, 0x83 }, /* CCP_LVDS_MODE/  */
170*4882a593Smuzhiyun 		{ ET8EK8_REG_TERM, 0, 0}
171*4882a593Smuzhiyun 	}
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun /* Mode3_4VGA_1296x984_29.99fps_DPCM10-8 */
175*4882a593Smuzhiyun static struct et8ek8_reglist mode3_4vga_1296x984_29_99fps_dpcm10_8 = {
176*4882a593Smuzhiyun /* (without the +1)
177*4882a593Smuzhiyun  * SPCK       = 96.5333333333333 MHz
178*4882a593Smuzhiyun  * CCP2       = 579.2 MHz
179*4882a593Smuzhiyun  * VCO        = 579.2 MHz
180*4882a593Smuzhiyun  * VCOUNT     = 84 (2016)
181*4882a593Smuzhiyun  * HCOUNT     = 133 (3192)
182*4882a593Smuzhiyun  * CKREF_DIV  = 2
183*4882a593Smuzhiyun  * CKVAR_DIV  = 181
184*4882a593Smuzhiyun  * VCO_DIV    = 0
185*4882a593Smuzhiyun  * SPCK_DIV   = 5
186*4882a593Smuzhiyun  * MRCK_DIV   = 7
187*4882a593Smuzhiyun  * LVDSCK_DIV = 0
188*4882a593Smuzhiyun  */
189*4882a593Smuzhiyun 	.type = ET8EK8_REGLIST_MODE,
190*4882a593Smuzhiyun 	.mode = {
191*4882a593Smuzhiyun 		.sensor_width = 2592,
192*4882a593Smuzhiyun 		.sensor_height = 1968,
193*4882a593Smuzhiyun 		.sensor_window_origin_x = 0,
194*4882a593Smuzhiyun 		.sensor_window_origin_y = 0,
195*4882a593Smuzhiyun 		.sensor_window_width = 2592,
196*4882a593Smuzhiyun 		.sensor_window_height = 1968,
197*4882a593Smuzhiyun 		.width = 3192,
198*4882a593Smuzhiyun 		.height = 1008,
199*4882a593Smuzhiyun 		.window_origin_x = 0,
200*4882a593Smuzhiyun 		.window_origin_y = 0,
201*4882a593Smuzhiyun 		.window_width = 1296,
202*4882a593Smuzhiyun 		.window_height = 984,
203*4882a593Smuzhiyun 		.pixel_clock = 96533333,
204*4882a593Smuzhiyun 		.ext_clock = 9600000,
205*4882a593Smuzhiyun 		.timeperframe = {
206*4882a593Smuzhiyun 			.numerator = 100,
207*4882a593Smuzhiyun 			.denominator = 3000
208*4882a593Smuzhiyun 		},
209*4882a593Smuzhiyun 		.max_exp = 1004,
210*4882a593Smuzhiyun 		/* .max_gain = 0, */
211*4882a593Smuzhiyun 		.bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
212*4882a593Smuzhiyun 		.sensitivity = 65536
213*4882a593Smuzhiyun 	},
214*4882a593Smuzhiyun 	.regs = {
215*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1239, 0x5A },
216*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1238, 0x82 },
217*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
218*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123A, 0x05 },
219*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121B, 0x63 },
220*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1220, 0x85 },
221*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
222*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
223*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
224*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121D, 0x63 },
225*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x125D, 0x83 }, /* CCP_LVDS_MODE/  */
226*4882a593Smuzhiyun 		{ ET8EK8_REG_TERM, 0, 0}
227*4882a593Smuzhiyun 	}
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun /* Mode4_SVGA_864x656_29.88fps */
231*4882a593Smuzhiyun static struct et8ek8_reglist mode4_svga_864x656_29_88fps = {
232*4882a593Smuzhiyun /* (without the +1)
233*4882a593Smuzhiyun  * SPCK       = 80 MHz
234*4882a593Smuzhiyun  * CCP2       = 320 MHz
235*4882a593Smuzhiyun  * VCO        = 640 MHz
236*4882a593Smuzhiyun  * VCOUNT     = 84 (2016)
237*4882a593Smuzhiyun  * HCOUNT     = 166 (3984)
238*4882a593Smuzhiyun  * CKREF_DIV  = 2
239*4882a593Smuzhiyun  * CKVAR_DIV  = 200
240*4882a593Smuzhiyun  * VCO_DIV    = 0
241*4882a593Smuzhiyun  * SPCK_DIV   = 7
242*4882a593Smuzhiyun  * MRCK_DIV   = 7
243*4882a593Smuzhiyun  * LVDSCK_DIV = 1
244*4882a593Smuzhiyun  */
245*4882a593Smuzhiyun 	.type = ET8EK8_REGLIST_MODE,
246*4882a593Smuzhiyun 	.mode = {
247*4882a593Smuzhiyun 		.sensor_width = 2592,
248*4882a593Smuzhiyun 		.sensor_height = 1968,
249*4882a593Smuzhiyun 		.sensor_window_origin_x = 0,
250*4882a593Smuzhiyun 		.sensor_window_origin_y = 0,
251*4882a593Smuzhiyun 		.sensor_window_width = 2592,
252*4882a593Smuzhiyun 		.sensor_window_height = 1968,
253*4882a593Smuzhiyun 		.width = 3984,
254*4882a593Smuzhiyun 		.height = 672,
255*4882a593Smuzhiyun 		.window_origin_x = 0,
256*4882a593Smuzhiyun 		.window_origin_y = 0,
257*4882a593Smuzhiyun 		.window_width = 864,
258*4882a593Smuzhiyun 		.window_height = 656,
259*4882a593Smuzhiyun 		.pixel_clock = 80000000,
260*4882a593Smuzhiyun 		.ext_clock = 9600000,
261*4882a593Smuzhiyun 		.timeperframe = {
262*4882a593Smuzhiyun 			.numerator = 100,
263*4882a593Smuzhiyun 			.denominator = 2988
264*4882a593Smuzhiyun 		},
265*4882a593Smuzhiyun 		.max_exp = 668,
266*4882a593Smuzhiyun 		/* .max_gain = 0, */
267*4882a593Smuzhiyun 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
268*4882a593Smuzhiyun 		.sensitivity = 65536
269*4882a593Smuzhiyun 	},
270*4882a593Smuzhiyun 	.regs = {
271*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
272*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
273*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123B, 0x71 },
274*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
275*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121B, 0x62 },
276*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121D, 0x62 },
277*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
278*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1220, 0xA6 },
279*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
280*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
281*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
282*4882a593Smuzhiyun 		{ ET8EK8_REG_TERM, 0, 0}
283*4882a593Smuzhiyun 	}
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun /* Mode5_VGA_648x492_29.93fps */
287*4882a593Smuzhiyun static struct et8ek8_reglist mode5_vga_648x492_29_93fps = {
288*4882a593Smuzhiyun /* (without the +1)
289*4882a593Smuzhiyun  * SPCK       = 80 MHz
290*4882a593Smuzhiyun  * CCP2       = 320 MHz
291*4882a593Smuzhiyun  * VCO        = 640 MHz
292*4882a593Smuzhiyun  * VCOUNT     = 84 (2016)
293*4882a593Smuzhiyun  * HCOUNT     = 221 (5304)
294*4882a593Smuzhiyun  * CKREF_DIV  = 2
295*4882a593Smuzhiyun  * CKVAR_DIV  = 200
296*4882a593Smuzhiyun  * VCO_DIV    = 0
297*4882a593Smuzhiyun  * SPCK_DIV   = 7
298*4882a593Smuzhiyun  * MRCK_DIV   = 7
299*4882a593Smuzhiyun  * LVDSCK_DIV = 1
300*4882a593Smuzhiyun  */
301*4882a593Smuzhiyun 	.type = ET8EK8_REGLIST_MODE,
302*4882a593Smuzhiyun 	.mode = {
303*4882a593Smuzhiyun 		.sensor_width = 2592,
304*4882a593Smuzhiyun 		.sensor_height = 1968,
305*4882a593Smuzhiyun 		.sensor_window_origin_x = 0,
306*4882a593Smuzhiyun 		.sensor_window_origin_y = 0,
307*4882a593Smuzhiyun 		.sensor_window_width = 2592,
308*4882a593Smuzhiyun 		.sensor_window_height = 1968,
309*4882a593Smuzhiyun 		.width = 5304,
310*4882a593Smuzhiyun 		.height = 504,
311*4882a593Smuzhiyun 		.window_origin_x = 0,
312*4882a593Smuzhiyun 		.window_origin_y = 0,
313*4882a593Smuzhiyun 		.window_width = 648,
314*4882a593Smuzhiyun 		.window_height = 492,
315*4882a593Smuzhiyun 		.pixel_clock = 80000000,
316*4882a593Smuzhiyun 		.ext_clock = 9600000,
317*4882a593Smuzhiyun 		.timeperframe = {
318*4882a593Smuzhiyun 			.numerator = 100,
319*4882a593Smuzhiyun 			.denominator = 2993
320*4882a593Smuzhiyun 		},
321*4882a593Smuzhiyun 		.max_exp = 500,
322*4882a593Smuzhiyun 		/* .max_gain = 0, */
323*4882a593Smuzhiyun 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
324*4882a593Smuzhiyun 		.sensitivity = 65536
325*4882a593Smuzhiyun 	},
326*4882a593Smuzhiyun 	.regs = {
327*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
328*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
329*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123B, 0x71 },
330*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
331*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121B, 0x61 },
332*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121D, 0x61 },
333*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
334*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1220, 0xDD },
335*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
336*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
337*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
338*4882a593Smuzhiyun 		{ ET8EK8_REG_TERM, 0, 0}
339*4882a593Smuzhiyun 	}
340*4882a593Smuzhiyun };
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun /* Mode2_16VGA_2592x1968_3.99fps */
343*4882a593Smuzhiyun static struct et8ek8_reglist mode2_16vga_2592x1968_3_99fps = {
344*4882a593Smuzhiyun /* (without the +1)
345*4882a593Smuzhiyun  * SPCK       = 80 MHz
346*4882a593Smuzhiyun  * CCP2       = 640 MHz
347*4882a593Smuzhiyun  * VCO        = 640 MHz
348*4882a593Smuzhiyun  * VCOUNT     = 254 (6096)
349*4882a593Smuzhiyun  * HCOUNT     = 137 (3288)
350*4882a593Smuzhiyun  * CKREF_DIV  = 2
351*4882a593Smuzhiyun  * CKVAR_DIV  = 200
352*4882a593Smuzhiyun  * VCO_DIV    = 0
353*4882a593Smuzhiyun  * SPCK_DIV   = 7
354*4882a593Smuzhiyun  * MRCK_DIV   = 7
355*4882a593Smuzhiyun  * LVDSCK_DIV = 0
356*4882a593Smuzhiyun  */
357*4882a593Smuzhiyun 	.type = ET8EK8_REGLIST_MODE,
358*4882a593Smuzhiyun 	.mode = {
359*4882a593Smuzhiyun 		.sensor_width = 2592,
360*4882a593Smuzhiyun 		.sensor_height = 1968,
361*4882a593Smuzhiyun 		.sensor_window_origin_x = 0,
362*4882a593Smuzhiyun 		.sensor_window_origin_y = 0,
363*4882a593Smuzhiyun 		.sensor_window_width = 2592,
364*4882a593Smuzhiyun 		.sensor_window_height = 1968,
365*4882a593Smuzhiyun 		.width = 3288,
366*4882a593Smuzhiyun 		.height = 6096,
367*4882a593Smuzhiyun 		.window_origin_x = 0,
368*4882a593Smuzhiyun 		.window_origin_y = 0,
369*4882a593Smuzhiyun 		.window_width = 2592,
370*4882a593Smuzhiyun 		.window_height = 1968,
371*4882a593Smuzhiyun 		.pixel_clock = 80000000,
372*4882a593Smuzhiyun 		.ext_clock = 9600000,
373*4882a593Smuzhiyun 		.timeperframe = {
374*4882a593Smuzhiyun 			.numerator = 100,
375*4882a593Smuzhiyun 			.denominator = 399
376*4882a593Smuzhiyun 		},
377*4882a593Smuzhiyun 		.max_exp = 6092,
378*4882a593Smuzhiyun 		/* .max_gain = 0, */
379*4882a593Smuzhiyun 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
380*4882a593Smuzhiyun 		.sensitivity = 65536
381*4882a593Smuzhiyun 	},
382*4882a593Smuzhiyun 	.regs = {
383*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
384*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
385*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
386*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
387*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121B, 0x64 },
388*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121D, 0x64 },
389*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
390*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
391*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
392*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1222, 0xFE },
393*4882a593Smuzhiyun 		{ ET8EK8_REG_TERM, 0, 0}
394*4882a593Smuzhiyun 	}
395*4882a593Smuzhiyun };
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun /* Mode_648x492_5fps */
398*4882a593Smuzhiyun static struct et8ek8_reglist mode_648x492_5fps = {
399*4882a593Smuzhiyun /* (without the +1)
400*4882a593Smuzhiyun  * SPCK       = 13.3333333333333 MHz
401*4882a593Smuzhiyun  * CCP2       = 53.3333333333333 MHz
402*4882a593Smuzhiyun  * VCO        = 640 MHz
403*4882a593Smuzhiyun  * VCOUNT     = 84 (2016)
404*4882a593Smuzhiyun  * HCOUNT     = 221 (5304)
405*4882a593Smuzhiyun  * CKREF_DIV  = 2
406*4882a593Smuzhiyun  * CKVAR_DIV  = 200
407*4882a593Smuzhiyun  * VCO_DIV    = 5
408*4882a593Smuzhiyun  * SPCK_DIV   = 7
409*4882a593Smuzhiyun  * MRCK_DIV   = 7
410*4882a593Smuzhiyun  * LVDSCK_DIV = 1
411*4882a593Smuzhiyun  */
412*4882a593Smuzhiyun 	.type = ET8EK8_REGLIST_MODE,
413*4882a593Smuzhiyun 	.mode = {
414*4882a593Smuzhiyun 		.sensor_width = 2592,
415*4882a593Smuzhiyun 		.sensor_height = 1968,
416*4882a593Smuzhiyun 		.sensor_window_origin_x = 0,
417*4882a593Smuzhiyun 		.sensor_window_origin_y = 0,
418*4882a593Smuzhiyun 		.sensor_window_width = 2592,
419*4882a593Smuzhiyun 		.sensor_window_height = 1968,
420*4882a593Smuzhiyun 		.width = 5304,
421*4882a593Smuzhiyun 		.height = 504,
422*4882a593Smuzhiyun 		.window_origin_x = 0,
423*4882a593Smuzhiyun 		.window_origin_y = 0,
424*4882a593Smuzhiyun 		.window_width = 648,
425*4882a593Smuzhiyun 		.window_height = 492,
426*4882a593Smuzhiyun 		.pixel_clock = 13333333,
427*4882a593Smuzhiyun 		.ext_clock = 9600000,
428*4882a593Smuzhiyun 		.timeperframe = {
429*4882a593Smuzhiyun 			.numerator = 100,
430*4882a593Smuzhiyun 			.denominator = 499
431*4882a593Smuzhiyun 		},
432*4882a593Smuzhiyun 		.max_exp = 500,
433*4882a593Smuzhiyun 		/* .max_gain = 0, */
434*4882a593Smuzhiyun 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
435*4882a593Smuzhiyun 		.sensitivity = 65536
436*4882a593Smuzhiyun 	},
437*4882a593Smuzhiyun 	.regs = {
438*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
439*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
440*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123B, 0x71 },
441*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123A, 0x57 },
442*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121B, 0x61 },
443*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121D, 0x61 },
444*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
445*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1220, 0xDD },
446*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
447*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
448*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
449*4882a593Smuzhiyun 		{ ET8EK8_REG_TERM, 0, 0}
450*4882a593Smuzhiyun 	}
451*4882a593Smuzhiyun };
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun /* Mode3_4VGA_1296x984_5fps */
454*4882a593Smuzhiyun static struct et8ek8_reglist mode3_4vga_1296x984_5fps = {
455*4882a593Smuzhiyun /* (without the +1)
456*4882a593Smuzhiyun  * SPCK       = 49.4 MHz
457*4882a593Smuzhiyun  * CCP2       = 395.2 MHz
458*4882a593Smuzhiyun  * VCO        = 790.4 MHz
459*4882a593Smuzhiyun  * VCOUNT     = 250 (6000)
460*4882a593Smuzhiyun  * HCOUNT     = 137 (3288)
461*4882a593Smuzhiyun  * CKREF_DIV  = 2
462*4882a593Smuzhiyun  * CKVAR_DIV  = 247
463*4882a593Smuzhiyun  * VCO_DIV    = 1
464*4882a593Smuzhiyun  * SPCK_DIV   = 7
465*4882a593Smuzhiyun  * MRCK_DIV   = 7
466*4882a593Smuzhiyun  * LVDSCK_DIV = 0
467*4882a593Smuzhiyun  */
468*4882a593Smuzhiyun 	.type = ET8EK8_REGLIST_MODE,
469*4882a593Smuzhiyun 	.mode = {
470*4882a593Smuzhiyun 		.sensor_width = 2592,
471*4882a593Smuzhiyun 		.sensor_height = 1968,
472*4882a593Smuzhiyun 		.sensor_window_origin_x = 0,
473*4882a593Smuzhiyun 		.sensor_window_origin_y = 0,
474*4882a593Smuzhiyun 		.sensor_window_width = 2592,
475*4882a593Smuzhiyun 		.sensor_window_height = 1968,
476*4882a593Smuzhiyun 		.width = 3288,
477*4882a593Smuzhiyun 		.height = 3000,
478*4882a593Smuzhiyun 		.window_origin_x = 0,
479*4882a593Smuzhiyun 		.window_origin_y = 0,
480*4882a593Smuzhiyun 		.window_width = 1296,
481*4882a593Smuzhiyun 		.window_height = 984,
482*4882a593Smuzhiyun 		.pixel_clock = 49400000,
483*4882a593Smuzhiyun 		.ext_clock = 9600000,
484*4882a593Smuzhiyun 		.timeperframe = {
485*4882a593Smuzhiyun 			.numerator = 100,
486*4882a593Smuzhiyun 			.denominator = 501
487*4882a593Smuzhiyun 		},
488*4882a593Smuzhiyun 		.max_exp = 2996,
489*4882a593Smuzhiyun 		/* .max_gain = 0, */
490*4882a593Smuzhiyun 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
491*4882a593Smuzhiyun 		.sensitivity = 65536
492*4882a593Smuzhiyun 	},
493*4882a593Smuzhiyun 	.regs = {
494*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1239, 0x7B },
495*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1238, 0x82 },
496*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
497*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123A, 0x17 },
498*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121B, 0x63 },
499*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121D, 0x63 },
500*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
501*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
502*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
503*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1222, 0xFA },
504*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
505*4882a593Smuzhiyun 		{ ET8EK8_REG_TERM, 0, 0}
506*4882a593Smuzhiyun 	}
507*4882a593Smuzhiyun };
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun /* Mode_4VGA_1296x984_25fps_DPCM10-8 */
510*4882a593Smuzhiyun static struct et8ek8_reglist mode_4vga_1296x984_25fps_dpcm10_8 = {
511*4882a593Smuzhiyun /* (without the +1)
512*4882a593Smuzhiyun  * SPCK       = 84.2666666666667 MHz
513*4882a593Smuzhiyun  * CCP2       = 505.6 MHz
514*4882a593Smuzhiyun  * VCO        = 505.6 MHz
515*4882a593Smuzhiyun  * VCOUNT     = 88 (2112)
516*4882a593Smuzhiyun  * HCOUNT     = 133 (3192)
517*4882a593Smuzhiyun  * CKREF_DIV  = 2
518*4882a593Smuzhiyun  * CKVAR_DIV  = 158
519*4882a593Smuzhiyun  * VCO_DIV    = 0
520*4882a593Smuzhiyun  * SPCK_DIV   = 5
521*4882a593Smuzhiyun  * MRCK_DIV   = 7
522*4882a593Smuzhiyun  * LVDSCK_DIV = 0
523*4882a593Smuzhiyun  */
524*4882a593Smuzhiyun 	.type = ET8EK8_REGLIST_MODE,
525*4882a593Smuzhiyun 	.mode = {
526*4882a593Smuzhiyun 		.sensor_width = 2592,
527*4882a593Smuzhiyun 		.sensor_height = 1968,
528*4882a593Smuzhiyun 		.sensor_window_origin_x = 0,
529*4882a593Smuzhiyun 		.sensor_window_origin_y = 0,
530*4882a593Smuzhiyun 		.sensor_window_width = 2592,
531*4882a593Smuzhiyun 		.sensor_window_height = 1968,
532*4882a593Smuzhiyun 		.width = 3192,
533*4882a593Smuzhiyun 		.height = 1056,
534*4882a593Smuzhiyun 		.window_origin_x = 0,
535*4882a593Smuzhiyun 		.window_origin_y = 0,
536*4882a593Smuzhiyun 		.window_width = 1296,
537*4882a593Smuzhiyun 		.window_height = 984,
538*4882a593Smuzhiyun 		.pixel_clock = 84266667,
539*4882a593Smuzhiyun 		.ext_clock = 9600000,
540*4882a593Smuzhiyun 		.timeperframe = {
541*4882a593Smuzhiyun 			.numerator = 100,
542*4882a593Smuzhiyun 			.denominator = 2500
543*4882a593Smuzhiyun 		},
544*4882a593Smuzhiyun 		.max_exp = 1052,
545*4882a593Smuzhiyun 		/* .max_gain = 0, */
546*4882a593Smuzhiyun 		.bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
547*4882a593Smuzhiyun 		.sensitivity = 65536
548*4882a593Smuzhiyun 	},
549*4882a593Smuzhiyun 	.regs = {
550*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1239, 0x4F },
551*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
552*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
553*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x123A, 0x05 },
554*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121B, 0x63 },
555*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1220, 0x85 },
556*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
557*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1222, 0x58 },
558*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
559*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x121D, 0x63 },
560*4882a593Smuzhiyun 		{ ET8EK8_REG_8BIT, 0x125D, 0x83 },
561*4882a593Smuzhiyun 		{ ET8EK8_REG_TERM, 0, 0}
562*4882a593Smuzhiyun 	}
563*4882a593Smuzhiyun };
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun struct et8ek8_meta_reglist meta_reglist = {
566*4882a593Smuzhiyun 	.version = "V14 03-June-2008",
567*4882a593Smuzhiyun 	.reglist = {
568*4882a593Smuzhiyun 		{ .ptr = &mode1_poweron_mode2_16vga_2592x1968_12_07fps },
569*4882a593Smuzhiyun 		{ .ptr = &mode1_16vga_2592x1968_13_12fps_dpcm10_8 },
570*4882a593Smuzhiyun 		{ .ptr = &mode3_4vga_1296x984_29_99fps_dpcm10_8 },
571*4882a593Smuzhiyun 		{ .ptr = &mode4_svga_864x656_29_88fps },
572*4882a593Smuzhiyun 		{ .ptr = &mode5_vga_648x492_29_93fps },
573*4882a593Smuzhiyun 		{ .ptr = &mode2_16vga_2592x1968_3_99fps },
574*4882a593Smuzhiyun 		{ .ptr = &mode_648x492_5fps },
575*4882a593Smuzhiyun 		{ .ptr = &mode3_4vga_1296x984_5fps },
576*4882a593Smuzhiyun 		{ .ptr = &mode_4vga_1296x984_25fps_dpcm10_8 },
577*4882a593Smuzhiyun 		{ .ptr = NULL }
578*4882a593Smuzhiyun 	}
579*4882a593Smuzhiyun };
580