1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Aptina Sensor PLL Configuration 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Laurent Pinchart <laurent.pinchart@ideasonboard.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __APTINA_PLL_H 9*4882a593Smuzhiyun #define __APTINA_PLL_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct aptina_pll { 12*4882a593Smuzhiyun unsigned int ext_clock; 13*4882a593Smuzhiyun unsigned int pix_clock; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun unsigned int n; 16*4882a593Smuzhiyun unsigned int m; 17*4882a593Smuzhiyun unsigned int p1; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct aptina_pll_limits { 21*4882a593Smuzhiyun unsigned int ext_clock_min; 22*4882a593Smuzhiyun unsigned int ext_clock_max; 23*4882a593Smuzhiyun unsigned int int_clock_min; 24*4882a593Smuzhiyun unsigned int int_clock_max; 25*4882a593Smuzhiyun unsigned int out_clock_min; 26*4882a593Smuzhiyun unsigned int out_clock_max; 27*4882a593Smuzhiyun unsigned int pix_clock_max; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun unsigned int n_min; 30*4882a593Smuzhiyun unsigned int n_max; 31*4882a593Smuzhiyun unsigned int m_min; 32*4882a593Smuzhiyun unsigned int m_max; 33*4882a593Smuzhiyun unsigned int p1_min; 34*4882a593Smuzhiyun unsigned int p1_max; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct device; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun int aptina_pll_calculate(struct device *dev, 40*4882a593Smuzhiyun const struct aptina_pll_limits *limits, 41*4882a593Smuzhiyun struct aptina_pll *pll); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #endif /* __APTINA_PLL_H */ 44