1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for Analog Devices ADV748X 8 channel analog front end (AFE) receiver
4*4882a593Smuzhiyun * with standard definition processor (SDP)
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2017 Renesas Electronics Corp.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/mutex.h>
12*4882a593Smuzhiyun #include <linux/v4l2-dv-timings.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
15*4882a593Smuzhiyun #include <media/v4l2-device.h>
16*4882a593Smuzhiyun #include <media/v4l2-dv-timings.h>
17*4882a593Smuzhiyun #include <media/v4l2-ioctl.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "adv748x.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
22*4882a593Smuzhiyun * SDP
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define ADV748X_AFE_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
26*4882a593Smuzhiyun #define ADV748X_AFE_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
27*4882a593Smuzhiyun #define ADV748X_AFE_STD_AD_PAL_N_NTSC_J_SECAM 0x2
28*4882a593Smuzhiyun #define ADV748X_AFE_STD_AD_PAL_N_NTSC_M_SECAM 0x3
29*4882a593Smuzhiyun #define ADV748X_AFE_STD_NTSC_J 0x4
30*4882a593Smuzhiyun #define ADV748X_AFE_STD_NTSC_M 0x5
31*4882a593Smuzhiyun #define ADV748X_AFE_STD_PAL60 0x6
32*4882a593Smuzhiyun #define ADV748X_AFE_STD_NTSC_443 0x7
33*4882a593Smuzhiyun #define ADV748X_AFE_STD_PAL_BG 0x8
34*4882a593Smuzhiyun #define ADV748X_AFE_STD_PAL_N 0x9
35*4882a593Smuzhiyun #define ADV748X_AFE_STD_PAL_M 0xa
36*4882a593Smuzhiyun #define ADV748X_AFE_STD_PAL_M_PED 0xb
37*4882a593Smuzhiyun #define ADV748X_AFE_STD_PAL_COMB_N 0xc
38*4882a593Smuzhiyun #define ADV748X_AFE_STD_PAL_COMB_N_PED 0xd
39*4882a593Smuzhiyun #define ADV748X_AFE_STD_PAL_SECAM 0xe
40*4882a593Smuzhiyun #define ADV748X_AFE_STD_PAL_SECAM_PED 0xf
41*4882a593Smuzhiyun
adv748x_afe_read_ro_map(struct adv748x_state * state,u8 reg)42*4882a593Smuzhiyun static int adv748x_afe_read_ro_map(struct adv748x_state *state, u8 reg)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun int ret;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Select SDP Read-Only Main Map */
47*4882a593Smuzhiyun ret = sdp_write(state, ADV748X_SDP_MAP_SEL,
48*4882a593Smuzhiyun ADV748X_SDP_MAP_SEL_RO_MAIN);
49*4882a593Smuzhiyun if (ret < 0)
50*4882a593Smuzhiyun return ret;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return sdp_read(state, reg);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
adv748x_afe_status(struct adv748x_afe * afe,u32 * signal,v4l2_std_id * std)55*4882a593Smuzhiyun static int adv748x_afe_status(struct adv748x_afe *afe, u32 *signal,
56*4882a593Smuzhiyun v4l2_std_id *std)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun struct adv748x_state *state = adv748x_afe_to_state(afe);
59*4882a593Smuzhiyun int info;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Read status from reg 0x10 of SDP RO Map */
62*4882a593Smuzhiyun info = adv748x_afe_read_ro_map(state, ADV748X_SDP_RO_10);
63*4882a593Smuzhiyun if (info < 0)
64*4882a593Smuzhiyun return info;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (signal)
67*4882a593Smuzhiyun *signal = info & ADV748X_SDP_RO_10_IN_LOCK ?
68*4882a593Smuzhiyun 0 : V4L2_IN_ST_NO_SIGNAL;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (!std)
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* Standard not valid if there is no signal */
74*4882a593Smuzhiyun if (!(info & ADV748X_SDP_RO_10_IN_LOCK)) {
75*4882a593Smuzhiyun *std = V4L2_STD_UNKNOWN;
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun switch (info & 0x70) {
80*4882a593Smuzhiyun case 0x00:
81*4882a593Smuzhiyun *std = V4L2_STD_NTSC;
82*4882a593Smuzhiyun break;
83*4882a593Smuzhiyun case 0x10:
84*4882a593Smuzhiyun *std = V4L2_STD_NTSC_443;
85*4882a593Smuzhiyun break;
86*4882a593Smuzhiyun case 0x20:
87*4882a593Smuzhiyun *std = V4L2_STD_PAL_M;
88*4882a593Smuzhiyun break;
89*4882a593Smuzhiyun case 0x30:
90*4882a593Smuzhiyun *std = V4L2_STD_PAL_60;
91*4882a593Smuzhiyun break;
92*4882a593Smuzhiyun case 0x40:
93*4882a593Smuzhiyun *std = V4L2_STD_PAL;
94*4882a593Smuzhiyun break;
95*4882a593Smuzhiyun case 0x50:
96*4882a593Smuzhiyun *std = V4L2_STD_SECAM;
97*4882a593Smuzhiyun break;
98*4882a593Smuzhiyun case 0x60:
99*4882a593Smuzhiyun *std = V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
100*4882a593Smuzhiyun break;
101*4882a593Smuzhiyun case 0x70:
102*4882a593Smuzhiyun *std = V4L2_STD_SECAM;
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun default:
105*4882a593Smuzhiyun *std = V4L2_STD_UNKNOWN;
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
adv748x_afe_fill_format(struct adv748x_afe * afe,struct v4l2_mbus_framefmt * fmt)112*4882a593Smuzhiyun static void adv748x_afe_fill_format(struct adv748x_afe *afe,
113*4882a593Smuzhiyun struct v4l2_mbus_framefmt *fmt)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun memset(fmt, 0, sizeof(*fmt));
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
118*4882a593Smuzhiyun fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
119*4882a593Smuzhiyun fmt->field = V4L2_FIELD_ALTERNATE;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun fmt->width = 720;
122*4882a593Smuzhiyun fmt->height = afe->curr_norm & V4L2_STD_525_60 ? 480 : 576;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* Field height */
125*4882a593Smuzhiyun fmt->height /= 2;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
adv748x_afe_std(v4l2_std_id std)128*4882a593Smuzhiyun static int adv748x_afe_std(v4l2_std_id std)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun if (std == V4L2_STD_PAL_60)
131*4882a593Smuzhiyun return ADV748X_AFE_STD_PAL60;
132*4882a593Smuzhiyun if (std == V4L2_STD_NTSC_443)
133*4882a593Smuzhiyun return ADV748X_AFE_STD_NTSC_443;
134*4882a593Smuzhiyun if (std == V4L2_STD_PAL_N)
135*4882a593Smuzhiyun return ADV748X_AFE_STD_PAL_N;
136*4882a593Smuzhiyun if (std == V4L2_STD_PAL_M)
137*4882a593Smuzhiyun return ADV748X_AFE_STD_PAL_M;
138*4882a593Smuzhiyun if (std == V4L2_STD_PAL_Nc)
139*4882a593Smuzhiyun return ADV748X_AFE_STD_PAL_COMB_N;
140*4882a593Smuzhiyun if (std & V4L2_STD_NTSC)
141*4882a593Smuzhiyun return ADV748X_AFE_STD_NTSC_M;
142*4882a593Smuzhiyun if (std & V4L2_STD_PAL)
143*4882a593Smuzhiyun return ADV748X_AFE_STD_PAL_BG;
144*4882a593Smuzhiyun if (std & V4L2_STD_SECAM)
145*4882a593Smuzhiyun return ADV748X_AFE_STD_PAL_SECAM;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return -EINVAL;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
adv748x_afe_set_video_standard(struct adv748x_state * state,int sdpstd)150*4882a593Smuzhiyun static void adv748x_afe_set_video_standard(struct adv748x_state *state,
151*4882a593Smuzhiyun int sdpstd)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun sdp_clrset(state, ADV748X_SDP_VID_SEL, ADV748X_SDP_VID_SEL_MASK,
154*4882a593Smuzhiyun (sdpstd & 0xf) << ADV748X_SDP_VID_SEL_SHIFT);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
adv748x_afe_s_input(struct adv748x_afe * afe,unsigned int input)157*4882a593Smuzhiyun static int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun struct adv748x_state *state = adv748x_afe_to_state(afe);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun return sdp_write(state, ADV748X_SDP_INSEL, input);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
adv748x_afe_g_pixelaspect(struct v4l2_subdev * sd,struct v4l2_fract * aspect)164*4882a593Smuzhiyun static int adv748x_afe_g_pixelaspect(struct v4l2_subdev *sd,
165*4882a593Smuzhiyun struct v4l2_fract *aspect)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun if (afe->curr_norm & V4L2_STD_525_60) {
170*4882a593Smuzhiyun aspect->numerator = 11;
171*4882a593Smuzhiyun aspect->denominator = 10;
172*4882a593Smuzhiyun } else {
173*4882a593Smuzhiyun aspect->numerator = 54;
174*4882a593Smuzhiyun aspect->denominator = 59;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun return 0;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
181*4882a593Smuzhiyun * v4l2_subdev_video_ops
182*4882a593Smuzhiyun */
183*4882a593Smuzhiyun
adv748x_afe_g_std(struct v4l2_subdev * sd,v4l2_std_id * norm)184*4882a593Smuzhiyun static int adv748x_afe_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun *norm = afe->curr_norm;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun return 0;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
adv748x_afe_s_std(struct v4l2_subdev * sd,v4l2_std_id std)193*4882a593Smuzhiyun static int adv748x_afe_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
196*4882a593Smuzhiyun struct adv748x_state *state = adv748x_afe_to_state(afe);
197*4882a593Smuzhiyun int afe_std = adv748x_afe_std(std);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun if (afe_std < 0)
200*4882a593Smuzhiyun return afe_std;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun mutex_lock(&state->mutex);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun adv748x_afe_set_video_standard(state, afe_std);
205*4882a593Smuzhiyun afe->curr_norm = std;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun mutex_unlock(&state->mutex);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun return 0;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
adv748x_afe_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)212*4882a593Smuzhiyun static int adv748x_afe_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
215*4882a593Smuzhiyun struct adv748x_state *state = adv748x_afe_to_state(afe);
216*4882a593Smuzhiyun int afe_std;
217*4882a593Smuzhiyun int ret;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun mutex_lock(&state->mutex);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun if (afe->streaming) {
222*4882a593Smuzhiyun ret = -EBUSY;
223*4882a593Smuzhiyun goto unlock;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* Set auto detect mode */
227*4882a593Smuzhiyun adv748x_afe_set_video_standard(state,
228*4882a593Smuzhiyun ADV748X_AFE_STD_AD_PAL_BG_NTSC_J_SECAM);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun msleep(100);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /* Read detected standard */
233*4882a593Smuzhiyun ret = adv748x_afe_status(afe, NULL, std);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun afe_std = adv748x_afe_std(afe->curr_norm);
236*4882a593Smuzhiyun if (afe_std < 0)
237*4882a593Smuzhiyun goto unlock;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /* Restore original state */
240*4882a593Smuzhiyun adv748x_afe_set_video_standard(state, afe_std);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun unlock:
243*4882a593Smuzhiyun mutex_unlock(&state->mutex);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun return ret;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
adv748x_afe_g_tvnorms(struct v4l2_subdev * sd,v4l2_std_id * norm)248*4882a593Smuzhiyun static int adv748x_afe_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun *norm = V4L2_STD_ALL;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun return 0;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
adv748x_afe_g_input_status(struct v4l2_subdev * sd,u32 * status)255*4882a593Smuzhiyun static int adv748x_afe_g_input_status(struct v4l2_subdev *sd, u32 *status)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
258*4882a593Smuzhiyun struct adv748x_state *state = adv748x_afe_to_state(afe);
259*4882a593Smuzhiyun int ret;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun mutex_lock(&state->mutex);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun ret = adv748x_afe_status(afe, status, NULL);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun mutex_unlock(&state->mutex);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun return ret;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
adv748x_afe_s_stream(struct v4l2_subdev * sd,int enable)270*4882a593Smuzhiyun static int adv748x_afe_s_stream(struct v4l2_subdev *sd, int enable)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
273*4882a593Smuzhiyun struct adv748x_state *state = adv748x_afe_to_state(afe);
274*4882a593Smuzhiyun u32 signal = V4L2_IN_ST_NO_SIGNAL;
275*4882a593Smuzhiyun int ret;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun mutex_lock(&state->mutex);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun if (enable) {
280*4882a593Smuzhiyun ret = adv748x_afe_s_input(afe, afe->input);
281*4882a593Smuzhiyun if (ret)
282*4882a593Smuzhiyun goto unlock;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun ret = adv748x_tx_power(afe->tx, enable);
286*4882a593Smuzhiyun if (ret)
287*4882a593Smuzhiyun goto unlock;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun afe->streaming = enable;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun adv748x_afe_status(afe, &signal, NULL);
292*4882a593Smuzhiyun if (signal != V4L2_IN_ST_NO_SIGNAL)
293*4882a593Smuzhiyun adv_dbg(state, "Detected SDP signal\n");
294*4882a593Smuzhiyun else
295*4882a593Smuzhiyun adv_dbg(state, "Couldn't detect SDP video signal\n");
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun unlock:
298*4882a593Smuzhiyun mutex_unlock(&state->mutex);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun return ret;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops adv748x_afe_video_ops = {
304*4882a593Smuzhiyun .g_std = adv748x_afe_g_std,
305*4882a593Smuzhiyun .s_std = adv748x_afe_s_std,
306*4882a593Smuzhiyun .querystd = adv748x_afe_querystd,
307*4882a593Smuzhiyun .g_tvnorms = adv748x_afe_g_tvnorms,
308*4882a593Smuzhiyun .g_input_status = adv748x_afe_g_input_status,
309*4882a593Smuzhiyun .s_stream = adv748x_afe_s_stream,
310*4882a593Smuzhiyun .g_pixelaspect = adv748x_afe_g_pixelaspect,
311*4882a593Smuzhiyun };
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
314*4882a593Smuzhiyun * v4l2_subdev_pad_ops
315*4882a593Smuzhiyun */
316*4882a593Smuzhiyun
adv748x_afe_propagate_pixelrate(struct adv748x_afe * afe)317*4882a593Smuzhiyun static int adv748x_afe_propagate_pixelrate(struct adv748x_afe *afe)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun struct v4l2_subdev *tx;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun tx = adv748x_get_remote_sd(&afe->pads[ADV748X_AFE_SOURCE]);
322*4882a593Smuzhiyun if (!tx)
323*4882a593Smuzhiyun return -ENOLINK;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /*
326*4882a593Smuzhiyun * The ADV748x ADC sampling frequency is twice the externally supplied
327*4882a593Smuzhiyun * clock whose frequency is required to be 28.63636 MHz. It oversamples
328*4882a593Smuzhiyun * with a factor of 4 resulting in a pixel rate of 14.3180180 MHz.
329*4882a593Smuzhiyun */
330*4882a593Smuzhiyun return adv748x_csi2_set_pixelrate(tx, 14318180);
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
adv748x_afe_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)333*4882a593Smuzhiyun static int adv748x_afe_enum_mbus_code(struct v4l2_subdev *sd,
334*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
335*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun if (code->index != 0)
338*4882a593Smuzhiyun return -EINVAL;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun code->code = MEDIA_BUS_FMT_UYVY8_2X8;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun return 0;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
adv748x_afe_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * sdformat)345*4882a593Smuzhiyun static int adv748x_afe_get_format(struct v4l2_subdev *sd,
346*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
347*4882a593Smuzhiyun struct v4l2_subdev_format *sdformat)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
350*4882a593Smuzhiyun struct v4l2_mbus_framefmt *mbusformat;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun /* It makes no sense to get the format of the analog sink pads */
353*4882a593Smuzhiyun if (sdformat->pad != ADV748X_AFE_SOURCE)
354*4882a593Smuzhiyun return -EINVAL;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun if (sdformat->which == V4L2_SUBDEV_FORMAT_TRY) {
357*4882a593Smuzhiyun mbusformat = v4l2_subdev_get_try_format(sd, cfg, sdformat->pad);
358*4882a593Smuzhiyun sdformat->format = *mbusformat;
359*4882a593Smuzhiyun } else {
360*4882a593Smuzhiyun adv748x_afe_fill_format(afe, &sdformat->format);
361*4882a593Smuzhiyun adv748x_afe_propagate_pixelrate(afe);
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun return 0;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
adv748x_afe_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * sdformat)367*4882a593Smuzhiyun static int adv748x_afe_set_format(struct v4l2_subdev *sd,
368*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
369*4882a593Smuzhiyun struct v4l2_subdev_format *sdformat)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun struct v4l2_mbus_framefmt *mbusformat;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun /* It makes no sense to get the format of the analog sink pads */
374*4882a593Smuzhiyun if (sdformat->pad != ADV748X_AFE_SOURCE)
375*4882a593Smuzhiyun return -EINVAL;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
378*4882a593Smuzhiyun return adv748x_afe_get_format(sd, cfg, sdformat);
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun mbusformat = v4l2_subdev_get_try_format(sd, cfg, sdformat->pad);
381*4882a593Smuzhiyun *mbusformat = sdformat->format;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun return 0;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops adv748x_afe_pad_ops = {
387*4882a593Smuzhiyun .enum_mbus_code = adv748x_afe_enum_mbus_code,
388*4882a593Smuzhiyun .set_fmt = adv748x_afe_set_format,
389*4882a593Smuzhiyun .get_fmt = adv748x_afe_get_format,
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
393*4882a593Smuzhiyun * v4l2_subdev_ops
394*4882a593Smuzhiyun */
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun static const struct v4l2_subdev_ops adv748x_afe_ops = {
397*4882a593Smuzhiyun .video = &adv748x_afe_video_ops,
398*4882a593Smuzhiyun .pad = &adv748x_afe_pad_ops,
399*4882a593Smuzhiyun };
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
402*4882a593Smuzhiyun * Controls
403*4882a593Smuzhiyun */
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun static const char * const afe_ctrl_frp_menu[] = {
406*4882a593Smuzhiyun "Disabled",
407*4882a593Smuzhiyun "Solid Blue",
408*4882a593Smuzhiyun "Color Bars",
409*4882a593Smuzhiyun "Grey Ramp",
410*4882a593Smuzhiyun "Cb Ramp",
411*4882a593Smuzhiyun "Cr Ramp",
412*4882a593Smuzhiyun "Boundary"
413*4882a593Smuzhiyun };
414*4882a593Smuzhiyun
adv748x_afe_s_ctrl(struct v4l2_ctrl * ctrl)415*4882a593Smuzhiyun static int adv748x_afe_s_ctrl(struct v4l2_ctrl *ctrl)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun struct adv748x_afe *afe = adv748x_ctrl_to_afe(ctrl);
418*4882a593Smuzhiyun struct adv748x_state *state = adv748x_afe_to_state(afe);
419*4882a593Smuzhiyun bool enable;
420*4882a593Smuzhiyun int ret;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun ret = sdp_write(state, 0x0e, 0x00);
423*4882a593Smuzhiyun if (ret < 0)
424*4882a593Smuzhiyun return ret;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun switch (ctrl->id) {
427*4882a593Smuzhiyun case V4L2_CID_BRIGHTNESS:
428*4882a593Smuzhiyun ret = sdp_write(state, ADV748X_SDP_BRI, ctrl->val);
429*4882a593Smuzhiyun break;
430*4882a593Smuzhiyun case V4L2_CID_HUE:
431*4882a593Smuzhiyun /* Hue is inverted according to HSL chart */
432*4882a593Smuzhiyun ret = sdp_write(state, ADV748X_SDP_HUE, -ctrl->val);
433*4882a593Smuzhiyun break;
434*4882a593Smuzhiyun case V4L2_CID_CONTRAST:
435*4882a593Smuzhiyun ret = sdp_write(state, ADV748X_SDP_CON, ctrl->val);
436*4882a593Smuzhiyun break;
437*4882a593Smuzhiyun case V4L2_CID_SATURATION:
438*4882a593Smuzhiyun ret = sdp_write(state, ADV748X_SDP_SD_SAT_U, ctrl->val);
439*4882a593Smuzhiyun if (ret)
440*4882a593Smuzhiyun break;
441*4882a593Smuzhiyun ret = sdp_write(state, ADV748X_SDP_SD_SAT_V, ctrl->val);
442*4882a593Smuzhiyun break;
443*4882a593Smuzhiyun case V4L2_CID_TEST_PATTERN:
444*4882a593Smuzhiyun enable = !!ctrl->val;
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun /* Enable/Disable Color bar test patterns */
447*4882a593Smuzhiyun ret = sdp_clrset(state, ADV748X_SDP_DEF, ADV748X_SDP_DEF_VAL_EN,
448*4882a593Smuzhiyun enable);
449*4882a593Smuzhiyun if (ret)
450*4882a593Smuzhiyun break;
451*4882a593Smuzhiyun ret = sdp_clrset(state, ADV748X_SDP_FRP, ADV748X_SDP_FRP_MASK,
452*4882a593Smuzhiyun enable ? ctrl->val - 1 : 0);
453*4882a593Smuzhiyun break;
454*4882a593Smuzhiyun default:
455*4882a593Smuzhiyun return -EINVAL;
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun return ret;
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun static const struct v4l2_ctrl_ops adv748x_afe_ctrl_ops = {
462*4882a593Smuzhiyun .s_ctrl = adv748x_afe_s_ctrl,
463*4882a593Smuzhiyun };
464*4882a593Smuzhiyun
adv748x_afe_init_controls(struct adv748x_afe * afe)465*4882a593Smuzhiyun static int adv748x_afe_init_controls(struct adv748x_afe *afe)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun struct adv748x_state *state = adv748x_afe_to_state(afe);
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun v4l2_ctrl_handler_init(&afe->ctrl_hdl, 5);
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun /* Use our mutex for the controls */
472*4882a593Smuzhiyun afe->ctrl_hdl.lock = &state->mutex;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun v4l2_ctrl_new_std(&afe->ctrl_hdl, &adv748x_afe_ctrl_ops,
475*4882a593Smuzhiyun V4L2_CID_BRIGHTNESS, ADV748X_SDP_BRI_MIN,
476*4882a593Smuzhiyun ADV748X_SDP_BRI_MAX, 1, ADV748X_SDP_BRI_DEF);
477*4882a593Smuzhiyun v4l2_ctrl_new_std(&afe->ctrl_hdl, &adv748x_afe_ctrl_ops,
478*4882a593Smuzhiyun V4L2_CID_CONTRAST, ADV748X_SDP_CON_MIN,
479*4882a593Smuzhiyun ADV748X_SDP_CON_MAX, 1, ADV748X_SDP_CON_DEF);
480*4882a593Smuzhiyun v4l2_ctrl_new_std(&afe->ctrl_hdl, &adv748x_afe_ctrl_ops,
481*4882a593Smuzhiyun V4L2_CID_SATURATION, ADV748X_SDP_SAT_MIN,
482*4882a593Smuzhiyun ADV748X_SDP_SAT_MAX, 1, ADV748X_SDP_SAT_DEF);
483*4882a593Smuzhiyun v4l2_ctrl_new_std(&afe->ctrl_hdl, &adv748x_afe_ctrl_ops,
484*4882a593Smuzhiyun V4L2_CID_HUE, ADV748X_SDP_HUE_MIN,
485*4882a593Smuzhiyun ADV748X_SDP_HUE_MAX, 1, ADV748X_SDP_HUE_DEF);
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun v4l2_ctrl_new_std_menu_items(&afe->ctrl_hdl, &adv748x_afe_ctrl_ops,
488*4882a593Smuzhiyun V4L2_CID_TEST_PATTERN,
489*4882a593Smuzhiyun ARRAY_SIZE(afe_ctrl_frp_menu) - 1,
490*4882a593Smuzhiyun 0, 0, afe_ctrl_frp_menu);
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun afe->sd.ctrl_handler = &afe->ctrl_hdl;
493*4882a593Smuzhiyun if (afe->ctrl_hdl.error) {
494*4882a593Smuzhiyun v4l2_ctrl_handler_free(&afe->ctrl_hdl);
495*4882a593Smuzhiyun return afe->ctrl_hdl.error;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun return v4l2_ctrl_handler_setup(&afe->ctrl_hdl);
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun
adv748x_afe_init(struct adv748x_afe * afe)501*4882a593Smuzhiyun int adv748x_afe_init(struct adv748x_afe *afe)
502*4882a593Smuzhiyun {
503*4882a593Smuzhiyun struct adv748x_state *state = adv748x_afe_to_state(afe);
504*4882a593Smuzhiyun int ret;
505*4882a593Smuzhiyun unsigned int i;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun afe->input = 0;
508*4882a593Smuzhiyun afe->streaming = false;
509*4882a593Smuzhiyun afe->curr_norm = V4L2_STD_NTSC_M;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun adv748x_subdev_init(&afe->sd, state, &adv748x_afe_ops,
512*4882a593Smuzhiyun MEDIA_ENT_F_ATV_DECODER, "afe");
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun /* Identify the first connector found as a default input if set */
515*4882a593Smuzhiyun for (i = ADV748X_PORT_AIN0; i <= ADV748X_PORT_AIN7; i++) {
516*4882a593Smuzhiyun /* Inputs and ports are 1-indexed to match the data sheet */
517*4882a593Smuzhiyun if (state->endpoints[i]) {
518*4882a593Smuzhiyun afe->input = i;
519*4882a593Smuzhiyun break;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun adv748x_afe_s_input(afe, afe->input);
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun adv_dbg(state, "AFE Default input set to %d\n", afe->input);
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun /* Entity pads and sinks are 0-indexed to match the pads */
528*4882a593Smuzhiyun for (i = ADV748X_AFE_SINK_AIN0; i <= ADV748X_AFE_SINK_AIN7; i++)
529*4882a593Smuzhiyun afe->pads[i].flags = MEDIA_PAD_FL_SINK;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun afe->pads[ADV748X_AFE_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun ret = media_entity_pads_init(&afe->sd.entity, ADV748X_AFE_NR_PADS,
534*4882a593Smuzhiyun afe->pads);
535*4882a593Smuzhiyun if (ret)
536*4882a593Smuzhiyun return ret;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun ret = adv748x_afe_init_controls(afe);
539*4882a593Smuzhiyun if (ret)
540*4882a593Smuzhiyun goto error;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun return 0;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun error:
545*4882a593Smuzhiyun media_entity_cleanup(&afe->sd.entity);
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun return ret;
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
adv748x_afe_cleanup(struct adv748x_afe * afe)550*4882a593Smuzhiyun void adv748x_afe_cleanup(struct adv748x_afe *afe)
551*4882a593Smuzhiyun {
552*4882a593Smuzhiyun v4l2_device_unregister_subdev(&afe->sd);
553*4882a593Smuzhiyun media_entity_cleanup(&afe->sd.entity);
554*4882a593Smuzhiyun v4l2_ctrl_handler_free(&afe->ctrl_hdl);
555*4882a593Smuzhiyun }
556