xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/adv7393.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * adv7393 - ADV7393 Video Encoder Driver
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * The encoder hardware does not support SECAM.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2010-2012 ADVANSEE - http://www.advansee.com/
7*4882a593Smuzhiyun  * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Based on ADV7343 driver,
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or
14*4882a593Smuzhiyun  * modify it under the terms of the GNU General Public License as
15*4882a593Smuzhiyun  * published by the Free Software Foundation version 2.
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
18*4882a593Smuzhiyun  * kind, whether express or implied; without even the implied warranty
19*4882a593Smuzhiyun  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20*4882a593Smuzhiyun  * GNU General Public License for more details.
21*4882a593Smuzhiyun  */
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include <linux/kernel.h>
24*4882a593Smuzhiyun #include <linux/init.h>
25*4882a593Smuzhiyun #include <linux/ctype.h>
26*4882a593Smuzhiyun #include <linux/slab.h>
27*4882a593Smuzhiyun #include <linux/i2c.h>
28*4882a593Smuzhiyun #include <linux/device.h>
29*4882a593Smuzhiyun #include <linux/delay.h>
30*4882a593Smuzhiyun #include <linux/module.h>
31*4882a593Smuzhiyun #include <linux/videodev2.h>
32*4882a593Smuzhiyun #include <linux/uaccess.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #include <media/i2c/adv7393.h>
35*4882a593Smuzhiyun #include <media/v4l2-device.h>
36*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #include "adv7393_regs.h"
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun MODULE_DESCRIPTION("ADV7393 video encoder driver");
41*4882a593Smuzhiyun MODULE_LICENSE("GPL");
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun static bool debug;
44*4882a593Smuzhiyun module_param(debug, bool, 0644);
45*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level 0-1");
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun struct adv7393_state {
48*4882a593Smuzhiyun 	struct v4l2_subdev sd;
49*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
50*4882a593Smuzhiyun 	u8 reg00;
51*4882a593Smuzhiyun 	u8 reg01;
52*4882a593Smuzhiyun 	u8 reg02;
53*4882a593Smuzhiyun 	u8 reg35;
54*4882a593Smuzhiyun 	u8 reg80;
55*4882a593Smuzhiyun 	u8 reg82;
56*4882a593Smuzhiyun 	u32 output;
57*4882a593Smuzhiyun 	v4l2_std_id std;
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
to_state(struct v4l2_subdev * sd)60*4882a593Smuzhiyun static inline struct adv7393_state *to_state(struct v4l2_subdev *sd)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun 	return container_of(sd, struct adv7393_state, sd);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
to_sd(struct v4l2_ctrl * ctrl)65*4882a593Smuzhiyun static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	return &container_of(ctrl->handler, struct adv7393_state, hdl)->sd;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
adv7393_write(struct v4l2_subdev * sd,u8 reg,u8 value)70*4882a593Smuzhiyun static inline int adv7393_write(struct v4l2_subdev *sd, u8 reg, u8 value)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	return i2c_smbus_write_byte_data(client, reg, value);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun static const u8 adv7393_init_reg_val[] = {
78*4882a593Smuzhiyun 	ADV7393_SOFT_RESET, ADV7393_SOFT_RESET_DEFAULT,
79*4882a593Smuzhiyun 	ADV7393_POWER_MODE_REG, ADV7393_POWER_MODE_REG_DEFAULT,
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	ADV7393_HD_MODE_REG1, ADV7393_HD_MODE_REG1_DEFAULT,
82*4882a593Smuzhiyun 	ADV7393_HD_MODE_REG2, ADV7393_HD_MODE_REG2_DEFAULT,
83*4882a593Smuzhiyun 	ADV7393_HD_MODE_REG3, ADV7393_HD_MODE_REG3_DEFAULT,
84*4882a593Smuzhiyun 	ADV7393_HD_MODE_REG4, ADV7393_HD_MODE_REG4_DEFAULT,
85*4882a593Smuzhiyun 	ADV7393_HD_MODE_REG5, ADV7393_HD_MODE_REG5_DEFAULT,
86*4882a593Smuzhiyun 	ADV7393_HD_MODE_REG6, ADV7393_HD_MODE_REG6_DEFAULT,
87*4882a593Smuzhiyun 	ADV7393_HD_MODE_REG7, ADV7393_HD_MODE_REG7_DEFAULT,
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	ADV7393_SD_MODE_REG1, ADV7393_SD_MODE_REG1_DEFAULT,
90*4882a593Smuzhiyun 	ADV7393_SD_MODE_REG2, ADV7393_SD_MODE_REG2_DEFAULT,
91*4882a593Smuzhiyun 	ADV7393_SD_MODE_REG3, ADV7393_SD_MODE_REG3_DEFAULT,
92*4882a593Smuzhiyun 	ADV7393_SD_MODE_REG4, ADV7393_SD_MODE_REG4_DEFAULT,
93*4882a593Smuzhiyun 	ADV7393_SD_MODE_REG5, ADV7393_SD_MODE_REG5_DEFAULT,
94*4882a593Smuzhiyun 	ADV7393_SD_MODE_REG6, ADV7393_SD_MODE_REG6_DEFAULT,
95*4882a593Smuzhiyun 	ADV7393_SD_MODE_REG7, ADV7393_SD_MODE_REG7_DEFAULT,
96*4882a593Smuzhiyun 	ADV7393_SD_MODE_REG8, ADV7393_SD_MODE_REG8_DEFAULT,
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	ADV7393_SD_TIMING_REG0, ADV7393_SD_TIMING_REG0_DEFAULT,
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	ADV7393_SD_HUE_ADJUST, ADV7393_SD_HUE_ADJUST_DEFAULT,
101*4882a593Smuzhiyun 	ADV7393_SD_CGMS_WSS0, ADV7393_SD_CGMS_WSS0_DEFAULT,
102*4882a593Smuzhiyun 	ADV7393_SD_BRIGHTNESS_WSS, ADV7393_SD_BRIGHTNESS_WSS_DEFAULT,
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun  *			    2^32
107*4882a593Smuzhiyun  * FSC(reg) =  FSC (HZ) * --------
108*4882a593Smuzhiyun  *			  27000000
109*4882a593Smuzhiyun  */
110*4882a593Smuzhiyun static const struct adv7393_std_info stdinfo[] = {
111*4882a593Smuzhiyun 	{
112*4882a593Smuzhiyun 		/* FSC(Hz) = 4,433,618.75 Hz */
113*4882a593Smuzhiyun 		SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
114*4882a593Smuzhiyun 	}, {
115*4882a593Smuzhiyun 		/* FSC(Hz) = 3,579,545.45 Hz */
116*4882a593Smuzhiyun 		SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
117*4882a593Smuzhiyun 	}, {
118*4882a593Smuzhiyun 		/* FSC(Hz) = 3,575,611.00 Hz */
119*4882a593Smuzhiyun 		SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
120*4882a593Smuzhiyun 	}, {
121*4882a593Smuzhiyun 		/* FSC(Hz) = 3,582,056.00 Hz */
122*4882a593Smuzhiyun 		SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
123*4882a593Smuzhiyun 	}, {
124*4882a593Smuzhiyun 		/* FSC(Hz) = 4,433,618.75 Hz */
125*4882a593Smuzhiyun 		SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
126*4882a593Smuzhiyun 	}, {
127*4882a593Smuzhiyun 		/* FSC(Hz) = 4,433,618.75 Hz */
128*4882a593Smuzhiyun 		SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
129*4882a593Smuzhiyun 	}, {
130*4882a593Smuzhiyun 		/* FSC(Hz) = 4,433,618.75 Hz */
131*4882a593Smuzhiyun 		SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
132*4882a593Smuzhiyun 	},
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
adv7393_setstd(struct v4l2_subdev * sd,v4l2_std_id std)135*4882a593Smuzhiyun static int adv7393_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	struct adv7393_state *state = to_state(sd);
138*4882a593Smuzhiyun 	const struct adv7393_std_info *std_info;
139*4882a593Smuzhiyun 	int num_std;
140*4882a593Smuzhiyun 	u8 reg;
141*4882a593Smuzhiyun 	u32 val;
142*4882a593Smuzhiyun 	int err = 0;
143*4882a593Smuzhiyun 	int i;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	num_std = ARRAY_SIZE(stdinfo);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	for (i = 0; i < num_std; i++) {
148*4882a593Smuzhiyun 		if (stdinfo[i].stdid & std)
149*4882a593Smuzhiyun 			break;
150*4882a593Smuzhiyun 	}
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	if (i == num_std) {
153*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd,
154*4882a593Smuzhiyun 				"Invalid std or std is not supported: %llx\n",
155*4882a593Smuzhiyun 						(unsigned long long)std);
156*4882a593Smuzhiyun 		return -EINVAL;
157*4882a593Smuzhiyun 	}
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	std_info = &stdinfo[i];
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	/* Set the standard */
162*4882a593Smuzhiyun 	val = state->reg80 & ~SD_STD_MASK;
163*4882a593Smuzhiyun 	val |= std_info->standard_val3;
164*4882a593Smuzhiyun 	err = adv7393_write(sd, ADV7393_SD_MODE_REG1, val);
165*4882a593Smuzhiyun 	if (err < 0)
166*4882a593Smuzhiyun 		goto setstd_exit;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	state->reg80 = val;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	/* Configure the input mode register */
171*4882a593Smuzhiyun 	val = state->reg01 & ~INPUT_MODE_MASK;
172*4882a593Smuzhiyun 	val |= SD_INPUT_MODE;
173*4882a593Smuzhiyun 	err = adv7393_write(sd, ADV7393_MODE_SELECT_REG, val);
174*4882a593Smuzhiyun 	if (err < 0)
175*4882a593Smuzhiyun 		goto setstd_exit;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	state->reg01 = val;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	/* Program the sub carrier frequency registers */
180*4882a593Smuzhiyun 	val = std_info->fsc_val;
181*4882a593Smuzhiyun 	for (reg = ADV7393_FSC_REG0; reg <= ADV7393_FSC_REG3; reg++) {
182*4882a593Smuzhiyun 		err = adv7393_write(sd, reg, val);
183*4882a593Smuzhiyun 		if (err < 0)
184*4882a593Smuzhiyun 			goto setstd_exit;
185*4882a593Smuzhiyun 		val >>= 8;
186*4882a593Smuzhiyun 	}
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	val = state->reg82;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	/* Pedestal settings */
191*4882a593Smuzhiyun 	if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
192*4882a593Smuzhiyun 		val |= SD_PEDESTAL_EN;
193*4882a593Smuzhiyun 	else
194*4882a593Smuzhiyun 		val &= SD_PEDESTAL_DI;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	err = adv7393_write(sd, ADV7393_SD_MODE_REG2, val);
197*4882a593Smuzhiyun 	if (err < 0)
198*4882a593Smuzhiyun 		goto setstd_exit;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	state->reg82 = val;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun setstd_exit:
203*4882a593Smuzhiyun 	if (err != 0)
204*4882a593Smuzhiyun 		v4l2_err(sd, "Error setting std, write failed\n");
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	return err;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun 
adv7393_setoutput(struct v4l2_subdev * sd,u32 output_type)209*4882a593Smuzhiyun static int adv7393_setoutput(struct v4l2_subdev *sd, u32 output_type)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun 	struct adv7393_state *state = to_state(sd);
212*4882a593Smuzhiyun 	u8 val;
213*4882a593Smuzhiyun 	int err = 0;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	if (output_type > ADV7393_SVIDEO_ID) {
216*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd,
217*4882a593Smuzhiyun 			"Invalid output type or output type not supported:%d\n",
218*4882a593Smuzhiyun 								output_type);
219*4882a593Smuzhiyun 		return -EINVAL;
220*4882a593Smuzhiyun 	}
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	/* Enable Appropriate DAC */
223*4882a593Smuzhiyun 	val = state->reg00 & 0x03;
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	if (output_type == ADV7393_COMPOSITE_ID)
226*4882a593Smuzhiyun 		val |= ADV7393_COMPOSITE_POWER_VALUE;
227*4882a593Smuzhiyun 	else if (output_type == ADV7393_COMPONENT_ID)
228*4882a593Smuzhiyun 		val |= ADV7393_COMPONENT_POWER_VALUE;
229*4882a593Smuzhiyun 	else
230*4882a593Smuzhiyun 		val |= ADV7393_SVIDEO_POWER_VALUE;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	err = adv7393_write(sd, ADV7393_POWER_MODE_REG, val);
233*4882a593Smuzhiyun 	if (err < 0)
234*4882a593Smuzhiyun 		goto setoutput_exit;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	state->reg00 = val;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	/* Enable YUV output */
239*4882a593Smuzhiyun 	val = state->reg02 | YUV_OUTPUT_SELECT;
240*4882a593Smuzhiyun 	err = adv7393_write(sd, ADV7393_MODE_REG0, val);
241*4882a593Smuzhiyun 	if (err < 0)
242*4882a593Smuzhiyun 		goto setoutput_exit;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	state->reg02 = val;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	/* configure SD DAC Output 1 bit */
247*4882a593Smuzhiyun 	val = state->reg82;
248*4882a593Smuzhiyun 	if (output_type == ADV7393_COMPONENT_ID)
249*4882a593Smuzhiyun 		val &= SD_DAC_OUT1_DI;
250*4882a593Smuzhiyun 	else
251*4882a593Smuzhiyun 		val |= SD_DAC_OUT1_EN;
252*4882a593Smuzhiyun 	err = adv7393_write(sd, ADV7393_SD_MODE_REG2, val);
253*4882a593Smuzhiyun 	if (err < 0)
254*4882a593Smuzhiyun 		goto setoutput_exit;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	state->reg82 = val;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	/* configure ED/HD Color DAC Swap bit to zero */
259*4882a593Smuzhiyun 	val = state->reg35 & HD_DAC_SWAP_DI;
260*4882a593Smuzhiyun 	err = adv7393_write(sd, ADV7393_HD_MODE_REG6, val);
261*4882a593Smuzhiyun 	if (err < 0)
262*4882a593Smuzhiyun 		goto setoutput_exit;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	state->reg35 = val;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun setoutput_exit:
267*4882a593Smuzhiyun 	if (err != 0)
268*4882a593Smuzhiyun 		v4l2_err(sd, "Error setting output, write failed\n");
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	return err;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun 
adv7393_log_status(struct v4l2_subdev * sd)273*4882a593Smuzhiyun static int adv7393_log_status(struct v4l2_subdev *sd)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun 	struct adv7393_state *state = to_state(sd);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
278*4882a593Smuzhiyun 	v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
279*4882a593Smuzhiyun 			((state->output == 1) ? "Component" : "S-Video"));
280*4882a593Smuzhiyun 	return 0;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
adv7393_s_ctrl(struct v4l2_ctrl * ctrl)283*4882a593Smuzhiyun static int adv7393_s_ctrl(struct v4l2_ctrl *ctrl)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	struct v4l2_subdev *sd = to_sd(ctrl);
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	switch (ctrl->id) {
288*4882a593Smuzhiyun 	case V4L2_CID_BRIGHTNESS:
289*4882a593Smuzhiyun 		return adv7393_write(sd, ADV7393_SD_BRIGHTNESS_WSS,
290*4882a593Smuzhiyun 					ctrl->val & SD_BRIGHTNESS_VALUE_MASK);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	case V4L2_CID_HUE:
293*4882a593Smuzhiyun 		return adv7393_write(sd, ADV7393_SD_HUE_ADJUST,
294*4882a593Smuzhiyun 					ctrl->val - ADV7393_HUE_MIN);
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	case V4L2_CID_GAIN:
297*4882a593Smuzhiyun 		return adv7393_write(sd, ADV7393_DAC123_OUTPUT_LEVEL,
298*4882a593Smuzhiyun 					ctrl->val);
299*4882a593Smuzhiyun 	}
300*4882a593Smuzhiyun 	return -EINVAL;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun static const struct v4l2_ctrl_ops adv7393_ctrl_ops = {
304*4882a593Smuzhiyun 	.s_ctrl = adv7393_s_ctrl,
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops adv7393_core_ops = {
308*4882a593Smuzhiyun 	.log_status = adv7393_log_status,
309*4882a593Smuzhiyun };
310*4882a593Smuzhiyun 
adv7393_s_std_output(struct v4l2_subdev * sd,v4l2_std_id std)311*4882a593Smuzhiyun static int adv7393_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun 	struct adv7393_state *state = to_state(sd);
314*4882a593Smuzhiyun 	int err = 0;
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	if (state->std == std)
317*4882a593Smuzhiyun 		return 0;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	err = adv7393_setstd(sd, std);
320*4882a593Smuzhiyun 	if (!err)
321*4882a593Smuzhiyun 		state->std = std;
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	return err;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun 
adv7393_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)326*4882a593Smuzhiyun static int adv7393_s_routing(struct v4l2_subdev *sd,
327*4882a593Smuzhiyun 		u32 input, u32 output, u32 config)
328*4882a593Smuzhiyun {
329*4882a593Smuzhiyun 	struct adv7393_state *state = to_state(sd);
330*4882a593Smuzhiyun 	int err = 0;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	if (state->output == output)
333*4882a593Smuzhiyun 		return 0;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	err = adv7393_setoutput(sd, output);
336*4882a593Smuzhiyun 	if (!err)
337*4882a593Smuzhiyun 		state->output = output;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	return err;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops adv7393_video_ops = {
343*4882a593Smuzhiyun 	.s_std_output	= adv7393_s_std_output,
344*4882a593Smuzhiyun 	.s_routing	= adv7393_s_routing,
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun static const struct v4l2_subdev_ops adv7393_ops = {
348*4882a593Smuzhiyun 	.core	= &adv7393_core_ops,
349*4882a593Smuzhiyun 	.video	= &adv7393_video_ops,
350*4882a593Smuzhiyun };
351*4882a593Smuzhiyun 
adv7393_initialize(struct v4l2_subdev * sd)352*4882a593Smuzhiyun static int adv7393_initialize(struct v4l2_subdev *sd)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun 	struct adv7393_state *state = to_state(sd);
355*4882a593Smuzhiyun 	int err = 0;
356*4882a593Smuzhiyun 	int i;
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(adv7393_init_reg_val); i += 2) {
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 		err = adv7393_write(sd, adv7393_init_reg_val[i],
361*4882a593Smuzhiyun 					adv7393_init_reg_val[i+1]);
362*4882a593Smuzhiyun 		if (err) {
363*4882a593Smuzhiyun 			v4l2_err(sd, "Error initializing\n");
364*4882a593Smuzhiyun 			return err;
365*4882a593Smuzhiyun 		}
366*4882a593Smuzhiyun 	}
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	/* Configure for default video standard */
369*4882a593Smuzhiyun 	err = adv7393_setoutput(sd, state->output);
370*4882a593Smuzhiyun 	if (err < 0) {
371*4882a593Smuzhiyun 		v4l2_err(sd, "Error setting output during init\n");
372*4882a593Smuzhiyun 		return -EINVAL;
373*4882a593Smuzhiyun 	}
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	err = adv7393_setstd(sd, state->std);
376*4882a593Smuzhiyun 	if (err < 0) {
377*4882a593Smuzhiyun 		v4l2_err(sd, "Error setting std during init\n");
378*4882a593Smuzhiyun 		return -EINVAL;
379*4882a593Smuzhiyun 	}
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	return err;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun 
adv7393_probe(struct i2c_client * client,const struct i2c_device_id * id)384*4882a593Smuzhiyun static int adv7393_probe(struct i2c_client *client,
385*4882a593Smuzhiyun 				const struct i2c_device_id *id)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun 	struct adv7393_state *state;
388*4882a593Smuzhiyun 	int err;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
391*4882a593Smuzhiyun 		return -ENODEV;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	v4l_info(client, "chip found @ 0x%x (%s)\n",
394*4882a593Smuzhiyun 			client->addr << 1, client->adapter->name);
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
397*4882a593Smuzhiyun 	if (state == NULL)
398*4882a593Smuzhiyun 		return -ENOMEM;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	state->reg00	= ADV7393_POWER_MODE_REG_DEFAULT;
401*4882a593Smuzhiyun 	state->reg01	= 0x00;
402*4882a593Smuzhiyun 	state->reg02	= 0x20;
403*4882a593Smuzhiyun 	state->reg35	= ADV7393_HD_MODE_REG6_DEFAULT;
404*4882a593Smuzhiyun 	state->reg80	= ADV7393_SD_MODE_REG1_DEFAULT;
405*4882a593Smuzhiyun 	state->reg82	= ADV7393_SD_MODE_REG2_DEFAULT;
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	state->output = ADV7393_COMPOSITE_ID;
408*4882a593Smuzhiyun 	state->std = V4L2_STD_NTSC;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(&state->sd, client, &adv7393_ops);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(&state->hdl, 3);
413*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops,
414*4882a593Smuzhiyun 			V4L2_CID_BRIGHTNESS, ADV7393_BRIGHTNESS_MIN,
415*4882a593Smuzhiyun 					     ADV7393_BRIGHTNESS_MAX, 1,
416*4882a593Smuzhiyun 					     ADV7393_BRIGHTNESS_DEF);
417*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops,
418*4882a593Smuzhiyun 			V4L2_CID_HUE, ADV7393_HUE_MIN,
419*4882a593Smuzhiyun 				      ADV7393_HUE_MAX, 1,
420*4882a593Smuzhiyun 				      ADV7393_HUE_DEF);
421*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops,
422*4882a593Smuzhiyun 			V4L2_CID_GAIN, ADV7393_GAIN_MIN,
423*4882a593Smuzhiyun 				       ADV7393_GAIN_MAX, 1,
424*4882a593Smuzhiyun 				       ADV7393_GAIN_DEF);
425*4882a593Smuzhiyun 	state->sd.ctrl_handler = &state->hdl;
426*4882a593Smuzhiyun 	if (state->hdl.error) {
427*4882a593Smuzhiyun 		int err = state->hdl.error;
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 		v4l2_ctrl_handler_free(&state->hdl);
430*4882a593Smuzhiyun 		return err;
431*4882a593Smuzhiyun 	}
432*4882a593Smuzhiyun 	v4l2_ctrl_handler_setup(&state->hdl);
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	err = adv7393_initialize(&state->sd);
435*4882a593Smuzhiyun 	if (err)
436*4882a593Smuzhiyun 		v4l2_ctrl_handler_free(&state->hdl);
437*4882a593Smuzhiyun 	return err;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
adv7393_remove(struct i2c_client * client)440*4882a593Smuzhiyun static int adv7393_remove(struct i2c_client *client)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
443*4882a593Smuzhiyun 	struct adv7393_state *state = to_state(sd);
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
446*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&state->hdl);
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	return 0;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun static const struct i2c_device_id adv7393_id[] = {
452*4882a593Smuzhiyun 	{"adv7393", 0},
453*4882a593Smuzhiyun 	{},
454*4882a593Smuzhiyun };
455*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, adv7393_id);
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun static struct i2c_driver adv7393_driver = {
458*4882a593Smuzhiyun 	.driver = {
459*4882a593Smuzhiyun 		.name	= "adv7393",
460*4882a593Smuzhiyun 	},
461*4882a593Smuzhiyun 	.probe		= adv7393_probe,
462*4882a593Smuzhiyun 	.remove		= adv7393_remove,
463*4882a593Smuzhiyun 	.id_table	= adv7393_id,
464*4882a593Smuzhiyun };
465*4882a593Smuzhiyun module_i2c_driver(adv7393_driver);
466