xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/adv7343.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * adv7343 - ADV7343 Video Encoder Driver
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * The encoder hardware does not support SECAM.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or
9*4882a593Smuzhiyun  * modify it under the terms of the GNU General Public License as
10*4882a593Smuzhiyun  * published by the Free Software Foundation version 2.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
13*4882a593Smuzhiyun  * kind, whether express or implied; without even the implied warranty
14*4882a593Smuzhiyun  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15*4882a593Smuzhiyun  * GNU General Public License for more details.
16*4882a593Smuzhiyun  */
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/init.h>
20*4882a593Smuzhiyun #include <linux/ctype.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun #include <linux/i2c.h>
23*4882a593Smuzhiyun #include <linux/device.h>
24*4882a593Smuzhiyun #include <linux/delay.h>
25*4882a593Smuzhiyun #include <linux/module.h>
26*4882a593Smuzhiyun #include <linux/videodev2.h>
27*4882a593Smuzhiyun #include <linux/uaccess.h>
28*4882a593Smuzhiyun #include <linux/of.h>
29*4882a593Smuzhiyun #include <linux/of_graph.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <media/i2c/adv7343.h>
32*4882a593Smuzhiyun #include <media/v4l2-async.h>
33*4882a593Smuzhiyun #include <media/v4l2-device.h>
34*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #include "adv7343_regs.h"
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun MODULE_DESCRIPTION("ADV7343 video encoder driver");
39*4882a593Smuzhiyun MODULE_LICENSE("GPL");
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun static int debug;
42*4882a593Smuzhiyun module_param(debug, int, 0644);
43*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level 0-1");
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun struct adv7343_state {
46*4882a593Smuzhiyun 	struct v4l2_subdev sd;
47*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
48*4882a593Smuzhiyun 	const struct adv7343_platform_data *pdata;
49*4882a593Smuzhiyun 	u8 reg00;
50*4882a593Smuzhiyun 	u8 reg01;
51*4882a593Smuzhiyun 	u8 reg02;
52*4882a593Smuzhiyun 	u8 reg35;
53*4882a593Smuzhiyun 	u8 reg80;
54*4882a593Smuzhiyun 	u8 reg82;
55*4882a593Smuzhiyun 	u32 output;
56*4882a593Smuzhiyun 	v4l2_std_id std;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
to_state(struct v4l2_subdev * sd)59*4882a593Smuzhiyun static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	return container_of(sd, struct adv7343_state, sd);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun 
to_sd(struct v4l2_ctrl * ctrl)64*4882a593Smuzhiyun static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun 	return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
adv7343_write(struct v4l2_subdev * sd,u8 reg,u8 value)69*4882a593Smuzhiyun static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	return i2c_smbus_write_byte_data(client, reg, value);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun static const u8 adv7343_init_reg_val[] = {
77*4882a593Smuzhiyun 	ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
78*4882a593Smuzhiyun 	ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
81*4882a593Smuzhiyun 	ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
82*4882a593Smuzhiyun 	ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
83*4882a593Smuzhiyun 	ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
84*4882a593Smuzhiyun 	ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
85*4882a593Smuzhiyun 	ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
86*4882a593Smuzhiyun 	ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
89*4882a593Smuzhiyun 	ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
90*4882a593Smuzhiyun 	ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
91*4882a593Smuzhiyun 	ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
92*4882a593Smuzhiyun 	ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
93*4882a593Smuzhiyun 	ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
94*4882a593Smuzhiyun 	ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
95*4882a593Smuzhiyun 	ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
98*4882a593Smuzhiyun 	ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
99*4882a593Smuzhiyun 	ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun  *			    2^32
104*4882a593Smuzhiyun  * FSC(reg) =  FSC (HZ) * --------
105*4882a593Smuzhiyun  *			  27000000
106*4882a593Smuzhiyun  */
107*4882a593Smuzhiyun static const struct adv7343_std_info stdinfo[] = {
108*4882a593Smuzhiyun 	{
109*4882a593Smuzhiyun 		/* FSC(Hz) = 3,579,545.45 Hz */
110*4882a593Smuzhiyun 		SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
111*4882a593Smuzhiyun 	}, {
112*4882a593Smuzhiyun 		/* FSC(Hz) = 3,575,611.00 Hz */
113*4882a593Smuzhiyun 		SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
114*4882a593Smuzhiyun 	}, {
115*4882a593Smuzhiyun 		/* FSC(Hz) = 3,582,056.00 */
116*4882a593Smuzhiyun 		SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
117*4882a593Smuzhiyun 	}, {
118*4882a593Smuzhiyun 		/* FSC(Hz) = 4,433,618.75 Hz */
119*4882a593Smuzhiyun 		SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
120*4882a593Smuzhiyun 	}, {
121*4882a593Smuzhiyun 		/* FSC(Hz) = 4,433,618.75 Hz */
122*4882a593Smuzhiyun 		SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
123*4882a593Smuzhiyun 	}, {
124*4882a593Smuzhiyun 		/* FSC(Hz) = 4,433,618.75 Hz */
125*4882a593Smuzhiyun 		SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
126*4882a593Smuzhiyun 	}, {
127*4882a593Smuzhiyun 		/* FSC(Hz) = 4,433,618.75 Hz */
128*4882a593Smuzhiyun 		SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
129*4882a593Smuzhiyun 	},
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun 
adv7343_setstd(struct v4l2_subdev * sd,v4l2_std_id std)132*4882a593Smuzhiyun static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	struct adv7343_state *state = to_state(sd);
135*4882a593Smuzhiyun 	struct adv7343_std_info *std_info;
136*4882a593Smuzhiyun 	int num_std;
137*4882a593Smuzhiyun 	char *fsc_ptr;
138*4882a593Smuzhiyun 	u8 reg, val;
139*4882a593Smuzhiyun 	int err = 0;
140*4882a593Smuzhiyun 	int i = 0;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	std_info = (struct adv7343_std_info *)stdinfo;
143*4882a593Smuzhiyun 	num_std = ARRAY_SIZE(stdinfo);
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	for (i = 0; i < num_std; i++) {
146*4882a593Smuzhiyun 		if (std_info[i].stdid & std)
147*4882a593Smuzhiyun 			break;
148*4882a593Smuzhiyun 	}
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	if (i == num_std) {
151*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd,
152*4882a593Smuzhiyun 				"Invalid std or std is not supported: %llx\n",
153*4882a593Smuzhiyun 						(unsigned long long)std);
154*4882a593Smuzhiyun 		return -EINVAL;
155*4882a593Smuzhiyun 	}
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/* Set the standard */
158*4882a593Smuzhiyun 	val = state->reg80 & (~(SD_STD_MASK));
159*4882a593Smuzhiyun 	val |= std_info[i].standard_val3;
160*4882a593Smuzhiyun 	err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
161*4882a593Smuzhiyun 	if (err < 0)
162*4882a593Smuzhiyun 		goto setstd_exit;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	state->reg80 = val;
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	/* Configure the input mode register */
167*4882a593Smuzhiyun 	val = state->reg01 & (~((u8) INPUT_MODE_MASK));
168*4882a593Smuzhiyun 	val |= SD_INPUT_MODE;
169*4882a593Smuzhiyun 	err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
170*4882a593Smuzhiyun 	if (err < 0)
171*4882a593Smuzhiyun 		goto setstd_exit;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	state->reg01 = val;
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	/* Program the sub carrier frequency registers */
176*4882a593Smuzhiyun 	fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
177*4882a593Smuzhiyun 	reg = ADV7343_FSC_REG0;
178*4882a593Smuzhiyun 	for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
179*4882a593Smuzhiyun 		err = adv7343_write(sd, reg, *fsc_ptr);
180*4882a593Smuzhiyun 		if (err < 0)
181*4882a593Smuzhiyun 			goto setstd_exit;
182*4882a593Smuzhiyun 	}
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	val = state->reg80;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	/* Filter settings */
187*4882a593Smuzhiyun 	if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
188*4882a593Smuzhiyun 		val &= 0x03;
189*4882a593Smuzhiyun 	else if (std & ~V4L2_STD_SECAM)
190*4882a593Smuzhiyun 		val |= 0x04;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
193*4882a593Smuzhiyun 	if (err < 0)
194*4882a593Smuzhiyun 		goto setstd_exit;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	state->reg80 = val;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun setstd_exit:
199*4882a593Smuzhiyun 	if (err != 0)
200*4882a593Smuzhiyun 		v4l2_err(sd, "Error setting std, write failed\n");
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	return err;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
adv7343_setoutput(struct v4l2_subdev * sd,u32 output_type)205*4882a593Smuzhiyun static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	struct adv7343_state *state = to_state(sd);
208*4882a593Smuzhiyun 	unsigned char val;
209*4882a593Smuzhiyun 	int err = 0;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	if (output_type > ADV7343_SVIDEO_ID) {
212*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd,
213*4882a593Smuzhiyun 			"Invalid output type or output type not supported:%d\n",
214*4882a593Smuzhiyun 								output_type);
215*4882a593Smuzhiyun 		return -EINVAL;
216*4882a593Smuzhiyun 	}
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	/* Enable Appropriate DAC */
219*4882a593Smuzhiyun 	val = state->reg00 & 0x03;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	/* configure default configuration */
222*4882a593Smuzhiyun 	if (!state->pdata)
223*4882a593Smuzhiyun 		if (output_type == ADV7343_COMPOSITE_ID)
224*4882a593Smuzhiyun 			val |= ADV7343_COMPOSITE_POWER_VALUE;
225*4882a593Smuzhiyun 		else if (output_type == ADV7343_COMPONENT_ID)
226*4882a593Smuzhiyun 			val |= ADV7343_COMPONENT_POWER_VALUE;
227*4882a593Smuzhiyun 		else
228*4882a593Smuzhiyun 			val |= ADV7343_SVIDEO_POWER_VALUE;
229*4882a593Smuzhiyun 	else
230*4882a593Smuzhiyun 		val = state->pdata->mode_config.sleep_mode << 0 |
231*4882a593Smuzhiyun 		      state->pdata->mode_config.pll_control << 1 |
232*4882a593Smuzhiyun 		      state->pdata->mode_config.dac[2] << 2 |
233*4882a593Smuzhiyun 		      state->pdata->mode_config.dac[1] << 3 |
234*4882a593Smuzhiyun 		      state->pdata->mode_config.dac[0] << 4 |
235*4882a593Smuzhiyun 		      state->pdata->mode_config.dac[5] << 5 |
236*4882a593Smuzhiyun 		      state->pdata->mode_config.dac[4] << 6 |
237*4882a593Smuzhiyun 		      state->pdata->mode_config.dac[3] << 7;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
240*4882a593Smuzhiyun 	if (err < 0)
241*4882a593Smuzhiyun 		goto setoutput_exit;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	state->reg00 = val;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	/* Enable YUV output */
246*4882a593Smuzhiyun 	val = state->reg02 | YUV_OUTPUT_SELECT;
247*4882a593Smuzhiyun 	err = adv7343_write(sd, ADV7343_MODE_REG0, val);
248*4882a593Smuzhiyun 	if (err < 0)
249*4882a593Smuzhiyun 		goto setoutput_exit;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	state->reg02 = val;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	/* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
254*4882a593Smuzhiyun 	val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	if (state->pdata && state->pdata->sd_config.sd_dac_out[0])
257*4882a593Smuzhiyun 		val = val | (state->pdata->sd_config.sd_dac_out[0] << 1);
258*4882a593Smuzhiyun 	else if (state->pdata && !state->pdata->sd_config.sd_dac_out[0])
259*4882a593Smuzhiyun 		val = val & ~(state->pdata->sd_config.sd_dac_out[0] << 1);
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	if (state->pdata && state->pdata->sd_config.sd_dac_out[1])
262*4882a593Smuzhiyun 		val = val | (state->pdata->sd_config.sd_dac_out[1] << 2);
263*4882a593Smuzhiyun 	else if (state->pdata && !state->pdata->sd_config.sd_dac_out[1])
264*4882a593Smuzhiyun 		val = val & ~(state->pdata->sd_config.sd_dac_out[1] << 2);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
267*4882a593Smuzhiyun 	if (err < 0)
268*4882a593Smuzhiyun 		goto setoutput_exit;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	state->reg82 = val;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	/* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
273*4882a593Smuzhiyun 	 * zero */
274*4882a593Smuzhiyun 	val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
275*4882a593Smuzhiyun 	err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
276*4882a593Smuzhiyun 	if (err < 0)
277*4882a593Smuzhiyun 		goto setoutput_exit;
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	state->reg35 = val;
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun setoutput_exit:
282*4882a593Smuzhiyun 	if (err != 0)
283*4882a593Smuzhiyun 		v4l2_err(sd, "Error setting output, write failed\n");
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	return err;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun 
adv7343_log_status(struct v4l2_subdev * sd)288*4882a593Smuzhiyun static int adv7343_log_status(struct v4l2_subdev *sd)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun 	struct adv7343_state *state = to_state(sd);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
293*4882a593Smuzhiyun 	v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
294*4882a593Smuzhiyun 			((state->output == 1) ? "Component" : "S-Video"));
295*4882a593Smuzhiyun 	return 0;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun 
adv7343_s_ctrl(struct v4l2_ctrl * ctrl)298*4882a593Smuzhiyun static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun 	struct v4l2_subdev *sd = to_sd(ctrl);
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	switch (ctrl->id) {
303*4882a593Smuzhiyun 	case V4L2_CID_BRIGHTNESS:
304*4882a593Smuzhiyun 		return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
305*4882a593Smuzhiyun 					ctrl->val);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	case V4L2_CID_HUE:
308*4882a593Smuzhiyun 		return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	case V4L2_CID_GAIN:
311*4882a593Smuzhiyun 		return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
312*4882a593Smuzhiyun 	}
313*4882a593Smuzhiyun 	return -EINVAL;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
317*4882a593Smuzhiyun 	.s_ctrl = adv7343_s_ctrl,
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops adv7343_core_ops = {
321*4882a593Smuzhiyun 	.log_status = adv7343_log_status,
322*4882a593Smuzhiyun };
323*4882a593Smuzhiyun 
adv7343_s_std_output(struct v4l2_subdev * sd,v4l2_std_id std)324*4882a593Smuzhiyun static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	struct adv7343_state *state = to_state(sd);
327*4882a593Smuzhiyun 	int err = 0;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	if (state->std == std)
330*4882a593Smuzhiyun 		return 0;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	err = adv7343_setstd(sd, std);
333*4882a593Smuzhiyun 	if (!err)
334*4882a593Smuzhiyun 		state->std = std;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	return err;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun 
adv7343_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)339*4882a593Smuzhiyun static int adv7343_s_routing(struct v4l2_subdev *sd,
340*4882a593Smuzhiyun 		u32 input, u32 output, u32 config)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun 	struct adv7343_state *state = to_state(sd);
343*4882a593Smuzhiyun 	int err = 0;
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	if (state->output == output)
346*4882a593Smuzhiyun 		return 0;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	err = adv7343_setoutput(sd, output);
349*4882a593Smuzhiyun 	if (!err)
350*4882a593Smuzhiyun 		state->output = output;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	return err;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops adv7343_video_ops = {
356*4882a593Smuzhiyun 	.s_std_output	= adv7343_s_std_output,
357*4882a593Smuzhiyun 	.s_routing	= adv7343_s_routing,
358*4882a593Smuzhiyun };
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun static const struct v4l2_subdev_ops adv7343_ops = {
361*4882a593Smuzhiyun 	.core	= &adv7343_core_ops,
362*4882a593Smuzhiyun 	.video	= &adv7343_video_ops,
363*4882a593Smuzhiyun };
364*4882a593Smuzhiyun 
adv7343_initialize(struct v4l2_subdev * sd)365*4882a593Smuzhiyun static int adv7343_initialize(struct v4l2_subdev *sd)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun 	struct adv7343_state *state = to_state(sd);
368*4882a593Smuzhiyun 	int err = 0;
369*4882a593Smuzhiyun 	int i;
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 		err = adv7343_write(sd, adv7343_init_reg_val[i],
374*4882a593Smuzhiyun 					adv7343_init_reg_val[i+1]);
375*4882a593Smuzhiyun 		if (err) {
376*4882a593Smuzhiyun 			v4l2_err(sd, "Error initializing\n");
377*4882a593Smuzhiyun 			return err;
378*4882a593Smuzhiyun 		}
379*4882a593Smuzhiyun 	}
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	/* Configure for default video standard */
382*4882a593Smuzhiyun 	err = adv7343_setoutput(sd, state->output);
383*4882a593Smuzhiyun 	if (err < 0) {
384*4882a593Smuzhiyun 		v4l2_err(sd, "Error setting output during init\n");
385*4882a593Smuzhiyun 		return -EINVAL;
386*4882a593Smuzhiyun 	}
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	err = adv7343_setstd(sd, state->std);
389*4882a593Smuzhiyun 	if (err < 0) {
390*4882a593Smuzhiyun 		v4l2_err(sd, "Error setting std during init\n");
391*4882a593Smuzhiyun 		return -EINVAL;
392*4882a593Smuzhiyun 	}
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	return err;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun static struct adv7343_platform_data *
adv7343_get_pdata(struct i2c_client * client)398*4882a593Smuzhiyun adv7343_get_pdata(struct i2c_client *client)
399*4882a593Smuzhiyun {
400*4882a593Smuzhiyun 	struct adv7343_platform_data *pdata;
401*4882a593Smuzhiyun 	struct device_node *np;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
404*4882a593Smuzhiyun 		return client->dev.platform_data;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
407*4882a593Smuzhiyun 	if (!np)
408*4882a593Smuzhiyun 		return NULL;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
411*4882a593Smuzhiyun 	if (!pdata)
412*4882a593Smuzhiyun 		goto done;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	pdata->mode_config.sleep_mode =
415*4882a593Smuzhiyun 			of_property_read_bool(np, "adi,power-mode-sleep-mode");
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	pdata->mode_config.pll_control =
418*4882a593Smuzhiyun 			of_property_read_bool(np, "adi,power-mode-pll-ctrl");
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	of_property_read_u32_array(np, "adi,dac-enable",
421*4882a593Smuzhiyun 				   pdata->mode_config.dac, 6);
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	of_property_read_u32_array(np, "adi,sd-dac-enable",
424*4882a593Smuzhiyun 				   pdata->sd_config.sd_dac_out, 2);
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun done:
427*4882a593Smuzhiyun 	of_node_put(np);
428*4882a593Smuzhiyun 	return pdata;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun 
adv7343_probe(struct i2c_client * client)431*4882a593Smuzhiyun static int adv7343_probe(struct i2c_client *client)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun 	struct adv7343_state *state;
434*4882a593Smuzhiyun 	int err;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
437*4882a593Smuzhiyun 		return -ENODEV;
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	v4l_info(client, "chip found @ 0x%x (%s)\n",
440*4882a593Smuzhiyun 			client->addr << 1, client->adapter->name);
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	state = devm_kzalloc(&client->dev, sizeof(struct adv7343_state),
443*4882a593Smuzhiyun 			     GFP_KERNEL);
444*4882a593Smuzhiyun 	if (state == NULL)
445*4882a593Smuzhiyun 		return -ENOMEM;
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	/* Copy board specific information here */
448*4882a593Smuzhiyun 	state->pdata = adv7343_get_pdata(client);
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	state->reg00	= 0x80;
451*4882a593Smuzhiyun 	state->reg01	= 0x00;
452*4882a593Smuzhiyun 	state->reg02	= 0x20;
453*4882a593Smuzhiyun 	state->reg35	= 0x00;
454*4882a593Smuzhiyun 	state->reg80	= ADV7343_SD_MODE_REG1_DEFAULT;
455*4882a593Smuzhiyun 	state->reg82	= ADV7343_SD_MODE_REG2_DEFAULT;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	state->output = ADV7343_COMPOSITE_ID;
458*4882a593Smuzhiyun 	state->std = V4L2_STD_NTSC;
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(&state->hdl, 2);
463*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
464*4882a593Smuzhiyun 			V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
465*4882a593Smuzhiyun 					     ADV7343_BRIGHTNESS_MAX, 1,
466*4882a593Smuzhiyun 					     ADV7343_BRIGHTNESS_DEF);
467*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
468*4882a593Smuzhiyun 			V4L2_CID_HUE, ADV7343_HUE_MIN,
469*4882a593Smuzhiyun 				      ADV7343_HUE_MAX, 1,
470*4882a593Smuzhiyun 				      ADV7343_HUE_DEF);
471*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
472*4882a593Smuzhiyun 			V4L2_CID_GAIN, ADV7343_GAIN_MIN,
473*4882a593Smuzhiyun 				       ADV7343_GAIN_MAX, 1,
474*4882a593Smuzhiyun 				       ADV7343_GAIN_DEF);
475*4882a593Smuzhiyun 	state->sd.ctrl_handler = &state->hdl;
476*4882a593Smuzhiyun 	if (state->hdl.error) {
477*4882a593Smuzhiyun 		err = state->hdl.error;
478*4882a593Smuzhiyun 		goto done;
479*4882a593Smuzhiyun 	}
480*4882a593Smuzhiyun 	v4l2_ctrl_handler_setup(&state->hdl);
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	err = adv7343_initialize(&state->sd);
483*4882a593Smuzhiyun 	if (err)
484*4882a593Smuzhiyun 		goto done;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	err = v4l2_async_register_subdev(&state->sd);
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun done:
489*4882a593Smuzhiyun 	if (err < 0)
490*4882a593Smuzhiyun 		v4l2_ctrl_handler_free(&state->hdl);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	return err;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun 
adv7343_remove(struct i2c_client * client)495*4882a593Smuzhiyun static int adv7343_remove(struct i2c_client *client)
496*4882a593Smuzhiyun {
497*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
498*4882a593Smuzhiyun 	struct adv7343_state *state = to_state(sd);
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(&state->sd);
501*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&state->hdl);
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	return 0;
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun static const struct i2c_device_id adv7343_id[] = {
507*4882a593Smuzhiyun 	{"adv7343", 0},
508*4882a593Smuzhiyun 	{},
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, adv7343_id);
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
514*4882a593Smuzhiyun static const struct of_device_id adv7343_of_match[] = {
515*4882a593Smuzhiyun 	{.compatible = "adi,adv7343", },
516*4882a593Smuzhiyun 	{ /* sentinel */ },
517*4882a593Smuzhiyun };
518*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, adv7343_of_match);
519*4882a593Smuzhiyun #endif
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun static struct i2c_driver adv7343_driver = {
522*4882a593Smuzhiyun 	.driver = {
523*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(adv7343_of_match),
524*4882a593Smuzhiyun 		.name	= "adv7343",
525*4882a593Smuzhiyun 	},
526*4882a593Smuzhiyun 	.probe_new	= adv7343_probe,
527*4882a593Smuzhiyun 	.remove		= adv7343_remove,
528*4882a593Smuzhiyun 	.id_table	= adv7343_id,
529*4882a593Smuzhiyun };
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun module_i2c_driver(adv7343_driver);
532