1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * adv7181 driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/pm_runtime.h>
14*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
15*4882a593Smuzhiyun #include <linux/sysfs.h>
16*4882a593Smuzhiyun #include <media/media-entity.h>
17*4882a593Smuzhiyun #include <media/v4l2-async.h>
18*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
19*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define REG_CHIP_ID 0x11
22*4882a593Smuzhiyun #define CHIP_ID 0x20
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define REG_SC_CTRL_MODE 0x03
25*4882a593Smuzhiyun #define SC_CTRL_MODE_STANDBY 0x4c
26*4882a593Smuzhiyun #define SC_CTRL_MODE_STREAMING 0x0c
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define REG_NULL 0xFF
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define ADV7181_XVCLK_FREQ 24000000
31*4882a593Smuzhiyun #define ADV7181_LANES 1
32*4882a593Smuzhiyun #define ADV7181_BITS_PER_SAMPLE 10
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define ADV7181_SKIP_TOP 24
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static const char * const adv7181_supply_names[] = {
37*4882a593Smuzhiyun "dvdd",
38*4882a593Smuzhiyun "dvddio",
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define ADV7181_NUM_SUPPLIES ARRAY_SIZE(adv7181_supply_names)
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct regval {
44*4882a593Smuzhiyun u8 addr;
45*4882a593Smuzhiyun u8 val;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun struct adv7181_mode {
49*4882a593Smuzhiyun u32 width;
50*4882a593Smuzhiyun u32 height;
51*4882a593Smuzhiyun const struct regval *reg_list;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun struct adv7181 {
55*4882a593Smuzhiyun struct i2c_client *client;
56*4882a593Smuzhiyun struct clk *xvclk;
57*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
58*4882a593Smuzhiyun struct regulator_bulk_data supplies[ADV7181_NUM_SUPPLIES];
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun bool streaming;
61*4882a593Smuzhiyun struct mutex mutex; /* lock to serialize v4l2 callback */
62*4882a593Smuzhiyun struct v4l2_subdev subdev;
63*4882a593Smuzhiyun struct media_pad pad;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun int skip_top;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun const struct adv7181_mode *cur_mode;
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define to_adv7181(sd) container_of(sd, struct adv7181, subdev)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* PLL settings bases on 28M xvclk, resolution 720x480 30fps*/
73*4882a593Smuzhiyun static struct regval adv7181_cvbs_30fps[] = {
74*4882a593Smuzhiyun {0x00, 0x0B},
75*4882a593Smuzhiyun {0x04, 0x77},
76*4882a593Smuzhiyun {0x17, 0x41},
77*4882a593Smuzhiyun {0x1D, 0x47},
78*4882a593Smuzhiyun {0x31, 0x02},
79*4882a593Smuzhiyun {0x3A, 0x17},
80*4882a593Smuzhiyun {0x3B, 0x81},
81*4882a593Smuzhiyun {0x3D, 0xA2},
82*4882a593Smuzhiyun {0x3E, 0x6A},
83*4882a593Smuzhiyun {0x3F, 0xA0},
84*4882a593Smuzhiyun {0x86, 0x0B},
85*4882a593Smuzhiyun {0xF3, 0x01},
86*4882a593Smuzhiyun {0xF9, 0x03},
87*4882a593Smuzhiyun {0x0E, 0x80},
88*4882a593Smuzhiyun {0x52, 0x46},
89*4882a593Smuzhiyun {0x54, 0x80},
90*4882a593Smuzhiyun {0x7F, 0xFF},
91*4882a593Smuzhiyun {0x81, 0x30},
92*4882a593Smuzhiyun {0x90, 0xC9},
93*4882a593Smuzhiyun {0x91, 0x40},
94*4882a593Smuzhiyun {0x92, 0x3C},
95*4882a593Smuzhiyun {0x93, 0xCA},
96*4882a593Smuzhiyun {0x94, 0xD5},
97*4882a593Smuzhiyun {0xB1, 0xFF},
98*4882a593Smuzhiyun {0xB6, 0x08},
99*4882a593Smuzhiyun {0xC0, 0x9A},
100*4882a593Smuzhiyun {0xCF, 0x50},
101*4882a593Smuzhiyun {0xD0, 0x4E},
102*4882a593Smuzhiyun {0xD1, 0xB9},
103*4882a593Smuzhiyun {0xD6, 0xDD},
104*4882a593Smuzhiyun {0xD7, 0xE2},
105*4882a593Smuzhiyun {0xE5, 0x51},
106*4882a593Smuzhiyun {0xF6, 0x3B},
107*4882a593Smuzhiyun {0x0E, 0x00},
108*4882a593Smuzhiyun {0x03, 0x4C},
109*4882a593Smuzhiyun {REG_NULL, 0x0},
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun static const struct adv7181_mode supported_modes[] = {
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun .width = 720,
115*4882a593Smuzhiyun .height = 480,
116*4882a593Smuzhiyun .reg_list = adv7181_cvbs_30fps,
117*4882a593Smuzhiyun },
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
adv7181_write_reg(struct i2c_client * client,u8 reg,u8 val)120*4882a593Smuzhiyun static int adv7181_write_reg(struct i2c_client *client, u8 reg, u8 val)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun int ret;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, reg, val);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun if (ret < 0)
127*4882a593Smuzhiyun dev_err(&client->dev, "write reg error: %d\n", ret);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return ret;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
adv7181_write_array(struct i2c_client * client,const struct regval * regs)132*4882a593Smuzhiyun static int adv7181_write_array(struct i2c_client *client,
133*4882a593Smuzhiyun const struct regval *regs)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun int i, ret = 0;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
138*4882a593Smuzhiyun ret = adv7181_write_reg(client, regs[i].addr, regs[i].val);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return ret;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
adv7181_read_reg(struct i2c_client * client,u8 reg)143*4882a593Smuzhiyun static inline u8 adv7181_read_reg(struct i2c_client *client, u8 reg)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun return i2c_smbus_read_byte_data(client, reg);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
adv7181_fill_fmt(const struct adv7181_mode * mode,struct v4l2_mbus_framefmt * fmt)148*4882a593Smuzhiyun static void adv7181_fill_fmt(const struct adv7181_mode *mode,
149*4882a593Smuzhiyun struct v4l2_mbus_framefmt *fmt)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
152*4882a593Smuzhiyun fmt->width = mode->width;
153*4882a593Smuzhiyun fmt->height = mode->height;
154*4882a593Smuzhiyun fmt->field = V4L2_FIELD_NONE;
155*4882a593Smuzhiyun fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
adv7181_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)158*4882a593Smuzhiyun static int adv7181_set_fmt(struct v4l2_subdev *sd,
159*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
160*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun struct adv7181 *adv7181 = to_adv7181(sd);
163*4882a593Smuzhiyun struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* only one mode supported for now */
166*4882a593Smuzhiyun adv7181_fill_fmt(adv7181->cur_mode, mbus_fmt);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
adv7181_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)171*4882a593Smuzhiyun static int adv7181_get_fmt(struct v4l2_subdev *sd,
172*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
173*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun struct adv7181 *adv7181 = to_adv7181(sd);
176*4882a593Smuzhiyun struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun adv7181_fill_fmt(adv7181->cur_mode, mbus_fmt);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun return 0;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
adv7181_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)183*4882a593Smuzhiyun static int adv7181_enum_mbus_code(struct v4l2_subdev *sd,
184*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
185*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun if (code->index >= ARRAY_SIZE(supported_modes))
188*4882a593Smuzhiyun return -EINVAL;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun code->code = MEDIA_BUS_FMT_UYVY8_2X8;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun return 0;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
adv7181_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)195*4882a593Smuzhiyun static int adv7181_enum_frame_sizes(struct v4l2_subdev *sd,
196*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
197*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun u32 index = fse->index;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun if (index >= ARRAY_SIZE(supported_modes))
202*4882a593Smuzhiyun return -EINVAL;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun fse->code = MEDIA_BUS_FMT_UYVY8_2X8;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun fse->min_width = supported_modes[index].width;
207*4882a593Smuzhiyun fse->max_width = supported_modes[index].width;
208*4882a593Smuzhiyun fse->max_height = supported_modes[index].height;
209*4882a593Smuzhiyun fse->min_height = supported_modes[index].height;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun return 0;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
adv7181_g_skip_top_lines(struct v4l2_subdev * sd,u32 * lines)214*4882a593Smuzhiyun static int adv7181_g_skip_top_lines(struct v4l2_subdev *sd, u32 *lines)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct adv7181 *adv7181 = to_adv7181(sd);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun *lines = adv7181->skip_top;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun return 0;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
adv7181_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)223*4882a593Smuzhiyun static int adv7181_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun /* Only NTSC now */
226*4882a593Smuzhiyun *std = V4L2_STD_NTSC;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun return 0;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
__adv7181_power_on(struct adv7181 * adv7181)231*4882a593Smuzhiyun static int __adv7181_power_on(struct adv7181 *adv7181)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun int ret;
234*4882a593Smuzhiyun struct device *dev = &adv7181->client->dev;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun if (!IS_ERR(adv7181->xvclk)) {
237*4882a593Smuzhiyun ret = clk_prepare_enable(adv7181->xvclk);
238*4882a593Smuzhiyun if (ret < 0) {
239*4882a593Smuzhiyun dev_err(dev, "Failed to enable xvclk\n");
240*4882a593Smuzhiyun return ret;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun gpiod_set_value_cansleep(adv7181->reset_gpio, 1);
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun ret = regulator_bulk_enable(ADV7181_NUM_SUPPLIES, adv7181->supplies);
247*4882a593Smuzhiyun if (ret < 0) {
248*4882a593Smuzhiyun dev_err(dev, "Failed to enable regulators\n");
249*4882a593Smuzhiyun goto disable_clk;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun gpiod_set_value_cansleep(adv7181->reset_gpio, 0);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun return 0;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun disable_clk:
257*4882a593Smuzhiyun if (!IS_ERR(adv7181->xvclk))
258*4882a593Smuzhiyun clk_disable_unprepare(adv7181->xvclk);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun return ret;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
__adv7181_power_off(struct adv7181 * adv7181)263*4882a593Smuzhiyun static void __adv7181_power_off(struct adv7181 *adv7181)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun if (!IS_ERR(adv7181->xvclk))
266*4882a593Smuzhiyun clk_disable_unprepare(adv7181->xvclk);
267*4882a593Smuzhiyun gpiod_set_value_cansleep(adv7181->reset_gpio, 1);
268*4882a593Smuzhiyun regulator_bulk_disable(ADV7181_NUM_SUPPLIES, adv7181->supplies);
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
adv7181_s_stream(struct v4l2_subdev * sd,int on)271*4882a593Smuzhiyun static int adv7181_s_stream(struct v4l2_subdev *sd, int on)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun struct adv7181 *adv7181 = to_adv7181(sd);
274*4882a593Smuzhiyun struct i2c_client *client = adv7181->client;
275*4882a593Smuzhiyun int ret = 0;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun mutex_lock(&adv7181->mutex);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun on = !!on;
280*4882a593Smuzhiyun if (on == adv7181->streaming)
281*4882a593Smuzhiyun goto unlock_and_return;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun if (on) {
284*4882a593Smuzhiyun ret = pm_runtime_get_sync(&adv7181->client->dev);
285*4882a593Smuzhiyun if (ret < 0) {
286*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
287*4882a593Smuzhiyun goto unlock_and_return;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun ret = adv7181_write_array(adv7181->client,
291*4882a593Smuzhiyun adv7181->cur_mode->reg_list);
292*4882a593Smuzhiyun if (ret) {
293*4882a593Smuzhiyun pm_runtime_put(&client->dev);
294*4882a593Smuzhiyun goto unlock_and_return;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun ret = adv7181_write_reg(client, REG_SC_CTRL_MODE,
298*4882a593Smuzhiyun SC_CTRL_MODE_STREAMING);
299*4882a593Smuzhiyun if (ret) {
300*4882a593Smuzhiyun pm_runtime_put(&client->dev);
301*4882a593Smuzhiyun goto unlock_and_return;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun } else {
304*4882a593Smuzhiyun adv7181_write_reg(client, REG_SC_CTRL_MODE,
305*4882a593Smuzhiyun SC_CTRL_MODE_STANDBY);
306*4882a593Smuzhiyun pm_runtime_put(&client->dev);
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun adv7181->streaming = on;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun unlock_and_return:
312*4882a593Smuzhiyun mutex_unlock(&adv7181->mutex);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun return ret;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
adv7181_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)318*4882a593Smuzhiyun static int adv7181_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun struct adv7181 *adv7181 = to_adv7181(sd);
321*4882a593Smuzhiyun struct v4l2_mbus_framefmt *try_fmt;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun mutex_lock(&adv7181->mutex);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun try_fmt = v4l2_subdev_get_try_format(sd, fh->pad, 0);
326*4882a593Smuzhiyun /* Initialize try_fmt */
327*4882a593Smuzhiyun adv7181_fill_fmt(&supported_modes[0], try_fmt);
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun mutex_unlock(&adv7181->mutex);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun return 0;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun #endif
334*4882a593Smuzhiyun
adv7181_runtime_resume(struct device * dev)335*4882a593Smuzhiyun static int adv7181_runtime_resume(struct device *dev)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
338*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
339*4882a593Smuzhiyun struct adv7181 *adv7181 = to_adv7181(sd);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun return __adv7181_power_on(adv7181);
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
adv7181_runtime_suspend(struct device * dev)344*4882a593Smuzhiyun static int adv7181_runtime_suspend(struct device *dev)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
347*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
348*4882a593Smuzhiyun struct adv7181 *adv7181 = to_adv7181(sd);
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun __adv7181_power_off(adv7181);
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun return 0;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun static const struct dev_pm_ops adv7181_pm_ops = {
356*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(adv7181_runtime_suspend,
357*4882a593Smuzhiyun adv7181_runtime_resume, NULL)
358*4882a593Smuzhiyun };
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops adv7181_video_ops = {
361*4882a593Smuzhiyun .s_stream = adv7181_s_stream,
362*4882a593Smuzhiyun .querystd = adv7181_querystd,
363*4882a593Smuzhiyun };
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops adv7181_pad_ops = {
366*4882a593Smuzhiyun .enum_mbus_code = adv7181_enum_mbus_code,
367*4882a593Smuzhiyun .enum_frame_size = adv7181_enum_frame_sizes,
368*4882a593Smuzhiyun .get_fmt = adv7181_get_fmt,
369*4882a593Smuzhiyun .set_fmt = adv7181_set_fmt,
370*4882a593Smuzhiyun };
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun static struct v4l2_subdev_sensor_ops adv7181_sensor_ops = {
373*4882a593Smuzhiyun .g_skip_top_lines = adv7181_g_skip_top_lines,
374*4882a593Smuzhiyun };
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun static const struct v4l2_subdev_ops adv7181_subdev_ops = {
377*4882a593Smuzhiyun .video = &adv7181_video_ops,
378*4882a593Smuzhiyun .pad = &adv7181_pad_ops,
379*4882a593Smuzhiyun .sensor = &adv7181_sensor_ops,
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
383*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops adv7181_internal_ops = {
384*4882a593Smuzhiyun .open = adv7181_open,
385*4882a593Smuzhiyun };
386*4882a593Smuzhiyun #endif
387*4882a593Smuzhiyun
adv7181_check_sensor_id(struct adv7181 * adv7181,struct i2c_client * client)388*4882a593Smuzhiyun static int adv7181_check_sensor_id(struct adv7181 *adv7181,
389*4882a593Smuzhiyun struct i2c_client *client)
390*4882a593Smuzhiyun {
391*4882a593Smuzhiyun struct device *dev = &adv7181->client->dev;
392*4882a593Smuzhiyun u8 id;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun id = adv7181_read_reg(client, REG_CHIP_ID);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun if (id != CHIP_ID) {
397*4882a593Smuzhiyun dev_err(dev, "Wrong camera sensor id(%04x)\n", id);
398*4882a593Smuzhiyun return -EINVAL;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun dev_info(dev, "Detected ADV7181 (%04x) sensor\n", CHIP_ID);
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun return 0;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
adv7181_configure_regulators(struct adv7181 * adv7181)406*4882a593Smuzhiyun static int adv7181_configure_regulators(struct adv7181 *adv7181)
407*4882a593Smuzhiyun {
408*4882a593Smuzhiyun u32 i;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun for (i = 0; i < ADV7181_NUM_SUPPLIES; i++)
411*4882a593Smuzhiyun adv7181->supplies[i].supply = adv7181_supply_names[i];
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun return devm_regulator_bulk_get(&adv7181->client->dev,
414*4882a593Smuzhiyun ADV7181_NUM_SUPPLIES,
415*4882a593Smuzhiyun adv7181->supplies);
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
adv7181_probe(struct i2c_client * client,const struct i2c_device_id * id)418*4882a593Smuzhiyun static int adv7181_probe(struct i2c_client *client,
419*4882a593Smuzhiyun const struct i2c_device_id *id)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun struct device *dev = &client->dev;
422*4882a593Smuzhiyun struct adv7181 *adv7181;
423*4882a593Smuzhiyun int ret;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun adv7181 = devm_kzalloc(dev, sizeof(*adv7181), GFP_KERNEL);
426*4882a593Smuzhiyun if (!adv7181)
427*4882a593Smuzhiyun return -ENOMEM;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun adv7181->skip_top = ADV7181_SKIP_TOP;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun adv7181->client = client;
432*4882a593Smuzhiyun adv7181->cur_mode = &supported_modes[0];
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun adv7181->xvclk = devm_clk_get(dev, "xvclk");
435*4882a593Smuzhiyun if (!IS_ERR(adv7181->xvclk)) {
436*4882a593Smuzhiyun ret = clk_set_rate(adv7181->xvclk, ADV7181_XVCLK_FREQ);
437*4882a593Smuzhiyun if (ret < 0) {
438*4882a593Smuzhiyun dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
439*4882a593Smuzhiyun return ret;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun if (clk_get_rate(adv7181->xvclk) != ADV7181_XVCLK_FREQ)
442*4882a593Smuzhiyun dev_warn(dev, "xvclk mismatched, it requires 24MHz\n");
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun adv7181->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
446*4882a593Smuzhiyun if (IS_ERR(adv7181->reset_gpio)) {
447*4882a593Smuzhiyun dev_err(dev, "Failed to get reset-gpios\n");
448*4882a593Smuzhiyun return -EINVAL;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun ret = adv7181_configure_regulators(adv7181);
452*4882a593Smuzhiyun if (ret) {
453*4882a593Smuzhiyun dev_err(dev, "Failed to get power regulators\n");
454*4882a593Smuzhiyun return ret;
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun mutex_init(&adv7181->mutex);
458*4882a593Smuzhiyun v4l2_i2c_subdev_init(&adv7181->subdev, client, &adv7181_subdev_ops);
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun ret = __adv7181_power_on(adv7181);
461*4882a593Smuzhiyun if (ret)
462*4882a593Smuzhiyun goto err_destroy_mutex;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun ret = adv7181_check_sensor_id(adv7181, client);
465*4882a593Smuzhiyun if (ret)
466*4882a593Smuzhiyun goto err_power_off;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
469*4882a593Smuzhiyun adv7181->subdev.internal_ops = &adv7181_internal_ops;
470*4882a593Smuzhiyun adv7181->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
471*4882a593Smuzhiyun #endif
472*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
473*4882a593Smuzhiyun adv7181->pad.flags = MEDIA_PAD_FL_SOURCE;
474*4882a593Smuzhiyun adv7181->subdev.entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
475*4882a593Smuzhiyun ret = media_entity_init(&adv7181->subdev.entity, 1, &adv7181->pad, 0);
476*4882a593Smuzhiyun if (ret < 0)
477*4882a593Smuzhiyun goto err_power_off;
478*4882a593Smuzhiyun #endif
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun ret = v4l2_async_register_subdev(&adv7181->subdev);
481*4882a593Smuzhiyun if (ret) {
482*4882a593Smuzhiyun dev_err(dev, "v4l2 async register subdev failed\n");
483*4882a593Smuzhiyun goto err_clean_entity;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun pm_runtime_set_active(dev);
487*4882a593Smuzhiyun pm_runtime_enable(dev);
488*4882a593Smuzhiyun pm_runtime_idle(dev);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun return 0;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun err_clean_entity:
493*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
494*4882a593Smuzhiyun media_entity_cleanup(&adv7181->subdev.entity);
495*4882a593Smuzhiyun #endif
496*4882a593Smuzhiyun err_power_off:
497*4882a593Smuzhiyun __adv7181_power_off(adv7181);
498*4882a593Smuzhiyun err_destroy_mutex:
499*4882a593Smuzhiyun mutex_destroy(&adv7181->mutex);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun return ret;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun
adv7181_remove(struct i2c_client * client)504*4882a593Smuzhiyun static int adv7181_remove(struct i2c_client *client)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
507*4882a593Smuzhiyun struct adv7181 *adv7181 = to_adv7181(sd);
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
510*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
511*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
512*4882a593Smuzhiyun #endif
513*4882a593Smuzhiyun mutex_destroy(&adv7181->mutex);
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
516*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&client->dev))
517*4882a593Smuzhiyun __adv7181_power_off(adv7181);
518*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun return 0;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun static const struct i2c_device_id adv7181_id[] = {
524*4882a593Smuzhiyun {"adv7181", 0},
525*4882a593Smuzhiyun {},
526*4882a593Smuzhiyun };
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
529*4882a593Smuzhiyun static const struct of_device_id adv7181_of_match[] = {
530*4882a593Smuzhiyun { .compatible = "adi,adv7181" },
531*4882a593Smuzhiyun {},
532*4882a593Smuzhiyun };
533*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, adv7181_of_match);
534*4882a593Smuzhiyun #endif
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun static struct i2c_driver adv7181_i2c_driver = {
537*4882a593Smuzhiyun .driver = {
538*4882a593Smuzhiyun .name = "adv7181",
539*4882a593Smuzhiyun .pm = &adv7181_pm_ops,
540*4882a593Smuzhiyun .of_match_table = adv7181_of_match
541*4882a593Smuzhiyun },
542*4882a593Smuzhiyun .probe = adv7181_probe,
543*4882a593Smuzhiyun .remove = adv7181_remove,
544*4882a593Smuzhiyun .id_table = adv7181_id,
545*4882a593Smuzhiyun };
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun module_i2c_driver(adv7181_i2c_driver);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun MODULE_DESCRIPTION("adv7181 sensor driver");
550*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
551