xref: /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/zl10353_priv.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Driver for Zarlink DVB-T ZL10353 demodulator
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef _ZL10353_PRIV_
9*4882a593Smuzhiyun #define _ZL10353_PRIV_
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define ID_ZL10353	0x14 /* Zarlink ZL10353 */
12*4882a593Smuzhiyun #define ID_CE6230	0x18 /* Intel CE6230 */
13*4882a593Smuzhiyun #define ID_CE6231	0x19 /* Intel CE6231 */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define msb(x) (((x) >> 8) & 0xff)
16*4882a593Smuzhiyun #define lsb(x) ((x) & 0xff)
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun enum zl10353_reg_addr {
19*4882a593Smuzhiyun 	INTERRUPT_0        = 0x00,
20*4882a593Smuzhiyun 	INTERRUPT_1        = 0x01,
21*4882a593Smuzhiyun 	INTERRUPT_2        = 0x02,
22*4882a593Smuzhiyun 	INTERRUPT_3        = 0x03,
23*4882a593Smuzhiyun 	INTERRUPT_4        = 0x04,
24*4882a593Smuzhiyun 	INTERRUPT_5        = 0x05,
25*4882a593Smuzhiyun 	STATUS_6           = 0x06,
26*4882a593Smuzhiyun 	STATUS_7           = 0x07,
27*4882a593Smuzhiyun 	STATUS_8           = 0x08,
28*4882a593Smuzhiyun 	STATUS_9           = 0x09,
29*4882a593Smuzhiyun 	AGC_GAIN_1         = 0x0A,
30*4882a593Smuzhiyun 	AGC_GAIN_0         = 0x0B,
31*4882a593Smuzhiyun 	SNR                = 0x10,
32*4882a593Smuzhiyun 	RS_ERR_CNT_2       = 0x11,
33*4882a593Smuzhiyun 	RS_ERR_CNT_1       = 0x12,
34*4882a593Smuzhiyun 	RS_ERR_CNT_0       = 0x13,
35*4882a593Smuzhiyun 	RS_UBC_1           = 0x14,
36*4882a593Smuzhiyun 	RS_UBC_0           = 0x15,
37*4882a593Smuzhiyun 	TPS_RECEIVED_1     = 0x1D,
38*4882a593Smuzhiyun 	TPS_RECEIVED_0     = 0x1E,
39*4882a593Smuzhiyun 	TPS_CURRENT_1      = 0x1F,
40*4882a593Smuzhiyun 	TPS_CURRENT_0      = 0x20,
41*4882a593Smuzhiyun 	CLOCK_CTL_0        = 0x51,
42*4882a593Smuzhiyun 	CLOCK_CTL_1        = 0x52,
43*4882a593Smuzhiyun 	PLL_0              = 0x53,
44*4882a593Smuzhiyun 	PLL_1              = 0x54,
45*4882a593Smuzhiyun 	RESET              = 0x55,
46*4882a593Smuzhiyun 	AGC_TARGET         = 0x56,
47*4882a593Smuzhiyun 	MCLK_RATIO         = 0x5C,
48*4882a593Smuzhiyun 	ACQ_CTL            = 0x5E,
49*4882a593Smuzhiyun 	TRL_NOMINAL_RATE_1 = 0x65,
50*4882a593Smuzhiyun 	TRL_NOMINAL_RATE_0 = 0x66,
51*4882a593Smuzhiyun 	INPUT_FREQ_1       = 0x6C,
52*4882a593Smuzhiyun 	INPUT_FREQ_0       = 0x6D,
53*4882a593Smuzhiyun 	TPS_GIVEN_1        = 0x6E,
54*4882a593Smuzhiyun 	TPS_GIVEN_0        = 0x6F,
55*4882a593Smuzhiyun 	TUNER_GO           = 0x70,
56*4882a593Smuzhiyun 	FSM_GO             = 0x71,
57*4882a593Smuzhiyun 	CHIP_ID            = 0x7F,
58*4882a593Smuzhiyun 	CHAN_STEP_1        = 0xE4,
59*4882a593Smuzhiyun 	CHAN_STEP_0        = 0xE5,
60*4882a593Smuzhiyun 	OFDM_LOCK_TIME     = 0xE7,
61*4882a593Smuzhiyun 	FEC_LOCK_TIME      = 0xE8,
62*4882a593Smuzhiyun 	ACQ_DELAY          = 0xE9,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #endif                          /* _ZL10353_PRIV_ */
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