1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /* z0194a.h Sharp z0194a tuner support
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2008 Igor M. Liplianin (liplianin@me.by)
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef Z0194A
10*4882a593Smuzhiyun #define Z0194A
11*4882a593Smuzhiyun
sharp_z0194a_set_symbol_rate(struct dvb_frontend * fe,u32 srate,u32 ratio)12*4882a593Smuzhiyun static int sharp_z0194a_set_symbol_rate(struct dvb_frontend *fe,
13*4882a593Smuzhiyun u32 srate, u32 ratio)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun u8 aclk = 0;
16*4882a593Smuzhiyun u8 bclk = 0;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun if (srate < 1500000) {
19*4882a593Smuzhiyun aclk = 0xb7; bclk = 0x47; }
20*4882a593Smuzhiyun else if (srate < 3000000) {
21*4882a593Smuzhiyun aclk = 0xb7; bclk = 0x4b; }
22*4882a593Smuzhiyun else if (srate < 7000000) {
23*4882a593Smuzhiyun aclk = 0xb7; bclk = 0x4f; }
24*4882a593Smuzhiyun else if (srate < 14000000) {
25*4882a593Smuzhiyun aclk = 0xb7; bclk = 0x53; }
26*4882a593Smuzhiyun else if (srate < 30000000) {
27*4882a593Smuzhiyun aclk = 0xb6; bclk = 0x53; }
28*4882a593Smuzhiyun else if (srate < 45000000) {
29*4882a593Smuzhiyun aclk = 0xb4; bclk = 0x51; }
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun stv0299_writereg(fe, 0x13, aclk);
32*4882a593Smuzhiyun stv0299_writereg(fe, 0x14, bclk);
33*4882a593Smuzhiyun stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
34*4882a593Smuzhiyun stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
35*4882a593Smuzhiyun stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun return 0;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static u8 sharp_z0194a_inittab[] = {
41*4882a593Smuzhiyun 0x01, 0x15,
42*4882a593Smuzhiyun 0x02, 0x30,
43*4882a593Smuzhiyun 0x03, 0x00,
44*4882a593Smuzhiyun 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
45*4882a593Smuzhiyun 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
46*4882a593Smuzhiyun 0x06, 0x40, /* DAC not used, set to high impendance mode */
47*4882a593Smuzhiyun 0x07, 0x00, /* DAC LSB */
48*4882a593Smuzhiyun 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
49*4882a593Smuzhiyun 0x09, 0x00, /* FIFO */
50*4882a593Smuzhiyun 0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
51*4882a593Smuzhiyun 0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
52*4882a593Smuzhiyun 0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
53*4882a593Smuzhiyun 0x10, 0x3f, /* AGC2 0x3d */
54*4882a593Smuzhiyun 0x11, 0x84,
55*4882a593Smuzhiyun 0x12, 0xb9,
56*4882a593Smuzhiyun 0x15, 0xc9, /* lock detector threshold */
57*4882a593Smuzhiyun 0x16, 0x00,
58*4882a593Smuzhiyun 0x17, 0x00,
59*4882a593Smuzhiyun 0x18, 0x00,
60*4882a593Smuzhiyun 0x19, 0x00,
61*4882a593Smuzhiyun 0x1a, 0x00,
62*4882a593Smuzhiyun 0x1f, 0x50,
63*4882a593Smuzhiyun 0x20, 0x00,
64*4882a593Smuzhiyun 0x21, 0x00,
65*4882a593Smuzhiyun 0x22, 0x00,
66*4882a593Smuzhiyun 0x23, 0x00,
67*4882a593Smuzhiyun 0x28, 0x00, /* out imp: normal out type: parallel FEC mode:0 */
68*4882a593Smuzhiyun 0x29, 0x1e, /* 1/2 threshold */
69*4882a593Smuzhiyun 0x2a, 0x14, /* 2/3 threshold */
70*4882a593Smuzhiyun 0x2b, 0x0f, /* 3/4 threshold */
71*4882a593Smuzhiyun 0x2c, 0x09, /* 5/6 threshold */
72*4882a593Smuzhiyun 0x2d, 0x05, /* 7/8 threshold */
73*4882a593Smuzhiyun 0x2e, 0x01,
74*4882a593Smuzhiyun 0x31, 0x1f, /* test all FECs */
75*4882a593Smuzhiyun 0x32, 0x19, /* viterbi and synchro search */
76*4882a593Smuzhiyun 0x33, 0xfc, /* rs control */
77*4882a593Smuzhiyun 0x34, 0x93, /* error control */
78*4882a593Smuzhiyun 0x0f, 0x52,
79*4882a593Smuzhiyun 0xff, 0xff
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #endif
83