xref: /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/tda10086.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun   /*
3*4882a593Smuzhiyun      Driver for Philips tda10086 DVBS Demodulator
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun      (c) 2006 Andrew de Quincey
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun    */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/jiffies.h>
14*4882a593Smuzhiyun #include <linux/string.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <media/dvb_frontend.h>
18*4882a593Smuzhiyun #include "tda10086.h"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define SACLK 96000000U
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun struct tda10086_state {
23*4882a593Smuzhiyun 	struct i2c_adapter* i2c;
24*4882a593Smuzhiyun 	const struct tda10086_config* config;
25*4882a593Smuzhiyun 	struct dvb_frontend frontend;
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	/* private demod data */
28*4882a593Smuzhiyun 	u32 frequency;
29*4882a593Smuzhiyun 	u32 symbol_rate;
30*4882a593Smuzhiyun 	bool has_lock;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun static int debug;
34*4882a593Smuzhiyun #define dprintk(args...) \
35*4882a593Smuzhiyun 	do { \
36*4882a593Smuzhiyun 		if (debug) printk(KERN_DEBUG "tda10086: " args); \
37*4882a593Smuzhiyun 	} while (0)
38*4882a593Smuzhiyun 
tda10086_write_byte(struct tda10086_state * state,int reg,int data)39*4882a593Smuzhiyun static int tda10086_write_byte(struct tda10086_state *state, int reg, int data)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	int ret;
42*4882a593Smuzhiyun 	u8 b0[] = { reg, data };
43*4882a593Smuzhiyun 	struct i2c_msg msg = { .flags = 0, .buf = b0, .len = 2 };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	msg.addr = state->config->demod_address;
46*4882a593Smuzhiyun 	ret = i2c_transfer(state->i2c, &msg, 1);
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	if (ret != 1)
49*4882a593Smuzhiyun 		dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
50*4882a593Smuzhiyun 			__func__, reg, data, ret);
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	return (ret != 1) ? ret : 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
tda10086_read_byte(struct tda10086_state * state,int reg)55*4882a593Smuzhiyun static int tda10086_read_byte(struct tda10086_state *state, int reg)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	int ret;
58*4882a593Smuzhiyun 	u8 b0[] = { reg };
59*4882a593Smuzhiyun 	u8 b1[] = { 0 };
60*4882a593Smuzhiyun 	struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
61*4882a593Smuzhiyun 				{ .flags = I2C_M_RD, .buf = b1, .len = 1 }};
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	msg[0].addr = state->config->demod_address;
64*4882a593Smuzhiyun 	msg[1].addr = state->config->demod_address;
65*4882a593Smuzhiyun 	ret = i2c_transfer(state->i2c, msg, 2);
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	if (ret != 2) {
68*4882a593Smuzhiyun 		dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
69*4882a593Smuzhiyun 			ret);
70*4882a593Smuzhiyun 		return ret;
71*4882a593Smuzhiyun 	}
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	return b1[0];
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
tda10086_write_mask(struct tda10086_state * state,int reg,int mask,int data)76*4882a593Smuzhiyun static int tda10086_write_mask(struct tda10086_state *state, int reg, int mask, int data)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	int val;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/* read a byte and check */
81*4882a593Smuzhiyun 	val = tda10086_read_byte(state, reg);
82*4882a593Smuzhiyun 	if (val < 0)
83*4882a593Smuzhiyun 		return val;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/* mask if off */
86*4882a593Smuzhiyun 	val = val & ~mask;
87*4882a593Smuzhiyun 	val |= data & 0xff;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	/* write it out again */
90*4882a593Smuzhiyun 	return tda10086_write_byte(state, reg, val);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
tda10086_init(struct dvb_frontend * fe)93*4882a593Smuzhiyun static int tda10086_init(struct dvb_frontend* fe)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
96*4882a593Smuzhiyun 	u8 t22k_off = 0x80;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	if (state->config->diseqc_tone)
101*4882a593Smuzhiyun 		t22k_off = 0;
102*4882a593Smuzhiyun 	/* reset */
103*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x00, 0x00);
104*4882a593Smuzhiyun 	msleep(10);
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	/* misc setup */
107*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x01, 0x94);
108*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x02, 0x35); /* NOTE: TT drivers appear to disable CSWP */
109*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x03, 0xe4);
110*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x04, 0x43);
111*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x0c, 0x0c);
112*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x1b, 0xb0); /* noise threshold */
113*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x20, 0x89); /* misc */
114*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x30, 0x04); /* acquisition period length */
115*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x32, 0x00); /* irq off */
116*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x31, 0x56); /* setup AFC */
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/* setup PLL (this assumes SACLK = 96MHz) */
119*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x55, 0x2c); /* misc PLL setup */
120*4882a593Smuzhiyun 	if (state->config->xtal_freq == TDA10086_XTAL_16M) {
121*4882a593Smuzhiyun 		tda10086_write_byte(state, 0x3a, 0x0b); /* M=12 */
122*4882a593Smuzhiyun 		tda10086_write_byte(state, 0x3b, 0x01); /* P=2 */
123*4882a593Smuzhiyun 	} else {
124*4882a593Smuzhiyun 		tda10086_write_byte(state, 0x3a, 0x17); /* M=24 */
125*4882a593Smuzhiyun 		tda10086_write_byte(state, 0x3b, 0x00); /* P=1 */
126*4882a593Smuzhiyun 	}
127*4882a593Smuzhiyun 	tda10086_write_mask(state, 0x55, 0x20, 0x00); /* powerup PLL */
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	/* setup TS interface */
130*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x11, 0x81);
131*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x12, 0x81);
132*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x19, 0x40); /* parallel mode A + MSBFIRST */
133*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x56, 0x80); /* powerdown WPLL - unused in the mode we use */
134*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x57, 0x08); /* bypass WPLL - unused in the mode we use */
135*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x10, 0x2a);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	/* setup ADC */
138*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x58, 0x61); /* ADC setup */
139*4882a593Smuzhiyun 	tda10086_write_mask(state, 0x58, 0x01, 0x00); /* powerup ADC */
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/* setup AGC */
142*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x05, 0x0B);
143*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x37, 0x63);
144*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x3f, 0x0a); /* NOTE: flydvb varies it */
145*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x40, 0x64);
146*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x41, 0x4f);
147*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x42, 0x43);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	/* setup viterbi */
150*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x1a, 0x11); /* VBER 10^6, DVB, QPSK */
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	/* setup carrier recovery */
153*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x3d, 0x80);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	/* setup SEC */
156*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x36, t22k_off); /* all SEC off, 22k tone */
157*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x34, (((1<<19) * (22000/1000)) / (SACLK/1000)));
158*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x35, (((1<<19) * (22000/1000)) / (SACLK/1000)) >> 8);
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	return 0;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun 
tda10086_diseqc_wait(struct tda10086_state * state)163*4882a593Smuzhiyun static void tda10086_diseqc_wait(struct tda10086_state *state)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun 	unsigned long timeout = jiffies + msecs_to_jiffies(200);
166*4882a593Smuzhiyun 	while (!(tda10086_read_byte(state, 0x50) & 0x01)) {
167*4882a593Smuzhiyun 		if(time_after(jiffies, timeout)) {
168*4882a593Smuzhiyun 			printk("%s: diseqc queue not ready, command may be lost.\n", __func__);
169*4882a593Smuzhiyun 			break;
170*4882a593Smuzhiyun 		}
171*4882a593Smuzhiyun 		msleep(10);
172*4882a593Smuzhiyun 	}
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun 
tda10086_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)175*4882a593Smuzhiyun static int tda10086_set_tone(struct dvb_frontend *fe,
176*4882a593Smuzhiyun 			     enum fe_sec_tone_mode tone)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
179*4882a593Smuzhiyun 	u8 t22k_off = 0x80;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	if (state->config->diseqc_tone)
184*4882a593Smuzhiyun 		t22k_off = 0;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	switch (tone) {
187*4882a593Smuzhiyun 	case SEC_TONE_OFF:
188*4882a593Smuzhiyun 		tda10086_write_byte(state, 0x36, t22k_off);
189*4882a593Smuzhiyun 		break;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	case SEC_TONE_ON:
192*4882a593Smuzhiyun 		tda10086_write_byte(state, 0x36, 0x01 + t22k_off);
193*4882a593Smuzhiyun 		break;
194*4882a593Smuzhiyun 	}
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	return 0;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun 
tda10086_send_master_cmd(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)199*4882a593Smuzhiyun static int tda10086_send_master_cmd (struct dvb_frontend* fe,
200*4882a593Smuzhiyun 				    struct dvb_diseqc_master_cmd* cmd)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
203*4882a593Smuzhiyun 	int i;
204*4882a593Smuzhiyun 	u8 oldval;
205*4882a593Smuzhiyun 	u8 t22k_off = 0x80;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	if (state->config->diseqc_tone)
210*4882a593Smuzhiyun 		t22k_off = 0;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	if (cmd->msg_len > 6)
213*4882a593Smuzhiyun 		return -EINVAL;
214*4882a593Smuzhiyun 	oldval = tda10086_read_byte(state, 0x36);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	for(i=0; i< cmd->msg_len; i++) {
217*4882a593Smuzhiyun 		tda10086_write_byte(state, 0x48+i, cmd->msg[i]);
218*4882a593Smuzhiyun 	}
219*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x36, (0x08 + t22k_off)
220*4882a593Smuzhiyun 					| ((cmd->msg_len - 1) << 4));
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	tda10086_diseqc_wait(state);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x36, oldval);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	return 0;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun 
tda10086_send_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd minicmd)229*4882a593Smuzhiyun static int tda10086_send_burst(struct dvb_frontend *fe,
230*4882a593Smuzhiyun 			       enum fe_sec_mini_cmd minicmd)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
233*4882a593Smuzhiyun 	u8 oldval = tda10086_read_byte(state, 0x36);
234*4882a593Smuzhiyun 	u8 t22k_off = 0x80;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	if (state->config->diseqc_tone)
239*4882a593Smuzhiyun 		t22k_off = 0;
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	switch(minicmd) {
242*4882a593Smuzhiyun 	case SEC_MINI_A:
243*4882a593Smuzhiyun 		tda10086_write_byte(state, 0x36, 0x04 + t22k_off);
244*4882a593Smuzhiyun 		break;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	case SEC_MINI_B:
247*4882a593Smuzhiyun 		tda10086_write_byte(state, 0x36, 0x06 + t22k_off);
248*4882a593Smuzhiyun 		break;
249*4882a593Smuzhiyun 	}
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	tda10086_diseqc_wait(state);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x36, oldval);
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	return 0;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun 
tda10086_set_inversion(struct tda10086_state * state,struct dtv_frontend_properties * fe_params)258*4882a593Smuzhiyun static int tda10086_set_inversion(struct tda10086_state *state,
259*4882a593Smuzhiyun 				  struct dtv_frontend_properties *fe_params)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	u8 invval = 0x80;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	dprintk ("%s %i %i\n", __func__, fe_params->inversion, state->config->invert);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	switch(fe_params->inversion) {
266*4882a593Smuzhiyun 	case INVERSION_OFF:
267*4882a593Smuzhiyun 		if (state->config->invert)
268*4882a593Smuzhiyun 			invval = 0x40;
269*4882a593Smuzhiyun 		break;
270*4882a593Smuzhiyun 	case INVERSION_ON:
271*4882a593Smuzhiyun 		if (!state->config->invert)
272*4882a593Smuzhiyun 			invval = 0x40;
273*4882a593Smuzhiyun 		break;
274*4882a593Smuzhiyun 	case INVERSION_AUTO:
275*4882a593Smuzhiyun 		invval = 0x00;
276*4882a593Smuzhiyun 		break;
277*4882a593Smuzhiyun 	}
278*4882a593Smuzhiyun 	tda10086_write_mask(state, 0x0c, 0xc0, invval);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	return 0;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
tda10086_set_symbol_rate(struct tda10086_state * state,struct dtv_frontend_properties * fe_params)283*4882a593Smuzhiyun static int tda10086_set_symbol_rate(struct tda10086_state *state,
284*4882a593Smuzhiyun 				    struct dtv_frontend_properties *fe_params)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun 	u8 dfn = 0;
287*4882a593Smuzhiyun 	u8 afs = 0;
288*4882a593Smuzhiyun 	u8 byp = 0;
289*4882a593Smuzhiyun 	u8 reg37 = 0x43;
290*4882a593Smuzhiyun 	u8 reg42 = 0x43;
291*4882a593Smuzhiyun 	u64 big;
292*4882a593Smuzhiyun 	u32 tmp;
293*4882a593Smuzhiyun 	u32 bdr;
294*4882a593Smuzhiyun 	u32 bdri;
295*4882a593Smuzhiyun 	u32 symbol_rate = fe_params->symbol_rate;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	dprintk ("%s %i\n", __func__, symbol_rate);
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	/* setup the decimation and anti-aliasing filters.. */
300*4882a593Smuzhiyun 	if (symbol_rate < SACLK / 10000 * 137) {
301*4882a593Smuzhiyun 		dfn=4;
302*4882a593Smuzhiyun 		afs=1;
303*4882a593Smuzhiyun 	} else if (symbol_rate < SACLK / 10000 * 208) {
304*4882a593Smuzhiyun 		dfn=4;
305*4882a593Smuzhiyun 		afs=0;
306*4882a593Smuzhiyun 	} else if (symbol_rate < SACLK / 10000 * 270) {
307*4882a593Smuzhiyun 		dfn=3;
308*4882a593Smuzhiyun 		afs=1;
309*4882a593Smuzhiyun 	} else if (symbol_rate < SACLK / 10000 * 416) {
310*4882a593Smuzhiyun 		dfn=3;
311*4882a593Smuzhiyun 		afs=0;
312*4882a593Smuzhiyun 	} else if (symbol_rate < SACLK / 10000 * 550) {
313*4882a593Smuzhiyun 		dfn=2;
314*4882a593Smuzhiyun 		afs=1;
315*4882a593Smuzhiyun 	} else if (symbol_rate < SACLK / 10000 * 833) {
316*4882a593Smuzhiyun 		dfn=2;
317*4882a593Smuzhiyun 		afs=0;
318*4882a593Smuzhiyun 	} else if (symbol_rate < SACLK / 10000 * 1100) {
319*4882a593Smuzhiyun 		dfn=1;
320*4882a593Smuzhiyun 		afs=1;
321*4882a593Smuzhiyun 	} else if (symbol_rate < SACLK / 10000 * 1666) {
322*4882a593Smuzhiyun 		dfn=1;
323*4882a593Smuzhiyun 		afs=0;
324*4882a593Smuzhiyun 	} else if (symbol_rate < SACLK / 10000 * 2200) {
325*4882a593Smuzhiyun 		dfn=0;
326*4882a593Smuzhiyun 		afs=1;
327*4882a593Smuzhiyun 	} else if (symbol_rate < SACLK / 10000 * 3333) {
328*4882a593Smuzhiyun 		dfn=0;
329*4882a593Smuzhiyun 		afs=0;
330*4882a593Smuzhiyun 	} else {
331*4882a593Smuzhiyun 		reg37 = 0x63;
332*4882a593Smuzhiyun 		reg42 = 0x4f;
333*4882a593Smuzhiyun 		byp=1;
334*4882a593Smuzhiyun 	}
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	/* calculate BDR */
337*4882a593Smuzhiyun 	big = (1ULL<<21) * ((u64) symbol_rate/1000ULL) * (1ULL<<dfn);
338*4882a593Smuzhiyun 	big += ((SACLK/1000ULL)-1ULL);
339*4882a593Smuzhiyun 	do_div(big, (SACLK/1000ULL));
340*4882a593Smuzhiyun 	bdr = big & 0xfffff;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	/* calculate BDRI */
343*4882a593Smuzhiyun 	tmp = (1<<dfn)*(symbol_rate/1000);
344*4882a593Smuzhiyun 	bdri = ((32 * (SACLK/1000)) + (tmp-1)) / tmp;
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x21, (afs << 7) | dfn);
347*4882a593Smuzhiyun 	tda10086_write_mask(state, 0x20, 0x08, byp << 3);
348*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x06, bdr);
349*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x07, bdr >> 8);
350*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x08, bdr >> 16);
351*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x09, bdri);
352*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x37, reg37);
353*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x42, reg42);
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	return 0;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun 
tda10086_set_fec(struct tda10086_state * state,struct dtv_frontend_properties * fe_params)358*4882a593Smuzhiyun static int tda10086_set_fec(struct tda10086_state *state,
359*4882a593Smuzhiyun 			    struct dtv_frontend_properties *fe_params)
360*4882a593Smuzhiyun {
361*4882a593Smuzhiyun 	u8 fecval;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	dprintk("%s %i\n", __func__, fe_params->fec_inner);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	switch (fe_params->fec_inner) {
366*4882a593Smuzhiyun 	case FEC_1_2:
367*4882a593Smuzhiyun 		fecval = 0x00;
368*4882a593Smuzhiyun 		break;
369*4882a593Smuzhiyun 	case FEC_2_3:
370*4882a593Smuzhiyun 		fecval = 0x01;
371*4882a593Smuzhiyun 		break;
372*4882a593Smuzhiyun 	case FEC_3_4:
373*4882a593Smuzhiyun 		fecval = 0x02;
374*4882a593Smuzhiyun 		break;
375*4882a593Smuzhiyun 	case FEC_4_5:
376*4882a593Smuzhiyun 		fecval = 0x03;
377*4882a593Smuzhiyun 		break;
378*4882a593Smuzhiyun 	case FEC_5_6:
379*4882a593Smuzhiyun 		fecval = 0x04;
380*4882a593Smuzhiyun 		break;
381*4882a593Smuzhiyun 	case FEC_6_7:
382*4882a593Smuzhiyun 		fecval = 0x05;
383*4882a593Smuzhiyun 		break;
384*4882a593Smuzhiyun 	case FEC_7_8:
385*4882a593Smuzhiyun 		fecval = 0x06;
386*4882a593Smuzhiyun 		break;
387*4882a593Smuzhiyun 	case FEC_8_9:
388*4882a593Smuzhiyun 		fecval = 0x07;
389*4882a593Smuzhiyun 		break;
390*4882a593Smuzhiyun 	case FEC_AUTO:
391*4882a593Smuzhiyun 		fecval = 0x08;
392*4882a593Smuzhiyun 		break;
393*4882a593Smuzhiyun 	default:
394*4882a593Smuzhiyun 		return -1;
395*4882a593Smuzhiyun 	}
396*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x0d, fecval);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	return 0;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun 
tda10086_set_frontend(struct dvb_frontend * fe)401*4882a593Smuzhiyun static int tda10086_set_frontend(struct dvb_frontend *fe)
402*4882a593Smuzhiyun {
403*4882a593Smuzhiyun 	struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
404*4882a593Smuzhiyun 	struct tda10086_state *state = fe->demodulator_priv;
405*4882a593Smuzhiyun 	int ret;
406*4882a593Smuzhiyun 	u32 freq = 0;
407*4882a593Smuzhiyun 	int freqoff;
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	/* modify parameters for tuning */
412*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x02, 0x35);
413*4882a593Smuzhiyun 	state->has_lock = false;
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	/* set params */
416*4882a593Smuzhiyun 	if (fe->ops.tuner_ops.set_params) {
417*4882a593Smuzhiyun 		fe->ops.tuner_ops.set_params(fe);
418*4882a593Smuzhiyun 		if (fe->ops.i2c_gate_ctrl)
419*4882a593Smuzhiyun 			fe->ops.i2c_gate_ctrl(fe, 0);
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 		if (fe->ops.tuner_ops.get_frequency)
422*4882a593Smuzhiyun 			fe->ops.tuner_ops.get_frequency(fe, &freq);
423*4882a593Smuzhiyun 		if (fe->ops.i2c_gate_ctrl)
424*4882a593Smuzhiyun 			fe->ops.i2c_gate_ctrl(fe, 0);
425*4882a593Smuzhiyun 	}
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	/* calculate the frequency offset (in *Hz* not kHz) */
428*4882a593Smuzhiyun 	freqoff = fe_params->frequency - freq;
429*4882a593Smuzhiyun 	freqoff = ((1<<16) * freqoff) / (SACLK/1000);
430*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x3d, 0x80 | ((freqoff >> 8) & 0x7f));
431*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x3e, freqoff);
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	if ((ret = tda10086_set_inversion(state, fe_params)) < 0)
434*4882a593Smuzhiyun 		return ret;
435*4882a593Smuzhiyun 	if ((ret = tda10086_set_symbol_rate(state, fe_params)) < 0)
436*4882a593Smuzhiyun 		return ret;
437*4882a593Smuzhiyun 	if ((ret = tda10086_set_fec(state, fe_params)) < 0)
438*4882a593Smuzhiyun 		return ret;
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 	/* soft reset + disable TS output until lock */
441*4882a593Smuzhiyun 	tda10086_write_mask(state, 0x10, 0x40, 0x40);
442*4882a593Smuzhiyun 	tda10086_write_mask(state, 0x00, 0x01, 0x00);
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	state->symbol_rate = fe_params->symbol_rate;
445*4882a593Smuzhiyun 	state->frequency = fe_params->frequency;
446*4882a593Smuzhiyun 	return 0;
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun 
tda10086_get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * fe_params)449*4882a593Smuzhiyun static int tda10086_get_frontend(struct dvb_frontend *fe,
450*4882a593Smuzhiyun 				 struct dtv_frontend_properties *fe_params)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
453*4882a593Smuzhiyun 	u8 val;
454*4882a593Smuzhiyun 	int tmp;
455*4882a593Smuzhiyun 	u64 tmp64;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	/* check for invalid symbol rate */
460*4882a593Smuzhiyun 	if (fe_params->symbol_rate < 500000)
461*4882a593Smuzhiyun 		return -EINVAL;
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	/* calculate the updated frequency (note: we convert from Hz->kHz) */
464*4882a593Smuzhiyun 	tmp64 = ((u64)tda10086_read_byte(state, 0x52)
465*4882a593Smuzhiyun 		| (tda10086_read_byte(state, 0x51) << 8));
466*4882a593Smuzhiyun 	if (tmp64 & 0x8000)
467*4882a593Smuzhiyun 		tmp64 |= 0xffffffffffff0000ULL;
468*4882a593Smuzhiyun 	tmp64 = (tmp64 * (SACLK/1000ULL));
469*4882a593Smuzhiyun 	do_div(tmp64, (1ULL<<15) * (1ULL<<1));
470*4882a593Smuzhiyun 	fe_params->frequency = (int) state->frequency + (int) tmp64;
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	/* the inversion */
473*4882a593Smuzhiyun 	val = tda10086_read_byte(state, 0x0c);
474*4882a593Smuzhiyun 	if (val & 0x80) {
475*4882a593Smuzhiyun 		switch(val & 0x40) {
476*4882a593Smuzhiyun 		case 0x00:
477*4882a593Smuzhiyun 			fe_params->inversion = INVERSION_OFF;
478*4882a593Smuzhiyun 			if (state->config->invert)
479*4882a593Smuzhiyun 				fe_params->inversion = INVERSION_ON;
480*4882a593Smuzhiyun 			break;
481*4882a593Smuzhiyun 		default:
482*4882a593Smuzhiyun 			fe_params->inversion = INVERSION_ON;
483*4882a593Smuzhiyun 			if (state->config->invert)
484*4882a593Smuzhiyun 				fe_params->inversion = INVERSION_OFF;
485*4882a593Smuzhiyun 			break;
486*4882a593Smuzhiyun 		}
487*4882a593Smuzhiyun 	} else {
488*4882a593Smuzhiyun 		tda10086_read_byte(state, 0x0f);
489*4882a593Smuzhiyun 		switch(val & 0x02) {
490*4882a593Smuzhiyun 		case 0x00:
491*4882a593Smuzhiyun 			fe_params->inversion = INVERSION_OFF;
492*4882a593Smuzhiyun 			if (state->config->invert)
493*4882a593Smuzhiyun 				fe_params->inversion = INVERSION_ON;
494*4882a593Smuzhiyun 			break;
495*4882a593Smuzhiyun 		default:
496*4882a593Smuzhiyun 			fe_params->inversion = INVERSION_ON;
497*4882a593Smuzhiyun 			if (state->config->invert)
498*4882a593Smuzhiyun 				fe_params->inversion = INVERSION_OFF;
499*4882a593Smuzhiyun 			break;
500*4882a593Smuzhiyun 		}
501*4882a593Smuzhiyun 	}
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	/* calculate the updated symbol rate */
504*4882a593Smuzhiyun 	tmp = tda10086_read_byte(state, 0x1d);
505*4882a593Smuzhiyun 	if (tmp & 0x80)
506*4882a593Smuzhiyun 		tmp |= 0xffffff00;
507*4882a593Smuzhiyun 	tmp = (tmp * 480 * (1<<1)) / 128;
508*4882a593Smuzhiyun 	tmp = ((state->symbol_rate/1000) * tmp) / (1000000/1000);
509*4882a593Smuzhiyun 	fe_params->symbol_rate = state->symbol_rate + tmp;
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 	/* the FEC */
512*4882a593Smuzhiyun 	val = (tda10086_read_byte(state, 0x0d) & 0x70) >> 4;
513*4882a593Smuzhiyun 	switch(val) {
514*4882a593Smuzhiyun 	case 0x00:
515*4882a593Smuzhiyun 		fe_params->fec_inner = FEC_1_2;
516*4882a593Smuzhiyun 		break;
517*4882a593Smuzhiyun 	case 0x01:
518*4882a593Smuzhiyun 		fe_params->fec_inner = FEC_2_3;
519*4882a593Smuzhiyun 		break;
520*4882a593Smuzhiyun 	case 0x02:
521*4882a593Smuzhiyun 		fe_params->fec_inner = FEC_3_4;
522*4882a593Smuzhiyun 		break;
523*4882a593Smuzhiyun 	case 0x03:
524*4882a593Smuzhiyun 		fe_params->fec_inner = FEC_4_5;
525*4882a593Smuzhiyun 		break;
526*4882a593Smuzhiyun 	case 0x04:
527*4882a593Smuzhiyun 		fe_params->fec_inner = FEC_5_6;
528*4882a593Smuzhiyun 		break;
529*4882a593Smuzhiyun 	case 0x05:
530*4882a593Smuzhiyun 		fe_params->fec_inner = FEC_6_7;
531*4882a593Smuzhiyun 		break;
532*4882a593Smuzhiyun 	case 0x06:
533*4882a593Smuzhiyun 		fe_params->fec_inner = FEC_7_8;
534*4882a593Smuzhiyun 		break;
535*4882a593Smuzhiyun 	case 0x07:
536*4882a593Smuzhiyun 		fe_params->fec_inner = FEC_8_9;
537*4882a593Smuzhiyun 		break;
538*4882a593Smuzhiyun 	}
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	return 0;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun 
tda10086_read_status(struct dvb_frontend * fe,enum fe_status * fe_status)543*4882a593Smuzhiyun static int tda10086_read_status(struct dvb_frontend *fe,
544*4882a593Smuzhiyun 				enum fe_status *fe_status)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
547*4882a593Smuzhiyun 	u8 val;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	val = tda10086_read_byte(state, 0x0e);
552*4882a593Smuzhiyun 	*fe_status = 0;
553*4882a593Smuzhiyun 	if (val & 0x01)
554*4882a593Smuzhiyun 		*fe_status |= FE_HAS_SIGNAL;
555*4882a593Smuzhiyun 	if (val & 0x02)
556*4882a593Smuzhiyun 		*fe_status |= FE_HAS_CARRIER;
557*4882a593Smuzhiyun 	if (val & 0x04)
558*4882a593Smuzhiyun 		*fe_status |= FE_HAS_VITERBI;
559*4882a593Smuzhiyun 	if (val & 0x08)
560*4882a593Smuzhiyun 		*fe_status |= FE_HAS_SYNC;
561*4882a593Smuzhiyun 	if (val & 0x10) {
562*4882a593Smuzhiyun 		*fe_status |= FE_HAS_LOCK;
563*4882a593Smuzhiyun 		if (!state->has_lock) {
564*4882a593Smuzhiyun 			state->has_lock = true;
565*4882a593Smuzhiyun 			/* modify parameters for stable reception */
566*4882a593Smuzhiyun 			tda10086_write_byte(state, 0x02, 0x00);
567*4882a593Smuzhiyun 		}
568*4882a593Smuzhiyun 	}
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	return 0;
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun 
tda10086_read_signal_strength(struct dvb_frontend * fe,u16 * signal)573*4882a593Smuzhiyun static int tda10086_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
576*4882a593Smuzhiyun 	u8 _str;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	_str = 0xff - tda10086_read_byte(state, 0x43);
581*4882a593Smuzhiyun 	*signal = (_str << 8) | _str;
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 	return 0;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun 
tda10086_read_snr(struct dvb_frontend * fe,u16 * snr)586*4882a593Smuzhiyun static int tda10086_read_snr(struct dvb_frontend* fe, u16 * snr)
587*4882a593Smuzhiyun {
588*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
589*4882a593Smuzhiyun 	u8 _snr;
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	_snr = 0xff - tda10086_read_byte(state, 0x1c);
594*4882a593Smuzhiyun 	*snr = (_snr << 8) | _snr;
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	return 0;
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun 
tda10086_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)599*4882a593Smuzhiyun static int tda10086_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
600*4882a593Smuzhiyun {
601*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun 	/* read it */
606*4882a593Smuzhiyun 	*ucblocks = tda10086_read_byte(state, 0x18) & 0x7f;
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	/* reset counter */
609*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x18, 0x00);
610*4882a593Smuzhiyun 	tda10086_write_byte(state, 0x18, 0x80);
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 	return 0;
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun 
tda10086_read_ber(struct dvb_frontend * fe,u32 * ber)615*4882a593Smuzhiyun static int tda10086_read_ber(struct dvb_frontend* fe, u32* ber)
616*4882a593Smuzhiyun {
617*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	/* read it */
622*4882a593Smuzhiyun 	*ber = 0;
623*4882a593Smuzhiyun 	*ber |= tda10086_read_byte(state, 0x15);
624*4882a593Smuzhiyun 	*ber |= tda10086_read_byte(state, 0x16) << 8;
625*4882a593Smuzhiyun 	*ber |= (tda10086_read_byte(state, 0x17) & 0xf) << 16;
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	return 0;
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun 
tda10086_sleep(struct dvb_frontend * fe)630*4882a593Smuzhiyun static int tda10086_sleep(struct dvb_frontend* fe)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun 	tda10086_write_mask(state, 0x00, 0x08, 0x08);
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 	return 0;
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun 
tda10086_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)641*4882a593Smuzhiyun static int tda10086_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun 	struct tda10086_state* state = fe->demodulator_priv;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	if (enable) {
648*4882a593Smuzhiyun 		tda10086_write_mask(state, 0x00, 0x10, 0x10);
649*4882a593Smuzhiyun 	} else {
650*4882a593Smuzhiyun 		tda10086_write_mask(state, 0x00, 0x10, 0x00);
651*4882a593Smuzhiyun 	}
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	return 0;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun 
tda10086_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * fesettings)656*4882a593Smuzhiyun static int tda10086_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
657*4882a593Smuzhiyun {
658*4882a593Smuzhiyun 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	if (p->symbol_rate > 20000000) {
661*4882a593Smuzhiyun 		fesettings->min_delay_ms = 50;
662*4882a593Smuzhiyun 		fesettings->step_size = 2000;
663*4882a593Smuzhiyun 		fesettings->max_drift = 8000;
664*4882a593Smuzhiyun 	} else if (p->symbol_rate > 12000000) {
665*4882a593Smuzhiyun 		fesettings->min_delay_ms = 100;
666*4882a593Smuzhiyun 		fesettings->step_size = 1500;
667*4882a593Smuzhiyun 		fesettings->max_drift = 9000;
668*4882a593Smuzhiyun 	} else if (p->symbol_rate > 8000000) {
669*4882a593Smuzhiyun 		fesettings->min_delay_ms = 100;
670*4882a593Smuzhiyun 		fesettings->step_size = 1000;
671*4882a593Smuzhiyun 		fesettings->max_drift = 8000;
672*4882a593Smuzhiyun 	} else if (p->symbol_rate > 4000000) {
673*4882a593Smuzhiyun 		fesettings->min_delay_ms = 100;
674*4882a593Smuzhiyun 		fesettings->step_size = 500;
675*4882a593Smuzhiyun 		fesettings->max_drift = 7000;
676*4882a593Smuzhiyun 	} else if (p->symbol_rate > 2000000) {
677*4882a593Smuzhiyun 		fesettings->min_delay_ms = 200;
678*4882a593Smuzhiyun 		fesettings->step_size = p->symbol_rate / 8000;
679*4882a593Smuzhiyun 		fesettings->max_drift = 14 * fesettings->step_size;
680*4882a593Smuzhiyun 	} else {
681*4882a593Smuzhiyun 		fesettings->min_delay_ms = 200;
682*4882a593Smuzhiyun 		fesettings->step_size =  p->symbol_rate / 8000;
683*4882a593Smuzhiyun 		fesettings->max_drift = 18 * fesettings->step_size;
684*4882a593Smuzhiyun 	}
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun 	return 0;
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun 
tda10086_release(struct dvb_frontend * fe)689*4882a593Smuzhiyun static void tda10086_release(struct dvb_frontend* fe)
690*4882a593Smuzhiyun {
691*4882a593Smuzhiyun 	struct tda10086_state *state = fe->demodulator_priv;
692*4882a593Smuzhiyun 	tda10086_sleep(fe);
693*4882a593Smuzhiyun 	kfree(state);
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun static const struct dvb_frontend_ops tda10086_ops = {
697*4882a593Smuzhiyun 	.delsys = { SYS_DVBS },
698*4882a593Smuzhiyun 	.info = {
699*4882a593Smuzhiyun 		.name     = "Philips TDA10086 DVB-S",
700*4882a593Smuzhiyun 		.frequency_min_hz      =  950 * MHz,
701*4882a593Smuzhiyun 		.frequency_max_hz      = 2150 * MHz,
702*4882a593Smuzhiyun 		.frequency_stepsize_hz =  125 * kHz,
703*4882a593Smuzhiyun 		.symbol_rate_min  = 1000000,
704*4882a593Smuzhiyun 		.symbol_rate_max  = 45000000,
705*4882a593Smuzhiyun 		.caps = FE_CAN_INVERSION_AUTO |
706*4882a593Smuzhiyun 			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
707*4882a593Smuzhiyun 			FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
708*4882a593Smuzhiyun 			FE_CAN_QPSK
709*4882a593Smuzhiyun 	},
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun 	.release = tda10086_release,
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun 	.init = tda10086_init,
714*4882a593Smuzhiyun 	.sleep = tda10086_sleep,
715*4882a593Smuzhiyun 	.i2c_gate_ctrl = tda10086_i2c_gate_ctrl,
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	.set_frontend = tda10086_set_frontend,
718*4882a593Smuzhiyun 	.get_frontend = tda10086_get_frontend,
719*4882a593Smuzhiyun 	.get_tune_settings = tda10086_get_tune_settings,
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	.read_status = tda10086_read_status,
722*4882a593Smuzhiyun 	.read_ber = tda10086_read_ber,
723*4882a593Smuzhiyun 	.read_signal_strength = tda10086_read_signal_strength,
724*4882a593Smuzhiyun 	.read_snr = tda10086_read_snr,
725*4882a593Smuzhiyun 	.read_ucblocks = tda10086_read_ucblocks,
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	.diseqc_send_master_cmd = tda10086_send_master_cmd,
728*4882a593Smuzhiyun 	.diseqc_send_burst = tda10086_send_burst,
729*4882a593Smuzhiyun 	.set_tone = tda10086_set_tone,
730*4882a593Smuzhiyun };
731*4882a593Smuzhiyun 
tda10086_attach(const struct tda10086_config * config,struct i2c_adapter * i2c)732*4882a593Smuzhiyun struct dvb_frontend* tda10086_attach(const struct tda10086_config* config,
733*4882a593Smuzhiyun 				     struct i2c_adapter* i2c)
734*4882a593Smuzhiyun {
735*4882a593Smuzhiyun 	struct tda10086_state *state;
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun 	dprintk ("%s\n", __func__);
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun 	/* allocate memory for the internal state */
740*4882a593Smuzhiyun 	state = kzalloc(sizeof(struct tda10086_state), GFP_KERNEL);
741*4882a593Smuzhiyun 	if (!state)
742*4882a593Smuzhiyun 		return NULL;
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	/* setup the state */
745*4882a593Smuzhiyun 	state->config = config;
746*4882a593Smuzhiyun 	state->i2c = i2c;
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 	/* check if the demod is there */
749*4882a593Smuzhiyun 	if (tda10086_read_byte(state, 0x1e) != 0xe1) {
750*4882a593Smuzhiyun 		kfree(state);
751*4882a593Smuzhiyun 		return NULL;
752*4882a593Smuzhiyun 	}
753*4882a593Smuzhiyun 
754*4882a593Smuzhiyun 	/* create dvb_frontend */
755*4882a593Smuzhiyun 	memcpy(&state->frontend.ops, &tda10086_ops, sizeof(struct dvb_frontend_ops));
756*4882a593Smuzhiyun 	state->frontend.demodulator_priv = state;
757*4882a593Smuzhiyun 	return &state->frontend;
758*4882a593Smuzhiyun }
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun module_param(debug, int, 0644);
761*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun MODULE_DESCRIPTION("Philips TDA10086 DVB-S Demodulator");
764*4882a593Smuzhiyun MODULE_AUTHOR("Andrew de Quincey");
765*4882a593Smuzhiyun MODULE_LICENSE("GPL");
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun EXPORT_SYMBOL(tda10086_attach);
768