1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun STV6110(A) Silicon tuner driver 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun Copyright (C) Manu Abraham <abraham.manu@gmail.com> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun Copyright (C) ST Microelectronics 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __STV6110x_REG_H 12*4882a593Smuzhiyun #define __STV6110x_REG_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define STV6110x_CTRL1 0x00 15*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL1_K 3 16*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL1_K 5 17*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL1_LPT 2 18*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL1_LPT 1 19*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL1_RX 1 20*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL1_RX 1 21*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL1_SYN 0 22*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL1_SYN 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define STV6110x_CTRL2 0x01 25*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL2_CO_DIV 6 26*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL2_CO_DIV 2 27*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL2_RSVD 5 28*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL2_RSVD 1 29*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL2_REFOUT_SEL 4 30*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL2_REFOUT_SEL 1 31*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL2_BBGAIN 0 32*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL2_BBGAIN 4 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define STV6110x_TNG0 0x02 35*4882a593Smuzhiyun #define STV6110x_OFFST_TNG0_N_DIV_7_0 0 36*4882a593Smuzhiyun #define STV6110x_WIDTH_TNG0_N_DIV_7_0 8 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define STV6110x_TNG1 0x03 39*4882a593Smuzhiyun #define STV6110x_OFFST_TNG1_R_DIV 6 40*4882a593Smuzhiyun #define STV6110x_WIDTH_TNG1_R_DIV 2 41*4882a593Smuzhiyun #define STV6110x_OFFST_TNG1_PRESC32_ON 5 42*4882a593Smuzhiyun #define STV6110x_WIDTH_TNG1_PRESC32_ON 1 43*4882a593Smuzhiyun #define STV6110x_OFFST_TNG1_DIV4SEL 4 44*4882a593Smuzhiyun #define STV6110x_WIDTH_TNG1_DIV4SEL 1 45*4882a593Smuzhiyun #define STV6110x_OFFST_TNG1_N_DIV_11_8 0 46*4882a593Smuzhiyun #define STV6110x_WIDTH_TNG1_N_DIV_11_8 4 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define STV6110x_CTRL3 0x04 50*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL3_DCLOOP_OFF 7 51*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL3_DCLOOP_OFF 1 52*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL3_RCCLK_OFF 6 53*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL3_RCCLK_OFF 1 54*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL3_ICP 5 55*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL3_ICP 1 56*4882a593Smuzhiyun #define STV6110x_OFFST_CTRL3_CF 0 57*4882a593Smuzhiyun #define STV6110x_WIDTH_CTRL3_CF 5 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define STV6110x_STAT1 0x05 60*4882a593Smuzhiyun #define STV6110x_OFFST_STAT1_CALVCO_STRT 2 61*4882a593Smuzhiyun #define STV6110x_WIDTH_STAT1_CALVCO_STRT 1 62*4882a593Smuzhiyun #define STV6110x_OFFST_STAT1_CALRC_STRT 1 63*4882a593Smuzhiyun #define STV6110x_WIDTH_STAT1_CALRC_STRT 1 64*4882a593Smuzhiyun #define STV6110x_OFFST_STAT1_LOCK 0 65*4882a593Smuzhiyun #define STV6110x_WIDTH_STAT1_LOCK 1 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define STV6110x_STAT2 0x06 68*4882a593Smuzhiyun #define STV6110x_STAT3 0x07 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* __STV6110x_REG_H */ 71