1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun STV0900/0903 Multistandard Broadcast Frontend driver
4*4882a593Smuzhiyun Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun Copyright (C) ST Microelectronics
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/string.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/mutex.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/dvb/frontend.h>
18*4882a593Smuzhiyun #include <media/dvb_frontend.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "stv6110x.h" /* for demodulator internal modes */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include "stv090x_reg.h"
23*4882a593Smuzhiyun #include "stv090x.h"
24*4882a593Smuzhiyun #include "stv090x_priv.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Max transfer size done by I2C transfer functions */
27*4882a593Smuzhiyun #define MAX_XFER_SIZE 64
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static unsigned int verbose;
30*4882a593Smuzhiyun module_param(verbose, int, 0644);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* internal params node */
33*4882a593Smuzhiyun struct stv090x_dev {
34*4882a593Smuzhiyun /* pointer for internal params, one for each pair of demods */
35*4882a593Smuzhiyun struct stv090x_internal *internal;
36*4882a593Smuzhiyun struct stv090x_dev *next_dev;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* first internal params */
40*4882a593Smuzhiyun static struct stv090x_dev *stv090x_first_dev;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* find chip by i2c adapter and i2c address */
find_dev(struct i2c_adapter * i2c_adap,u8 i2c_addr)43*4882a593Smuzhiyun static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
44*4882a593Smuzhiyun u8 i2c_addr)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct stv090x_dev *temp_dev = stv090x_first_dev;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun Search of the last stv0900 chip or
50*4882a593Smuzhiyun find it by i2c adapter and i2c address */
51*4882a593Smuzhiyun while ((temp_dev != NULL) &&
52*4882a593Smuzhiyun ((temp_dev->internal->i2c_adap != i2c_adap) ||
53*4882a593Smuzhiyun (temp_dev->internal->i2c_addr != i2c_addr))) {
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun temp_dev = temp_dev->next_dev;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return temp_dev;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* deallocating chip */
remove_dev(struct stv090x_internal * internal)62*4882a593Smuzhiyun static void remove_dev(struct stv090x_internal *internal)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct stv090x_dev *prev_dev = stv090x_first_dev;
65*4882a593Smuzhiyun struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
66*4882a593Smuzhiyun internal->i2c_addr);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (del_dev != NULL) {
69*4882a593Smuzhiyun if (del_dev == stv090x_first_dev) {
70*4882a593Smuzhiyun stv090x_first_dev = del_dev->next_dev;
71*4882a593Smuzhiyun } else {
72*4882a593Smuzhiyun while (prev_dev->next_dev != del_dev)
73*4882a593Smuzhiyun prev_dev = prev_dev->next_dev;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun prev_dev->next_dev = del_dev->next_dev;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun kfree(del_dev);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* allocating new chip */
append_internal(struct stv090x_internal * internal)83*4882a593Smuzhiyun static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct stv090x_dev *new_dev;
86*4882a593Smuzhiyun struct stv090x_dev *temp_dev;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
89*4882a593Smuzhiyun if (new_dev != NULL) {
90*4882a593Smuzhiyun new_dev->internal = internal;
91*4882a593Smuzhiyun new_dev->next_dev = NULL;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* append to list */
94*4882a593Smuzhiyun if (stv090x_first_dev == NULL) {
95*4882a593Smuzhiyun stv090x_first_dev = new_dev;
96*4882a593Smuzhiyun } else {
97*4882a593Smuzhiyun temp_dev = stv090x_first_dev;
98*4882a593Smuzhiyun while (temp_dev->next_dev != NULL)
99*4882a593Smuzhiyun temp_dev = temp_dev->next_dev;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun temp_dev->next_dev = new_dev;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return new_dev;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* DVBS1 and DSS C/N Lookup table */
110*4882a593Smuzhiyun static const struct stv090x_tab stv090x_s1cn_tab[] = {
111*4882a593Smuzhiyun { 0, 8917 }, /* 0.0dB */
112*4882a593Smuzhiyun { 5, 8801 }, /* 0.5dB */
113*4882a593Smuzhiyun { 10, 8667 }, /* 1.0dB */
114*4882a593Smuzhiyun { 15, 8522 }, /* 1.5dB */
115*4882a593Smuzhiyun { 20, 8355 }, /* 2.0dB */
116*4882a593Smuzhiyun { 25, 8175 }, /* 2.5dB */
117*4882a593Smuzhiyun { 30, 7979 }, /* 3.0dB */
118*4882a593Smuzhiyun { 35, 7763 }, /* 3.5dB */
119*4882a593Smuzhiyun { 40, 7530 }, /* 4.0dB */
120*4882a593Smuzhiyun { 45, 7282 }, /* 4.5dB */
121*4882a593Smuzhiyun { 50, 7026 }, /* 5.0dB */
122*4882a593Smuzhiyun { 55, 6781 }, /* 5.5dB */
123*4882a593Smuzhiyun { 60, 6514 }, /* 6.0dB */
124*4882a593Smuzhiyun { 65, 6241 }, /* 6.5dB */
125*4882a593Smuzhiyun { 70, 5965 }, /* 7.0dB */
126*4882a593Smuzhiyun { 75, 5690 }, /* 7.5dB */
127*4882a593Smuzhiyun { 80, 5424 }, /* 8.0dB */
128*4882a593Smuzhiyun { 85, 5161 }, /* 8.5dB */
129*4882a593Smuzhiyun { 90, 4902 }, /* 9.0dB */
130*4882a593Smuzhiyun { 95, 4654 }, /* 9.5dB */
131*4882a593Smuzhiyun { 100, 4417 }, /* 10.0dB */
132*4882a593Smuzhiyun { 105, 4186 }, /* 10.5dB */
133*4882a593Smuzhiyun { 110, 3968 }, /* 11.0dB */
134*4882a593Smuzhiyun { 115, 3757 }, /* 11.5dB */
135*4882a593Smuzhiyun { 120, 3558 }, /* 12.0dB */
136*4882a593Smuzhiyun { 125, 3366 }, /* 12.5dB */
137*4882a593Smuzhiyun { 130, 3185 }, /* 13.0dB */
138*4882a593Smuzhiyun { 135, 3012 }, /* 13.5dB */
139*4882a593Smuzhiyun { 140, 2850 }, /* 14.0dB */
140*4882a593Smuzhiyun { 145, 2698 }, /* 14.5dB */
141*4882a593Smuzhiyun { 150, 2550 }, /* 15.0dB */
142*4882a593Smuzhiyun { 160, 2283 }, /* 16.0dB */
143*4882a593Smuzhiyun { 170, 2042 }, /* 17.0dB */
144*4882a593Smuzhiyun { 180, 1827 }, /* 18.0dB */
145*4882a593Smuzhiyun { 190, 1636 }, /* 19.0dB */
146*4882a593Smuzhiyun { 200, 1466 }, /* 20.0dB */
147*4882a593Smuzhiyun { 210, 1315 }, /* 21.0dB */
148*4882a593Smuzhiyun { 220, 1181 }, /* 22.0dB */
149*4882a593Smuzhiyun { 230, 1064 }, /* 23.0dB */
150*4882a593Smuzhiyun { 240, 960 }, /* 24.0dB */
151*4882a593Smuzhiyun { 250, 869 }, /* 25.0dB */
152*4882a593Smuzhiyun { 260, 792 }, /* 26.0dB */
153*4882a593Smuzhiyun { 270, 724 }, /* 27.0dB */
154*4882a593Smuzhiyun { 280, 665 }, /* 28.0dB */
155*4882a593Smuzhiyun { 290, 616 }, /* 29.0dB */
156*4882a593Smuzhiyun { 300, 573 }, /* 30.0dB */
157*4882a593Smuzhiyun { 310, 537 }, /* 31.0dB */
158*4882a593Smuzhiyun { 320, 507 }, /* 32.0dB */
159*4882a593Smuzhiyun { 330, 483 }, /* 33.0dB */
160*4882a593Smuzhiyun { 400, 398 }, /* 40.0dB */
161*4882a593Smuzhiyun { 450, 381 }, /* 45.0dB */
162*4882a593Smuzhiyun { 500, 377 } /* 50.0dB */
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* DVBS2 C/N Lookup table */
166*4882a593Smuzhiyun static const struct stv090x_tab stv090x_s2cn_tab[] = {
167*4882a593Smuzhiyun { -30, 13348 }, /* -3.0dB */
168*4882a593Smuzhiyun { -20, 12640 }, /* -2d.0B */
169*4882a593Smuzhiyun { -10, 11883 }, /* -1.0dB */
170*4882a593Smuzhiyun { 0, 11101 }, /* -0.0dB */
171*4882a593Smuzhiyun { 5, 10718 }, /* 0.5dB */
172*4882a593Smuzhiyun { 10, 10339 }, /* 1.0dB */
173*4882a593Smuzhiyun { 15, 9947 }, /* 1.5dB */
174*4882a593Smuzhiyun { 20, 9552 }, /* 2.0dB */
175*4882a593Smuzhiyun { 25, 9183 }, /* 2.5dB */
176*4882a593Smuzhiyun { 30, 8799 }, /* 3.0dB */
177*4882a593Smuzhiyun { 35, 8422 }, /* 3.5dB */
178*4882a593Smuzhiyun { 40, 8062 }, /* 4.0dB */
179*4882a593Smuzhiyun { 45, 7707 }, /* 4.5dB */
180*4882a593Smuzhiyun { 50, 7353 }, /* 5.0dB */
181*4882a593Smuzhiyun { 55, 7025 }, /* 5.5dB */
182*4882a593Smuzhiyun { 60, 6684 }, /* 6.0dB */
183*4882a593Smuzhiyun { 65, 6331 }, /* 6.5dB */
184*4882a593Smuzhiyun { 70, 6036 }, /* 7.0dB */
185*4882a593Smuzhiyun { 75, 5727 }, /* 7.5dB */
186*4882a593Smuzhiyun { 80, 5437 }, /* 8.0dB */
187*4882a593Smuzhiyun { 85, 5164 }, /* 8.5dB */
188*4882a593Smuzhiyun { 90, 4902 }, /* 9.0dB */
189*4882a593Smuzhiyun { 95, 4653 }, /* 9.5dB */
190*4882a593Smuzhiyun { 100, 4408 }, /* 10.0dB */
191*4882a593Smuzhiyun { 105, 4187 }, /* 10.5dB */
192*4882a593Smuzhiyun { 110, 3961 }, /* 11.0dB */
193*4882a593Smuzhiyun { 115, 3751 }, /* 11.5dB */
194*4882a593Smuzhiyun { 120, 3558 }, /* 12.0dB */
195*4882a593Smuzhiyun { 125, 3368 }, /* 12.5dB */
196*4882a593Smuzhiyun { 130, 3191 }, /* 13.0dB */
197*4882a593Smuzhiyun { 135, 3017 }, /* 13.5dB */
198*4882a593Smuzhiyun { 140, 2862 }, /* 14.0dB */
199*4882a593Smuzhiyun { 145, 2710 }, /* 14.5dB */
200*4882a593Smuzhiyun { 150, 2565 }, /* 15.0dB */
201*4882a593Smuzhiyun { 160, 2300 }, /* 16.0dB */
202*4882a593Smuzhiyun { 170, 2058 }, /* 17.0dB */
203*4882a593Smuzhiyun { 180, 1849 }, /* 18.0dB */
204*4882a593Smuzhiyun { 190, 1663 }, /* 19.0dB */
205*4882a593Smuzhiyun { 200, 1495 }, /* 20.0dB */
206*4882a593Smuzhiyun { 210, 1349 }, /* 21.0dB */
207*4882a593Smuzhiyun { 220, 1222 }, /* 22.0dB */
208*4882a593Smuzhiyun { 230, 1110 }, /* 23.0dB */
209*4882a593Smuzhiyun { 240, 1011 }, /* 24.0dB */
210*4882a593Smuzhiyun { 250, 925 }, /* 25.0dB */
211*4882a593Smuzhiyun { 260, 853 }, /* 26.0dB */
212*4882a593Smuzhiyun { 270, 789 }, /* 27.0dB */
213*4882a593Smuzhiyun { 280, 734 }, /* 28.0dB */
214*4882a593Smuzhiyun { 290, 690 }, /* 29.0dB */
215*4882a593Smuzhiyun { 300, 650 }, /* 30.0dB */
216*4882a593Smuzhiyun { 310, 619 }, /* 31.0dB */
217*4882a593Smuzhiyun { 320, 593 }, /* 32.0dB */
218*4882a593Smuzhiyun { 330, 571 }, /* 33.0dB */
219*4882a593Smuzhiyun { 400, 498 }, /* 40.0dB */
220*4882a593Smuzhiyun { 450, 484 }, /* 45.0dB */
221*4882a593Smuzhiyun { 500, 481 } /* 50.0dB */
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /* RF level C/N lookup table */
225*4882a593Smuzhiyun static const struct stv090x_tab stv090x_rf_tab[] = {
226*4882a593Smuzhiyun { -5, 0xcaa1 }, /* -5dBm */
227*4882a593Smuzhiyun { -10, 0xc229 }, /* -10dBm */
228*4882a593Smuzhiyun { -15, 0xbb08 }, /* -15dBm */
229*4882a593Smuzhiyun { -20, 0xb4bc }, /* -20dBm */
230*4882a593Smuzhiyun { -25, 0xad5a }, /* -25dBm */
231*4882a593Smuzhiyun { -30, 0xa298 }, /* -30dBm */
232*4882a593Smuzhiyun { -35, 0x98a8 }, /* -35dBm */
233*4882a593Smuzhiyun { -40, 0x8389 }, /* -40dBm */
234*4882a593Smuzhiyun { -45, 0x59be }, /* -45dBm */
235*4882a593Smuzhiyun { -50, 0x3a14 }, /* -50dBm */
236*4882a593Smuzhiyun { -55, 0x2d11 }, /* -55dBm */
237*4882a593Smuzhiyun { -60, 0x210d }, /* -60dBm */
238*4882a593Smuzhiyun { -65, 0xa14f }, /* -65dBm */
239*4882a593Smuzhiyun { -70, 0x07aa } /* -70dBm */
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun static struct stv090x_reg stv0900_initval[] = {
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun { STV090x_OUTCFG, 0x00 },
246*4882a593Smuzhiyun { STV090x_MODECFG, 0xff },
247*4882a593Smuzhiyun { STV090x_AGCRF1CFG, 0x11 },
248*4882a593Smuzhiyun { STV090x_AGCRF2CFG, 0x13 },
249*4882a593Smuzhiyun { STV090x_TSGENERAL1X, 0x14 },
250*4882a593Smuzhiyun { STV090x_TSTTNR2, 0x21 },
251*4882a593Smuzhiyun { STV090x_TSTTNR4, 0x21 },
252*4882a593Smuzhiyun { STV090x_P2_DISTXCTL, 0x22 },
253*4882a593Smuzhiyun { STV090x_P2_F22TX, 0xc0 },
254*4882a593Smuzhiyun { STV090x_P2_F22RX, 0xc0 },
255*4882a593Smuzhiyun { STV090x_P2_DISRXCTL, 0x00 },
256*4882a593Smuzhiyun { STV090x_P2_DMDCFGMD, 0xF9 },
257*4882a593Smuzhiyun { STV090x_P2_DEMOD, 0x08 },
258*4882a593Smuzhiyun { STV090x_P2_DMDCFG3, 0xc4 },
259*4882a593Smuzhiyun { STV090x_P2_CARFREQ, 0xed },
260*4882a593Smuzhiyun { STV090x_P2_LDT, 0xd0 },
261*4882a593Smuzhiyun { STV090x_P2_LDT2, 0xb8 },
262*4882a593Smuzhiyun { STV090x_P2_TMGCFG, 0xd2 },
263*4882a593Smuzhiyun { STV090x_P2_TMGTHRISE, 0x20 },
264*4882a593Smuzhiyun { STV090x_P1_TMGCFG, 0xd2 },
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun { STV090x_P2_TMGTHFALL, 0x00 },
267*4882a593Smuzhiyun { STV090x_P2_FECSPY, 0x88 },
268*4882a593Smuzhiyun { STV090x_P2_FSPYDATA, 0x3a },
269*4882a593Smuzhiyun { STV090x_P2_FBERCPT4, 0x00 },
270*4882a593Smuzhiyun { STV090x_P2_FSPYBER, 0x10 },
271*4882a593Smuzhiyun { STV090x_P2_ERRCTRL1, 0x35 },
272*4882a593Smuzhiyun { STV090x_P2_ERRCTRL2, 0xc1 },
273*4882a593Smuzhiyun { STV090x_P2_CFRICFG, 0xf8 },
274*4882a593Smuzhiyun { STV090x_P2_NOSCFG, 0x1c },
275*4882a593Smuzhiyun { STV090x_P2_DMDTOM, 0x20 },
276*4882a593Smuzhiyun { STV090x_P2_CORRELMANT, 0x70 },
277*4882a593Smuzhiyun { STV090x_P2_CORRELABS, 0x88 },
278*4882a593Smuzhiyun { STV090x_P2_AGC2O, 0x5b },
279*4882a593Smuzhiyun { STV090x_P2_AGC2REF, 0x38 },
280*4882a593Smuzhiyun { STV090x_P2_CARCFG, 0xe4 },
281*4882a593Smuzhiyun { STV090x_P2_ACLC, 0x1A },
282*4882a593Smuzhiyun { STV090x_P2_BCLC, 0x09 },
283*4882a593Smuzhiyun { STV090x_P2_CARHDR, 0x08 },
284*4882a593Smuzhiyun { STV090x_P2_KREFTMG, 0xc1 },
285*4882a593Smuzhiyun { STV090x_P2_SFRUPRATIO, 0xf0 },
286*4882a593Smuzhiyun { STV090x_P2_SFRLOWRATIO, 0x70 },
287*4882a593Smuzhiyun { STV090x_P2_SFRSTEP, 0x58 },
288*4882a593Smuzhiyun { STV090x_P2_TMGCFG2, 0x01 },
289*4882a593Smuzhiyun { STV090x_P2_CAR2CFG, 0x26 },
290*4882a593Smuzhiyun { STV090x_P2_BCLC2S2Q, 0x86 },
291*4882a593Smuzhiyun { STV090x_P2_BCLC2S28, 0x86 },
292*4882a593Smuzhiyun { STV090x_P2_SMAPCOEF7, 0x77 },
293*4882a593Smuzhiyun { STV090x_P2_SMAPCOEF6, 0x85 },
294*4882a593Smuzhiyun { STV090x_P2_SMAPCOEF5, 0x77 },
295*4882a593Smuzhiyun { STV090x_P2_TSCFGL, 0x20 },
296*4882a593Smuzhiyun { STV090x_P2_DMDCFG2, 0x3b },
297*4882a593Smuzhiyun { STV090x_P2_MODCODLST0, 0xff },
298*4882a593Smuzhiyun { STV090x_P2_MODCODLST1, 0xff },
299*4882a593Smuzhiyun { STV090x_P2_MODCODLST2, 0xff },
300*4882a593Smuzhiyun { STV090x_P2_MODCODLST3, 0xff },
301*4882a593Smuzhiyun { STV090x_P2_MODCODLST4, 0xff },
302*4882a593Smuzhiyun { STV090x_P2_MODCODLST5, 0xff },
303*4882a593Smuzhiyun { STV090x_P2_MODCODLST6, 0xff },
304*4882a593Smuzhiyun { STV090x_P2_MODCODLST7, 0xcc },
305*4882a593Smuzhiyun { STV090x_P2_MODCODLST8, 0xcc },
306*4882a593Smuzhiyun { STV090x_P2_MODCODLST9, 0xcc },
307*4882a593Smuzhiyun { STV090x_P2_MODCODLSTA, 0xcc },
308*4882a593Smuzhiyun { STV090x_P2_MODCODLSTB, 0xcc },
309*4882a593Smuzhiyun { STV090x_P2_MODCODLSTC, 0xcc },
310*4882a593Smuzhiyun { STV090x_P2_MODCODLSTD, 0xcc },
311*4882a593Smuzhiyun { STV090x_P2_MODCODLSTE, 0xcc },
312*4882a593Smuzhiyun { STV090x_P2_MODCODLSTF, 0xcf },
313*4882a593Smuzhiyun { STV090x_P1_DISTXCTL, 0x22 },
314*4882a593Smuzhiyun { STV090x_P1_F22TX, 0xc0 },
315*4882a593Smuzhiyun { STV090x_P1_F22RX, 0xc0 },
316*4882a593Smuzhiyun { STV090x_P1_DISRXCTL, 0x00 },
317*4882a593Smuzhiyun { STV090x_P1_DMDCFGMD, 0xf9 },
318*4882a593Smuzhiyun { STV090x_P1_DEMOD, 0x08 },
319*4882a593Smuzhiyun { STV090x_P1_DMDCFG3, 0xc4 },
320*4882a593Smuzhiyun { STV090x_P1_DMDTOM, 0x20 },
321*4882a593Smuzhiyun { STV090x_P1_CARFREQ, 0xed },
322*4882a593Smuzhiyun { STV090x_P1_LDT, 0xd0 },
323*4882a593Smuzhiyun { STV090x_P1_LDT2, 0xb8 },
324*4882a593Smuzhiyun { STV090x_P1_TMGCFG, 0xd2 },
325*4882a593Smuzhiyun { STV090x_P1_TMGTHRISE, 0x20 },
326*4882a593Smuzhiyun { STV090x_P1_TMGTHFALL, 0x00 },
327*4882a593Smuzhiyun { STV090x_P1_SFRUPRATIO, 0xf0 },
328*4882a593Smuzhiyun { STV090x_P1_SFRLOWRATIO, 0x70 },
329*4882a593Smuzhiyun { STV090x_P1_TSCFGL, 0x20 },
330*4882a593Smuzhiyun { STV090x_P1_FECSPY, 0x88 },
331*4882a593Smuzhiyun { STV090x_P1_FSPYDATA, 0x3a },
332*4882a593Smuzhiyun { STV090x_P1_FBERCPT4, 0x00 },
333*4882a593Smuzhiyun { STV090x_P1_FSPYBER, 0x10 },
334*4882a593Smuzhiyun { STV090x_P1_ERRCTRL1, 0x35 },
335*4882a593Smuzhiyun { STV090x_P1_ERRCTRL2, 0xc1 },
336*4882a593Smuzhiyun { STV090x_P1_CFRICFG, 0xf8 },
337*4882a593Smuzhiyun { STV090x_P1_NOSCFG, 0x1c },
338*4882a593Smuzhiyun { STV090x_P1_CORRELMANT, 0x70 },
339*4882a593Smuzhiyun { STV090x_P1_CORRELABS, 0x88 },
340*4882a593Smuzhiyun { STV090x_P1_AGC2O, 0x5b },
341*4882a593Smuzhiyun { STV090x_P1_AGC2REF, 0x38 },
342*4882a593Smuzhiyun { STV090x_P1_CARCFG, 0xe4 },
343*4882a593Smuzhiyun { STV090x_P1_ACLC, 0x1A },
344*4882a593Smuzhiyun { STV090x_P1_BCLC, 0x09 },
345*4882a593Smuzhiyun { STV090x_P1_CARHDR, 0x08 },
346*4882a593Smuzhiyun { STV090x_P1_KREFTMG, 0xc1 },
347*4882a593Smuzhiyun { STV090x_P1_SFRSTEP, 0x58 },
348*4882a593Smuzhiyun { STV090x_P1_TMGCFG2, 0x01 },
349*4882a593Smuzhiyun { STV090x_P1_CAR2CFG, 0x26 },
350*4882a593Smuzhiyun { STV090x_P1_BCLC2S2Q, 0x86 },
351*4882a593Smuzhiyun { STV090x_P1_BCLC2S28, 0x86 },
352*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF7, 0x77 },
353*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF6, 0x85 },
354*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF5, 0x77 },
355*4882a593Smuzhiyun { STV090x_P1_DMDCFG2, 0x3b },
356*4882a593Smuzhiyun { STV090x_P1_MODCODLST0, 0xff },
357*4882a593Smuzhiyun { STV090x_P1_MODCODLST1, 0xff },
358*4882a593Smuzhiyun { STV090x_P1_MODCODLST2, 0xff },
359*4882a593Smuzhiyun { STV090x_P1_MODCODLST3, 0xff },
360*4882a593Smuzhiyun { STV090x_P1_MODCODLST4, 0xff },
361*4882a593Smuzhiyun { STV090x_P1_MODCODLST5, 0xff },
362*4882a593Smuzhiyun { STV090x_P1_MODCODLST6, 0xff },
363*4882a593Smuzhiyun { STV090x_P1_MODCODLST7, 0xcc },
364*4882a593Smuzhiyun { STV090x_P1_MODCODLST8, 0xcc },
365*4882a593Smuzhiyun { STV090x_P1_MODCODLST9, 0xcc },
366*4882a593Smuzhiyun { STV090x_P1_MODCODLSTA, 0xcc },
367*4882a593Smuzhiyun { STV090x_P1_MODCODLSTB, 0xcc },
368*4882a593Smuzhiyun { STV090x_P1_MODCODLSTC, 0xcc },
369*4882a593Smuzhiyun { STV090x_P1_MODCODLSTD, 0xcc },
370*4882a593Smuzhiyun { STV090x_P1_MODCODLSTE, 0xcc },
371*4882a593Smuzhiyun { STV090x_P1_MODCODLSTF, 0xcf },
372*4882a593Smuzhiyun { STV090x_GENCFG, 0x1d },
373*4882a593Smuzhiyun { STV090x_NBITER_NF4, 0x37 },
374*4882a593Smuzhiyun { STV090x_NBITER_NF5, 0x29 },
375*4882a593Smuzhiyun { STV090x_NBITER_NF6, 0x37 },
376*4882a593Smuzhiyun { STV090x_NBITER_NF7, 0x33 },
377*4882a593Smuzhiyun { STV090x_NBITER_NF8, 0x31 },
378*4882a593Smuzhiyun { STV090x_NBITER_NF9, 0x2f },
379*4882a593Smuzhiyun { STV090x_NBITER_NF10, 0x39 },
380*4882a593Smuzhiyun { STV090x_NBITER_NF11, 0x3a },
381*4882a593Smuzhiyun { STV090x_NBITER_NF12, 0x29 },
382*4882a593Smuzhiyun { STV090x_NBITER_NF13, 0x37 },
383*4882a593Smuzhiyun { STV090x_NBITER_NF14, 0x33 },
384*4882a593Smuzhiyun { STV090x_NBITER_NF15, 0x2f },
385*4882a593Smuzhiyun { STV090x_NBITER_NF16, 0x39 },
386*4882a593Smuzhiyun { STV090x_NBITER_NF17, 0x3a },
387*4882a593Smuzhiyun { STV090x_NBITERNOERR, 0x04 },
388*4882a593Smuzhiyun { STV090x_GAINLLR_NF4, 0x0C },
389*4882a593Smuzhiyun { STV090x_GAINLLR_NF5, 0x0F },
390*4882a593Smuzhiyun { STV090x_GAINLLR_NF6, 0x11 },
391*4882a593Smuzhiyun { STV090x_GAINLLR_NF7, 0x14 },
392*4882a593Smuzhiyun { STV090x_GAINLLR_NF8, 0x17 },
393*4882a593Smuzhiyun { STV090x_GAINLLR_NF9, 0x19 },
394*4882a593Smuzhiyun { STV090x_GAINLLR_NF10, 0x20 },
395*4882a593Smuzhiyun { STV090x_GAINLLR_NF11, 0x21 },
396*4882a593Smuzhiyun { STV090x_GAINLLR_NF12, 0x0D },
397*4882a593Smuzhiyun { STV090x_GAINLLR_NF13, 0x0F },
398*4882a593Smuzhiyun { STV090x_GAINLLR_NF14, 0x13 },
399*4882a593Smuzhiyun { STV090x_GAINLLR_NF15, 0x1A },
400*4882a593Smuzhiyun { STV090x_GAINLLR_NF16, 0x1F },
401*4882a593Smuzhiyun { STV090x_GAINLLR_NF17, 0x21 },
402*4882a593Smuzhiyun { STV090x_RCCFGH, 0x20 },
403*4882a593Smuzhiyun { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
404*4882a593Smuzhiyun { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
405*4882a593Smuzhiyun { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
406*4882a593Smuzhiyun { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun static struct stv090x_reg stv0903_initval[] = {
410*4882a593Smuzhiyun { STV090x_OUTCFG, 0x00 },
411*4882a593Smuzhiyun { STV090x_AGCRF1CFG, 0x11 },
412*4882a593Smuzhiyun { STV090x_STOPCLK1, 0x48 },
413*4882a593Smuzhiyun { STV090x_STOPCLK2, 0x14 },
414*4882a593Smuzhiyun { STV090x_TSTTNR1, 0x27 },
415*4882a593Smuzhiyun { STV090x_TSTTNR2, 0x21 },
416*4882a593Smuzhiyun { STV090x_P1_DISTXCTL, 0x22 },
417*4882a593Smuzhiyun { STV090x_P1_F22TX, 0xc0 },
418*4882a593Smuzhiyun { STV090x_P1_F22RX, 0xc0 },
419*4882a593Smuzhiyun { STV090x_P1_DISRXCTL, 0x00 },
420*4882a593Smuzhiyun { STV090x_P1_DMDCFGMD, 0xF9 },
421*4882a593Smuzhiyun { STV090x_P1_DEMOD, 0x08 },
422*4882a593Smuzhiyun { STV090x_P1_DMDCFG3, 0xc4 },
423*4882a593Smuzhiyun { STV090x_P1_CARFREQ, 0xed },
424*4882a593Smuzhiyun { STV090x_P1_TNRCFG2, 0x82 },
425*4882a593Smuzhiyun { STV090x_P1_LDT, 0xd0 },
426*4882a593Smuzhiyun { STV090x_P1_LDT2, 0xb8 },
427*4882a593Smuzhiyun { STV090x_P1_TMGCFG, 0xd2 },
428*4882a593Smuzhiyun { STV090x_P1_TMGTHRISE, 0x20 },
429*4882a593Smuzhiyun { STV090x_P1_TMGTHFALL, 0x00 },
430*4882a593Smuzhiyun { STV090x_P1_SFRUPRATIO, 0xf0 },
431*4882a593Smuzhiyun { STV090x_P1_SFRLOWRATIO, 0x70 },
432*4882a593Smuzhiyun { STV090x_P1_TSCFGL, 0x20 },
433*4882a593Smuzhiyun { STV090x_P1_FECSPY, 0x88 },
434*4882a593Smuzhiyun { STV090x_P1_FSPYDATA, 0x3a },
435*4882a593Smuzhiyun { STV090x_P1_FBERCPT4, 0x00 },
436*4882a593Smuzhiyun { STV090x_P1_FSPYBER, 0x10 },
437*4882a593Smuzhiyun { STV090x_P1_ERRCTRL1, 0x35 },
438*4882a593Smuzhiyun { STV090x_P1_ERRCTRL2, 0xc1 },
439*4882a593Smuzhiyun { STV090x_P1_CFRICFG, 0xf8 },
440*4882a593Smuzhiyun { STV090x_P1_NOSCFG, 0x1c },
441*4882a593Smuzhiyun { STV090x_P1_DMDTOM, 0x20 },
442*4882a593Smuzhiyun { STV090x_P1_CORRELMANT, 0x70 },
443*4882a593Smuzhiyun { STV090x_P1_CORRELABS, 0x88 },
444*4882a593Smuzhiyun { STV090x_P1_AGC2O, 0x5b },
445*4882a593Smuzhiyun { STV090x_P1_AGC2REF, 0x38 },
446*4882a593Smuzhiyun { STV090x_P1_CARCFG, 0xe4 },
447*4882a593Smuzhiyun { STV090x_P1_ACLC, 0x1A },
448*4882a593Smuzhiyun { STV090x_P1_BCLC, 0x09 },
449*4882a593Smuzhiyun { STV090x_P1_CARHDR, 0x08 },
450*4882a593Smuzhiyun { STV090x_P1_KREFTMG, 0xc1 },
451*4882a593Smuzhiyun { STV090x_P1_SFRSTEP, 0x58 },
452*4882a593Smuzhiyun { STV090x_P1_TMGCFG2, 0x01 },
453*4882a593Smuzhiyun { STV090x_P1_CAR2CFG, 0x26 },
454*4882a593Smuzhiyun { STV090x_P1_BCLC2S2Q, 0x86 },
455*4882a593Smuzhiyun { STV090x_P1_BCLC2S28, 0x86 },
456*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF7, 0x77 },
457*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF6, 0x85 },
458*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF5, 0x77 },
459*4882a593Smuzhiyun { STV090x_P1_DMDCFG2, 0x3b },
460*4882a593Smuzhiyun { STV090x_P1_MODCODLST0, 0xff },
461*4882a593Smuzhiyun { STV090x_P1_MODCODLST1, 0xff },
462*4882a593Smuzhiyun { STV090x_P1_MODCODLST2, 0xff },
463*4882a593Smuzhiyun { STV090x_P1_MODCODLST3, 0xff },
464*4882a593Smuzhiyun { STV090x_P1_MODCODLST4, 0xff },
465*4882a593Smuzhiyun { STV090x_P1_MODCODLST5, 0xff },
466*4882a593Smuzhiyun { STV090x_P1_MODCODLST6, 0xff },
467*4882a593Smuzhiyun { STV090x_P1_MODCODLST7, 0xcc },
468*4882a593Smuzhiyun { STV090x_P1_MODCODLST8, 0xcc },
469*4882a593Smuzhiyun { STV090x_P1_MODCODLST9, 0xcc },
470*4882a593Smuzhiyun { STV090x_P1_MODCODLSTA, 0xcc },
471*4882a593Smuzhiyun { STV090x_P1_MODCODLSTB, 0xcc },
472*4882a593Smuzhiyun { STV090x_P1_MODCODLSTC, 0xcc },
473*4882a593Smuzhiyun { STV090x_P1_MODCODLSTD, 0xcc },
474*4882a593Smuzhiyun { STV090x_P1_MODCODLSTE, 0xcc },
475*4882a593Smuzhiyun { STV090x_P1_MODCODLSTF, 0xcf },
476*4882a593Smuzhiyun { STV090x_GENCFG, 0x1c },
477*4882a593Smuzhiyun { STV090x_NBITER_NF4, 0x37 },
478*4882a593Smuzhiyun { STV090x_NBITER_NF5, 0x29 },
479*4882a593Smuzhiyun { STV090x_NBITER_NF6, 0x37 },
480*4882a593Smuzhiyun { STV090x_NBITER_NF7, 0x33 },
481*4882a593Smuzhiyun { STV090x_NBITER_NF8, 0x31 },
482*4882a593Smuzhiyun { STV090x_NBITER_NF9, 0x2f },
483*4882a593Smuzhiyun { STV090x_NBITER_NF10, 0x39 },
484*4882a593Smuzhiyun { STV090x_NBITER_NF11, 0x3a },
485*4882a593Smuzhiyun { STV090x_NBITER_NF12, 0x29 },
486*4882a593Smuzhiyun { STV090x_NBITER_NF13, 0x37 },
487*4882a593Smuzhiyun { STV090x_NBITER_NF14, 0x33 },
488*4882a593Smuzhiyun { STV090x_NBITER_NF15, 0x2f },
489*4882a593Smuzhiyun { STV090x_NBITER_NF16, 0x39 },
490*4882a593Smuzhiyun { STV090x_NBITER_NF17, 0x3a },
491*4882a593Smuzhiyun { STV090x_NBITERNOERR, 0x04 },
492*4882a593Smuzhiyun { STV090x_GAINLLR_NF4, 0x0C },
493*4882a593Smuzhiyun { STV090x_GAINLLR_NF5, 0x0F },
494*4882a593Smuzhiyun { STV090x_GAINLLR_NF6, 0x11 },
495*4882a593Smuzhiyun { STV090x_GAINLLR_NF7, 0x14 },
496*4882a593Smuzhiyun { STV090x_GAINLLR_NF8, 0x17 },
497*4882a593Smuzhiyun { STV090x_GAINLLR_NF9, 0x19 },
498*4882a593Smuzhiyun { STV090x_GAINLLR_NF10, 0x20 },
499*4882a593Smuzhiyun { STV090x_GAINLLR_NF11, 0x21 },
500*4882a593Smuzhiyun { STV090x_GAINLLR_NF12, 0x0D },
501*4882a593Smuzhiyun { STV090x_GAINLLR_NF13, 0x0F },
502*4882a593Smuzhiyun { STV090x_GAINLLR_NF14, 0x13 },
503*4882a593Smuzhiyun { STV090x_GAINLLR_NF15, 0x1A },
504*4882a593Smuzhiyun { STV090x_GAINLLR_NF16, 0x1F },
505*4882a593Smuzhiyun { STV090x_GAINLLR_NF17, 0x21 },
506*4882a593Smuzhiyun { STV090x_RCCFGH, 0x20 },
507*4882a593Smuzhiyun { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
508*4882a593Smuzhiyun { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun static struct stv090x_reg stv0900_cut20_val[] = {
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun { STV090x_P2_DMDCFG3, 0xe8 },
514*4882a593Smuzhiyun { STV090x_P2_DMDCFG4, 0x10 },
515*4882a593Smuzhiyun { STV090x_P2_CARFREQ, 0x38 },
516*4882a593Smuzhiyun { STV090x_P2_CARHDR, 0x20 },
517*4882a593Smuzhiyun { STV090x_P2_KREFTMG, 0x5a },
518*4882a593Smuzhiyun { STV090x_P2_SMAPCOEF7, 0x06 },
519*4882a593Smuzhiyun { STV090x_P2_SMAPCOEF6, 0x00 },
520*4882a593Smuzhiyun { STV090x_P2_SMAPCOEF5, 0x04 },
521*4882a593Smuzhiyun { STV090x_P2_NOSCFG, 0x0c },
522*4882a593Smuzhiyun { STV090x_P1_DMDCFG3, 0xe8 },
523*4882a593Smuzhiyun { STV090x_P1_DMDCFG4, 0x10 },
524*4882a593Smuzhiyun { STV090x_P1_CARFREQ, 0x38 },
525*4882a593Smuzhiyun { STV090x_P1_CARHDR, 0x20 },
526*4882a593Smuzhiyun { STV090x_P1_KREFTMG, 0x5a },
527*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF7, 0x06 },
528*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF6, 0x00 },
529*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF5, 0x04 },
530*4882a593Smuzhiyun { STV090x_P1_NOSCFG, 0x0c },
531*4882a593Smuzhiyun { STV090x_GAINLLR_NF4, 0x21 },
532*4882a593Smuzhiyun { STV090x_GAINLLR_NF5, 0x21 },
533*4882a593Smuzhiyun { STV090x_GAINLLR_NF6, 0x20 },
534*4882a593Smuzhiyun { STV090x_GAINLLR_NF7, 0x1F },
535*4882a593Smuzhiyun { STV090x_GAINLLR_NF8, 0x1E },
536*4882a593Smuzhiyun { STV090x_GAINLLR_NF9, 0x1E },
537*4882a593Smuzhiyun { STV090x_GAINLLR_NF10, 0x1D },
538*4882a593Smuzhiyun { STV090x_GAINLLR_NF11, 0x1B },
539*4882a593Smuzhiyun { STV090x_GAINLLR_NF12, 0x20 },
540*4882a593Smuzhiyun { STV090x_GAINLLR_NF13, 0x20 },
541*4882a593Smuzhiyun { STV090x_GAINLLR_NF14, 0x20 },
542*4882a593Smuzhiyun { STV090x_GAINLLR_NF15, 0x20 },
543*4882a593Smuzhiyun { STV090x_GAINLLR_NF16, 0x20 },
544*4882a593Smuzhiyun { STV090x_GAINLLR_NF17, 0x21 },
545*4882a593Smuzhiyun };
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun static struct stv090x_reg stv0903_cut20_val[] = {
548*4882a593Smuzhiyun { STV090x_P1_DMDCFG3, 0xe8 },
549*4882a593Smuzhiyun { STV090x_P1_DMDCFG4, 0x10 },
550*4882a593Smuzhiyun { STV090x_P1_CARFREQ, 0x38 },
551*4882a593Smuzhiyun { STV090x_P1_CARHDR, 0x20 },
552*4882a593Smuzhiyun { STV090x_P1_KREFTMG, 0x5a },
553*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF7, 0x06 },
554*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF6, 0x00 },
555*4882a593Smuzhiyun { STV090x_P1_SMAPCOEF5, 0x04 },
556*4882a593Smuzhiyun { STV090x_P1_NOSCFG, 0x0c },
557*4882a593Smuzhiyun { STV090x_GAINLLR_NF4, 0x21 },
558*4882a593Smuzhiyun { STV090x_GAINLLR_NF5, 0x21 },
559*4882a593Smuzhiyun { STV090x_GAINLLR_NF6, 0x20 },
560*4882a593Smuzhiyun { STV090x_GAINLLR_NF7, 0x1F },
561*4882a593Smuzhiyun { STV090x_GAINLLR_NF8, 0x1E },
562*4882a593Smuzhiyun { STV090x_GAINLLR_NF9, 0x1E },
563*4882a593Smuzhiyun { STV090x_GAINLLR_NF10, 0x1D },
564*4882a593Smuzhiyun { STV090x_GAINLLR_NF11, 0x1B },
565*4882a593Smuzhiyun { STV090x_GAINLLR_NF12, 0x20 },
566*4882a593Smuzhiyun { STV090x_GAINLLR_NF13, 0x20 },
567*4882a593Smuzhiyun { STV090x_GAINLLR_NF14, 0x20 },
568*4882a593Smuzhiyun { STV090x_GAINLLR_NF15, 0x20 },
569*4882a593Smuzhiyun { STV090x_GAINLLR_NF16, 0x20 },
570*4882a593Smuzhiyun { STV090x_GAINLLR_NF17, 0x21 }
571*4882a593Smuzhiyun };
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun /* Cut 2.0 Long Frame Tracking CR loop */
574*4882a593Smuzhiyun static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
575*4882a593Smuzhiyun /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
576*4882a593Smuzhiyun { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
577*4882a593Smuzhiyun { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
578*4882a593Smuzhiyun { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
579*4882a593Smuzhiyun { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
580*4882a593Smuzhiyun { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
581*4882a593Smuzhiyun { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
582*4882a593Smuzhiyun { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
583*4882a593Smuzhiyun { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
584*4882a593Smuzhiyun { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
585*4882a593Smuzhiyun { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
586*4882a593Smuzhiyun { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
587*4882a593Smuzhiyun { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
588*4882a593Smuzhiyun { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
589*4882a593Smuzhiyun { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
590*4882a593Smuzhiyun };
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun /* Cut 3.0 Long Frame Tracking CR loop */
593*4882a593Smuzhiyun static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
594*4882a593Smuzhiyun /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
595*4882a593Smuzhiyun { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
596*4882a593Smuzhiyun { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
597*4882a593Smuzhiyun { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
598*4882a593Smuzhiyun { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
599*4882a593Smuzhiyun { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
600*4882a593Smuzhiyun { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
601*4882a593Smuzhiyun { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
602*4882a593Smuzhiyun { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
603*4882a593Smuzhiyun { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
604*4882a593Smuzhiyun { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
605*4882a593Smuzhiyun { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
606*4882a593Smuzhiyun { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
607*4882a593Smuzhiyun { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
608*4882a593Smuzhiyun { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
609*4882a593Smuzhiyun };
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun /* Cut 2.0 Long Frame Tracking CR Loop */
612*4882a593Smuzhiyun static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
613*4882a593Smuzhiyun /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
614*4882a593Smuzhiyun { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
615*4882a593Smuzhiyun { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
616*4882a593Smuzhiyun { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
617*4882a593Smuzhiyun { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
618*4882a593Smuzhiyun { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
619*4882a593Smuzhiyun { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
620*4882a593Smuzhiyun { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
621*4882a593Smuzhiyun { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
622*4882a593Smuzhiyun { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
623*4882a593Smuzhiyun { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
624*4882a593Smuzhiyun { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
625*4882a593Smuzhiyun };
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun /* Cut 3.0 Long Frame Tracking CR Loop */
628*4882a593Smuzhiyun static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
629*4882a593Smuzhiyun /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
630*4882a593Smuzhiyun { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
631*4882a593Smuzhiyun { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
632*4882a593Smuzhiyun { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
633*4882a593Smuzhiyun { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
634*4882a593Smuzhiyun { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
635*4882a593Smuzhiyun { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
636*4882a593Smuzhiyun { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
637*4882a593Smuzhiyun { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
638*4882a593Smuzhiyun { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
639*4882a593Smuzhiyun { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
640*4882a593Smuzhiyun { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
641*4882a593Smuzhiyun };
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
644*4882a593Smuzhiyun /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
645*4882a593Smuzhiyun { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
646*4882a593Smuzhiyun { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
647*4882a593Smuzhiyun { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
648*4882a593Smuzhiyun };
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
651*4882a593Smuzhiyun /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
652*4882a593Smuzhiyun { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
653*4882a593Smuzhiyun { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
654*4882a593Smuzhiyun { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
655*4882a593Smuzhiyun };
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun /* Cut 2.0 Short Frame Tracking CR Loop */
658*4882a593Smuzhiyun static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
659*4882a593Smuzhiyun /* MODCOD 2M 5M 10M 20M 30M */
660*4882a593Smuzhiyun { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
661*4882a593Smuzhiyun { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
662*4882a593Smuzhiyun { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
663*4882a593Smuzhiyun { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
664*4882a593Smuzhiyun };
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun /* Cut 3.0 Short Frame Tracking CR Loop */
667*4882a593Smuzhiyun static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
668*4882a593Smuzhiyun /* MODCOD 2M 5M 10M 20M 30M */
669*4882a593Smuzhiyun { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
670*4882a593Smuzhiyun { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
671*4882a593Smuzhiyun { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
672*4882a593Smuzhiyun { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
673*4882a593Smuzhiyun };
674*4882a593Smuzhiyun
comp2(s32 __x,s32 __width)675*4882a593Smuzhiyun static inline s32 comp2(s32 __x, s32 __width)
676*4882a593Smuzhiyun {
677*4882a593Smuzhiyun if (__width == 32)
678*4882a593Smuzhiyun return __x;
679*4882a593Smuzhiyun else
680*4882a593Smuzhiyun return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun
stv090x_read_reg(struct stv090x_state * state,unsigned int reg)683*4882a593Smuzhiyun static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun const struct stv090x_config *config = state->config;
686*4882a593Smuzhiyun int ret;
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun u8 b0[] = { reg >> 8, reg & 0xff };
689*4882a593Smuzhiyun u8 buf;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun struct i2c_msg msg[] = {
692*4882a593Smuzhiyun { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
693*4882a593Smuzhiyun { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
694*4882a593Smuzhiyun };
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun ret = i2c_transfer(state->i2c, msg, 2);
697*4882a593Smuzhiyun if (ret != 2) {
698*4882a593Smuzhiyun if (ret != -ERESTARTSYS)
699*4882a593Smuzhiyun dprintk(FE_ERROR, 1,
700*4882a593Smuzhiyun "Read error, Reg=[0x%02x], Status=%d",
701*4882a593Smuzhiyun reg, ret);
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun return ret < 0 ? ret : -EREMOTEIO;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun if (unlikely(*state->verbose >= FE_DEBUGREG))
706*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
707*4882a593Smuzhiyun reg, buf);
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun return (unsigned int) buf;
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun
stv090x_write_regs(struct stv090x_state * state,unsigned int reg,u8 * data,u32 count)712*4882a593Smuzhiyun static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
713*4882a593Smuzhiyun {
714*4882a593Smuzhiyun const struct stv090x_config *config = state->config;
715*4882a593Smuzhiyun int ret;
716*4882a593Smuzhiyun u8 buf[MAX_XFER_SIZE];
717*4882a593Smuzhiyun struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun if (2 + count > sizeof(buf)) {
720*4882a593Smuzhiyun printk(KERN_WARNING
721*4882a593Smuzhiyun "%s: i2c wr reg=%04x: len=%d is too big!\n",
722*4882a593Smuzhiyun KBUILD_MODNAME, reg, count);
723*4882a593Smuzhiyun return -EINVAL;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun buf[0] = reg >> 8;
727*4882a593Smuzhiyun buf[1] = reg & 0xff;
728*4882a593Smuzhiyun memcpy(&buf[2], data, count);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun dprintk(FE_DEBUGREG, 1, "%s [0x%04x]: %*ph",
731*4882a593Smuzhiyun __func__, reg, count, data);
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun ret = i2c_transfer(state->i2c, &i2c_msg, 1);
734*4882a593Smuzhiyun if (ret != 1) {
735*4882a593Smuzhiyun if (ret != -ERESTARTSYS)
736*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
737*4882a593Smuzhiyun reg, data[0], count, ret);
738*4882a593Smuzhiyun return ret < 0 ? ret : -EREMOTEIO;
739*4882a593Smuzhiyun }
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun return 0;
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun
stv090x_write_reg(struct stv090x_state * state,unsigned int reg,u8 data)744*4882a593Smuzhiyun static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun return stv090x_write_regs(state, reg, &tmp, 1);
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun
stv090x_i2c_gate_ctrl(struct stv090x_state * state,int enable)751*4882a593Smuzhiyun static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
752*4882a593Smuzhiyun {
753*4882a593Smuzhiyun u32 reg;
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun /*
756*4882a593Smuzhiyun * NOTE! A lock is used as a FSM to control the state in which
757*4882a593Smuzhiyun * access is serialized between two tuners on the same demod.
758*4882a593Smuzhiyun * This has nothing to do with a lock to protect a critical section
759*4882a593Smuzhiyun * which may in some other cases be confused with protecting I/O
760*4882a593Smuzhiyun * access to the demodulator gate.
761*4882a593Smuzhiyun * In case of any error, the lock is unlocked and exit within the
762*4882a593Smuzhiyun * relevant operations themselves.
763*4882a593Smuzhiyun */
764*4882a593Smuzhiyun if (enable) {
765*4882a593Smuzhiyun if (state->config->tuner_i2c_lock)
766*4882a593Smuzhiyun state->config->tuner_i2c_lock(&state->frontend, 1);
767*4882a593Smuzhiyun else
768*4882a593Smuzhiyun mutex_lock(&state->internal->tuner_lock);
769*4882a593Smuzhiyun }
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, I2CRPT);
772*4882a593Smuzhiyun if (enable) {
773*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Enable Gate");
774*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
775*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
776*4882a593Smuzhiyun goto err;
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun } else {
779*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Disable Gate");
780*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
781*4882a593Smuzhiyun if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
782*4882a593Smuzhiyun goto err;
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun if (!enable) {
786*4882a593Smuzhiyun if (state->config->tuner_i2c_lock)
787*4882a593Smuzhiyun state->config->tuner_i2c_lock(&state->frontend, 0);
788*4882a593Smuzhiyun else
789*4882a593Smuzhiyun mutex_unlock(&state->internal->tuner_lock);
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun return 0;
793*4882a593Smuzhiyun err:
794*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
795*4882a593Smuzhiyun if (state->config->tuner_i2c_lock)
796*4882a593Smuzhiyun state->config->tuner_i2c_lock(&state->frontend, 0);
797*4882a593Smuzhiyun else
798*4882a593Smuzhiyun mutex_unlock(&state->internal->tuner_lock);
799*4882a593Smuzhiyun return -1;
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun
stv090x_get_lock_tmg(struct stv090x_state * state)802*4882a593Smuzhiyun static void stv090x_get_lock_tmg(struct stv090x_state *state)
803*4882a593Smuzhiyun {
804*4882a593Smuzhiyun switch (state->algo) {
805*4882a593Smuzhiyun case STV090x_BLIND_SEARCH:
806*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Blind Search");
807*4882a593Smuzhiyun if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
808*4882a593Smuzhiyun state->DemodTimeout = 1500;
809*4882a593Smuzhiyun state->FecTimeout = 400;
810*4882a593Smuzhiyun } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
811*4882a593Smuzhiyun state->DemodTimeout = 1000;
812*4882a593Smuzhiyun state->FecTimeout = 300;
813*4882a593Smuzhiyun } else { /*SR >20Msps*/
814*4882a593Smuzhiyun state->DemodTimeout = 700;
815*4882a593Smuzhiyun state->FecTimeout = 100;
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun break;
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun case STV090x_COLD_SEARCH:
820*4882a593Smuzhiyun case STV090x_WARM_SEARCH:
821*4882a593Smuzhiyun default:
822*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Normal Search");
823*4882a593Smuzhiyun if (state->srate <= 1000000) { /*SR <=1Msps*/
824*4882a593Smuzhiyun state->DemodTimeout = 4500;
825*4882a593Smuzhiyun state->FecTimeout = 1700;
826*4882a593Smuzhiyun } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
827*4882a593Smuzhiyun state->DemodTimeout = 2500;
828*4882a593Smuzhiyun state->FecTimeout = 1100;
829*4882a593Smuzhiyun } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
830*4882a593Smuzhiyun state->DemodTimeout = 1000;
831*4882a593Smuzhiyun state->FecTimeout = 550;
832*4882a593Smuzhiyun } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
833*4882a593Smuzhiyun state->DemodTimeout = 700;
834*4882a593Smuzhiyun state->FecTimeout = 250;
835*4882a593Smuzhiyun } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
836*4882a593Smuzhiyun state->DemodTimeout = 400;
837*4882a593Smuzhiyun state->FecTimeout = 130;
838*4882a593Smuzhiyun } else { /*SR >20Msps*/
839*4882a593Smuzhiyun state->DemodTimeout = 300;
840*4882a593Smuzhiyun state->FecTimeout = 100;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun break;
843*4882a593Smuzhiyun }
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun if (state->algo == STV090x_WARM_SEARCH)
846*4882a593Smuzhiyun state->DemodTimeout /= 2;
847*4882a593Smuzhiyun }
848*4882a593Smuzhiyun
stv090x_set_srate(struct stv090x_state * state,u32 srate)849*4882a593Smuzhiyun static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
850*4882a593Smuzhiyun {
851*4882a593Smuzhiyun u32 sym;
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun if (srate > 60000000) {
854*4882a593Smuzhiyun sym = (srate << 4); /* SR * 2^16 / master_clk */
855*4882a593Smuzhiyun sym /= (state->internal->mclk >> 12);
856*4882a593Smuzhiyun } else if (srate > 6000000) {
857*4882a593Smuzhiyun sym = (srate << 6);
858*4882a593Smuzhiyun sym /= (state->internal->mclk >> 10);
859*4882a593Smuzhiyun } else {
860*4882a593Smuzhiyun sym = (srate << 9);
861*4882a593Smuzhiyun sym /= (state->internal->mclk >> 7);
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
865*4882a593Smuzhiyun goto err;
866*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
867*4882a593Smuzhiyun goto err;
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun return 0;
870*4882a593Smuzhiyun err:
871*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
872*4882a593Smuzhiyun return -1;
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun
stv090x_set_max_srate(struct stv090x_state * state,u32 clk,u32 srate)875*4882a593Smuzhiyun static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
876*4882a593Smuzhiyun {
877*4882a593Smuzhiyun u32 sym;
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun srate = 105 * (srate / 100);
880*4882a593Smuzhiyun if (srate > 60000000) {
881*4882a593Smuzhiyun sym = (srate << 4); /* SR * 2^16 / master_clk */
882*4882a593Smuzhiyun sym /= (state->internal->mclk >> 12);
883*4882a593Smuzhiyun } else if (srate > 6000000) {
884*4882a593Smuzhiyun sym = (srate << 6);
885*4882a593Smuzhiyun sym /= (state->internal->mclk >> 10);
886*4882a593Smuzhiyun } else {
887*4882a593Smuzhiyun sym = (srate << 9);
888*4882a593Smuzhiyun sym /= (state->internal->mclk >> 7);
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun if (sym < 0x7fff) {
892*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
893*4882a593Smuzhiyun goto err;
894*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
895*4882a593Smuzhiyun goto err;
896*4882a593Smuzhiyun } else {
897*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
898*4882a593Smuzhiyun goto err;
899*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
900*4882a593Smuzhiyun goto err;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun return 0;
904*4882a593Smuzhiyun err:
905*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
906*4882a593Smuzhiyun return -1;
907*4882a593Smuzhiyun }
908*4882a593Smuzhiyun
stv090x_set_min_srate(struct stv090x_state * state,u32 clk,u32 srate)909*4882a593Smuzhiyun static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
910*4882a593Smuzhiyun {
911*4882a593Smuzhiyun u32 sym;
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun srate = 95 * (srate / 100);
914*4882a593Smuzhiyun if (srate > 60000000) {
915*4882a593Smuzhiyun sym = (srate << 4); /* SR * 2^16 / master_clk */
916*4882a593Smuzhiyun sym /= (state->internal->mclk >> 12);
917*4882a593Smuzhiyun } else if (srate > 6000000) {
918*4882a593Smuzhiyun sym = (srate << 6);
919*4882a593Smuzhiyun sym /= (state->internal->mclk >> 10);
920*4882a593Smuzhiyun } else {
921*4882a593Smuzhiyun sym = (srate << 9);
922*4882a593Smuzhiyun sym /= (state->internal->mclk >> 7);
923*4882a593Smuzhiyun }
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
926*4882a593Smuzhiyun goto err;
927*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
928*4882a593Smuzhiyun goto err;
929*4882a593Smuzhiyun return 0;
930*4882a593Smuzhiyun err:
931*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
932*4882a593Smuzhiyun return -1;
933*4882a593Smuzhiyun }
934*4882a593Smuzhiyun
stv090x_car_width(u32 srate,enum stv090x_rolloff rolloff)935*4882a593Smuzhiyun static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
936*4882a593Smuzhiyun {
937*4882a593Smuzhiyun u32 ro;
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun switch (rolloff) {
940*4882a593Smuzhiyun case STV090x_RO_20:
941*4882a593Smuzhiyun ro = 20;
942*4882a593Smuzhiyun break;
943*4882a593Smuzhiyun case STV090x_RO_25:
944*4882a593Smuzhiyun ro = 25;
945*4882a593Smuzhiyun break;
946*4882a593Smuzhiyun case STV090x_RO_35:
947*4882a593Smuzhiyun default:
948*4882a593Smuzhiyun ro = 35;
949*4882a593Smuzhiyun break;
950*4882a593Smuzhiyun }
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun return srate + (srate * ro) / 100;
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun
stv090x_set_vit_thacq(struct stv090x_state * state)955*4882a593Smuzhiyun static int stv090x_set_vit_thacq(struct stv090x_state *state)
956*4882a593Smuzhiyun {
957*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
958*4882a593Smuzhiyun goto err;
959*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
960*4882a593Smuzhiyun goto err;
961*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
962*4882a593Smuzhiyun goto err;
963*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
964*4882a593Smuzhiyun goto err;
965*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
966*4882a593Smuzhiyun goto err;
967*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
968*4882a593Smuzhiyun goto err;
969*4882a593Smuzhiyun return 0;
970*4882a593Smuzhiyun err:
971*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
972*4882a593Smuzhiyun return -1;
973*4882a593Smuzhiyun }
974*4882a593Smuzhiyun
stv090x_set_vit_thtracq(struct stv090x_state * state)975*4882a593Smuzhiyun static int stv090x_set_vit_thtracq(struct stv090x_state *state)
976*4882a593Smuzhiyun {
977*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
978*4882a593Smuzhiyun goto err;
979*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
980*4882a593Smuzhiyun goto err;
981*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
982*4882a593Smuzhiyun goto err;
983*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
984*4882a593Smuzhiyun goto err;
985*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
986*4882a593Smuzhiyun goto err;
987*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
988*4882a593Smuzhiyun goto err;
989*4882a593Smuzhiyun return 0;
990*4882a593Smuzhiyun err:
991*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
992*4882a593Smuzhiyun return -1;
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun
stv090x_set_viterbi(struct stv090x_state * state)995*4882a593Smuzhiyun static int stv090x_set_viterbi(struct stv090x_state *state)
996*4882a593Smuzhiyun {
997*4882a593Smuzhiyun switch (state->search_mode) {
998*4882a593Smuzhiyun case STV090x_SEARCH_AUTO:
999*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
1000*4882a593Smuzhiyun goto err;
1001*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
1002*4882a593Smuzhiyun goto err;
1003*4882a593Smuzhiyun break;
1004*4882a593Smuzhiyun case STV090x_SEARCH_DVBS1:
1005*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
1006*4882a593Smuzhiyun goto err;
1007*4882a593Smuzhiyun switch (state->fec) {
1008*4882a593Smuzhiyun case STV090x_PR12:
1009*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1010*4882a593Smuzhiyun goto err;
1011*4882a593Smuzhiyun break;
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun case STV090x_PR23:
1014*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1015*4882a593Smuzhiyun goto err;
1016*4882a593Smuzhiyun break;
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun case STV090x_PR34:
1019*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
1020*4882a593Smuzhiyun goto err;
1021*4882a593Smuzhiyun break;
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun case STV090x_PR56:
1024*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
1025*4882a593Smuzhiyun goto err;
1026*4882a593Smuzhiyun break;
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun case STV090x_PR78:
1029*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
1030*4882a593Smuzhiyun goto err;
1031*4882a593Smuzhiyun break;
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun default:
1034*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
1035*4882a593Smuzhiyun goto err;
1036*4882a593Smuzhiyun break;
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun break;
1039*4882a593Smuzhiyun case STV090x_SEARCH_DSS:
1040*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
1041*4882a593Smuzhiyun goto err;
1042*4882a593Smuzhiyun switch (state->fec) {
1043*4882a593Smuzhiyun case STV090x_PR12:
1044*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1045*4882a593Smuzhiyun goto err;
1046*4882a593Smuzhiyun break;
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun case STV090x_PR23:
1049*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1050*4882a593Smuzhiyun goto err;
1051*4882a593Smuzhiyun break;
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun case STV090x_PR67:
1054*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
1055*4882a593Smuzhiyun goto err;
1056*4882a593Smuzhiyun break;
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun default:
1059*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
1060*4882a593Smuzhiyun goto err;
1061*4882a593Smuzhiyun break;
1062*4882a593Smuzhiyun }
1063*4882a593Smuzhiyun break;
1064*4882a593Smuzhiyun default:
1065*4882a593Smuzhiyun break;
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun return 0;
1068*4882a593Smuzhiyun err:
1069*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1070*4882a593Smuzhiyun return -1;
1071*4882a593Smuzhiyun }
1072*4882a593Smuzhiyun
stv090x_stop_modcod(struct stv090x_state * state)1073*4882a593Smuzhiyun static int stv090x_stop_modcod(struct stv090x_state *state)
1074*4882a593Smuzhiyun {
1075*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1076*4882a593Smuzhiyun goto err;
1077*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
1078*4882a593Smuzhiyun goto err;
1079*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
1080*4882a593Smuzhiyun goto err;
1081*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
1082*4882a593Smuzhiyun goto err;
1083*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
1084*4882a593Smuzhiyun goto err;
1085*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
1086*4882a593Smuzhiyun goto err;
1087*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
1088*4882a593Smuzhiyun goto err;
1089*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
1090*4882a593Smuzhiyun goto err;
1091*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
1092*4882a593Smuzhiyun goto err;
1093*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
1094*4882a593Smuzhiyun goto err;
1095*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1096*4882a593Smuzhiyun goto err;
1097*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1098*4882a593Smuzhiyun goto err;
1099*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1100*4882a593Smuzhiyun goto err;
1101*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1102*4882a593Smuzhiyun goto err;
1103*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1104*4882a593Smuzhiyun goto err;
1105*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1106*4882a593Smuzhiyun goto err;
1107*4882a593Smuzhiyun return 0;
1108*4882a593Smuzhiyun err:
1109*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1110*4882a593Smuzhiyun return -1;
1111*4882a593Smuzhiyun }
1112*4882a593Smuzhiyun
stv090x_activate_modcod(struct stv090x_state * state)1113*4882a593Smuzhiyun static int stv090x_activate_modcod(struct stv090x_state *state)
1114*4882a593Smuzhiyun {
1115*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1116*4882a593Smuzhiyun goto err;
1117*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1118*4882a593Smuzhiyun goto err;
1119*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1120*4882a593Smuzhiyun goto err;
1121*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1122*4882a593Smuzhiyun goto err;
1123*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1124*4882a593Smuzhiyun goto err;
1125*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1126*4882a593Smuzhiyun goto err;
1127*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1128*4882a593Smuzhiyun goto err;
1129*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1130*4882a593Smuzhiyun goto err;
1131*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1132*4882a593Smuzhiyun goto err;
1133*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1134*4882a593Smuzhiyun goto err;
1135*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1136*4882a593Smuzhiyun goto err;
1137*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1138*4882a593Smuzhiyun goto err;
1139*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1140*4882a593Smuzhiyun goto err;
1141*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1142*4882a593Smuzhiyun goto err;
1143*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1144*4882a593Smuzhiyun goto err;
1145*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1146*4882a593Smuzhiyun goto err;
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun return 0;
1149*4882a593Smuzhiyun err:
1150*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1151*4882a593Smuzhiyun return -1;
1152*4882a593Smuzhiyun }
1153*4882a593Smuzhiyun
stv090x_activate_modcod_single(struct stv090x_state * state)1154*4882a593Smuzhiyun static int stv090x_activate_modcod_single(struct stv090x_state *state)
1155*4882a593Smuzhiyun {
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1158*4882a593Smuzhiyun goto err;
1159*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1160*4882a593Smuzhiyun goto err;
1161*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1162*4882a593Smuzhiyun goto err;
1163*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1164*4882a593Smuzhiyun goto err;
1165*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1166*4882a593Smuzhiyun goto err;
1167*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1168*4882a593Smuzhiyun goto err;
1169*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1170*4882a593Smuzhiyun goto err;
1171*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1172*4882a593Smuzhiyun goto err;
1173*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1174*4882a593Smuzhiyun goto err;
1175*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1176*4882a593Smuzhiyun goto err;
1177*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1178*4882a593Smuzhiyun goto err;
1179*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1180*4882a593Smuzhiyun goto err;
1181*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1182*4882a593Smuzhiyun goto err;
1183*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1184*4882a593Smuzhiyun goto err;
1185*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1186*4882a593Smuzhiyun goto err;
1187*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1188*4882a593Smuzhiyun goto err;
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun return 0;
1191*4882a593Smuzhiyun
1192*4882a593Smuzhiyun err:
1193*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1194*4882a593Smuzhiyun return -1;
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun
stv090x_vitclk_ctl(struct stv090x_state * state,int enable)1197*4882a593Smuzhiyun static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1198*4882a593Smuzhiyun {
1199*4882a593Smuzhiyun u32 reg;
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun switch (state->demod) {
1202*4882a593Smuzhiyun case STV090x_DEMODULATOR_0:
1203*4882a593Smuzhiyun mutex_lock(&state->internal->demod_lock);
1204*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1205*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1206*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1207*4882a593Smuzhiyun goto err;
1208*4882a593Smuzhiyun mutex_unlock(&state->internal->demod_lock);
1209*4882a593Smuzhiyun break;
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun case STV090x_DEMODULATOR_1:
1212*4882a593Smuzhiyun mutex_lock(&state->internal->demod_lock);
1213*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1214*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1215*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1216*4882a593Smuzhiyun goto err;
1217*4882a593Smuzhiyun mutex_unlock(&state->internal->demod_lock);
1218*4882a593Smuzhiyun break;
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun default:
1221*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "Wrong demodulator!");
1222*4882a593Smuzhiyun break;
1223*4882a593Smuzhiyun }
1224*4882a593Smuzhiyun return 0;
1225*4882a593Smuzhiyun err:
1226*4882a593Smuzhiyun mutex_unlock(&state->internal->demod_lock);
1227*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1228*4882a593Smuzhiyun return -1;
1229*4882a593Smuzhiyun }
1230*4882a593Smuzhiyun
stv090x_dvbs_track_crl(struct stv090x_state * state)1231*4882a593Smuzhiyun static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1232*4882a593Smuzhiyun {
1233*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x30) {
1234*4882a593Smuzhiyun /* Set ACLC BCLC optimised value vs SR */
1235*4882a593Smuzhiyun if (state->srate >= 15000000) {
1236*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1237*4882a593Smuzhiyun goto err;
1238*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1239*4882a593Smuzhiyun goto err;
1240*4882a593Smuzhiyun } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1241*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1242*4882a593Smuzhiyun goto err;
1243*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1244*4882a593Smuzhiyun goto err;
1245*4882a593Smuzhiyun } else if (state->srate < 7000000) {
1246*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1247*4882a593Smuzhiyun goto err;
1248*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1249*4882a593Smuzhiyun goto err;
1250*4882a593Smuzhiyun }
1251*4882a593Smuzhiyun
1252*4882a593Smuzhiyun } else {
1253*4882a593Smuzhiyun /* Cut 2.0 */
1254*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1255*4882a593Smuzhiyun goto err;
1256*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1257*4882a593Smuzhiyun goto err;
1258*4882a593Smuzhiyun }
1259*4882a593Smuzhiyun return 0;
1260*4882a593Smuzhiyun err:
1261*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1262*4882a593Smuzhiyun return -1;
1263*4882a593Smuzhiyun }
1264*4882a593Smuzhiyun
stv090x_delivery_search(struct stv090x_state * state)1265*4882a593Smuzhiyun static int stv090x_delivery_search(struct stv090x_state *state)
1266*4882a593Smuzhiyun {
1267*4882a593Smuzhiyun u32 reg;
1268*4882a593Smuzhiyun
1269*4882a593Smuzhiyun switch (state->search_mode) {
1270*4882a593Smuzhiyun case STV090x_SEARCH_DVBS1:
1271*4882a593Smuzhiyun case STV090x_SEARCH_DSS:
1272*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1273*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1274*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1275*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1276*4882a593Smuzhiyun goto err;
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun /* Activate Viterbi decoder in legacy search,
1279*4882a593Smuzhiyun * do not use FRESVIT1, might impact VITERBI2
1280*4882a593Smuzhiyun */
1281*4882a593Smuzhiyun if (stv090x_vitclk_ctl(state, 0) < 0)
1282*4882a593Smuzhiyun goto err;
1283*4882a593Smuzhiyun
1284*4882a593Smuzhiyun if (stv090x_dvbs_track_crl(state) < 0)
1285*4882a593Smuzhiyun goto err;
1286*4882a593Smuzhiyun
1287*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1288*4882a593Smuzhiyun goto err;
1289*4882a593Smuzhiyun
1290*4882a593Smuzhiyun if (stv090x_set_vit_thacq(state) < 0)
1291*4882a593Smuzhiyun goto err;
1292*4882a593Smuzhiyun if (stv090x_set_viterbi(state) < 0)
1293*4882a593Smuzhiyun goto err;
1294*4882a593Smuzhiyun break;
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun case STV090x_SEARCH_DVBS2:
1297*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1298*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1299*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1300*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1301*4882a593Smuzhiyun goto err;
1302*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1303*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1304*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1305*4882a593Smuzhiyun goto err;
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun if (stv090x_vitclk_ctl(state, 1) < 0)
1308*4882a593Smuzhiyun goto err;
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1311*4882a593Smuzhiyun goto err;
1312*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1313*4882a593Smuzhiyun goto err;
1314*4882a593Smuzhiyun
1315*4882a593Smuzhiyun if (state->internal->dev_ver <= 0x20) {
1316*4882a593Smuzhiyun /* enable S2 carrier loop */
1317*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1318*4882a593Smuzhiyun goto err;
1319*4882a593Smuzhiyun } else {
1320*4882a593Smuzhiyun /* > Cut 3: Stop carrier 3 */
1321*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1322*4882a593Smuzhiyun goto err;
1323*4882a593Smuzhiyun }
1324*4882a593Smuzhiyun
1325*4882a593Smuzhiyun if (state->demod_mode != STV090x_SINGLE) {
1326*4882a593Smuzhiyun /* Cut 2: enable link during search */
1327*4882a593Smuzhiyun if (stv090x_activate_modcod(state) < 0)
1328*4882a593Smuzhiyun goto err;
1329*4882a593Smuzhiyun } else {
1330*4882a593Smuzhiyun /* Single demodulator
1331*4882a593Smuzhiyun * Authorize SHORT and LONG frames,
1332*4882a593Smuzhiyun * QPSK, 8PSK, 16APSK and 32APSK
1333*4882a593Smuzhiyun */
1334*4882a593Smuzhiyun if (stv090x_activate_modcod_single(state) < 0)
1335*4882a593Smuzhiyun goto err;
1336*4882a593Smuzhiyun }
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun if (stv090x_set_vit_thtracq(state) < 0)
1339*4882a593Smuzhiyun goto err;
1340*4882a593Smuzhiyun break;
1341*4882a593Smuzhiyun
1342*4882a593Smuzhiyun case STV090x_SEARCH_AUTO:
1343*4882a593Smuzhiyun default:
1344*4882a593Smuzhiyun /* enable DVB-S2 and DVB-S2 in Auto MODE */
1345*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1346*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1347*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1348*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1349*4882a593Smuzhiyun goto err;
1350*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1351*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1352*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1353*4882a593Smuzhiyun goto err;
1354*4882a593Smuzhiyun
1355*4882a593Smuzhiyun if (stv090x_vitclk_ctl(state, 0) < 0)
1356*4882a593Smuzhiyun goto err;
1357*4882a593Smuzhiyun
1358*4882a593Smuzhiyun if (stv090x_dvbs_track_crl(state) < 0)
1359*4882a593Smuzhiyun goto err;
1360*4882a593Smuzhiyun
1361*4882a593Smuzhiyun if (state->internal->dev_ver <= 0x20) {
1362*4882a593Smuzhiyun /* enable S2 carrier loop */
1363*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1364*4882a593Smuzhiyun goto err;
1365*4882a593Smuzhiyun } else {
1366*4882a593Smuzhiyun /* > Cut 3: Stop carrier 3 */
1367*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1368*4882a593Smuzhiyun goto err;
1369*4882a593Smuzhiyun }
1370*4882a593Smuzhiyun
1371*4882a593Smuzhiyun if (state->demod_mode != STV090x_SINGLE) {
1372*4882a593Smuzhiyun /* Cut 2: enable link during search */
1373*4882a593Smuzhiyun if (stv090x_activate_modcod(state) < 0)
1374*4882a593Smuzhiyun goto err;
1375*4882a593Smuzhiyun } else {
1376*4882a593Smuzhiyun /* Single demodulator
1377*4882a593Smuzhiyun * Authorize SHORT and LONG frames,
1378*4882a593Smuzhiyun * QPSK, 8PSK, 16APSK and 32APSK
1379*4882a593Smuzhiyun */
1380*4882a593Smuzhiyun if (stv090x_activate_modcod_single(state) < 0)
1381*4882a593Smuzhiyun goto err;
1382*4882a593Smuzhiyun }
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun if (stv090x_set_vit_thacq(state) < 0)
1385*4882a593Smuzhiyun goto err;
1386*4882a593Smuzhiyun
1387*4882a593Smuzhiyun if (stv090x_set_viterbi(state) < 0)
1388*4882a593Smuzhiyun goto err;
1389*4882a593Smuzhiyun break;
1390*4882a593Smuzhiyun }
1391*4882a593Smuzhiyun return 0;
1392*4882a593Smuzhiyun err:
1393*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1394*4882a593Smuzhiyun return -1;
1395*4882a593Smuzhiyun }
1396*4882a593Smuzhiyun
stv090x_start_search(struct stv090x_state * state)1397*4882a593Smuzhiyun static int stv090x_start_search(struct stv090x_state *state)
1398*4882a593Smuzhiyun {
1399*4882a593Smuzhiyun u32 reg, freq_abs;
1400*4882a593Smuzhiyun s16 freq;
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun /* Reset demodulator */
1403*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDISTATE);
1404*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1405*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1406*4882a593Smuzhiyun goto err;
1407*4882a593Smuzhiyun
1408*4882a593Smuzhiyun if (state->internal->dev_ver <= 0x20) {
1409*4882a593Smuzhiyun if (state->srate <= 5000000) {
1410*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1411*4882a593Smuzhiyun goto err;
1412*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1413*4882a593Smuzhiyun goto err;
1414*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
1415*4882a593Smuzhiyun goto err;
1416*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1417*4882a593Smuzhiyun goto err;
1418*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1419*4882a593Smuzhiyun goto err;
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun /*enlarge the timing bandwidth for Low SR*/
1422*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1423*4882a593Smuzhiyun goto err;
1424*4882a593Smuzhiyun } else {
1425*4882a593Smuzhiyun /* If the symbol rate is >5 Msps
1426*4882a593Smuzhiyun Set The carrier search up and low to auto mode */
1427*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1428*4882a593Smuzhiyun goto err;
1429*4882a593Smuzhiyun /*reduce the timing bandwidth for high SR*/
1430*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1431*4882a593Smuzhiyun goto err;
1432*4882a593Smuzhiyun }
1433*4882a593Smuzhiyun } else {
1434*4882a593Smuzhiyun /* >= Cut 3 */
1435*4882a593Smuzhiyun if (state->srate <= 5000000) {
1436*4882a593Smuzhiyun /* enlarge the timing bandwidth for Low SR */
1437*4882a593Smuzhiyun STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1438*4882a593Smuzhiyun } else {
1439*4882a593Smuzhiyun /* reduce timing bandwidth for high SR */
1440*4882a593Smuzhiyun STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1441*4882a593Smuzhiyun }
1442*4882a593Smuzhiyun
1443*4882a593Smuzhiyun /* Set CFR min and max to manual mode */
1444*4882a593Smuzhiyun STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1445*4882a593Smuzhiyun
1446*4882a593Smuzhiyun if (state->algo == STV090x_WARM_SEARCH) {
1447*4882a593Smuzhiyun /* WARM Start
1448*4882a593Smuzhiyun * CFR min = -1MHz,
1449*4882a593Smuzhiyun * CFR max = +1MHz
1450*4882a593Smuzhiyun */
1451*4882a593Smuzhiyun freq_abs = 1000 << 16;
1452*4882a593Smuzhiyun freq_abs /= (state->internal->mclk / 1000);
1453*4882a593Smuzhiyun freq = (s16) freq_abs;
1454*4882a593Smuzhiyun } else {
1455*4882a593Smuzhiyun /* COLD Start
1456*4882a593Smuzhiyun * CFR min =- (SearchRange / 2 + 600KHz)
1457*4882a593Smuzhiyun * CFR max = +(SearchRange / 2 + 600KHz)
1458*4882a593Smuzhiyun * (600KHz for the tuner step size)
1459*4882a593Smuzhiyun */
1460*4882a593Smuzhiyun freq_abs = (state->search_range / 2000) + 600;
1461*4882a593Smuzhiyun freq_abs = freq_abs << 16;
1462*4882a593Smuzhiyun freq_abs /= (state->internal->mclk / 1000);
1463*4882a593Smuzhiyun freq = (s16) freq_abs;
1464*4882a593Smuzhiyun }
1465*4882a593Smuzhiyun
1466*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
1467*4882a593Smuzhiyun goto err;
1468*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
1469*4882a593Smuzhiyun goto err;
1470*4882a593Smuzhiyun
1471*4882a593Smuzhiyun freq *= -1;
1472*4882a593Smuzhiyun
1473*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
1474*4882a593Smuzhiyun goto err;
1475*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
1476*4882a593Smuzhiyun goto err;
1477*4882a593Smuzhiyun
1478*4882a593Smuzhiyun }
1479*4882a593Smuzhiyun
1480*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1481*4882a593Smuzhiyun goto err;
1482*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1483*4882a593Smuzhiyun goto err;
1484*4882a593Smuzhiyun
1485*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
1486*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1487*4882a593Smuzhiyun goto err;
1488*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1489*4882a593Smuzhiyun goto err;
1490*4882a593Smuzhiyun
1491*4882a593Smuzhiyun if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
1492*4882a593Smuzhiyun (state->search_mode == STV090x_SEARCH_DSS) ||
1493*4882a593Smuzhiyun (state->search_mode == STV090x_SEARCH_AUTO)) {
1494*4882a593Smuzhiyun
1495*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1496*4882a593Smuzhiyun goto err;
1497*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1498*4882a593Smuzhiyun goto err;
1499*4882a593Smuzhiyun }
1500*4882a593Smuzhiyun }
1501*4882a593Smuzhiyun
1502*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1503*4882a593Smuzhiyun goto err;
1504*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1505*4882a593Smuzhiyun goto err;
1506*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1507*4882a593Smuzhiyun goto err;
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1510*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1511*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1512*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1513*4882a593Smuzhiyun goto err;
1514*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFG2);
1515*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1516*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1517*4882a593Smuzhiyun goto err;
1518*4882a593Smuzhiyun
1519*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1520*4882a593Smuzhiyun goto err;
1521*4882a593Smuzhiyun
1522*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
1523*4882a593Smuzhiyun /*Frequency offset detector setting*/
1524*4882a593Smuzhiyun if (state->srate < 2000000) {
1525*4882a593Smuzhiyun if (state->internal->dev_ver <= 0x20) {
1526*4882a593Smuzhiyun /* Cut 2 */
1527*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1528*4882a593Smuzhiyun goto err;
1529*4882a593Smuzhiyun } else {
1530*4882a593Smuzhiyun /* Cut 3 */
1531*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1532*4882a593Smuzhiyun goto err;
1533*4882a593Smuzhiyun }
1534*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1535*4882a593Smuzhiyun goto err;
1536*4882a593Smuzhiyun } else if (state->srate < 10000000) {
1537*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1538*4882a593Smuzhiyun goto err;
1539*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1540*4882a593Smuzhiyun goto err;
1541*4882a593Smuzhiyun } else {
1542*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1543*4882a593Smuzhiyun goto err;
1544*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1545*4882a593Smuzhiyun goto err;
1546*4882a593Smuzhiyun }
1547*4882a593Smuzhiyun } else {
1548*4882a593Smuzhiyun if (state->srate < 10000000) {
1549*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1550*4882a593Smuzhiyun goto err;
1551*4882a593Smuzhiyun } else {
1552*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1553*4882a593Smuzhiyun goto err;
1554*4882a593Smuzhiyun }
1555*4882a593Smuzhiyun }
1556*4882a593Smuzhiyun
1557*4882a593Smuzhiyun switch (state->algo) {
1558*4882a593Smuzhiyun case STV090x_WARM_SEARCH:
1559*4882a593Smuzhiyun /* The symbol rate and the exact
1560*4882a593Smuzhiyun * carrier Frequency are known
1561*4882a593Smuzhiyun */
1562*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1563*4882a593Smuzhiyun goto err;
1564*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1565*4882a593Smuzhiyun goto err;
1566*4882a593Smuzhiyun break;
1567*4882a593Smuzhiyun
1568*4882a593Smuzhiyun case STV090x_COLD_SEARCH:
1569*4882a593Smuzhiyun /* The symbol rate is known */
1570*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1571*4882a593Smuzhiyun goto err;
1572*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1573*4882a593Smuzhiyun goto err;
1574*4882a593Smuzhiyun break;
1575*4882a593Smuzhiyun
1576*4882a593Smuzhiyun default:
1577*4882a593Smuzhiyun break;
1578*4882a593Smuzhiyun }
1579*4882a593Smuzhiyun return 0;
1580*4882a593Smuzhiyun err:
1581*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1582*4882a593Smuzhiyun return -1;
1583*4882a593Smuzhiyun }
1584*4882a593Smuzhiyun
stv090x_get_agc2_min_level(struct stv090x_state * state)1585*4882a593Smuzhiyun static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1586*4882a593Smuzhiyun {
1587*4882a593Smuzhiyun u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
1588*4882a593Smuzhiyun s32 i, j, steps, dir;
1589*4882a593Smuzhiyun
1590*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1591*4882a593Smuzhiyun goto err;
1592*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1593*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1594*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1595*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1596*4882a593Smuzhiyun goto err;
1597*4882a593Smuzhiyun
1598*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1599*4882a593Smuzhiyun goto err;
1600*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1601*4882a593Smuzhiyun goto err;
1602*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1603*4882a593Smuzhiyun goto err;
1604*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1605*4882a593Smuzhiyun goto err;
1606*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1607*4882a593Smuzhiyun goto err;
1608*4882a593Smuzhiyun if (stv090x_set_srate(state, 1000000) < 0)
1609*4882a593Smuzhiyun goto err;
1610*4882a593Smuzhiyun
1611*4882a593Smuzhiyun steps = state->search_range / 1000000;
1612*4882a593Smuzhiyun if (steps <= 0)
1613*4882a593Smuzhiyun steps = 1;
1614*4882a593Smuzhiyun
1615*4882a593Smuzhiyun dir = 1;
1616*4882a593Smuzhiyun freq_step = (1000000 * 256) / (state->internal->mclk / 256);
1617*4882a593Smuzhiyun freq_init = 0;
1618*4882a593Smuzhiyun
1619*4882a593Smuzhiyun for (i = 0; i < steps; i++) {
1620*4882a593Smuzhiyun if (dir > 0)
1621*4882a593Smuzhiyun freq_init = freq_init + (freq_step * i);
1622*4882a593Smuzhiyun else
1623*4882a593Smuzhiyun freq_init = freq_init - (freq_step * i);
1624*4882a593Smuzhiyun
1625*4882a593Smuzhiyun dir *= -1;
1626*4882a593Smuzhiyun
1627*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1628*4882a593Smuzhiyun goto err;
1629*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1630*4882a593Smuzhiyun goto err;
1631*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1632*4882a593Smuzhiyun goto err;
1633*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1634*4882a593Smuzhiyun goto err;
1635*4882a593Smuzhiyun msleep(10);
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun agc2 = 0;
1638*4882a593Smuzhiyun for (j = 0; j < 10; j++) {
1639*4882a593Smuzhiyun agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1640*4882a593Smuzhiyun STV090x_READ_DEMOD(state, AGC2I0);
1641*4882a593Smuzhiyun }
1642*4882a593Smuzhiyun agc2 /= 10;
1643*4882a593Smuzhiyun if (agc2 < agc2_min)
1644*4882a593Smuzhiyun agc2_min = agc2;
1645*4882a593Smuzhiyun }
1646*4882a593Smuzhiyun
1647*4882a593Smuzhiyun return agc2_min;
1648*4882a593Smuzhiyun err:
1649*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1650*4882a593Smuzhiyun return -1;
1651*4882a593Smuzhiyun }
1652*4882a593Smuzhiyun
stv090x_get_srate(struct stv090x_state * state,u32 clk)1653*4882a593Smuzhiyun static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1654*4882a593Smuzhiyun {
1655*4882a593Smuzhiyun u8 r3, r2, r1, r0;
1656*4882a593Smuzhiyun s32 srate, int_1, int_2, tmp_1, tmp_2;
1657*4882a593Smuzhiyun
1658*4882a593Smuzhiyun r3 = STV090x_READ_DEMOD(state, SFR3);
1659*4882a593Smuzhiyun r2 = STV090x_READ_DEMOD(state, SFR2);
1660*4882a593Smuzhiyun r1 = STV090x_READ_DEMOD(state, SFR1);
1661*4882a593Smuzhiyun r0 = STV090x_READ_DEMOD(state, SFR0);
1662*4882a593Smuzhiyun
1663*4882a593Smuzhiyun srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1664*4882a593Smuzhiyun
1665*4882a593Smuzhiyun int_1 = clk >> 16;
1666*4882a593Smuzhiyun int_2 = srate >> 16;
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun tmp_1 = clk % 0x10000;
1669*4882a593Smuzhiyun tmp_2 = srate % 0x10000;
1670*4882a593Smuzhiyun
1671*4882a593Smuzhiyun srate = (int_1 * int_2) +
1672*4882a593Smuzhiyun ((int_1 * tmp_2) >> 16) +
1673*4882a593Smuzhiyun ((int_2 * tmp_1) >> 16);
1674*4882a593Smuzhiyun
1675*4882a593Smuzhiyun return srate;
1676*4882a593Smuzhiyun }
1677*4882a593Smuzhiyun
stv090x_srate_srch_coarse(struct stv090x_state * state)1678*4882a593Smuzhiyun static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1679*4882a593Smuzhiyun {
1680*4882a593Smuzhiyun struct dvb_frontend *fe = &state->frontend;
1681*4882a593Smuzhiyun
1682*4882a593Smuzhiyun int tmg_lock = 0, i;
1683*4882a593Smuzhiyun s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1684*4882a593Smuzhiyun u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1685*4882a593Smuzhiyun u32 agc2th;
1686*4882a593Smuzhiyun
1687*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x30)
1688*4882a593Smuzhiyun agc2th = 0x2e00;
1689*4882a593Smuzhiyun else
1690*4882a593Smuzhiyun agc2th = 0x1f00;
1691*4882a593Smuzhiyun
1692*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDISTATE);
1693*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1694*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1695*4882a593Smuzhiyun goto err;
1696*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1697*4882a593Smuzhiyun goto err;
1698*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1699*4882a593Smuzhiyun goto err;
1700*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1701*4882a593Smuzhiyun goto err;
1702*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1703*4882a593Smuzhiyun goto err;
1704*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1705*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1706*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1707*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1708*4882a593Smuzhiyun goto err;
1709*4882a593Smuzhiyun
1710*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1711*4882a593Smuzhiyun goto err;
1712*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1713*4882a593Smuzhiyun goto err;
1714*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1715*4882a593Smuzhiyun goto err;
1716*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1717*4882a593Smuzhiyun goto err;
1718*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1719*4882a593Smuzhiyun goto err;
1720*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
1721*4882a593Smuzhiyun goto err;
1722*4882a593Smuzhiyun
1723*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x30) {
1724*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
1725*4882a593Smuzhiyun goto err;
1726*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
1727*4882a593Smuzhiyun goto err;
1728*4882a593Smuzhiyun
1729*4882a593Smuzhiyun } else if (state->internal->dev_ver >= 0x20) {
1730*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1731*4882a593Smuzhiyun goto err;
1732*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1733*4882a593Smuzhiyun goto err;
1734*4882a593Smuzhiyun }
1735*4882a593Smuzhiyun
1736*4882a593Smuzhiyun if (state->srate <= 2000000)
1737*4882a593Smuzhiyun car_step = 1000;
1738*4882a593Smuzhiyun else if (state->srate <= 5000000)
1739*4882a593Smuzhiyun car_step = 2000;
1740*4882a593Smuzhiyun else if (state->srate <= 12000000)
1741*4882a593Smuzhiyun car_step = 3000;
1742*4882a593Smuzhiyun else
1743*4882a593Smuzhiyun car_step = 5000;
1744*4882a593Smuzhiyun
1745*4882a593Smuzhiyun steps = -1 + ((state->search_range / 1000) / car_step);
1746*4882a593Smuzhiyun steps /= 2;
1747*4882a593Smuzhiyun steps = (2 * steps) + 1;
1748*4882a593Smuzhiyun if (steps < 0)
1749*4882a593Smuzhiyun steps = 1;
1750*4882a593Smuzhiyun else if (steps > 10) {
1751*4882a593Smuzhiyun steps = 11;
1752*4882a593Smuzhiyun car_step = (state->search_range / 1000) / 10;
1753*4882a593Smuzhiyun }
1754*4882a593Smuzhiyun cur_step = 0;
1755*4882a593Smuzhiyun dir = 1;
1756*4882a593Smuzhiyun freq = state->frequency;
1757*4882a593Smuzhiyun
1758*4882a593Smuzhiyun while ((!tmg_lock) && (cur_step < steps)) {
1759*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1760*4882a593Smuzhiyun goto err;
1761*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1762*4882a593Smuzhiyun goto err;
1763*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1764*4882a593Smuzhiyun goto err;
1765*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1766*4882a593Smuzhiyun goto err;
1767*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1768*4882a593Smuzhiyun goto err;
1769*4882a593Smuzhiyun /* trigger acquisition */
1770*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
1771*4882a593Smuzhiyun goto err;
1772*4882a593Smuzhiyun msleep(50);
1773*4882a593Smuzhiyun for (i = 0; i < 10; i++) {
1774*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DSTATUS);
1775*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1776*4882a593Smuzhiyun tmg_cpt++;
1777*4882a593Smuzhiyun agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1778*4882a593Smuzhiyun STV090x_READ_DEMOD(state, AGC2I0);
1779*4882a593Smuzhiyun }
1780*4882a593Smuzhiyun agc2 /= 10;
1781*4882a593Smuzhiyun srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1782*4882a593Smuzhiyun cur_step++;
1783*4882a593Smuzhiyun dir *= -1;
1784*4882a593Smuzhiyun if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1785*4882a593Smuzhiyun (srate_coarse < 50000000) && (srate_coarse > 850000))
1786*4882a593Smuzhiyun tmg_lock = 1;
1787*4882a593Smuzhiyun else if (cur_step < steps) {
1788*4882a593Smuzhiyun if (dir > 0)
1789*4882a593Smuzhiyun freq += cur_step * car_step;
1790*4882a593Smuzhiyun else
1791*4882a593Smuzhiyun freq -= cur_step * car_step;
1792*4882a593Smuzhiyun
1793*4882a593Smuzhiyun /* Setup tuner */
1794*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
1795*4882a593Smuzhiyun goto err;
1796*4882a593Smuzhiyun
1797*4882a593Smuzhiyun if (state->config->tuner_set_frequency) {
1798*4882a593Smuzhiyun if (state->config->tuner_set_frequency(fe, freq) < 0)
1799*4882a593Smuzhiyun goto err_gateoff;
1800*4882a593Smuzhiyun }
1801*4882a593Smuzhiyun
1802*4882a593Smuzhiyun if (state->config->tuner_set_bandwidth) {
1803*4882a593Smuzhiyun if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
1804*4882a593Smuzhiyun goto err_gateoff;
1805*4882a593Smuzhiyun }
1806*4882a593Smuzhiyun
1807*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
1808*4882a593Smuzhiyun goto err;
1809*4882a593Smuzhiyun
1810*4882a593Smuzhiyun msleep(50);
1811*4882a593Smuzhiyun
1812*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
1813*4882a593Smuzhiyun goto err;
1814*4882a593Smuzhiyun
1815*4882a593Smuzhiyun if (state->config->tuner_get_status) {
1816*4882a593Smuzhiyun if (state->config->tuner_get_status(fe, ®) < 0)
1817*4882a593Smuzhiyun goto err_gateoff;
1818*4882a593Smuzhiyun }
1819*4882a593Smuzhiyun
1820*4882a593Smuzhiyun if (reg)
1821*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Tuner phase locked");
1822*4882a593Smuzhiyun else
1823*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Tuner unlocked");
1824*4882a593Smuzhiyun
1825*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
1826*4882a593Smuzhiyun goto err;
1827*4882a593Smuzhiyun
1828*4882a593Smuzhiyun }
1829*4882a593Smuzhiyun }
1830*4882a593Smuzhiyun if (!tmg_lock)
1831*4882a593Smuzhiyun srate_coarse = 0;
1832*4882a593Smuzhiyun else
1833*4882a593Smuzhiyun srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1834*4882a593Smuzhiyun
1835*4882a593Smuzhiyun return srate_coarse;
1836*4882a593Smuzhiyun
1837*4882a593Smuzhiyun err_gateoff:
1838*4882a593Smuzhiyun stv090x_i2c_gate_ctrl(state, 0);
1839*4882a593Smuzhiyun err:
1840*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1841*4882a593Smuzhiyun return -1;
1842*4882a593Smuzhiyun }
1843*4882a593Smuzhiyun
stv090x_srate_srch_fine(struct stv090x_state * state)1844*4882a593Smuzhiyun static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1845*4882a593Smuzhiyun {
1846*4882a593Smuzhiyun u32 srate_coarse, freq_coarse, sym, reg;
1847*4882a593Smuzhiyun
1848*4882a593Smuzhiyun srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1849*4882a593Smuzhiyun freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1850*4882a593Smuzhiyun freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1851*4882a593Smuzhiyun sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1852*4882a593Smuzhiyun
1853*4882a593Smuzhiyun if (sym < state->srate)
1854*4882a593Smuzhiyun srate_coarse = 0;
1855*4882a593Smuzhiyun else {
1856*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1857*4882a593Smuzhiyun goto err;
1858*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
1859*4882a593Smuzhiyun goto err;
1860*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1861*4882a593Smuzhiyun goto err;
1862*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1863*4882a593Smuzhiyun goto err;
1864*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1865*4882a593Smuzhiyun goto err;
1866*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1867*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1868*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1869*4882a593Smuzhiyun goto err;
1870*4882a593Smuzhiyun
1871*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1872*4882a593Smuzhiyun goto err;
1873*4882a593Smuzhiyun
1874*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x30) {
1875*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
1876*4882a593Smuzhiyun goto err;
1877*4882a593Smuzhiyun } else if (state->internal->dev_ver >= 0x20) {
1878*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1879*4882a593Smuzhiyun goto err;
1880*4882a593Smuzhiyun }
1881*4882a593Smuzhiyun
1882*4882a593Smuzhiyun if (srate_coarse > 3000000) {
1883*4882a593Smuzhiyun sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1884*4882a593Smuzhiyun sym = (sym / 1000) * 65536;
1885*4882a593Smuzhiyun sym /= (state->internal->mclk / 1000);
1886*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1887*4882a593Smuzhiyun goto err;
1888*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1889*4882a593Smuzhiyun goto err;
1890*4882a593Smuzhiyun sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1891*4882a593Smuzhiyun sym = (sym / 1000) * 65536;
1892*4882a593Smuzhiyun sym /= (state->internal->mclk / 1000);
1893*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1894*4882a593Smuzhiyun goto err;
1895*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1896*4882a593Smuzhiyun goto err;
1897*4882a593Smuzhiyun sym = (srate_coarse / 1000) * 65536;
1898*4882a593Smuzhiyun sym /= (state->internal->mclk / 1000);
1899*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1900*4882a593Smuzhiyun goto err;
1901*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1902*4882a593Smuzhiyun goto err;
1903*4882a593Smuzhiyun } else {
1904*4882a593Smuzhiyun sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1905*4882a593Smuzhiyun sym = (sym / 100) * 65536;
1906*4882a593Smuzhiyun sym /= (state->internal->mclk / 100);
1907*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1908*4882a593Smuzhiyun goto err;
1909*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1910*4882a593Smuzhiyun goto err;
1911*4882a593Smuzhiyun sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1912*4882a593Smuzhiyun sym = (sym / 100) * 65536;
1913*4882a593Smuzhiyun sym /= (state->internal->mclk / 100);
1914*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1915*4882a593Smuzhiyun goto err;
1916*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1917*4882a593Smuzhiyun goto err;
1918*4882a593Smuzhiyun sym = (srate_coarse / 100) * 65536;
1919*4882a593Smuzhiyun sym /= (state->internal->mclk / 100);
1920*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1921*4882a593Smuzhiyun goto err;
1922*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1923*4882a593Smuzhiyun goto err;
1924*4882a593Smuzhiyun }
1925*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1926*4882a593Smuzhiyun goto err;
1927*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1928*4882a593Smuzhiyun goto err;
1929*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1930*4882a593Smuzhiyun goto err;
1931*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1932*4882a593Smuzhiyun goto err;
1933*4882a593Smuzhiyun }
1934*4882a593Smuzhiyun
1935*4882a593Smuzhiyun return srate_coarse;
1936*4882a593Smuzhiyun
1937*4882a593Smuzhiyun err:
1938*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
1939*4882a593Smuzhiyun return -1;
1940*4882a593Smuzhiyun }
1941*4882a593Smuzhiyun
stv090x_get_dmdlock(struct stv090x_state * state,s32 timeout)1942*4882a593Smuzhiyun static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1943*4882a593Smuzhiyun {
1944*4882a593Smuzhiyun s32 timer = 0, lock = 0;
1945*4882a593Smuzhiyun u32 reg;
1946*4882a593Smuzhiyun u8 stat;
1947*4882a593Smuzhiyun
1948*4882a593Smuzhiyun while ((timer < timeout) && (!lock)) {
1949*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDSTATE);
1950*4882a593Smuzhiyun stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1951*4882a593Smuzhiyun
1952*4882a593Smuzhiyun switch (stat) {
1953*4882a593Smuzhiyun case 0: /* searching */
1954*4882a593Smuzhiyun case 1: /* first PLH detected */
1955*4882a593Smuzhiyun default:
1956*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1957*4882a593Smuzhiyun lock = 0;
1958*4882a593Smuzhiyun break;
1959*4882a593Smuzhiyun case 2: /* DVB-S2 mode */
1960*4882a593Smuzhiyun case 3: /* DVB-S1/legacy mode */
1961*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DSTATUS);
1962*4882a593Smuzhiyun lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1963*4882a593Smuzhiyun break;
1964*4882a593Smuzhiyun }
1965*4882a593Smuzhiyun
1966*4882a593Smuzhiyun if (!lock)
1967*4882a593Smuzhiyun msleep(10);
1968*4882a593Smuzhiyun else
1969*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1970*4882a593Smuzhiyun
1971*4882a593Smuzhiyun timer += 10;
1972*4882a593Smuzhiyun }
1973*4882a593Smuzhiyun return lock;
1974*4882a593Smuzhiyun }
1975*4882a593Smuzhiyun
stv090x_blind_search(struct stv090x_state * state)1976*4882a593Smuzhiyun static int stv090x_blind_search(struct stv090x_state *state)
1977*4882a593Smuzhiyun {
1978*4882a593Smuzhiyun u32 agc2, reg, srate_coarse;
1979*4882a593Smuzhiyun s32 cpt_fail, agc2_ovflw, i;
1980*4882a593Smuzhiyun u8 k_ref, k_max, k_min;
1981*4882a593Smuzhiyun int coarse_fail = 0;
1982*4882a593Smuzhiyun int lock;
1983*4882a593Smuzhiyun
1984*4882a593Smuzhiyun k_max = 110;
1985*4882a593Smuzhiyun k_min = 10;
1986*4882a593Smuzhiyun
1987*4882a593Smuzhiyun agc2 = stv090x_get_agc2_min_level(state);
1988*4882a593Smuzhiyun
1989*4882a593Smuzhiyun if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
1990*4882a593Smuzhiyun lock = 0;
1991*4882a593Smuzhiyun } else {
1992*4882a593Smuzhiyun
1993*4882a593Smuzhiyun if (state->internal->dev_ver <= 0x20) {
1994*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1995*4882a593Smuzhiyun goto err;
1996*4882a593Smuzhiyun } else {
1997*4882a593Smuzhiyun /* > Cut 3 */
1998*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
1999*4882a593Smuzhiyun goto err;
2000*4882a593Smuzhiyun }
2001*4882a593Smuzhiyun
2002*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
2003*4882a593Smuzhiyun goto err;
2004*4882a593Smuzhiyun
2005*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
2006*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
2007*4882a593Smuzhiyun goto err;
2008*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
2009*4882a593Smuzhiyun goto err;
2010*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
2011*4882a593Smuzhiyun goto err;
2012*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
2013*4882a593Smuzhiyun goto err;
2014*4882a593Smuzhiyun }
2015*4882a593Smuzhiyun
2016*4882a593Smuzhiyun k_ref = k_max;
2017*4882a593Smuzhiyun do {
2018*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
2019*4882a593Smuzhiyun goto err;
2020*4882a593Smuzhiyun if (stv090x_srate_srch_coarse(state) != 0) {
2021*4882a593Smuzhiyun srate_coarse = stv090x_srate_srch_fine(state);
2022*4882a593Smuzhiyun if (srate_coarse != 0) {
2023*4882a593Smuzhiyun stv090x_get_lock_tmg(state);
2024*4882a593Smuzhiyun lock = stv090x_get_dmdlock(state,
2025*4882a593Smuzhiyun state->DemodTimeout);
2026*4882a593Smuzhiyun } else {
2027*4882a593Smuzhiyun lock = 0;
2028*4882a593Smuzhiyun }
2029*4882a593Smuzhiyun } else {
2030*4882a593Smuzhiyun cpt_fail = 0;
2031*4882a593Smuzhiyun agc2_ovflw = 0;
2032*4882a593Smuzhiyun for (i = 0; i < 10; i++) {
2033*4882a593Smuzhiyun agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
2034*4882a593Smuzhiyun STV090x_READ_DEMOD(state, AGC2I0);
2035*4882a593Smuzhiyun if (agc2 >= 0xff00)
2036*4882a593Smuzhiyun agc2_ovflw++;
2037*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DSTATUS2);
2038*4882a593Smuzhiyun if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
2039*4882a593Smuzhiyun (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
2040*4882a593Smuzhiyun
2041*4882a593Smuzhiyun cpt_fail++;
2042*4882a593Smuzhiyun }
2043*4882a593Smuzhiyun if ((cpt_fail > 7) || (agc2_ovflw > 7))
2044*4882a593Smuzhiyun coarse_fail = 1;
2045*4882a593Smuzhiyun
2046*4882a593Smuzhiyun lock = 0;
2047*4882a593Smuzhiyun }
2048*4882a593Smuzhiyun k_ref -= 20;
2049*4882a593Smuzhiyun } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
2050*4882a593Smuzhiyun }
2051*4882a593Smuzhiyun
2052*4882a593Smuzhiyun return lock;
2053*4882a593Smuzhiyun
2054*4882a593Smuzhiyun err:
2055*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
2056*4882a593Smuzhiyun return -1;
2057*4882a593Smuzhiyun }
2058*4882a593Smuzhiyun
stv090x_chk_tmg(struct stv090x_state * state)2059*4882a593Smuzhiyun static int stv090x_chk_tmg(struct stv090x_state *state)
2060*4882a593Smuzhiyun {
2061*4882a593Smuzhiyun u32 reg;
2062*4882a593Smuzhiyun s32 tmg_cpt = 0, i;
2063*4882a593Smuzhiyun u8 freq, tmg_thh, tmg_thl;
2064*4882a593Smuzhiyun int tmg_lock = 0;
2065*4882a593Smuzhiyun
2066*4882a593Smuzhiyun freq = STV090x_READ_DEMOD(state, CARFREQ);
2067*4882a593Smuzhiyun tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
2068*4882a593Smuzhiyun tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
2069*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
2070*4882a593Smuzhiyun goto err;
2071*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
2072*4882a593Smuzhiyun goto err;
2073*4882a593Smuzhiyun
2074*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2075*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
2076*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2077*4882a593Smuzhiyun goto err;
2078*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
2079*4882a593Smuzhiyun goto err;
2080*4882a593Smuzhiyun
2081*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
2082*4882a593Smuzhiyun goto err;
2083*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
2084*4882a593Smuzhiyun goto err;
2085*4882a593Smuzhiyun
2086*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
2087*4882a593Smuzhiyun goto err;
2088*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2089*4882a593Smuzhiyun goto err;
2090*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
2091*4882a593Smuzhiyun goto err;
2092*4882a593Smuzhiyun
2093*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
2094*4882a593Smuzhiyun goto err;
2095*4882a593Smuzhiyun msleep(10);
2096*4882a593Smuzhiyun
2097*4882a593Smuzhiyun for (i = 0; i < 10; i++) {
2098*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DSTATUS);
2099*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
2100*4882a593Smuzhiyun tmg_cpt++;
2101*4882a593Smuzhiyun msleep(1);
2102*4882a593Smuzhiyun }
2103*4882a593Smuzhiyun if (tmg_cpt >= 3)
2104*4882a593Smuzhiyun tmg_lock = 1;
2105*4882a593Smuzhiyun
2106*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2107*4882a593Smuzhiyun goto err;
2108*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
2109*4882a593Smuzhiyun goto err;
2110*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2111*4882a593Smuzhiyun goto err;
2112*4882a593Smuzhiyun
2113*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2114*4882a593Smuzhiyun goto err;
2115*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2116*4882a593Smuzhiyun goto err;
2117*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2118*4882a593Smuzhiyun goto err;
2119*4882a593Smuzhiyun
2120*4882a593Smuzhiyun return tmg_lock;
2121*4882a593Smuzhiyun
2122*4882a593Smuzhiyun err:
2123*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
2124*4882a593Smuzhiyun return -1;
2125*4882a593Smuzhiyun }
2126*4882a593Smuzhiyun
stv090x_get_coldlock(struct stv090x_state * state,s32 timeout_dmd)2127*4882a593Smuzhiyun static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2128*4882a593Smuzhiyun {
2129*4882a593Smuzhiyun struct dvb_frontend *fe = &state->frontend;
2130*4882a593Smuzhiyun
2131*4882a593Smuzhiyun u32 reg;
2132*4882a593Smuzhiyun s32 car_step, steps, cur_step, dir, freq, timeout_lock;
2133*4882a593Smuzhiyun int lock;
2134*4882a593Smuzhiyun
2135*4882a593Smuzhiyun if (state->srate >= 10000000)
2136*4882a593Smuzhiyun timeout_lock = timeout_dmd / 3;
2137*4882a593Smuzhiyun else
2138*4882a593Smuzhiyun timeout_lock = timeout_dmd / 2;
2139*4882a593Smuzhiyun
2140*4882a593Smuzhiyun lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2141*4882a593Smuzhiyun if (lock)
2142*4882a593Smuzhiyun return lock;
2143*4882a593Smuzhiyun
2144*4882a593Smuzhiyun if (state->srate >= 10000000) {
2145*4882a593Smuzhiyun if (stv090x_chk_tmg(state)) {
2146*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2147*4882a593Smuzhiyun goto err;
2148*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2149*4882a593Smuzhiyun goto err;
2150*4882a593Smuzhiyun return stv090x_get_dmdlock(state, timeout_dmd);
2151*4882a593Smuzhiyun }
2152*4882a593Smuzhiyun return 0;
2153*4882a593Smuzhiyun }
2154*4882a593Smuzhiyun
2155*4882a593Smuzhiyun if (state->srate <= 4000000)
2156*4882a593Smuzhiyun car_step = 1000;
2157*4882a593Smuzhiyun else if (state->srate <= 7000000)
2158*4882a593Smuzhiyun car_step = 2000;
2159*4882a593Smuzhiyun else if (state->srate <= 10000000)
2160*4882a593Smuzhiyun car_step = 3000;
2161*4882a593Smuzhiyun else
2162*4882a593Smuzhiyun car_step = 5000;
2163*4882a593Smuzhiyun
2164*4882a593Smuzhiyun steps = (state->search_range / 1000) / car_step;
2165*4882a593Smuzhiyun steps /= 2;
2166*4882a593Smuzhiyun steps = 2 * (steps + 1);
2167*4882a593Smuzhiyun if (steps < 0)
2168*4882a593Smuzhiyun steps = 2;
2169*4882a593Smuzhiyun else if (steps > 12)
2170*4882a593Smuzhiyun steps = 12;
2171*4882a593Smuzhiyun
2172*4882a593Smuzhiyun cur_step = 1;
2173*4882a593Smuzhiyun dir = 1;
2174*4882a593Smuzhiyun
2175*4882a593Smuzhiyun freq = state->frequency;
2176*4882a593Smuzhiyun state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2177*4882a593Smuzhiyun while ((cur_step <= steps) && (!lock)) {
2178*4882a593Smuzhiyun if (dir > 0)
2179*4882a593Smuzhiyun freq += cur_step * car_step;
2180*4882a593Smuzhiyun else
2181*4882a593Smuzhiyun freq -= cur_step * car_step;
2182*4882a593Smuzhiyun
2183*4882a593Smuzhiyun /* Setup tuner */
2184*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2185*4882a593Smuzhiyun goto err;
2186*4882a593Smuzhiyun
2187*4882a593Smuzhiyun if (state->config->tuner_set_frequency) {
2188*4882a593Smuzhiyun if (state->config->tuner_set_frequency(fe, freq) < 0)
2189*4882a593Smuzhiyun goto err_gateoff;
2190*4882a593Smuzhiyun }
2191*4882a593Smuzhiyun
2192*4882a593Smuzhiyun if (state->config->tuner_set_bandwidth) {
2193*4882a593Smuzhiyun if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2194*4882a593Smuzhiyun goto err_gateoff;
2195*4882a593Smuzhiyun }
2196*4882a593Smuzhiyun
2197*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2198*4882a593Smuzhiyun goto err;
2199*4882a593Smuzhiyun
2200*4882a593Smuzhiyun msleep(50);
2201*4882a593Smuzhiyun
2202*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2203*4882a593Smuzhiyun goto err;
2204*4882a593Smuzhiyun
2205*4882a593Smuzhiyun if (state->config->tuner_get_status) {
2206*4882a593Smuzhiyun if (state->config->tuner_get_status(fe, ®) < 0)
2207*4882a593Smuzhiyun goto err_gateoff;
2208*4882a593Smuzhiyun if (reg)
2209*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Tuner phase locked");
2210*4882a593Smuzhiyun else
2211*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Tuner unlocked");
2212*4882a593Smuzhiyun }
2213*4882a593Smuzhiyun
2214*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2215*4882a593Smuzhiyun goto err;
2216*4882a593Smuzhiyun
2217*4882a593Smuzhiyun STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
2218*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2219*4882a593Smuzhiyun goto err;
2220*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2221*4882a593Smuzhiyun goto err;
2222*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2223*4882a593Smuzhiyun goto err;
2224*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2225*4882a593Smuzhiyun goto err;
2226*4882a593Smuzhiyun lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2227*4882a593Smuzhiyun
2228*4882a593Smuzhiyun dir *= -1;
2229*4882a593Smuzhiyun cur_step++;
2230*4882a593Smuzhiyun }
2231*4882a593Smuzhiyun
2232*4882a593Smuzhiyun return lock;
2233*4882a593Smuzhiyun
2234*4882a593Smuzhiyun err_gateoff:
2235*4882a593Smuzhiyun stv090x_i2c_gate_ctrl(state, 0);
2236*4882a593Smuzhiyun err:
2237*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
2238*4882a593Smuzhiyun return -1;
2239*4882a593Smuzhiyun }
2240*4882a593Smuzhiyun
stv090x_get_loop_params(struct stv090x_state * state,s32 * freq_inc,s32 * timeout_sw,s32 * steps)2241*4882a593Smuzhiyun static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2242*4882a593Smuzhiyun {
2243*4882a593Smuzhiyun s32 timeout, inc, steps_max, srate, car_max;
2244*4882a593Smuzhiyun
2245*4882a593Smuzhiyun srate = state->srate;
2246*4882a593Smuzhiyun car_max = state->search_range / 1000;
2247*4882a593Smuzhiyun car_max += car_max / 10;
2248*4882a593Smuzhiyun car_max = 65536 * (car_max / 2);
2249*4882a593Smuzhiyun car_max /= (state->internal->mclk / 1000);
2250*4882a593Smuzhiyun
2251*4882a593Smuzhiyun if (car_max > 0x4000)
2252*4882a593Smuzhiyun car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
2253*4882a593Smuzhiyun
2254*4882a593Smuzhiyun inc = srate;
2255*4882a593Smuzhiyun inc /= state->internal->mclk / 1000;
2256*4882a593Smuzhiyun inc *= 256;
2257*4882a593Smuzhiyun inc *= 256;
2258*4882a593Smuzhiyun inc /= 1000;
2259*4882a593Smuzhiyun
2260*4882a593Smuzhiyun switch (state->search_mode) {
2261*4882a593Smuzhiyun case STV090x_SEARCH_DVBS1:
2262*4882a593Smuzhiyun case STV090x_SEARCH_DSS:
2263*4882a593Smuzhiyun inc *= 3; /* freq step = 3% of srate */
2264*4882a593Smuzhiyun timeout = 20;
2265*4882a593Smuzhiyun break;
2266*4882a593Smuzhiyun
2267*4882a593Smuzhiyun case STV090x_SEARCH_DVBS2:
2268*4882a593Smuzhiyun inc *= 4;
2269*4882a593Smuzhiyun timeout = 25;
2270*4882a593Smuzhiyun break;
2271*4882a593Smuzhiyun
2272*4882a593Smuzhiyun case STV090x_SEARCH_AUTO:
2273*4882a593Smuzhiyun default:
2274*4882a593Smuzhiyun inc *= 3;
2275*4882a593Smuzhiyun timeout = 25;
2276*4882a593Smuzhiyun break;
2277*4882a593Smuzhiyun }
2278*4882a593Smuzhiyun inc /= 100;
2279*4882a593Smuzhiyun if ((inc > car_max) || (inc < 0))
2280*4882a593Smuzhiyun inc = car_max / 2; /* increment <= 1/8 Mclk */
2281*4882a593Smuzhiyun
2282*4882a593Smuzhiyun timeout *= 27500; /* 27.5 Msps reference */
2283*4882a593Smuzhiyun if (srate > 0)
2284*4882a593Smuzhiyun timeout /= (srate / 1000);
2285*4882a593Smuzhiyun
2286*4882a593Smuzhiyun if ((timeout > 100) || (timeout < 0))
2287*4882a593Smuzhiyun timeout = 100;
2288*4882a593Smuzhiyun
2289*4882a593Smuzhiyun steps_max = (car_max / inc) + 1; /* min steps = 3 */
2290*4882a593Smuzhiyun if ((steps_max > 100) || (steps_max < 0)) {
2291*4882a593Smuzhiyun steps_max = 100; /* max steps <= 100 */
2292*4882a593Smuzhiyun inc = car_max / steps_max;
2293*4882a593Smuzhiyun }
2294*4882a593Smuzhiyun *freq_inc = inc;
2295*4882a593Smuzhiyun *timeout_sw = timeout;
2296*4882a593Smuzhiyun *steps = steps_max;
2297*4882a593Smuzhiyun
2298*4882a593Smuzhiyun return 0;
2299*4882a593Smuzhiyun }
2300*4882a593Smuzhiyun
stv090x_chk_signal(struct stv090x_state * state)2301*4882a593Smuzhiyun static int stv090x_chk_signal(struct stv090x_state *state)
2302*4882a593Smuzhiyun {
2303*4882a593Smuzhiyun s32 offst_car, agc2, car_max;
2304*4882a593Smuzhiyun int no_signal;
2305*4882a593Smuzhiyun
2306*4882a593Smuzhiyun offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2307*4882a593Smuzhiyun offst_car |= STV090x_READ_DEMOD(state, CFR1);
2308*4882a593Smuzhiyun offst_car = comp2(offst_car, 16);
2309*4882a593Smuzhiyun
2310*4882a593Smuzhiyun agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2311*4882a593Smuzhiyun agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2312*4882a593Smuzhiyun car_max = state->search_range / 1000;
2313*4882a593Smuzhiyun
2314*4882a593Smuzhiyun car_max += (car_max / 10); /* 10% margin */
2315*4882a593Smuzhiyun car_max = (65536 * car_max / 2);
2316*4882a593Smuzhiyun car_max /= state->internal->mclk / 1000;
2317*4882a593Smuzhiyun
2318*4882a593Smuzhiyun if (car_max > 0x4000)
2319*4882a593Smuzhiyun car_max = 0x4000;
2320*4882a593Smuzhiyun
2321*4882a593Smuzhiyun if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2322*4882a593Smuzhiyun no_signal = 1;
2323*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "No Signal");
2324*4882a593Smuzhiyun } else {
2325*4882a593Smuzhiyun no_signal = 0;
2326*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Found Signal");
2327*4882a593Smuzhiyun }
2328*4882a593Smuzhiyun
2329*4882a593Smuzhiyun return no_signal;
2330*4882a593Smuzhiyun }
2331*4882a593Smuzhiyun
stv090x_search_car_loop(struct stv090x_state * state,s32 inc,s32 timeout,int zigzag,s32 steps_max)2332*4882a593Smuzhiyun static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2333*4882a593Smuzhiyun {
2334*4882a593Smuzhiyun int no_signal, lock = 0;
2335*4882a593Smuzhiyun s32 cpt_step = 0, offst_freq, car_max;
2336*4882a593Smuzhiyun u32 reg;
2337*4882a593Smuzhiyun
2338*4882a593Smuzhiyun car_max = state->search_range / 1000;
2339*4882a593Smuzhiyun car_max += (car_max / 10);
2340*4882a593Smuzhiyun car_max = (65536 * car_max / 2);
2341*4882a593Smuzhiyun car_max /= (state->internal->mclk / 1000);
2342*4882a593Smuzhiyun if (car_max > 0x4000)
2343*4882a593Smuzhiyun car_max = 0x4000;
2344*4882a593Smuzhiyun
2345*4882a593Smuzhiyun if (zigzag)
2346*4882a593Smuzhiyun offst_freq = 0;
2347*4882a593Smuzhiyun else
2348*4882a593Smuzhiyun offst_freq = -car_max + inc;
2349*4882a593Smuzhiyun
2350*4882a593Smuzhiyun do {
2351*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2352*4882a593Smuzhiyun goto err;
2353*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2354*4882a593Smuzhiyun goto err;
2355*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2356*4882a593Smuzhiyun goto err;
2357*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2358*4882a593Smuzhiyun goto err;
2359*4882a593Smuzhiyun
2360*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2361*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2362*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2363*4882a593Smuzhiyun goto err;
2364*4882a593Smuzhiyun
2365*4882a593Smuzhiyun if (zigzag) {
2366*4882a593Smuzhiyun if (offst_freq >= 0)
2367*4882a593Smuzhiyun offst_freq = -offst_freq - 2 * inc;
2368*4882a593Smuzhiyun else
2369*4882a593Smuzhiyun offst_freq = -offst_freq;
2370*4882a593Smuzhiyun } else {
2371*4882a593Smuzhiyun offst_freq += 2 * inc;
2372*4882a593Smuzhiyun }
2373*4882a593Smuzhiyun
2374*4882a593Smuzhiyun cpt_step++;
2375*4882a593Smuzhiyun
2376*4882a593Smuzhiyun lock = stv090x_get_dmdlock(state, timeout);
2377*4882a593Smuzhiyun no_signal = stv090x_chk_signal(state);
2378*4882a593Smuzhiyun
2379*4882a593Smuzhiyun } while ((!lock) &&
2380*4882a593Smuzhiyun (!no_signal) &&
2381*4882a593Smuzhiyun ((offst_freq - inc) < car_max) &&
2382*4882a593Smuzhiyun ((offst_freq + inc) > -car_max) &&
2383*4882a593Smuzhiyun (cpt_step < steps_max));
2384*4882a593Smuzhiyun
2385*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2386*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2387*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2388*4882a593Smuzhiyun goto err;
2389*4882a593Smuzhiyun
2390*4882a593Smuzhiyun return lock;
2391*4882a593Smuzhiyun err:
2392*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
2393*4882a593Smuzhiyun return -1;
2394*4882a593Smuzhiyun }
2395*4882a593Smuzhiyun
stv090x_sw_algo(struct stv090x_state * state)2396*4882a593Smuzhiyun static int stv090x_sw_algo(struct stv090x_state *state)
2397*4882a593Smuzhiyun {
2398*4882a593Smuzhiyun int no_signal, zigzag, lock = 0;
2399*4882a593Smuzhiyun u32 reg;
2400*4882a593Smuzhiyun
2401*4882a593Smuzhiyun s32 dvbs2_fly_wheel;
2402*4882a593Smuzhiyun s32 inc, timeout_step, trials, steps_max;
2403*4882a593Smuzhiyun
2404*4882a593Smuzhiyun /* get params */
2405*4882a593Smuzhiyun stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
2406*4882a593Smuzhiyun
2407*4882a593Smuzhiyun switch (state->search_mode) {
2408*4882a593Smuzhiyun case STV090x_SEARCH_DVBS1:
2409*4882a593Smuzhiyun case STV090x_SEARCH_DSS:
2410*4882a593Smuzhiyun /* accelerate the frequency detector */
2411*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
2412*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2413*4882a593Smuzhiyun goto err;
2414*4882a593Smuzhiyun }
2415*4882a593Smuzhiyun
2416*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2417*4882a593Smuzhiyun goto err;
2418*4882a593Smuzhiyun zigzag = 0;
2419*4882a593Smuzhiyun break;
2420*4882a593Smuzhiyun
2421*4882a593Smuzhiyun case STV090x_SEARCH_DVBS2:
2422*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
2423*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2424*4882a593Smuzhiyun goto err;
2425*4882a593Smuzhiyun }
2426*4882a593Smuzhiyun
2427*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2428*4882a593Smuzhiyun goto err;
2429*4882a593Smuzhiyun zigzag = 1;
2430*4882a593Smuzhiyun break;
2431*4882a593Smuzhiyun
2432*4882a593Smuzhiyun case STV090x_SEARCH_AUTO:
2433*4882a593Smuzhiyun default:
2434*4882a593Smuzhiyun /* accelerate the frequency detector */
2435*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
2436*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2437*4882a593Smuzhiyun goto err;
2438*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2439*4882a593Smuzhiyun goto err;
2440*4882a593Smuzhiyun }
2441*4882a593Smuzhiyun
2442*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
2443*4882a593Smuzhiyun goto err;
2444*4882a593Smuzhiyun zigzag = 0;
2445*4882a593Smuzhiyun break;
2446*4882a593Smuzhiyun }
2447*4882a593Smuzhiyun
2448*4882a593Smuzhiyun trials = 0;
2449*4882a593Smuzhiyun do {
2450*4882a593Smuzhiyun lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2451*4882a593Smuzhiyun no_signal = stv090x_chk_signal(state);
2452*4882a593Smuzhiyun trials++;
2453*4882a593Smuzhiyun
2454*4882a593Smuzhiyun /*run the SW search 2 times maximum*/
2455*4882a593Smuzhiyun if (lock || no_signal || (trials == 2)) {
2456*4882a593Smuzhiyun /*Check if the demod is not losing lock in DVBS2*/
2457*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
2458*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2459*4882a593Smuzhiyun goto err;
2460*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2461*4882a593Smuzhiyun goto err;
2462*4882a593Smuzhiyun }
2463*4882a593Smuzhiyun
2464*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDSTATE);
2465*4882a593Smuzhiyun if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2466*4882a593Smuzhiyun /*Check if the demod is not losing lock in DVBS2*/
2467*4882a593Smuzhiyun msleep(timeout_step);
2468*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDFLYW);
2469*4882a593Smuzhiyun dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2470*4882a593Smuzhiyun if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2471*4882a593Smuzhiyun msleep(timeout_step);
2472*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDFLYW);
2473*4882a593Smuzhiyun dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2474*4882a593Smuzhiyun }
2475*4882a593Smuzhiyun if (dvbs2_fly_wheel < 0xd) {
2476*4882a593Smuzhiyun /*FALSE lock, The demod is losing lock */
2477*4882a593Smuzhiyun lock = 0;
2478*4882a593Smuzhiyun if (trials < 2) {
2479*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
2480*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2481*4882a593Smuzhiyun goto err;
2482*4882a593Smuzhiyun }
2483*4882a593Smuzhiyun
2484*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2485*4882a593Smuzhiyun goto err;
2486*4882a593Smuzhiyun }
2487*4882a593Smuzhiyun }
2488*4882a593Smuzhiyun }
2489*4882a593Smuzhiyun }
2490*4882a593Smuzhiyun } while ((!lock) && (trials < 2) && (!no_signal));
2491*4882a593Smuzhiyun
2492*4882a593Smuzhiyun return lock;
2493*4882a593Smuzhiyun err:
2494*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
2495*4882a593Smuzhiyun return -1;
2496*4882a593Smuzhiyun }
2497*4882a593Smuzhiyun
stv090x_get_std(struct stv090x_state * state)2498*4882a593Smuzhiyun static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2499*4882a593Smuzhiyun {
2500*4882a593Smuzhiyun u32 reg;
2501*4882a593Smuzhiyun enum stv090x_delsys delsys;
2502*4882a593Smuzhiyun
2503*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDSTATE);
2504*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2505*4882a593Smuzhiyun delsys = STV090x_DVBS2;
2506*4882a593Smuzhiyun else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2507*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, FECM);
2508*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2509*4882a593Smuzhiyun delsys = STV090x_DSS;
2510*4882a593Smuzhiyun else
2511*4882a593Smuzhiyun delsys = STV090x_DVBS1;
2512*4882a593Smuzhiyun } else {
2513*4882a593Smuzhiyun delsys = STV090x_ERROR;
2514*4882a593Smuzhiyun }
2515*4882a593Smuzhiyun
2516*4882a593Smuzhiyun return delsys;
2517*4882a593Smuzhiyun }
2518*4882a593Smuzhiyun
2519*4882a593Smuzhiyun /* in Hz */
stv090x_get_car_freq(struct stv090x_state * state,u32 mclk)2520*4882a593Smuzhiyun static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2521*4882a593Smuzhiyun {
2522*4882a593Smuzhiyun s32 derot, int_1, int_2, tmp_1, tmp_2;
2523*4882a593Smuzhiyun
2524*4882a593Smuzhiyun derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2525*4882a593Smuzhiyun derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2526*4882a593Smuzhiyun derot |= STV090x_READ_DEMOD(state, CFR0);
2527*4882a593Smuzhiyun
2528*4882a593Smuzhiyun derot = comp2(derot, 24);
2529*4882a593Smuzhiyun int_1 = mclk >> 12;
2530*4882a593Smuzhiyun int_2 = derot >> 12;
2531*4882a593Smuzhiyun
2532*4882a593Smuzhiyun /* carrier_frequency = MasterClock * Reg / 2^24 */
2533*4882a593Smuzhiyun tmp_1 = mclk % 0x1000;
2534*4882a593Smuzhiyun tmp_2 = derot % 0x1000;
2535*4882a593Smuzhiyun
2536*4882a593Smuzhiyun derot = (int_1 * int_2) +
2537*4882a593Smuzhiyun ((int_1 * tmp_2) >> 12) +
2538*4882a593Smuzhiyun ((int_2 * tmp_1) >> 12);
2539*4882a593Smuzhiyun
2540*4882a593Smuzhiyun return derot;
2541*4882a593Smuzhiyun }
2542*4882a593Smuzhiyun
stv090x_get_viterbi(struct stv090x_state * state)2543*4882a593Smuzhiyun static int stv090x_get_viterbi(struct stv090x_state *state)
2544*4882a593Smuzhiyun {
2545*4882a593Smuzhiyun u32 reg, rate;
2546*4882a593Smuzhiyun
2547*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, VITCURPUN);
2548*4882a593Smuzhiyun rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2549*4882a593Smuzhiyun
2550*4882a593Smuzhiyun switch (rate) {
2551*4882a593Smuzhiyun case 13:
2552*4882a593Smuzhiyun state->fec = STV090x_PR12;
2553*4882a593Smuzhiyun break;
2554*4882a593Smuzhiyun
2555*4882a593Smuzhiyun case 18:
2556*4882a593Smuzhiyun state->fec = STV090x_PR23;
2557*4882a593Smuzhiyun break;
2558*4882a593Smuzhiyun
2559*4882a593Smuzhiyun case 21:
2560*4882a593Smuzhiyun state->fec = STV090x_PR34;
2561*4882a593Smuzhiyun break;
2562*4882a593Smuzhiyun
2563*4882a593Smuzhiyun case 24:
2564*4882a593Smuzhiyun state->fec = STV090x_PR56;
2565*4882a593Smuzhiyun break;
2566*4882a593Smuzhiyun
2567*4882a593Smuzhiyun case 25:
2568*4882a593Smuzhiyun state->fec = STV090x_PR67;
2569*4882a593Smuzhiyun break;
2570*4882a593Smuzhiyun
2571*4882a593Smuzhiyun case 26:
2572*4882a593Smuzhiyun state->fec = STV090x_PR78;
2573*4882a593Smuzhiyun break;
2574*4882a593Smuzhiyun
2575*4882a593Smuzhiyun default:
2576*4882a593Smuzhiyun state->fec = STV090x_PRERR;
2577*4882a593Smuzhiyun break;
2578*4882a593Smuzhiyun }
2579*4882a593Smuzhiyun
2580*4882a593Smuzhiyun return 0;
2581*4882a593Smuzhiyun }
2582*4882a593Smuzhiyun
stv090x_get_sig_params(struct stv090x_state * state)2583*4882a593Smuzhiyun static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2584*4882a593Smuzhiyun {
2585*4882a593Smuzhiyun struct dvb_frontend *fe = &state->frontend;
2586*4882a593Smuzhiyun
2587*4882a593Smuzhiyun u8 tmg;
2588*4882a593Smuzhiyun u32 reg;
2589*4882a593Smuzhiyun s32 i = 0, offst_freq;
2590*4882a593Smuzhiyun
2591*4882a593Smuzhiyun msleep(5);
2592*4882a593Smuzhiyun
2593*4882a593Smuzhiyun if (state->algo == STV090x_BLIND_SEARCH) {
2594*4882a593Smuzhiyun tmg = STV090x_READ_DEMOD(state, TMGREG2);
2595*4882a593Smuzhiyun STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2596*4882a593Smuzhiyun while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
2597*4882a593Smuzhiyun tmg = STV090x_READ_DEMOD(state, TMGREG2);
2598*4882a593Smuzhiyun msleep(5);
2599*4882a593Smuzhiyun i += 5;
2600*4882a593Smuzhiyun }
2601*4882a593Smuzhiyun }
2602*4882a593Smuzhiyun state->delsys = stv090x_get_std(state);
2603*4882a593Smuzhiyun
2604*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2605*4882a593Smuzhiyun goto err;
2606*4882a593Smuzhiyun
2607*4882a593Smuzhiyun if (state->config->tuner_get_frequency) {
2608*4882a593Smuzhiyun if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2609*4882a593Smuzhiyun goto err_gateoff;
2610*4882a593Smuzhiyun }
2611*4882a593Smuzhiyun
2612*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2613*4882a593Smuzhiyun goto err;
2614*4882a593Smuzhiyun
2615*4882a593Smuzhiyun offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
2616*4882a593Smuzhiyun state->frequency += offst_freq;
2617*4882a593Smuzhiyun
2618*4882a593Smuzhiyun if (stv090x_get_viterbi(state) < 0)
2619*4882a593Smuzhiyun goto err;
2620*4882a593Smuzhiyun
2621*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2622*4882a593Smuzhiyun state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2623*4882a593Smuzhiyun state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2624*4882a593Smuzhiyun state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2625*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, TMGOBS);
2626*4882a593Smuzhiyun state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2627*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, FECM);
2628*4882a593Smuzhiyun state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2629*4882a593Smuzhiyun
2630*4882a593Smuzhiyun if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2631*4882a593Smuzhiyun
2632*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2633*4882a593Smuzhiyun goto err;
2634*4882a593Smuzhiyun
2635*4882a593Smuzhiyun if (state->config->tuner_get_frequency) {
2636*4882a593Smuzhiyun if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2637*4882a593Smuzhiyun goto err_gateoff;
2638*4882a593Smuzhiyun }
2639*4882a593Smuzhiyun
2640*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2641*4882a593Smuzhiyun goto err;
2642*4882a593Smuzhiyun
2643*4882a593Smuzhiyun if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2644*4882a593Smuzhiyun return STV090x_RANGEOK;
2645*4882a593Smuzhiyun else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2646*4882a593Smuzhiyun return STV090x_RANGEOK;
2647*4882a593Smuzhiyun } else {
2648*4882a593Smuzhiyun if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2649*4882a593Smuzhiyun return STV090x_RANGEOK;
2650*4882a593Smuzhiyun }
2651*4882a593Smuzhiyun
2652*4882a593Smuzhiyun return STV090x_OUTOFRANGE;
2653*4882a593Smuzhiyun
2654*4882a593Smuzhiyun err_gateoff:
2655*4882a593Smuzhiyun stv090x_i2c_gate_ctrl(state, 0);
2656*4882a593Smuzhiyun err:
2657*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
2658*4882a593Smuzhiyun return -1;
2659*4882a593Smuzhiyun }
2660*4882a593Smuzhiyun
stv090x_get_tmgoffst(struct stv090x_state * state,u32 srate)2661*4882a593Smuzhiyun static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2662*4882a593Smuzhiyun {
2663*4882a593Smuzhiyun s32 offst_tmg;
2664*4882a593Smuzhiyun
2665*4882a593Smuzhiyun offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2666*4882a593Smuzhiyun offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2667*4882a593Smuzhiyun offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2668*4882a593Smuzhiyun
2669*4882a593Smuzhiyun offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2670*4882a593Smuzhiyun if (!offst_tmg)
2671*4882a593Smuzhiyun offst_tmg = 1;
2672*4882a593Smuzhiyun
2673*4882a593Smuzhiyun offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
2674*4882a593Smuzhiyun offst_tmg /= 320;
2675*4882a593Smuzhiyun
2676*4882a593Smuzhiyun return offst_tmg;
2677*4882a593Smuzhiyun }
2678*4882a593Smuzhiyun
stv090x_optimize_carloop(struct stv090x_state * state,enum stv090x_modcod modcod,s32 pilots)2679*4882a593Smuzhiyun static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2680*4882a593Smuzhiyun {
2681*4882a593Smuzhiyun u8 aclc = 0x29;
2682*4882a593Smuzhiyun s32 i;
2683*4882a593Smuzhiyun struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
2684*4882a593Smuzhiyun
2685*4882a593Smuzhiyun if (state->internal->dev_ver == 0x20) {
2686*4882a593Smuzhiyun car_loop = stv090x_s2_crl_cut20;
2687*4882a593Smuzhiyun car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
2688*4882a593Smuzhiyun car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
2689*4882a593Smuzhiyun } else {
2690*4882a593Smuzhiyun /* >= Cut 3 */
2691*4882a593Smuzhiyun car_loop = stv090x_s2_crl_cut30;
2692*4882a593Smuzhiyun car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
2693*4882a593Smuzhiyun car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
2694*4882a593Smuzhiyun }
2695*4882a593Smuzhiyun
2696*4882a593Smuzhiyun if (modcod < STV090x_QPSK_12) {
2697*4882a593Smuzhiyun i = 0;
2698*4882a593Smuzhiyun while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
2699*4882a593Smuzhiyun i++;
2700*4882a593Smuzhiyun
2701*4882a593Smuzhiyun if (i >= 3)
2702*4882a593Smuzhiyun i = 2;
2703*4882a593Smuzhiyun
2704*4882a593Smuzhiyun } else {
2705*4882a593Smuzhiyun i = 0;
2706*4882a593Smuzhiyun while ((i < 14) && (modcod != car_loop[i].modcod))
2707*4882a593Smuzhiyun i++;
2708*4882a593Smuzhiyun
2709*4882a593Smuzhiyun if (i >= 14) {
2710*4882a593Smuzhiyun i = 0;
2711*4882a593Smuzhiyun while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
2712*4882a593Smuzhiyun i++;
2713*4882a593Smuzhiyun
2714*4882a593Smuzhiyun if (i >= 11)
2715*4882a593Smuzhiyun i = 10;
2716*4882a593Smuzhiyun }
2717*4882a593Smuzhiyun }
2718*4882a593Smuzhiyun
2719*4882a593Smuzhiyun if (modcod <= STV090x_QPSK_25) {
2720*4882a593Smuzhiyun if (pilots) {
2721*4882a593Smuzhiyun if (state->srate <= 3000000)
2722*4882a593Smuzhiyun aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
2723*4882a593Smuzhiyun else if (state->srate <= 7000000)
2724*4882a593Smuzhiyun aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
2725*4882a593Smuzhiyun else if (state->srate <= 15000000)
2726*4882a593Smuzhiyun aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
2727*4882a593Smuzhiyun else if (state->srate <= 25000000)
2728*4882a593Smuzhiyun aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
2729*4882a593Smuzhiyun else
2730*4882a593Smuzhiyun aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
2731*4882a593Smuzhiyun } else {
2732*4882a593Smuzhiyun if (state->srate <= 3000000)
2733*4882a593Smuzhiyun aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
2734*4882a593Smuzhiyun else if (state->srate <= 7000000)
2735*4882a593Smuzhiyun aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
2736*4882a593Smuzhiyun else if (state->srate <= 15000000)
2737*4882a593Smuzhiyun aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
2738*4882a593Smuzhiyun else if (state->srate <= 25000000)
2739*4882a593Smuzhiyun aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
2740*4882a593Smuzhiyun else
2741*4882a593Smuzhiyun aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
2742*4882a593Smuzhiyun }
2743*4882a593Smuzhiyun
2744*4882a593Smuzhiyun } else if (modcod <= STV090x_8PSK_910) {
2745*4882a593Smuzhiyun if (pilots) {
2746*4882a593Smuzhiyun if (state->srate <= 3000000)
2747*4882a593Smuzhiyun aclc = car_loop[i].crl_pilots_on_2;
2748*4882a593Smuzhiyun else if (state->srate <= 7000000)
2749*4882a593Smuzhiyun aclc = car_loop[i].crl_pilots_on_5;
2750*4882a593Smuzhiyun else if (state->srate <= 15000000)
2751*4882a593Smuzhiyun aclc = car_loop[i].crl_pilots_on_10;
2752*4882a593Smuzhiyun else if (state->srate <= 25000000)
2753*4882a593Smuzhiyun aclc = car_loop[i].crl_pilots_on_20;
2754*4882a593Smuzhiyun else
2755*4882a593Smuzhiyun aclc = car_loop[i].crl_pilots_on_30;
2756*4882a593Smuzhiyun } else {
2757*4882a593Smuzhiyun if (state->srate <= 3000000)
2758*4882a593Smuzhiyun aclc = car_loop[i].crl_pilots_off_2;
2759*4882a593Smuzhiyun else if (state->srate <= 7000000)
2760*4882a593Smuzhiyun aclc = car_loop[i].crl_pilots_off_5;
2761*4882a593Smuzhiyun else if (state->srate <= 15000000)
2762*4882a593Smuzhiyun aclc = car_loop[i].crl_pilots_off_10;
2763*4882a593Smuzhiyun else if (state->srate <= 25000000)
2764*4882a593Smuzhiyun aclc = car_loop[i].crl_pilots_off_20;
2765*4882a593Smuzhiyun else
2766*4882a593Smuzhiyun aclc = car_loop[i].crl_pilots_off_30;
2767*4882a593Smuzhiyun }
2768*4882a593Smuzhiyun } else { /* 16APSK and 32APSK */
2769*4882a593Smuzhiyun /*
2770*4882a593Smuzhiyun * This should never happen in practice, except if
2771*4882a593Smuzhiyun * something is really wrong at the car_loop table.
2772*4882a593Smuzhiyun */
2773*4882a593Smuzhiyun if (i >= 11)
2774*4882a593Smuzhiyun i = 10;
2775*4882a593Smuzhiyun if (state->srate <= 3000000)
2776*4882a593Smuzhiyun aclc = car_loop_apsk_low[i].crl_pilots_on_2;
2777*4882a593Smuzhiyun else if (state->srate <= 7000000)
2778*4882a593Smuzhiyun aclc = car_loop_apsk_low[i].crl_pilots_on_5;
2779*4882a593Smuzhiyun else if (state->srate <= 15000000)
2780*4882a593Smuzhiyun aclc = car_loop_apsk_low[i].crl_pilots_on_10;
2781*4882a593Smuzhiyun else if (state->srate <= 25000000)
2782*4882a593Smuzhiyun aclc = car_loop_apsk_low[i].crl_pilots_on_20;
2783*4882a593Smuzhiyun else
2784*4882a593Smuzhiyun aclc = car_loop_apsk_low[i].crl_pilots_on_30;
2785*4882a593Smuzhiyun }
2786*4882a593Smuzhiyun
2787*4882a593Smuzhiyun return aclc;
2788*4882a593Smuzhiyun }
2789*4882a593Smuzhiyun
stv090x_optimize_carloop_short(struct stv090x_state * state)2790*4882a593Smuzhiyun static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2791*4882a593Smuzhiyun {
2792*4882a593Smuzhiyun struct stv090x_short_frame_crloop *short_crl = NULL;
2793*4882a593Smuzhiyun s32 index = 0;
2794*4882a593Smuzhiyun u8 aclc = 0x0b;
2795*4882a593Smuzhiyun
2796*4882a593Smuzhiyun switch (state->modulation) {
2797*4882a593Smuzhiyun case STV090x_QPSK:
2798*4882a593Smuzhiyun default:
2799*4882a593Smuzhiyun index = 0;
2800*4882a593Smuzhiyun break;
2801*4882a593Smuzhiyun case STV090x_8PSK:
2802*4882a593Smuzhiyun index = 1;
2803*4882a593Smuzhiyun break;
2804*4882a593Smuzhiyun case STV090x_16APSK:
2805*4882a593Smuzhiyun index = 2;
2806*4882a593Smuzhiyun break;
2807*4882a593Smuzhiyun case STV090x_32APSK:
2808*4882a593Smuzhiyun index = 3;
2809*4882a593Smuzhiyun break;
2810*4882a593Smuzhiyun }
2811*4882a593Smuzhiyun
2812*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x30) {
2813*4882a593Smuzhiyun /* Cut 3.0 and up */
2814*4882a593Smuzhiyun short_crl = stv090x_s2_short_crl_cut30;
2815*4882a593Smuzhiyun } else {
2816*4882a593Smuzhiyun /* Cut 2.0 and up: we don't support cuts older than 2.0 */
2817*4882a593Smuzhiyun short_crl = stv090x_s2_short_crl_cut20;
2818*4882a593Smuzhiyun }
2819*4882a593Smuzhiyun
2820*4882a593Smuzhiyun if (state->srate <= 3000000)
2821*4882a593Smuzhiyun aclc = short_crl[index].crl_2;
2822*4882a593Smuzhiyun else if (state->srate <= 7000000)
2823*4882a593Smuzhiyun aclc = short_crl[index].crl_5;
2824*4882a593Smuzhiyun else if (state->srate <= 15000000)
2825*4882a593Smuzhiyun aclc = short_crl[index].crl_10;
2826*4882a593Smuzhiyun else if (state->srate <= 25000000)
2827*4882a593Smuzhiyun aclc = short_crl[index].crl_20;
2828*4882a593Smuzhiyun else
2829*4882a593Smuzhiyun aclc = short_crl[index].crl_30;
2830*4882a593Smuzhiyun
2831*4882a593Smuzhiyun return aclc;
2832*4882a593Smuzhiyun }
2833*4882a593Smuzhiyun
stv090x_optimize_track(struct stv090x_state * state)2834*4882a593Smuzhiyun static int stv090x_optimize_track(struct stv090x_state *state)
2835*4882a593Smuzhiyun {
2836*4882a593Smuzhiyun struct dvb_frontend *fe = &state->frontend;
2837*4882a593Smuzhiyun
2838*4882a593Smuzhiyun enum stv090x_modcod modcod;
2839*4882a593Smuzhiyun
2840*4882a593Smuzhiyun s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2841*4882a593Smuzhiyun u32 reg;
2842*4882a593Smuzhiyun
2843*4882a593Smuzhiyun srate = stv090x_get_srate(state, state->internal->mclk);
2844*4882a593Smuzhiyun srate += stv090x_get_tmgoffst(state, srate);
2845*4882a593Smuzhiyun
2846*4882a593Smuzhiyun switch (state->delsys) {
2847*4882a593Smuzhiyun case STV090x_DVBS1:
2848*4882a593Smuzhiyun case STV090x_DSS:
2849*4882a593Smuzhiyun if (state->search_mode == STV090x_SEARCH_AUTO) {
2850*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2851*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2852*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2853*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2854*4882a593Smuzhiyun goto err;
2855*4882a593Smuzhiyun }
2856*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DEMOD);
2857*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2858*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
2859*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2860*4882a593Smuzhiyun goto err;
2861*4882a593Smuzhiyun
2862*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x30) {
2863*4882a593Smuzhiyun if (stv090x_get_viterbi(state) < 0)
2864*4882a593Smuzhiyun goto err;
2865*4882a593Smuzhiyun
2866*4882a593Smuzhiyun if (state->fec == STV090x_PR12) {
2867*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2868*4882a593Smuzhiyun goto err;
2869*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2870*4882a593Smuzhiyun goto err;
2871*4882a593Smuzhiyun } else {
2872*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2873*4882a593Smuzhiyun goto err;
2874*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2875*4882a593Smuzhiyun goto err;
2876*4882a593Smuzhiyun }
2877*4882a593Smuzhiyun }
2878*4882a593Smuzhiyun
2879*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2880*4882a593Smuzhiyun goto err;
2881*4882a593Smuzhiyun break;
2882*4882a593Smuzhiyun
2883*4882a593Smuzhiyun case STV090x_DVBS2:
2884*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2885*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2886*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2887*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2888*4882a593Smuzhiyun goto err;
2889*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x30) {
2890*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2891*4882a593Smuzhiyun goto err;
2892*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2893*4882a593Smuzhiyun goto err;
2894*4882a593Smuzhiyun }
2895*4882a593Smuzhiyun if (state->frame_len == STV090x_LONG_FRAME) {
2896*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2897*4882a593Smuzhiyun modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2898*4882a593Smuzhiyun pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2899*4882a593Smuzhiyun aclc = stv090x_optimize_carloop(state, modcod, pilots);
2900*4882a593Smuzhiyun if (modcod <= STV090x_QPSK_910) {
2901*4882a593Smuzhiyun STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2902*4882a593Smuzhiyun } else if (modcod <= STV090x_8PSK_910) {
2903*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2904*4882a593Smuzhiyun goto err;
2905*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2906*4882a593Smuzhiyun goto err;
2907*4882a593Smuzhiyun }
2908*4882a593Smuzhiyun if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2909*4882a593Smuzhiyun if (modcod <= STV090x_16APSK_910) {
2910*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2911*4882a593Smuzhiyun goto err;
2912*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2913*4882a593Smuzhiyun goto err;
2914*4882a593Smuzhiyun } else {
2915*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2916*4882a593Smuzhiyun goto err;
2917*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2918*4882a593Smuzhiyun goto err;
2919*4882a593Smuzhiyun }
2920*4882a593Smuzhiyun }
2921*4882a593Smuzhiyun } else {
2922*4882a593Smuzhiyun /*Carrier loop setting for short frame*/
2923*4882a593Smuzhiyun aclc = stv090x_optimize_carloop_short(state);
2924*4882a593Smuzhiyun if (state->modulation == STV090x_QPSK) {
2925*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2926*4882a593Smuzhiyun goto err;
2927*4882a593Smuzhiyun } else if (state->modulation == STV090x_8PSK) {
2928*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2929*4882a593Smuzhiyun goto err;
2930*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2931*4882a593Smuzhiyun goto err;
2932*4882a593Smuzhiyun } else if (state->modulation == STV090x_16APSK) {
2933*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2934*4882a593Smuzhiyun goto err;
2935*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2936*4882a593Smuzhiyun goto err;
2937*4882a593Smuzhiyun } else if (state->modulation == STV090x_32APSK) {
2938*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2939*4882a593Smuzhiyun goto err;
2940*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2941*4882a593Smuzhiyun goto err;
2942*4882a593Smuzhiyun }
2943*4882a593Smuzhiyun }
2944*4882a593Smuzhiyun
2945*4882a593Smuzhiyun STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2946*4882a593Smuzhiyun break;
2947*4882a593Smuzhiyun
2948*4882a593Smuzhiyun case STV090x_ERROR:
2949*4882a593Smuzhiyun default:
2950*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2951*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2952*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2953*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2954*4882a593Smuzhiyun goto err;
2955*4882a593Smuzhiyun break;
2956*4882a593Smuzhiyun }
2957*4882a593Smuzhiyun
2958*4882a593Smuzhiyun f_1 = STV090x_READ_DEMOD(state, CFR2);
2959*4882a593Smuzhiyun f_0 = STV090x_READ_DEMOD(state, CFR1);
2960*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, TMGOBS);
2961*4882a593Smuzhiyun
2962*4882a593Smuzhiyun if (state->algo == STV090x_BLIND_SEARCH) {
2963*4882a593Smuzhiyun STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2964*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2965*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2966*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2967*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2968*4882a593Smuzhiyun goto err;
2969*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2970*4882a593Smuzhiyun goto err;
2971*4882a593Smuzhiyun
2972*4882a593Smuzhiyun if (stv090x_set_srate(state, srate) < 0)
2973*4882a593Smuzhiyun goto err;
2974*4882a593Smuzhiyun blind_tune = 1;
2975*4882a593Smuzhiyun
2976*4882a593Smuzhiyun if (stv090x_dvbs_track_crl(state) < 0)
2977*4882a593Smuzhiyun goto err;
2978*4882a593Smuzhiyun }
2979*4882a593Smuzhiyun
2980*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
2981*4882a593Smuzhiyun if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2982*4882a593Smuzhiyun (state->search_mode == STV090x_SEARCH_DSS) ||
2983*4882a593Smuzhiyun (state->search_mode == STV090x_SEARCH_AUTO)) {
2984*4882a593Smuzhiyun
2985*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2986*4882a593Smuzhiyun goto err;
2987*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2988*4882a593Smuzhiyun goto err;
2989*4882a593Smuzhiyun }
2990*4882a593Smuzhiyun }
2991*4882a593Smuzhiyun
2992*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2993*4882a593Smuzhiyun goto err;
2994*4882a593Smuzhiyun
2995*4882a593Smuzhiyun /* AUTO tracking MODE */
2996*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
2997*4882a593Smuzhiyun goto err;
2998*4882a593Smuzhiyun /* AUTO tracking MODE */
2999*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
3000*4882a593Smuzhiyun goto err;
3001*4882a593Smuzhiyun
3002*4882a593Smuzhiyun if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
3003*4882a593Smuzhiyun (state->srate < 10000000)) {
3004*4882a593Smuzhiyun /* update initial carrier freq with the found freq offset */
3005*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3006*4882a593Smuzhiyun goto err;
3007*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3008*4882a593Smuzhiyun goto err;
3009*4882a593Smuzhiyun state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
3010*4882a593Smuzhiyun
3011*4882a593Smuzhiyun if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
3012*4882a593Smuzhiyun
3013*4882a593Smuzhiyun if (state->algo != STV090x_WARM_SEARCH) {
3014*4882a593Smuzhiyun
3015*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3016*4882a593Smuzhiyun goto err;
3017*4882a593Smuzhiyun
3018*4882a593Smuzhiyun if (state->config->tuner_set_bandwidth) {
3019*4882a593Smuzhiyun if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3020*4882a593Smuzhiyun goto err_gateoff;
3021*4882a593Smuzhiyun }
3022*4882a593Smuzhiyun
3023*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3024*4882a593Smuzhiyun goto err;
3025*4882a593Smuzhiyun
3026*4882a593Smuzhiyun }
3027*4882a593Smuzhiyun }
3028*4882a593Smuzhiyun if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
3029*4882a593Smuzhiyun msleep(50); /* blind search: wait 50ms for SR stabilization */
3030*4882a593Smuzhiyun else
3031*4882a593Smuzhiyun msleep(5);
3032*4882a593Smuzhiyun
3033*4882a593Smuzhiyun stv090x_get_lock_tmg(state);
3034*4882a593Smuzhiyun
3035*4882a593Smuzhiyun if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
3036*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3037*4882a593Smuzhiyun goto err;
3038*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3039*4882a593Smuzhiyun goto err;
3040*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3041*4882a593Smuzhiyun goto err;
3042*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3043*4882a593Smuzhiyun goto err;
3044*4882a593Smuzhiyun
3045*4882a593Smuzhiyun i = 0;
3046*4882a593Smuzhiyun
3047*4882a593Smuzhiyun while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
3048*4882a593Smuzhiyun
3049*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3050*4882a593Smuzhiyun goto err;
3051*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3052*4882a593Smuzhiyun goto err;
3053*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3054*4882a593Smuzhiyun goto err;
3055*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3056*4882a593Smuzhiyun goto err;
3057*4882a593Smuzhiyun i++;
3058*4882a593Smuzhiyun }
3059*4882a593Smuzhiyun }
3060*4882a593Smuzhiyun
3061*4882a593Smuzhiyun }
3062*4882a593Smuzhiyun
3063*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
3064*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
3065*4882a593Smuzhiyun goto err;
3066*4882a593Smuzhiyun }
3067*4882a593Smuzhiyun
3068*4882a593Smuzhiyun if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
3069*4882a593Smuzhiyun stv090x_set_vit_thtracq(state);
3070*4882a593Smuzhiyun
3071*4882a593Smuzhiyun return 0;
3072*4882a593Smuzhiyun
3073*4882a593Smuzhiyun err_gateoff:
3074*4882a593Smuzhiyun stv090x_i2c_gate_ctrl(state, 0);
3075*4882a593Smuzhiyun err:
3076*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
3077*4882a593Smuzhiyun return -1;
3078*4882a593Smuzhiyun }
3079*4882a593Smuzhiyun
stv090x_get_feclock(struct stv090x_state * state,s32 timeout)3080*4882a593Smuzhiyun static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
3081*4882a593Smuzhiyun {
3082*4882a593Smuzhiyun s32 timer = 0, lock = 0, stat;
3083*4882a593Smuzhiyun u32 reg;
3084*4882a593Smuzhiyun
3085*4882a593Smuzhiyun while ((timer < timeout) && (!lock)) {
3086*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDSTATE);
3087*4882a593Smuzhiyun stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3088*4882a593Smuzhiyun
3089*4882a593Smuzhiyun switch (stat) {
3090*4882a593Smuzhiyun case 0: /* searching */
3091*4882a593Smuzhiyun case 1: /* first PLH detected */
3092*4882a593Smuzhiyun default:
3093*4882a593Smuzhiyun lock = 0;
3094*4882a593Smuzhiyun break;
3095*4882a593Smuzhiyun
3096*4882a593Smuzhiyun case 2: /* DVB-S2 mode */
3097*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3098*4882a593Smuzhiyun lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
3099*4882a593Smuzhiyun break;
3100*4882a593Smuzhiyun
3101*4882a593Smuzhiyun case 3: /* DVB-S1/legacy mode */
3102*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3103*4882a593Smuzhiyun lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3104*4882a593Smuzhiyun break;
3105*4882a593Smuzhiyun }
3106*4882a593Smuzhiyun if (!lock) {
3107*4882a593Smuzhiyun msleep(10);
3108*4882a593Smuzhiyun timer += 10;
3109*4882a593Smuzhiyun }
3110*4882a593Smuzhiyun }
3111*4882a593Smuzhiyun return lock;
3112*4882a593Smuzhiyun }
3113*4882a593Smuzhiyun
stv090x_get_lock(struct stv090x_state * state,s32 timeout_dmd,s32 timeout_fec)3114*4882a593Smuzhiyun static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3115*4882a593Smuzhiyun {
3116*4882a593Smuzhiyun u32 reg;
3117*4882a593Smuzhiyun s32 timer = 0;
3118*4882a593Smuzhiyun int lock;
3119*4882a593Smuzhiyun
3120*4882a593Smuzhiyun lock = stv090x_get_dmdlock(state, timeout_dmd);
3121*4882a593Smuzhiyun if (lock)
3122*4882a593Smuzhiyun lock = stv090x_get_feclock(state, timeout_fec);
3123*4882a593Smuzhiyun
3124*4882a593Smuzhiyun if (lock) {
3125*4882a593Smuzhiyun lock = 0;
3126*4882a593Smuzhiyun
3127*4882a593Smuzhiyun while ((timer < timeout_fec) && (!lock)) {
3128*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, TSSTATUS);
3129*4882a593Smuzhiyun lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3130*4882a593Smuzhiyun msleep(1);
3131*4882a593Smuzhiyun timer++;
3132*4882a593Smuzhiyun }
3133*4882a593Smuzhiyun }
3134*4882a593Smuzhiyun
3135*4882a593Smuzhiyun return lock;
3136*4882a593Smuzhiyun }
3137*4882a593Smuzhiyun
stv090x_set_s2rolloff(struct stv090x_state * state)3138*4882a593Smuzhiyun static int stv090x_set_s2rolloff(struct stv090x_state *state)
3139*4882a593Smuzhiyun {
3140*4882a593Smuzhiyun u32 reg;
3141*4882a593Smuzhiyun
3142*4882a593Smuzhiyun if (state->internal->dev_ver <= 0x20) {
3143*4882a593Smuzhiyun /* rolloff to auto mode if DVBS2 */
3144*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DEMOD);
3145*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
3146*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3147*4882a593Smuzhiyun goto err;
3148*4882a593Smuzhiyun } else {
3149*4882a593Smuzhiyun /* DVB-S2 rolloff to auto mode if DVBS2 */
3150*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DEMOD);
3151*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
3152*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3153*4882a593Smuzhiyun goto err;
3154*4882a593Smuzhiyun }
3155*4882a593Smuzhiyun return 0;
3156*4882a593Smuzhiyun err:
3157*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
3158*4882a593Smuzhiyun return -1;
3159*4882a593Smuzhiyun }
3160*4882a593Smuzhiyun
3161*4882a593Smuzhiyun
stv090x_algo(struct stv090x_state * state)3162*4882a593Smuzhiyun static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3163*4882a593Smuzhiyun {
3164*4882a593Smuzhiyun struct dvb_frontend *fe = &state->frontend;
3165*4882a593Smuzhiyun enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3166*4882a593Smuzhiyun u32 reg;
3167*4882a593Smuzhiyun s32 agc1_power, power_iq = 0, i;
3168*4882a593Smuzhiyun int lock = 0, low_sr = 0;
3169*4882a593Smuzhiyun
3170*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, TSCFGH);
3171*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3172*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3173*4882a593Smuzhiyun goto err;
3174*4882a593Smuzhiyun
3175*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3176*4882a593Smuzhiyun goto err;
3177*4882a593Smuzhiyun
3178*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
3179*4882a593Smuzhiyun if (state->srate > 5000000) {
3180*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3181*4882a593Smuzhiyun goto err;
3182*4882a593Smuzhiyun } else {
3183*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3184*4882a593Smuzhiyun goto err;
3185*4882a593Smuzhiyun }
3186*4882a593Smuzhiyun }
3187*4882a593Smuzhiyun
3188*4882a593Smuzhiyun stv090x_get_lock_tmg(state);
3189*4882a593Smuzhiyun
3190*4882a593Smuzhiyun if (state->algo == STV090x_BLIND_SEARCH) {
3191*4882a593Smuzhiyun state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
3192*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3193*4882a593Smuzhiyun goto err;
3194*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3195*4882a593Smuzhiyun goto err;
3196*4882a593Smuzhiyun if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */
3197*4882a593Smuzhiyun goto err;
3198*4882a593Smuzhiyun } else {
3199*4882a593Smuzhiyun /* known srate */
3200*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3201*4882a593Smuzhiyun goto err;
3202*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3203*4882a593Smuzhiyun goto err;
3204*4882a593Smuzhiyun
3205*4882a593Smuzhiyun if (state->srate < 2000000) {
3206*4882a593Smuzhiyun /* SR < 2MSPS */
3207*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
3208*4882a593Smuzhiyun goto err;
3209*4882a593Smuzhiyun } else {
3210*4882a593Smuzhiyun /* SR >= 2Msps */
3211*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3212*4882a593Smuzhiyun goto err;
3213*4882a593Smuzhiyun }
3214*4882a593Smuzhiyun
3215*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3216*4882a593Smuzhiyun goto err;
3217*4882a593Smuzhiyun
3218*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
3219*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3220*4882a593Smuzhiyun goto err;
3221*4882a593Smuzhiyun if (state->algo == STV090x_COLD_SEARCH)
3222*4882a593Smuzhiyun state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
3223*4882a593Smuzhiyun else if (state->algo == STV090x_WARM_SEARCH)
3224*4882a593Smuzhiyun state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
3225*4882a593Smuzhiyun }
3226*4882a593Smuzhiyun
3227*4882a593Smuzhiyun /* if cold start or warm (Symbolrate is known)
3228*4882a593Smuzhiyun * use a Narrow symbol rate scan range
3229*4882a593Smuzhiyun */
3230*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3231*4882a593Smuzhiyun goto err;
3232*4882a593Smuzhiyun
3233*4882a593Smuzhiyun if (stv090x_set_srate(state, state->srate) < 0)
3234*4882a593Smuzhiyun goto err;
3235*4882a593Smuzhiyun
3236*4882a593Smuzhiyun if (stv090x_set_max_srate(state, state->internal->mclk,
3237*4882a593Smuzhiyun state->srate) < 0)
3238*4882a593Smuzhiyun goto err;
3239*4882a593Smuzhiyun if (stv090x_set_min_srate(state, state->internal->mclk,
3240*4882a593Smuzhiyun state->srate) < 0)
3241*4882a593Smuzhiyun goto err;
3242*4882a593Smuzhiyun
3243*4882a593Smuzhiyun if (state->srate >= 10000000)
3244*4882a593Smuzhiyun low_sr = 0;
3245*4882a593Smuzhiyun else
3246*4882a593Smuzhiyun low_sr = 1;
3247*4882a593Smuzhiyun }
3248*4882a593Smuzhiyun
3249*4882a593Smuzhiyun /* Setup tuner */
3250*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3251*4882a593Smuzhiyun goto err;
3252*4882a593Smuzhiyun
3253*4882a593Smuzhiyun if (state->config->tuner_set_bbgain) {
3254*4882a593Smuzhiyun reg = state->config->tuner_bbgain;
3255*4882a593Smuzhiyun if (reg == 0)
3256*4882a593Smuzhiyun reg = 10; /* default: 10dB */
3257*4882a593Smuzhiyun if (state->config->tuner_set_bbgain(fe, reg) < 0)
3258*4882a593Smuzhiyun goto err_gateoff;
3259*4882a593Smuzhiyun }
3260*4882a593Smuzhiyun
3261*4882a593Smuzhiyun if (state->config->tuner_set_frequency) {
3262*4882a593Smuzhiyun if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
3263*4882a593Smuzhiyun goto err_gateoff;
3264*4882a593Smuzhiyun }
3265*4882a593Smuzhiyun
3266*4882a593Smuzhiyun if (state->config->tuner_set_bandwidth) {
3267*4882a593Smuzhiyun if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3268*4882a593Smuzhiyun goto err_gateoff;
3269*4882a593Smuzhiyun }
3270*4882a593Smuzhiyun
3271*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3272*4882a593Smuzhiyun goto err;
3273*4882a593Smuzhiyun
3274*4882a593Smuzhiyun msleep(50);
3275*4882a593Smuzhiyun
3276*4882a593Smuzhiyun if (state->config->tuner_get_status) {
3277*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3278*4882a593Smuzhiyun goto err;
3279*4882a593Smuzhiyun if (state->config->tuner_get_status(fe, ®) < 0)
3280*4882a593Smuzhiyun goto err_gateoff;
3281*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3282*4882a593Smuzhiyun goto err;
3283*4882a593Smuzhiyun
3284*4882a593Smuzhiyun if (reg)
3285*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Tuner phase locked");
3286*4882a593Smuzhiyun else {
3287*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Tuner unlocked");
3288*4882a593Smuzhiyun return STV090x_NOCARRIER;
3289*4882a593Smuzhiyun }
3290*4882a593Smuzhiyun }
3291*4882a593Smuzhiyun
3292*4882a593Smuzhiyun msleep(10);
3293*4882a593Smuzhiyun agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3294*4882a593Smuzhiyun STV090x_READ_DEMOD(state, AGCIQIN0));
3295*4882a593Smuzhiyun
3296*4882a593Smuzhiyun if (agc1_power == 0) {
3297*4882a593Smuzhiyun /* If AGC1 integrator value is 0
3298*4882a593Smuzhiyun * then read POWERI, POWERQ
3299*4882a593Smuzhiyun */
3300*4882a593Smuzhiyun for (i = 0; i < 5; i++) {
3301*4882a593Smuzhiyun power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3302*4882a593Smuzhiyun STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3303*4882a593Smuzhiyun }
3304*4882a593Smuzhiyun power_iq /= 5;
3305*4882a593Smuzhiyun }
3306*4882a593Smuzhiyun
3307*4882a593Smuzhiyun if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3308*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3309*4882a593Smuzhiyun lock = 0;
3310*4882a593Smuzhiyun signal_state = STV090x_NOAGC1;
3311*4882a593Smuzhiyun } else {
3312*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DEMOD);
3313*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3314*4882a593Smuzhiyun
3315*4882a593Smuzhiyun if (state->internal->dev_ver <= 0x20) {
3316*4882a593Smuzhiyun /* rolloff to auto mode if DVBS2 */
3317*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3318*4882a593Smuzhiyun } else {
3319*4882a593Smuzhiyun /* DVB-S2 rolloff to auto mode if DVBS2 */
3320*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3321*4882a593Smuzhiyun }
3322*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3323*4882a593Smuzhiyun goto err;
3324*4882a593Smuzhiyun
3325*4882a593Smuzhiyun if (stv090x_delivery_search(state) < 0)
3326*4882a593Smuzhiyun goto err;
3327*4882a593Smuzhiyun
3328*4882a593Smuzhiyun if (state->algo != STV090x_BLIND_SEARCH) {
3329*4882a593Smuzhiyun if (stv090x_start_search(state) < 0)
3330*4882a593Smuzhiyun goto err;
3331*4882a593Smuzhiyun }
3332*4882a593Smuzhiyun }
3333*4882a593Smuzhiyun
3334*4882a593Smuzhiyun if (signal_state == STV090x_NOAGC1)
3335*4882a593Smuzhiyun return signal_state;
3336*4882a593Smuzhiyun
3337*4882a593Smuzhiyun if (state->algo == STV090x_BLIND_SEARCH)
3338*4882a593Smuzhiyun lock = stv090x_blind_search(state);
3339*4882a593Smuzhiyun
3340*4882a593Smuzhiyun else if (state->algo == STV090x_COLD_SEARCH)
3341*4882a593Smuzhiyun lock = stv090x_get_coldlock(state, state->DemodTimeout);
3342*4882a593Smuzhiyun
3343*4882a593Smuzhiyun else if (state->algo == STV090x_WARM_SEARCH)
3344*4882a593Smuzhiyun lock = stv090x_get_dmdlock(state, state->DemodTimeout);
3345*4882a593Smuzhiyun
3346*4882a593Smuzhiyun if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3347*4882a593Smuzhiyun if (!low_sr) {
3348*4882a593Smuzhiyun if (stv090x_chk_tmg(state))
3349*4882a593Smuzhiyun lock = stv090x_sw_algo(state);
3350*4882a593Smuzhiyun }
3351*4882a593Smuzhiyun }
3352*4882a593Smuzhiyun
3353*4882a593Smuzhiyun if (lock)
3354*4882a593Smuzhiyun signal_state = stv090x_get_sig_params(state);
3355*4882a593Smuzhiyun
3356*4882a593Smuzhiyun if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3357*4882a593Smuzhiyun stv090x_optimize_track(state);
3358*4882a593Smuzhiyun
3359*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
3360*4882a593Smuzhiyun /* >= Cut 2.0 :release TS reset after
3361*4882a593Smuzhiyun * demod lock and optimized Tracking
3362*4882a593Smuzhiyun */
3363*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, TSCFGH);
3364*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3365*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3366*4882a593Smuzhiyun goto err;
3367*4882a593Smuzhiyun
3368*4882a593Smuzhiyun msleep(3);
3369*4882a593Smuzhiyun
3370*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3371*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3372*4882a593Smuzhiyun goto err;
3373*4882a593Smuzhiyun
3374*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3375*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3376*4882a593Smuzhiyun goto err;
3377*4882a593Smuzhiyun }
3378*4882a593Smuzhiyun
3379*4882a593Smuzhiyun lock = stv090x_get_lock(state, state->FecTimeout,
3380*4882a593Smuzhiyun state->FecTimeout);
3381*4882a593Smuzhiyun if (lock) {
3382*4882a593Smuzhiyun if (state->delsys == STV090x_DVBS2) {
3383*4882a593Smuzhiyun stv090x_set_s2rolloff(state);
3384*4882a593Smuzhiyun
3385*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3386*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3387*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3388*4882a593Smuzhiyun goto err;
3389*4882a593Smuzhiyun /* Reset DVBS2 packet delinator error counter */
3390*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3391*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3392*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3393*4882a593Smuzhiyun goto err;
3394*4882a593Smuzhiyun
3395*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3396*4882a593Smuzhiyun goto err;
3397*4882a593Smuzhiyun } else {
3398*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3399*4882a593Smuzhiyun goto err;
3400*4882a593Smuzhiyun }
3401*4882a593Smuzhiyun /* Reset the Total packet counter */
3402*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3403*4882a593Smuzhiyun goto err;
3404*4882a593Smuzhiyun /* Reset the packet Error counter2 */
3405*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3406*4882a593Smuzhiyun goto err;
3407*4882a593Smuzhiyun } else {
3408*4882a593Smuzhiyun signal_state = STV090x_NODATA;
3409*4882a593Smuzhiyun stv090x_chk_signal(state);
3410*4882a593Smuzhiyun }
3411*4882a593Smuzhiyun }
3412*4882a593Smuzhiyun return signal_state;
3413*4882a593Smuzhiyun
3414*4882a593Smuzhiyun err_gateoff:
3415*4882a593Smuzhiyun stv090x_i2c_gate_ctrl(state, 0);
3416*4882a593Smuzhiyun err:
3417*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
3418*4882a593Smuzhiyun return -1;
3419*4882a593Smuzhiyun }
3420*4882a593Smuzhiyun
stv090x_set_pls(struct stv090x_state * state,u32 pls_code)3421*4882a593Smuzhiyun static int stv090x_set_pls(struct stv090x_state *state, u32 pls_code)
3422*4882a593Smuzhiyun {
3423*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Set Gold PLS code %d", pls_code);
3424*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PLROOT0, pls_code & 0xff) < 0)
3425*4882a593Smuzhiyun goto err;
3426*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PLROOT1, (pls_code >> 8) & 0xff) < 0)
3427*4882a593Smuzhiyun goto err;
3428*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PLROOT2, 0x04 | (pls_code >> 16)) < 0)
3429*4882a593Smuzhiyun goto err;
3430*4882a593Smuzhiyun return 0;
3431*4882a593Smuzhiyun err:
3432*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
3433*4882a593Smuzhiyun return -1;
3434*4882a593Smuzhiyun }
3435*4882a593Smuzhiyun
stv090x_set_mis(struct stv090x_state * state,int mis)3436*4882a593Smuzhiyun static int stv090x_set_mis(struct stv090x_state *state, int mis)
3437*4882a593Smuzhiyun {
3438*4882a593Smuzhiyun u32 reg;
3439*4882a593Smuzhiyun
3440*4882a593Smuzhiyun if (mis < 0 || mis > 255) {
3441*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Disable MIS filtering");
3442*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3443*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00);
3444*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3445*4882a593Smuzhiyun goto err;
3446*4882a593Smuzhiyun } else {
3447*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis);
3448*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3449*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01);
3450*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3451*4882a593Smuzhiyun goto err;
3452*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0)
3453*4882a593Smuzhiyun goto err;
3454*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0)
3455*4882a593Smuzhiyun goto err;
3456*4882a593Smuzhiyun }
3457*4882a593Smuzhiyun return 0;
3458*4882a593Smuzhiyun err:
3459*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
3460*4882a593Smuzhiyun return -1;
3461*4882a593Smuzhiyun }
3462*4882a593Smuzhiyun
stv090x_search(struct dvb_frontend * fe)3463*4882a593Smuzhiyun static enum dvbfe_search stv090x_search(struct dvb_frontend *fe)
3464*4882a593Smuzhiyun {
3465*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
3466*4882a593Smuzhiyun struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3467*4882a593Smuzhiyun
3468*4882a593Smuzhiyun if (props->frequency == 0)
3469*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_INVALID;
3470*4882a593Smuzhiyun
3471*4882a593Smuzhiyun switch (props->delivery_system) {
3472*4882a593Smuzhiyun case SYS_DSS:
3473*4882a593Smuzhiyun state->delsys = STV090x_DSS;
3474*4882a593Smuzhiyun break;
3475*4882a593Smuzhiyun case SYS_DVBS:
3476*4882a593Smuzhiyun state->delsys = STV090x_DVBS1;
3477*4882a593Smuzhiyun break;
3478*4882a593Smuzhiyun case SYS_DVBS2:
3479*4882a593Smuzhiyun state->delsys = STV090x_DVBS2;
3480*4882a593Smuzhiyun break;
3481*4882a593Smuzhiyun default:
3482*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_INVALID;
3483*4882a593Smuzhiyun }
3484*4882a593Smuzhiyun
3485*4882a593Smuzhiyun state->frequency = props->frequency;
3486*4882a593Smuzhiyun state->srate = props->symbol_rate;
3487*4882a593Smuzhiyun state->search_mode = STV090x_SEARCH_AUTO;
3488*4882a593Smuzhiyun state->algo = STV090x_COLD_SEARCH;
3489*4882a593Smuzhiyun state->fec = STV090x_PRERR;
3490*4882a593Smuzhiyun if (state->srate > 10000000) {
3491*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3492*4882a593Smuzhiyun state->search_range = 10000000;
3493*4882a593Smuzhiyun } else {
3494*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3495*4882a593Smuzhiyun state->search_range = 5000000;
3496*4882a593Smuzhiyun }
3497*4882a593Smuzhiyun
3498*4882a593Smuzhiyun stv090x_set_pls(state, props->scrambling_sequence_index);
3499*4882a593Smuzhiyun stv090x_set_mis(state, props->stream_id);
3500*4882a593Smuzhiyun
3501*4882a593Smuzhiyun if (stv090x_algo(state) == STV090x_RANGEOK) {
3502*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Search success!");
3503*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_SUCCESS;
3504*4882a593Smuzhiyun } else {
3505*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Search failed!");
3506*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_FAILED;
3507*4882a593Smuzhiyun }
3508*4882a593Smuzhiyun
3509*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_ERROR;
3510*4882a593Smuzhiyun }
3511*4882a593Smuzhiyun
stv090x_read_status(struct dvb_frontend * fe,enum fe_status * status)3512*4882a593Smuzhiyun static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3513*4882a593Smuzhiyun {
3514*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
3515*4882a593Smuzhiyun u32 reg, dstatus;
3516*4882a593Smuzhiyun u8 search_state;
3517*4882a593Smuzhiyun
3518*4882a593Smuzhiyun *status = 0;
3519*4882a593Smuzhiyun
3520*4882a593Smuzhiyun dstatus = STV090x_READ_DEMOD(state, DSTATUS);
3521*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD))
3522*4882a593Smuzhiyun *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
3523*4882a593Smuzhiyun
3524*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DMDSTATE);
3525*4882a593Smuzhiyun search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3526*4882a593Smuzhiyun
3527*4882a593Smuzhiyun switch (search_state) {
3528*4882a593Smuzhiyun case 0: /* searching */
3529*4882a593Smuzhiyun case 1: /* first PLH detected */
3530*4882a593Smuzhiyun default:
3531*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3532*4882a593Smuzhiyun break;
3533*4882a593Smuzhiyun
3534*4882a593Smuzhiyun case 2: /* DVB-S2 mode */
3535*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3536*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
3537*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3538*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3539*4882a593Smuzhiyun *status |= FE_HAS_VITERBI;
3540*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, TSSTATUS);
3541*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
3542*4882a593Smuzhiyun *status |= FE_HAS_SYNC | FE_HAS_LOCK;
3543*4882a593Smuzhiyun }
3544*4882a593Smuzhiyun }
3545*4882a593Smuzhiyun break;
3546*4882a593Smuzhiyun
3547*4882a593Smuzhiyun case 3: /* DVB-S1/legacy mode */
3548*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3549*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
3550*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3551*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3552*4882a593Smuzhiyun *status |= FE_HAS_VITERBI;
3553*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, TSSTATUS);
3554*4882a593Smuzhiyun if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
3555*4882a593Smuzhiyun *status |= FE_HAS_SYNC | FE_HAS_LOCK;
3556*4882a593Smuzhiyun }
3557*4882a593Smuzhiyun }
3558*4882a593Smuzhiyun break;
3559*4882a593Smuzhiyun }
3560*4882a593Smuzhiyun
3561*4882a593Smuzhiyun return 0;
3562*4882a593Smuzhiyun }
3563*4882a593Smuzhiyun
stv090x_read_per(struct dvb_frontend * fe,u32 * per)3564*4882a593Smuzhiyun static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3565*4882a593Smuzhiyun {
3566*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
3567*4882a593Smuzhiyun
3568*4882a593Smuzhiyun s32 count_4, count_3, count_2, count_1, count_0, count;
3569*4882a593Smuzhiyun u32 reg, h, m, l;
3570*4882a593Smuzhiyun enum fe_status status;
3571*4882a593Smuzhiyun
3572*4882a593Smuzhiyun stv090x_read_status(fe, &status);
3573*4882a593Smuzhiyun if (!(status & FE_HAS_LOCK)) {
3574*4882a593Smuzhiyun *per = 1 << 23; /* Max PER */
3575*4882a593Smuzhiyun } else {
3576*4882a593Smuzhiyun /* Counter 2 */
3577*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, ERRCNT22);
3578*4882a593Smuzhiyun h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3579*4882a593Smuzhiyun
3580*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, ERRCNT21);
3581*4882a593Smuzhiyun m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3582*4882a593Smuzhiyun
3583*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, ERRCNT20);
3584*4882a593Smuzhiyun l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3585*4882a593Smuzhiyun
3586*4882a593Smuzhiyun *per = ((h << 16) | (m << 8) | l);
3587*4882a593Smuzhiyun
3588*4882a593Smuzhiyun count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3589*4882a593Smuzhiyun count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3590*4882a593Smuzhiyun count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3591*4882a593Smuzhiyun count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3592*4882a593Smuzhiyun count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3593*4882a593Smuzhiyun
3594*4882a593Smuzhiyun if ((!count_4) && (!count_3)) {
3595*4882a593Smuzhiyun count = (count_2 & 0xff) << 16;
3596*4882a593Smuzhiyun count |= (count_1 & 0xff) << 8;
3597*4882a593Smuzhiyun count |= count_0 & 0xff;
3598*4882a593Smuzhiyun } else {
3599*4882a593Smuzhiyun count = 1 << 24;
3600*4882a593Smuzhiyun }
3601*4882a593Smuzhiyun if (count == 0)
3602*4882a593Smuzhiyun *per = 1;
3603*4882a593Smuzhiyun }
3604*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3605*4882a593Smuzhiyun goto err;
3606*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3607*4882a593Smuzhiyun goto err;
3608*4882a593Smuzhiyun
3609*4882a593Smuzhiyun return 0;
3610*4882a593Smuzhiyun err:
3611*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
3612*4882a593Smuzhiyun return -1;
3613*4882a593Smuzhiyun }
3614*4882a593Smuzhiyun
stv090x_table_lookup(const struct stv090x_tab * tab,int max,int val)3615*4882a593Smuzhiyun static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3616*4882a593Smuzhiyun {
3617*4882a593Smuzhiyun int res = 0;
3618*4882a593Smuzhiyun int min = 0, med;
3619*4882a593Smuzhiyun
3620*4882a593Smuzhiyun if ((val >= tab[min].read && val < tab[max].read) ||
3621*4882a593Smuzhiyun (val >= tab[max].read && val < tab[min].read)) {
3622*4882a593Smuzhiyun while ((max - min) > 1) {
3623*4882a593Smuzhiyun med = (max + min) / 2;
3624*4882a593Smuzhiyun if ((val >= tab[min].read && val < tab[med].read) ||
3625*4882a593Smuzhiyun (val >= tab[med].read && val < tab[min].read))
3626*4882a593Smuzhiyun max = med;
3627*4882a593Smuzhiyun else
3628*4882a593Smuzhiyun min = med;
3629*4882a593Smuzhiyun }
3630*4882a593Smuzhiyun res = ((val - tab[min].read) *
3631*4882a593Smuzhiyun (tab[max].real - tab[min].real) /
3632*4882a593Smuzhiyun (tab[max].read - tab[min].read)) +
3633*4882a593Smuzhiyun tab[min].real;
3634*4882a593Smuzhiyun } else {
3635*4882a593Smuzhiyun if (tab[min].read < tab[max].read) {
3636*4882a593Smuzhiyun if (val < tab[min].read)
3637*4882a593Smuzhiyun res = tab[min].real;
3638*4882a593Smuzhiyun else if (val >= tab[max].read)
3639*4882a593Smuzhiyun res = tab[max].real;
3640*4882a593Smuzhiyun } else {
3641*4882a593Smuzhiyun if (val >= tab[min].read)
3642*4882a593Smuzhiyun res = tab[min].real;
3643*4882a593Smuzhiyun else if (val < tab[max].read)
3644*4882a593Smuzhiyun res = tab[max].real;
3645*4882a593Smuzhiyun }
3646*4882a593Smuzhiyun }
3647*4882a593Smuzhiyun
3648*4882a593Smuzhiyun return res;
3649*4882a593Smuzhiyun }
3650*4882a593Smuzhiyun
stv090x_read_signal_strength(struct dvb_frontend * fe,u16 * strength)3651*4882a593Smuzhiyun static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3652*4882a593Smuzhiyun {
3653*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
3654*4882a593Smuzhiyun u32 reg;
3655*4882a593Smuzhiyun s32 agc_0, agc_1, agc;
3656*4882a593Smuzhiyun s32 str;
3657*4882a593Smuzhiyun
3658*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3659*4882a593Smuzhiyun agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3660*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3661*4882a593Smuzhiyun agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3662*4882a593Smuzhiyun agc = MAKEWORD16(agc_1, agc_0);
3663*4882a593Smuzhiyun
3664*4882a593Smuzhiyun str = stv090x_table_lookup(stv090x_rf_tab,
3665*4882a593Smuzhiyun ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3666*4882a593Smuzhiyun if (agc > stv090x_rf_tab[0].read)
3667*4882a593Smuzhiyun str = 0;
3668*4882a593Smuzhiyun else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3669*4882a593Smuzhiyun str = -100;
3670*4882a593Smuzhiyun *strength = (str + 100) * 0xFFFF / 100;
3671*4882a593Smuzhiyun
3672*4882a593Smuzhiyun return 0;
3673*4882a593Smuzhiyun }
3674*4882a593Smuzhiyun
stv090x_read_cnr(struct dvb_frontend * fe,u16 * cnr)3675*4882a593Smuzhiyun static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3676*4882a593Smuzhiyun {
3677*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
3678*4882a593Smuzhiyun u32 reg_0, reg_1, reg, i;
3679*4882a593Smuzhiyun s32 val_0, val_1, val = 0;
3680*4882a593Smuzhiyun u8 lock_f;
3681*4882a593Smuzhiyun s32 div;
3682*4882a593Smuzhiyun u32 last;
3683*4882a593Smuzhiyun
3684*4882a593Smuzhiyun switch (state->delsys) {
3685*4882a593Smuzhiyun case STV090x_DVBS2:
3686*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DSTATUS);
3687*4882a593Smuzhiyun lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3688*4882a593Smuzhiyun if (lock_f) {
3689*4882a593Smuzhiyun msleep(5);
3690*4882a593Smuzhiyun for (i = 0; i < 16; i++) {
3691*4882a593Smuzhiyun reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3692*4882a593Smuzhiyun val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3693*4882a593Smuzhiyun reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3694*4882a593Smuzhiyun val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
3695*4882a593Smuzhiyun val += MAKEWORD16(val_1, val_0);
3696*4882a593Smuzhiyun msleep(1);
3697*4882a593Smuzhiyun }
3698*4882a593Smuzhiyun val /= 16;
3699*4882a593Smuzhiyun last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3700*4882a593Smuzhiyun div = stv090x_s2cn_tab[last].real -
3701*4882a593Smuzhiyun stv090x_s2cn_tab[3].real;
3702*4882a593Smuzhiyun val = stv090x_table_lookup(stv090x_s2cn_tab, last, val);
3703*4882a593Smuzhiyun if (val < 0)
3704*4882a593Smuzhiyun val = 0;
3705*4882a593Smuzhiyun *cnr = val * 0xFFFF / div;
3706*4882a593Smuzhiyun }
3707*4882a593Smuzhiyun break;
3708*4882a593Smuzhiyun
3709*4882a593Smuzhiyun case STV090x_DVBS1:
3710*4882a593Smuzhiyun case STV090x_DSS:
3711*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DSTATUS);
3712*4882a593Smuzhiyun lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3713*4882a593Smuzhiyun if (lock_f) {
3714*4882a593Smuzhiyun msleep(5);
3715*4882a593Smuzhiyun for (i = 0; i < 16; i++) {
3716*4882a593Smuzhiyun reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3717*4882a593Smuzhiyun val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3718*4882a593Smuzhiyun reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3719*4882a593Smuzhiyun val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
3720*4882a593Smuzhiyun val += MAKEWORD16(val_1, val_0);
3721*4882a593Smuzhiyun msleep(1);
3722*4882a593Smuzhiyun }
3723*4882a593Smuzhiyun val /= 16;
3724*4882a593Smuzhiyun last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3725*4882a593Smuzhiyun div = stv090x_s1cn_tab[last].real -
3726*4882a593Smuzhiyun stv090x_s1cn_tab[0].real;
3727*4882a593Smuzhiyun val = stv090x_table_lookup(stv090x_s1cn_tab, last, val);
3728*4882a593Smuzhiyun *cnr = val * 0xFFFF / div;
3729*4882a593Smuzhiyun }
3730*4882a593Smuzhiyun break;
3731*4882a593Smuzhiyun default:
3732*4882a593Smuzhiyun break;
3733*4882a593Smuzhiyun }
3734*4882a593Smuzhiyun
3735*4882a593Smuzhiyun return 0;
3736*4882a593Smuzhiyun }
3737*4882a593Smuzhiyun
stv090x_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)3738*4882a593Smuzhiyun static int stv090x_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
3739*4882a593Smuzhiyun {
3740*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
3741*4882a593Smuzhiyun u32 reg;
3742*4882a593Smuzhiyun
3743*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DISTXCTL);
3744*4882a593Smuzhiyun switch (tone) {
3745*4882a593Smuzhiyun case SEC_TONE_ON:
3746*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3747*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3748*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3749*4882a593Smuzhiyun goto err;
3750*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3751*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3752*4882a593Smuzhiyun goto err;
3753*4882a593Smuzhiyun break;
3754*4882a593Smuzhiyun
3755*4882a593Smuzhiyun case SEC_TONE_OFF:
3756*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3757*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3758*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3759*4882a593Smuzhiyun goto err;
3760*4882a593Smuzhiyun break;
3761*4882a593Smuzhiyun default:
3762*4882a593Smuzhiyun return -EINVAL;
3763*4882a593Smuzhiyun }
3764*4882a593Smuzhiyun
3765*4882a593Smuzhiyun return 0;
3766*4882a593Smuzhiyun err:
3767*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
3768*4882a593Smuzhiyun return -1;
3769*4882a593Smuzhiyun }
3770*4882a593Smuzhiyun
3771*4882a593Smuzhiyun
stv090x_frontend_algo(struct dvb_frontend * fe)3772*4882a593Smuzhiyun static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3773*4882a593Smuzhiyun {
3774*4882a593Smuzhiyun return DVBFE_ALGO_CUSTOM;
3775*4882a593Smuzhiyun }
3776*4882a593Smuzhiyun
stv090x_send_diseqc_msg(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)3777*4882a593Smuzhiyun static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3778*4882a593Smuzhiyun {
3779*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
3780*4882a593Smuzhiyun u32 reg, idle = 0, fifo_full = 1;
3781*4882a593Smuzhiyun int i;
3782*4882a593Smuzhiyun
3783*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DISTXCTL);
3784*4882a593Smuzhiyun
3785*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
3786*4882a593Smuzhiyun (state->config->diseqc_envelope_mode) ? 4 : 2);
3787*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3788*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3789*4882a593Smuzhiyun goto err;
3790*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3791*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3792*4882a593Smuzhiyun goto err;
3793*4882a593Smuzhiyun
3794*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3795*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3796*4882a593Smuzhiyun goto err;
3797*4882a593Smuzhiyun
3798*4882a593Smuzhiyun for (i = 0; i < cmd->msg_len; i++) {
3799*4882a593Smuzhiyun
3800*4882a593Smuzhiyun while (fifo_full) {
3801*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3802*4882a593Smuzhiyun fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3803*4882a593Smuzhiyun }
3804*4882a593Smuzhiyun
3805*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3806*4882a593Smuzhiyun goto err;
3807*4882a593Smuzhiyun }
3808*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DISTXCTL);
3809*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3810*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3811*4882a593Smuzhiyun goto err;
3812*4882a593Smuzhiyun
3813*4882a593Smuzhiyun i = 0;
3814*4882a593Smuzhiyun
3815*4882a593Smuzhiyun while ((!idle) && (i < 10)) {
3816*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3817*4882a593Smuzhiyun idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3818*4882a593Smuzhiyun msleep(10);
3819*4882a593Smuzhiyun i++;
3820*4882a593Smuzhiyun }
3821*4882a593Smuzhiyun
3822*4882a593Smuzhiyun return 0;
3823*4882a593Smuzhiyun err:
3824*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
3825*4882a593Smuzhiyun return -1;
3826*4882a593Smuzhiyun }
3827*4882a593Smuzhiyun
stv090x_send_diseqc_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd burst)3828*4882a593Smuzhiyun static int stv090x_send_diseqc_burst(struct dvb_frontend *fe,
3829*4882a593Smuzhiyun enum fe_sec_mini_cmd burst)
3830*4882a593Smuzhiyun {
3831*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
3832*4882a593Smuzhiyun u32 reg, idle = 0, fifo_full = 1;
3833*4882a593Smuzhiyun u8 mode, value;
3834*4882a593Smuzhiyun int i;
3835*4882a593Smuzhiyun
3836*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DISTXCTL);
3837*4882a593Smuzhiyun
3838*4882a593Smuzhiyun if (burst == SEC_MINI_A) {
3839*4882a593Smuzhiyun mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
3840*4882a593Smuzhiyun value = 0x00;
3841*4882a593Smuzhiyun } else {
3842*4882a593Smuzhiyun mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
3843*4882a593Smuzhiyun value = 0xFF;
3844*4882a593Smuzhiyun }
3845*4882a593Smuzhiyun
3846*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3847*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3848*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3849*4882a593Smuzhiyun goto err;
3850*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3851*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3852*4882a593Smuzhiyun goto err;
3853*4882a593Smuzhiyun
3854*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3855*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3856*4882a593Smuzhiyun goto err;
3857*4882a593Smuzhiyun
3858*4882a593Smuzhiyun while (fifo_full) {
3859*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3860*4882a593Smuzhiyun fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3861*4882a593Smuzhiyun }
3862*4882a593Smuzhiyun
3863*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3864*4882a593Smuzhiyun goto err;
3865*4882a593Smuzhiyun
3866*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DISTXCTL);
3867*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3868*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3869*4882a593Smuzhiyun goto err;
3870*4882a593Smuzhiyun
3871*4882a593Smuzhiyun i = 0;
3872*4882a593Smuzhiyun
3873*4882a593Smuzhiyun while ((!idle) && (i < 10)) {
3874*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3875*4882a593Smuzhiyun idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3876*4882a593Smuzhiyun msleep(10);
3877*4882a593Smuzhiyun i++;
3878*4882a593Smuzhiyun }
3879*4882a593Smuzhiyun
3880*4882a593Smuzhiyun return 0;
3881*4882a593Smuzhiyun err:
3882*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
3883*4882a593Smuzhiyun return -1;
3884*4882a593Smuzhiyun }
3885*4882a593Smuzhiyun
stv090x_recv_slave_reply(struct dvb_frontend * fe,struct dvb_diseqc_slave_reply * reply)3886*4882a593Smuzhiyun static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3887*4882a593Smuzhiyun {
3888*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
3889*4882a593Smuzhiyun u32 reg = 0, i = 0, rx_end = 0;
3890*4882a593Smuzhiyun
3891*4882a593Smuzhiyun while ((rx_end != 1) && (i < 10)) {
3892*4882a593Smuzhiyun msleep(10);
3893*4882a593Smuzhiyun i++;
3894*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3895*4882a593Smuzhiyun rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3896*4882a593Smuzhiyun }
3897*4882a593Smuzhiyun
3898*4882a593Smuzhiyun if (rx_end) {
3899*4882a593Smuzhiyun reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3900*4882a593Smuzhiyun for (i = 0; i < reply->msg_len; i++)
3901*4882a593Smuzhiyun reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3902*4882a593Smuzhiyun }
3903*4882a593Smuzhiyun
3904*4882a593Smuzhiyun return 0;
3905*4882a593Smuzhiyun }
3906*4882a593Smuzhiyun
stv090x_sleep(struct dvb_frontend * fe)3907*4882a593Smuzhiyun static int stv090x_sleep(struct dvb_frontend *fe)
3908*4882a593Smuzhiyun {
3909*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
3910*4882a593Smuzhiyun u32 reg;
3911*4882a593Smuzhiyun u8 full_standby = 0;
3912*4882a593Smuzhiyun
3913*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3914*4882a593Smuzhiyun goto err;
3915*4882a593Smuzhiyun
3916*4882a593Smuzhiyun if (state->config->tuner_sleep) {
3917*4882a593Smuzhiyun if (state->config->tuner_sleep(fe) < 0)
3918*4882a593Smuzhiyun goto err_gateoff;
3919*4882a593Smuzhiyun }
3920*4882a593Smuzhiyun
3921*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3922*4882a593Smuzhiyun goto err;
3923*4882a593Smuzhiyun
3924*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep",
3925*4882a593Smuzhiyun state->device == STV0900 ? "STV0900" : "STV0903",
3926*4882a593Smuzhiyun state->demod);
3927*4882a593Smuzhiyun
3928*4882a593Smuzhiyun mutex_lock(&state->internal->demod_lock);
3929*4882a593Smuzhiyun
3930*4882a593Smuzhiyun switch (state->demod) {
3931*4882a593Smuzhiyun case STV090x_DEMODULATOR_0:
3932*4882a593Smuzhiyun /* power off ADC 1 */
3933*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3934*4882a593Smuzhiyun STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3935*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3936*4882a593Smuzhiyun goto err_unlock;
3937*4882a593Smuzhiyun /* power off DiSEqC 1 */
3938*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR2);
3939*4882a593Smuzhiyun STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0);
3940*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
3941*4882a593Smuzhiyun goto err_unlock;
3942*4882a593Smuzhiyun
3943*4882a593Smuzhiyun /* check whether path 2 is already sleeping, that is when
3944*4882a593Smuzhiyun ADC2 is off */
3945*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3946*4882a593Smuzhiyun if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0)
3947*4882a593Smuzhiyun full_standby = 1;
3948*4882a593Smuzhiyun
3949*4882a593Smuzhiyun /* stop clocks */
3950*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3951*4882a593Smuzhiyun /* packet delineator 1 clock */
3952*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1);
3953*4882a593Smuzhiyun /* ADC 1 clock */
3954*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1);
3955*4882a593Smuzhiyun /* FEC clock is shared between the two paths, only stop it
3956*4882a593Smuzhiyun when full standby is possible */
3957*4882a593Smuzhiyun if (full_standby)
3958*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
3959*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
3960*4882a593Smuzhiyun goto err_unlock;
3961*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_STOPCLK2);
3962*4882a593Smuzhiyun /* sampling 1 clock */
3963*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1);
3964*4882a593Smuzhiyun /* viterbi 1 clock */
3965*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1);
3966*4882a593Smuzhiyun /* TS clock is shared between the two paths, only stop it
3967*4882a593Smuzhiyun when full standby is possible */
3968*4882a593Smuzhiyun if (full_standby)
3969*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
3970*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
3971*4882a593Smuzhiyun goto err_unlock;
3972*4882a593Smuzhiyun break;
3973*4882a593Smuzhiyun
3974*4882a593Smuzhiyun case STV090x_DEMODULATOR_1:
3975*4882a593Smuzhiyun /* power off ADC 2 */
3976*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3977*4882a593Smuzhiyun STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0);
3978*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
3979*4882a593Smuzhiyun goto err_unlock;
3980*4882a593Smuzhiyun /* power off DiSEqC 2 */
3981*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR4);
3982*4882a593Smuzhiyun STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0);
3983*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
3984*4882a593Smuzhiyun goto err_unlock;
3985*4882a593Smuzhiyun
3986*4882a593Smuzhiyun /* check whether path 1 is already sleeping, that is when
3987*4882a593Smuzhiyun ADC1 is off */
3988*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3989*4882a593Smuzhiyun if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0)
3990*4882a593Smuzhiyun full_standby = 1;
3991*4882a593Smuzhiyun
3992*4882a593Smuzhiyun /* stop clocks */
3993*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3994*4882a593Smuzhiyun /* packet delineator 2 clock */
3995*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1);
3996*4882a593Smuzhiyun /* ADC 2 clock */
3997*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1);
3998*4882a593Smuzhiyun /* FEC clock is shared between the two paths, only stop it
3999*4882a593Smuzhiyun when full standby is possible */
4000*4882a593Smuzhiyun if (full_standby)
4001*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
4002*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4003*4882a593Smuzhiyun goto err_unlock;
4004*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4005*4882a593Smuzhiyun /* sampling 2 clock */
4006*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1);
4007*4882a593Smuzhiyun /* viterbi 2 clock */
4008*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1);
4009*4882a593Smuzhiyun /* TS clock is shared between the two paths, only stop it
4010*4882a593Smuzhiyun when full standby is possible */
4011*4882a593Smuzhiyun if (full_standby)
4012*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
4013*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4014*4882a593Smuzhiyun goto err_unlock;
4015*4882a593Smuzhiyun break;
4016*4882a593Smuzhiyun
4017*4882a593Smuzhiyun default:
4018*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "Wrong demodulator!");
4019*4882a593Smuzhiyun break;
4020*4882a593Smuzhiyun }
4021*4882a593Smuzhiyun
4022*4882a593Smuzhiyun if (full_standby) {
4023*4882a593Smuzhiyun /* general power off */
4024*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4025*4882a593Smuzhiyun STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
4026*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4027*4882a593Smuzhiyun goto err_unlock;
4028*4882a593Smuzhiyun }
4029*4882a593Smuzhiyun
4030*4882a593Smuzhiyun mutex_unlock(&state->internal->demod_lock);
4031*4882a593Smuzhiyun return 0;
4032*4882a593Smuzhiyun
4033*4882a593Smuzhiyun err_gateoff:
4034*4882a593Smuzhiyun stv090x_i2c_gate_ctrl(state, 0);
4035*4882a593Smuzhiyun goto err;
4036*4882a593Smuzhiyun err_unlock:
4037*4882a593Smuzhiyun mutex_unlock(&state->internal->demod_lock);
4038*4882a593Smuzhiyun err:
4039*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
4040*4882a593Smuzhiyun return -1;
4041*4882a593Smuzhiyun }
4042*4882a593Smuzhiyun
stv090x_wakeup(struct dvb_frontend * fe)4043*4882a593Smuzhiyun static int stv090x_wakeup(struct dvb_frontend *fe)
4044*4882a593Smuzhiyun {
4045*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
4046*4882a593Smuzhiyun u32 reg;
4047*4882a593Smuzhiyun
4048*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby",
4049*4882a593Smuzhiyun state->device == STV0900 ? "STV0900" : "STV0903",
4050*4882a593Smuzhiyun state->demod);
4051*4882a593Smuzhiyun
4052*4882a593Smuzhiyun mutex_lock(&state->internal->demod_lock);
4053*4882a593Smuzhiyun
4054*4882a593Smuzhiyun /* general power on */
4055*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4056*4882a593Smuzhiyun STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
4057*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4058*4882a593Smuzhiyun goto err;
4059*4882a593Smuzhiyun
4060*4882a593Smuzhiyun switch (state->demod) {
4061*4882a593Smuzhiyun case STV090x_DEMODULATOR_0:
4062*4882a593Smuzhiyun /* power on ADC 1 */
4063*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4064*4882a593Smuzhiyun STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
4065*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4066*4882a593Smuzhiyun goto err;
4067*4882a593Smuzhiyun /* power on DiSEqC 1 */
4068*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR2);
4069*4882a593Smuzhiyun STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1);
4070*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
4071*4882a593Smuzhiyun goto err;
4072*4882a593Smuzhiyun
4073*4882a593Smuzhiyun /* activate clocks */
4074*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4075*4882a593Smuzhiyun /* packet delineator 1 clock */
4076*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0);
4077*4882a593Smuzhiyun /* ADC 1 clock */
4078*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0);
4079*4882a593Smuzhiyun /* FEC clock */
4080*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4081*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4082*4882a593Smuzhiyun goto err;
4083*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4084*4882a593Smuzhiyun /* sampling 1 clock */
4085*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0);
4086*4882a593Smuzhiyun /* viterbi 1 clock */
4087*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0);
4088*4882a593Smuzhiyun /* TS clock */
4089*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4090*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4091*4882a593Smuzhiyun goto err;
4092*4882a593Smuzhiyun break;
4093*4882a593Smuzhiyun
4094*4882a593Smuzhiyun case STV090x_DEMODULATOR_1:
4095*4882a593Smuzhiyun /* power on ADC 2 */
4096*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4097*4882a593Smuzhiyun STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1);
4098*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4099*4882a593Smuzhiyun goto err;
4100*4882a593Smuzhiyun /* power on DiSEqC 2 */
4101*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR4);
4102*4882a593Smuzhiyun STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1);
4103*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
4104*4882a593Smuzhiyun goto err;
4105*4882a593Smuzhiyun
4106*4882a593Smuzhiyun /* activate clocks */
4107*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4108*4882a593Smuzhiyun /* packet delineator 2 clock */
4109*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0);
4110*4882a593Smuzhiyun /* ADC 2 clock */
4111*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0);
4112*4882a593Smuzhiyun /* FEC clock */
4113*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4114*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4115*4882a593Smuzhiyun goto err;
4116*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4117*4882a593Smuzhiyun /* sampling 2 clock */
4118*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0);
4119*4882a593Smuzhiyun /* viterbi 2 clock */
4120*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0);
4121*4882a593Smuzhiyun /* TS clock */
4122*4882a593Smuzhiyun STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4123*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4124*4882a593Smuzhiyun goto err;
4125*4882a593Smuzhiyun break;
4126*4882a593Smuzhiyun
4127*4882a593Smuzhiyun default:
4128*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "Wrong demodulator!");
4129*4882a593Smuzhiyun break;
4130*4882a593Smuzhiyun }
4131*4882a593Smuzhiyun
4132*4882a593Smuzhiyun mutex_unlock(&state->internal->demod_lock);
4133*4882a593Smuzhiyun return 0;
4134*4882a593Smuzhiyun err:
4135*4882a593Smuzhiyun mutex_unlock(&state->internal->demod_lock);
4136*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
4137*4882a593Smuzhiyun return -1;
4138*4882a593Smuzhiyun }
4139*4882a593Smuzhiyun
stv090x_release(struct dvb_frontend * fe)4140*4882a593Smuzhiyun static void stv090x_release(struct dvb_frontend *fe)
4141*4882a593Smuzhiyun {
4142*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
4143*4882a593Smuzhiyun
4144*4882a593Smuzhiyun state->internal->num_used--;
4145*4882a593Smuzhiyun if (state->internal->num_used <= 0) {
4146*4882a593Smuzhiyun
4147*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "Actually removing");
4148*4882a593Smuzhiyun
4149*4882a593Smuzhiyun remove_dev(state->internal);
4150*4882a593Smuzhiyun kfree(state->internal);
4151*4882a593Smuzhiyun }
4152*4882a593Smuzhiyun
4153*4882a593Smuzhiyun kfree(state);
4154*4882a593Smuzhiyun }
4155*4882a593Smuzhiyun
stv090x_ldpc_mode(struct stv090x_state * state,enum stv090x_mode ldpc_mode)4156*4882a593Smuzhiyun static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
4157*4882a593Smuzhiyun {
4158*4882a593Smuzhiyun u32 reg = 0;
4159*4882a593Smuzhiyun
4160*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_GENCFG);
4161*4882a593Smuzhiyun
4162*4882a593Smuzhiyun switch (ldpc_mode) {
4163*4882a593Smuzhiyun case STV090x_DUAL:
4164*4882a593Smuzhiyun default:
4165*4882a593Smuzhiyun if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
4166*4882a593Smuzhiyun /* set LDPC to dual mode */
4167*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
4168*4882a593Smuzhiyun goto err;
4169*4882a593Smuzhiyun
4170*4882a593Smuzhiyun state->demod_mode = STV090x_DUAL;
4171*4882a593Smuzhiyun
4172*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTRES0);
4173*4882a593Smuzhiyun STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
4174*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4175*4882a593Smuzhiyun goto err;
4176*4882a593Smuzhiyun STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
4177*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4178*4882a593Smuzhiyun goto err;
4179*4882a593Smuzhiyun
4180*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
4181*4882a593Smuzhiyun goto err;
4182*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
4183*4882a593Smuzhiyun goto err;
4184*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
4185*4882a593Smuzhiyun goto err;
4186*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
4187*4882a593Smuzhiyun goto err;
4188*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
4189*4882a593Smuzhiyun goto err;
4190*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
4191*4882a593Smuzhiyun goto err;
4192*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
4193*4882a593Smuzhiyun goto err;
4194*4882a593Smuzhiyun
4195*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
4196*4882a593Smuzhiyun goto err;
4197*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
4198*4882a593Smuzhiyun goto err;
4199*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
4200*4882a593Smuzhiyun goto err;
4201*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
4202*4882a593Smuzhiyun goto err;
4203*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
4204*4882a593Smuzhiyun goto err;
4205*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
4206*4882a593Smuzhiyun goto err;
4207*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
4208*4882a593Smuzhiyun goto err;
4209*4882a593Smuzhiyun
4210*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
4211*4882a593Smuzhiyun goto err;
4212*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
4213*4882a593Smuzhiyun goto err;
4214*4882a593Smuzhiyun }
4215*4882a593Smuzhiyun break;
4216*4882a593Smuzhiyun
4217*4882a593Smuzhiyun case STV090x_SINGLE:
4218*4882a593Smuzhiyun if (stv090x_stop_modcod(state) < 0)
4219*4882a593Smuzhiyun goto err;
4220*4882a593Smuzhiyun if (stv090x_activate_modcod_single(state) < 0)
4221*4882a593Smuzhiyun goto err;
4222*4882a593Smuzhiyun
4223*4882a593Smuzhiyun if (state->demod == STV090x_DEMODULATOR_1) {
4224*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
4225*4882a593Smuzhiyun goto err;
4226*4882a593Smuzhiyun } else {
4227*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
4228*4882a593Smuzhiyun goto err;
4229*4882a593Smuzhiyun }
4230*4882a593Smuzhiyun
4231*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTRES0);
4232*4882a593Smuzhiyun STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
4233*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4234*4882a593Smuzhiyun goto err;
4235*4882a593Smuzhiyun STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
4236*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4237*4882a593Smuzhiyun goto err;
4238*4882a593Smuzhiyun
4239*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, PDELCTRL1);
4240*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
4241*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4242*4882a593Smuzhiyun goto err;
4243*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
4244*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4245*4882a593Smuzhiyun goto err;
4246*4882a593Smuzhiyun break;
4247*4882a593Smuzhiyun }
4248*4882a593Smuzhiyun
4249*4882a593Smuzhiyun return 0;
4250*4882a593Smuzhiyun err:
4251*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
4252*4882a593Smuzhiyun return -1;
4253*4882a593Smuzhiyun }
4254*4882a593Smuzhiyun
4255*4882a593Smuzhiyun /* return (Hz), clk in Hz*/
stv090x_get_mclk(struct stv090x_state * state)4256*4882a593Smuzhiyun static u32 stv090x_get_mclk(struct stv090x_state *state)
4257*4882a593Smuzhiyun {
4258*4882a593Smuzhiyun const struct stv090x_config *config = state->config;
4259*4882a593Smuzhiyun u32 div, reg;
4260*4882a593Smuzhiyun u8 ratio;
4261*4882a593Smuzhiyun
4262*4882a593Smuzhiyun div = stv090x_read_reg(state, STV090x_NCOARSE);
4263*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4264*4882a593Smuzhiyun ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
4265*4882a593Smuzhiyun
4266*4882a593Smuzhiyun return (div + 1) * config->xtal / ratio; /* kHz */
4267*4882a593Smuzhiyun }
4268*4882a593Smuzhiyun
stv090x_set_mclk(struct stv090x_state * state,u32 mclk,u32 clk)4269*4882a593Smuzhiyun static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
4270*4882a593Smuzhiyun {
4271*4882a593Smuzhiyun const struct stv090x_config *config = state->config;
4272*4882a593Smuzhiyun u32 reg, div, clk_sel;
4273*4882a593Smuzhiyun
4274*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4275*4882a593Smuzhiyun clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
4276*4882a593Smuzhiyun
4277*4882a593Smuzhiyun div = ((clk_sel * mclk) / config->xtal) - 1;
4278*4882a593Smuzhiyun
4279*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_NCOARSE);
4280*4882a593Smuzhiyun STV090x_SETFIELD(reg, M_DIV_FIELD, div);
4281*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4282*4882a593Smuzhiyun goto err;
4283*4882a593Smuzhiyun
4284*4882a593Smuzhiyun state->internal->mclk = stv090x_get_mclk(state);
4285*4882a593Smuzhiyun
4286*4882a593Smuzhiyun /*Set the DiseqC frequency to 22KHz */
4287*4882a593Smuzhiyun div = state->internal->mclk / 704000;
4288*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
4289*4882a593Smuzhiyun goto err;
4290*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
4291*4882a593Smuzhiyun goto err;
4292*4882a593Smuzhiyun
4293*4882a593Smuzhiyun return 0;
4294*4882a593Smuzhiyun err:
4295*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
4296*4882a593Smuzhiyun return -1;
4297*4882a593Smuzhiyun }
4298*4882a593Smuzhiyun
stv0900_set_tspath(struct stv090x_state * state)4299*4882a593Smuzhiyun static int stv0900_set_tspath(struct stv090x_state *state)
4300*4882a593Smuzhiyun {
4301*4882a593Smuzhiyun u32 reg;
4302*4882a593Smuzhiyun
4303*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
4304*4882a593Smuzhiyun switch (state->config->ts1_mode) {
4305*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4306*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4307*4882a593Smuzhiyun switch (state->config->ts2_mode) {
4308*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4309*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4310*4882a593Smuzhiyun default:
4311*4882a593Smuzhiyun stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4312*4882a593Smuzhiyun break;
4313*4882a593Smuzhiyun
4314*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4315*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4316*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
4317*4882a593Smuzhiyun goto err;
4318*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4319*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4320*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4321*4882a593Smuzhiyun goto err;
4322*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4323*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4324*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4325*4882a593Smuzhiyun goto err;
4326*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4327*4882a593Smuzhiyun goto err;
4328*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4329*4882a593Smuzhiyun goto err;
4330*4882a593Smuzhiyun break;
4331*4882a593Smuzhiyun }
4332*4882a593Smuzhiyun break;
4333*4882a593Smuzhiyun
4334*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4335*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4336*4882a593Smuzhiyun default:
4337*4882a593Smuzhiyun switch (state->config->ts2_mode) {
4338*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4339*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4340*4882a593Smuzhiyun default:
4341*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4342*4882a593Smuzhiyun goto err;
4343*4882a593Smuzhiyun break;
4344*4882a593Smuzhiyun
4345*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4346*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4347*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
4348*4882a593Smuzhiyun goto err;
4349*4882a593Smuzhiyun break;
4350*4882a593Smuzhiyun }
4351*4882a593Smuzhiyun break;
4352*4882a593Smuzhiyun }
4353*4882a593Smuzhiyun } else {
4354*4882a593Smuzhiyun switch (state->config->ts1_mode) {
4355*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4356*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4357*4882a593Smuzhiyun switch (state->config->ts2_mode) {
4358*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4359*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4360*4882a593Smuzhiyun default:
4361*4882a593Smuzhiyun stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4362*4882a593Smuzhiyun break;
4363*4882a593Smuzhiyun
4364*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4365*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4366*4882a593Smuzhiyun stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
4367*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4368*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4369*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4370*4882a593Smuzhiyun goto err;
4371*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4372*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
4373*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4374*4882a593Smuzhiyun goto err;
4375*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4376*4882a593Smuzhiyun goto err;
4377*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4378*4882a593Smuzhiyun goto err;
4379*4882a593Smuzhiyun break;
4380*4882a593Smuzhiyun }
4381*4882a593Smuzhiyun break;
4382*4882a593Smuzhiyun
4383*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4384*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4385*4882a593Smuzhiyun default:
4386*4882a593Smuzhiyun switch (state->config->ts2_mode) {
4387*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4388*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4389*4882a593Smuzhiyun default:
4390*4882a593Smuzhiyun stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4391*4882a593Smuzhiyun break;
4392*4882a593Smuzhiyun
4393*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4394*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4395*4882a593Smuzhiyun stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
4396*4882a593Smuzhiyun break;
4397*4882a593Smuzhiyun }
4398*4882a593Smuzhiyun break;
4399*4882a593Smuzhiyun }
4400*4882a593Smuzhiyun }
4401*4882a593Smuzhiyun
4402*4882a593Smuzhiyun switch (state->config->ts1_mode) {
4403*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4404*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4405*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4406*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4407*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4408*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4409*4882a593Smuzhiyun goto err;
4410*4882a593Smuzhiyun break;
4411*4882a593Smuzhiyun
4412*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4413*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4414*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4415*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4416*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4417*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4418*4882a593Smuzhiyun goto err;
4419*4882a593Smuzhiyun break;
4420*4882a593Smuzhiyun
4421*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4422*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4423*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4424*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4425*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4426*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4427*4882a593Smuzhiyun goto err;
4428*4882a593Smuzhiyun break;
4429*4882a593Smuzhiyun
4430*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4431*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4432*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4433*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4434*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4435*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4436*4882a593Smuzhiyun goto err;
4437*4882a593Smuzhiyun break;
4438*4882a593Smuzhiyun
4439*4882a593Smuzhiyun default:
4440*4882a593Smuzhiyun break;
4441*4882a593Smuzhiyun }
4442*4882a593Smuzhiyun
4443*4882a593Smuzhiyun switch (state->config->ts2_mode) {
4444*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4445*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4446*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4447*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4448*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4449*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4450*4882a593Smuzhiyun goto err;
4451*4882a593Smuzhiyun break;
4452*4882a593Smuzhiyun
4453*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4454*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4455*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4456*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4457*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4458*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4459*4882a593Smuzhiyun goto err;
4460*4882a593Smuzhiyun break;
4461*4882a593Smuzhiyun
4462*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4463*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4464*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4465*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4466*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4467*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4468*4882a593Smuzhiyun goto err;
4469*4882a593Smuzhiyun break;
4470*4882a593Smuzhiyun
4471*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4472*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4473*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4474*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4475*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4476*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4477*4882a593Smuzhiyun goto err;
4478*4882a593Smuzhiyun break;
4479*4882a593Smuzhiyun
4480*4882a593Smuzhiyun default:
4481*4882a593Smuzhiyun break;
4482*4882a593Smuzhiyun }
4483*4882a593Smuzhiyun
4484*4882a593Smuzhiyun if (state->config->ts1_clk > 0) {
4485*4882a593Smuzhiyun u32 speed;
4486*4882a593Smuzhiyun
4487*4882a593Smuzhiyun switch (state->config->ts1_mode) {
4488*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4489*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4490*4882a593Smuzhiyun default:
4491*4882a593Smuzhiyun speed = state->internal->mclk /
4492*4882a593Smuzhiyun (state->config->ts1_clk / 4);
4493*4882a593Smuzhiyun if (speed < 0x08)
4494*4882a593Smuzhiyun speed = 0x08;
4495*4882a593Smuzhiyun if (speed > 0xFF)
4496*4882a593Smuzhiyun speed = 0xFF;
4497*4882a593Smuzhiyun break;
4498*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4499*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4500*4882a593Smuzhiyun speed = state->internal->mclk /
4501*4882a593Smuzhiyun (state->config->ts1_clk / 32);
4502*4882a593Smuzhiyun if (speed < 0x20)
4503*4882a593Smuzhiyun speed = 0x20;
4504*4882a593Smuzhiyun if (speed > 0xFF)
4505*4882a593Smuzhiyun speed = 0xFF;
4506*4882a593Smuzhiyun break;
4507*4882a593Smuzhiyun }
4508*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4509*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4510*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4511*4882a593Smuzhiyun goto err;
4512*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4513*4882a593Smuzhiyun goto err;
4514*4882a593Smuzhiyun }
4515*4882a593Smuzhiyun
4516*4882a593Smuzhiyun if (state->config->ts2_clk > 0) {
4517*4882a593Smuzhiyun u32 speed;
4518*4882a593Smuzhiyun
4519*4882a593Smuzhiyun switch (state->config->ts2_mode) {
4520*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4521*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4522*4882a593Smuzhiyun default:
4523*4882a593Smuzhiyun speed = state->internal->mclk /
4524*4882a593Smuzhiyun (state->config->ts2_clk / 4);
4525*4882a593Smuzhiyun if (speed < 0x08)
4526*4882a593Smuzhiyun speed = 0x08;
4527*4882a593Smuzhiyun if (speed > 0xFF)
4528*4882a593Smuzhiyun speed = 0xFF;
4529*4882a593Smuzhiyun break;
4530*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4531*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4532*4882a593Smuzhiyun speed = state->internal->mclk /
4533*4882a593Smuzhiyun (state->config->ts2_clk / 32);
4534*4882a593Smuzhiyun if (speed < 0x20)
4535*4882a593Smuzhiyun speed = 0x20;
4536*4882a593Smuzhiyun if (speed > 0xFF)
4537*4882a593Smuzhiyun speed = 0xFF;
4538*4882a593Smuzhiyun break;
4539*4882a593Smuzhiyun }
4540*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4541*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4542*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4543*4882a593Smuzhiyun goto err;
4544*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
4545*4882a593Smuzhiyun goto err;
4546*4882a593Smuzhiyun }
4547*4882a593Smuzhiyun
4548*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4549*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4550*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4551*4882a593Smuzhiyun goto err;
4552*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4553*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4554*4882a593Smuzhiyun goto err;
4555*4882a593Smuzhiyun
4556*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4557*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4558*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4559*4882a593Smuzhiyun goto err;
4560*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4561*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4562*4882a593Smuzhiyun goto err;
4563*4882a593Smuzhiyun
4564*4882a593Smuzhiyun return 0;
4565*4882a593Smuzhiyun err:
4566*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
4567*4882a593Smuzhiyun return -1;
4568*4882a593Smuzhiyun }
4569*4882a593Smuzhiyun
stv0903_set_tspath(struct stv090x_state * state)4570*4882a593Smuzhiyun static int stv0903_set_tspath(struct stv090x_state *state)
4571*4882a593Smuzhiyun {
4572*4882a593Smuzhiyun u32 reg;
4573*4882a593Smuzhiyun
4574*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
4575*4882a593Smuzhiyun switch (state->config->ts1_mode) {
4576*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4577*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4578*4882a593Smuzhiyun stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4579*4882a593Smuzhiyun break;
4580*4882a593Smuzhiyun
4581*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4582*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4583*4882a593Smuzhiyun default:
4584*4882a593Smuzhiyun stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c);
4585*4882a593Smuzhiyun break;
4586*4882a593Smuzhiyun }
4587*4882a593Smuzhiyun } else {
4588*4882a593Smuzhiyun switch (state->config->ts1_mode) {
4589*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4590*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4591*4882a593Smuzhiyun stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4592*4882a593Smuzhiyun break;
4593*4882a593Smuzhiyun
4594*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4595*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4596*4882a593Smuzhiyun default:
4597*4882a593Smuzhiyun stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4598*4882a593Smuzhiyun break;
4599*4882a593Smuzhiyun }
4600*4882a593Smuzhiyun }
4601*4882a593Smuzhiyun
4602*4882a593Smuzhiyun switch (state->config->ts1_mode) {
4603*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4604*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4605*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4606*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4607*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4608*4882a593Smuzhiyun goto err;
4609*4882a593Smuzhiyun break;
4610*4882a593Smuzhiyun
4611*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4612*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4613*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4614*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4615*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4616*4882a593Smuzhiyun goto err;
4617*4882a593Smuzhiyun break;
4618*4882a593Smuzhiyun
4619*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4620*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4621*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4622*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4623*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4624*4882a593Smuzhiyun goto err;
4625*4882a593Smuzhiyun break;
4626*4882a593Smuzhiyun
4627*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4628*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4629*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4630*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4631*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4632*4882a593Smuzhiyun goto err;
4633*4882a593Smuzhiyun break;
4634*4882a593Smuzhiyun
4635*4882a593Smuzhiyun default:
4636*4882a593Smuzhiyun break;
4637*4882a593Smuzhiyun }
4638*4882a593Smuzhiyun
4639*4882a593Smuzhiyun if (state->config->ts1_clk > 0) {
4640*4882a593Smuzhiyun u32 speed;
4641*4882a593Smuzhiyun
4642*4882a593Smuzhiyun switch (state->config->ts1_mode) {
4643*4882a593Smuzhiyun case STV090x_TSMODE_PARALLEL_PUNCTURED:
4644*4882a593Smuzhiyun case STV090x_TSMODE_DVBCI:
4645*4882a593Smuzhiyun default:
4646*4882a593Smuzhiyun speed = state->internal->mclk /
4647*4882a593Smuzhiyun (state->config->ts1_clk / 4);
4648*4882a593Smuzhiyun if (speed < 0x08)
4649*4882a593Smuzhiyun speed = 0x08;
4650*4882a593Smuzhiyun if (speed > 0xFF)
4651*4882a593Smuzhiyun speed = 0xFF;
4652*4882a593Smuzhiyun break;
4653*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_PUNCTURED:
4654*4882a593Smuzhiyun case STV090x_TSMODE_SERIAL_CONTINUOUS:
4655*4882a593Smuzhiyun speed = state->internal->mclk /
4656*4882a593Smuzhiyun (state->config->ts1_clk / 32);
4657*4882a593Smuzhiyun if (speed < 0x20)
4658*4882a593Smuzhiyun speed = 0x20;
4659*4882a593Smuzhiyun if (speed > 0xFF)
4660*4882a593Smuzhiyun speed = 0xFF;
4661*4882a593Smuzhiyun break;
4662*4882a593Smuzhiyun }
4663*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4664*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4665*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4666*4882a593Smuzhiyun goto err;
4667*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4668*4882a593Smuzhiyun goto err;
4669*4882a593Smuzhiyun }
4670*4882a593Smuzhiyun
4671*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4672*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4673*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4674*4882a593Smuzhiyun goto err;
4675*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4676*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4677*4882a593Smuzhiyun goto err;
4678*4882a593Smuzhiyun
4679*4882a593Smuzhiyun return 0;
4680*4882a593Smuzhiyun err:
4681*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
4682*4882a593Smuzhiyun return -1;
4683*4882a593Smuzhiyun }
4684*4882a593Smuzhiyun
stv090x_init(struct dvb_frontend * fe)4685*4882a593Smuzhiyun static int stv090x_init(struct dvb_frontend *fe)
4686*4882a593Smuzhiyun {
4687*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
4688*4882a593Smuzhiyun const struct stv090x_config *config = state->config;
4689*4882a593Smuzhiyun u32 reg;
4690*4882a593Smuzhiyun
4691*4882a593Smuzhiyun if (state->internal->mclk == 0) {
4692*4882a593Smuzhiyun /* call tuner init to configure the tuner's clock output
4693*4882a593Smuzhiyun divider directly before setting up the master clock of
4694*4882a593Smuzhiyun the stv090x. */
4695*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
4696*4882a593Smuzhiyun goto err;
4697*4882a593Smuzhiyun
4698*4882a593Smuzhiyun if (config->tuner_init) {
4699*4882a593Smuzhiyun if (config->tuner_init(fe) < 0)
4700*4882a593Smuzhiyun goto err_gateoff;
4701*4882a593Smuzhiyun }
4702*4882a593Smuzhiyun
4703*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
4704*4882a593Smuzhiyun goto err;
4705*4882a593Smuzhiyun
4706*4882a593Smuzhiyun stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4707*4882a593Smuzhiyun msleep(5);
4708*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_SYNTCTRL,
4709*4882a593Smuzhiyun 0x20 | config->clk_mode) < 0)
4710*4882a593Smuzhiyun goto err;
4711*4882a593Smuzhiyun stv090x_get_mclk(state);
4712*4882a593Smuzhiyun }
4713*4882a593Smuzhiyun
4714*4882a593Smuzhiyun if (stv090x_wakeup(fe) < 0) {
4715*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "Error waking device");
4716*4882a593Smuzhiyun goto err;
4717*4882a593Smuzhiyun }
4718*4882a593Smuzhiyun
4719*4882a593Smuzhiyun if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4720*4882a593Smuzhiyun goto err;
4721*4882a593Smuzhiyun
4722*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, TNRCFG2);
4723*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4724*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4725*4882a593Smuzhiyun goto err;
4726*4882a593Smuzhiyun reg = STV090x_READ_DEMOD(state, DEMOD);
4727*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4728*4882a593Smuzhiyun if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4729*4882a593Smuzhiyun goto err;
4730*4882a593Smuzhiyun
4731*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 1) < 0)
4732*4882a593Smuzhiyun goto err;
4733*4882a593Smuzhiyun
4734*4882a593Smuzhiyun if (config->tuner_set_mode) {
4735*4882a593Smuzhiyun if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
4736*4882a593Smuzhiyun goto err_gateoff;
4737*4882a593Smuzhiyun }
4738*4882a593Smuzhiyun
4739*4882a593Smuzhiyun if (config->tuner_init) {
4740*4882a593Smuzhiyun if (config->tuner_init(fe) < 0)
4741*4882a593Smuzhiyun goto err_gateoff;
4742*4882a593Smuzhiyun }
4743*4882a593Smuzhiyun
4744*4882a593Smuzhiyun if (stv090x_i2c_gate_ctrl(state, 0) < 0)
4745*4882a593Smuzhiyun goto err;
4746*4882a593Smuzhiyun
4747*4882a593Smuzhiyun if (state->device == STV0900) {
4748*4882a593Smuzhiyun if (stv0900_set_tspath(state) < 0)
4749*4882a593Smuzhiyun goto err;
4750*4882a593Smuzhiyun } else {
4751*4882a593Smuzhiyun if (stv0903_set_tspath(state) < 0)
4752*4882a593Smuzhiyun goto err;
4753*4882a593Smuzhiyun }
4754*4882a593Smuzhiyun
4755*4882a593Smuzhiyun return 0;
4756*4882a593Smuzhiyun
4757*4882a593Smuzhiyun err_gateoff:
4758*4882a593Smuzhiyun stv090x_i2c_gate_ctrl(state, 0);
4759*4882a593Smuzhiyun err:
4760*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
4761*4882a593Smuzhiyun return -1;
4762*4882a593Smuzhiyun }
4763*4882a593Smuzhiyun
stv090x_setup(struct dvb_frontend * fe)4764*4882a593Smuzhiyun static int stv090x_setup(struct dvb_frontend *fe)
4765*4882a593Smuzhiyun {
4766*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
4767*4882a593Smuzhiyun const struct stv090x_config *config = state->config;
4768*4882a593Smuzhiyun const struct stv090x_reg *stv090x_initval = NULL;
4769*4882a593Smuzhiyun const struct stv090x_reg *stv090x_cut20_val = NULL;
4770*4882a593Smuzhiyun unsigned long t1_size = 0, t2_size = 0;
4771*4882a593Smuzhiyun u32 reg = 0;
4772*4882a593Smuzhiyun
4773*4882a593Smuzhiyun int i;
4774*4882a593Smuzhiyun
4775*4882a593Smuzhiyun if (state->device == STV0900) {
4776*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Initializing STV0900");
4777*4882a593Smuzhiyun stv090x_initval = stv0900_initval;
4778*4882a593Smuzhiyun t1_size = ARRAY_SIZE(stv0900_initval);
4779*4882a593Smuzhiyun stv090x_cut20_val = stv0900_cut20_val;
4780*4882a593Smuzhiyun t2_size = ARRAY_SIZE(stv0900_cut20_val);
4781*4882a593Smuzhiyun } else if (state->device == STV0903) {
4782*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Initializing STV0903");
4783*4882a593Smuzhiyun stv090x_initval = stv0903_initval;
4784*4882a593Smuzhiyun t1_size = ARRAY_SIZE(stv0903_initval);
4785*4882a593Smuzhiyun stv090x_cut20_val = stv0903_cut20_val;
4786*4882a593Smuzhiyun t2_size = ARRAY_SIZE(stv0903_cut20_val);
4787*4882a593Smuzhiyun }
4788*4882a593Smuzhiyun
4789*4882a593Smuzhiyun /* STV090x init */
4790*4882a593Smuzhiyun
4791*4882a593Smuzhiyun /* Stop Demod */
4792*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
4793*4882a593Smuzhiyun goto err;
4794*4882a593Smuzhiyun if (state->device == STV0900)
4795*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
4796*4882a593Smuzhiyun goto err;
4797*4882a593Smuzhiyun
4798*4882a593Smuzhiyun msleep(5);
4799*4882a593Smuzhiyun
4800*4882a593Smuzhiyun /* Set No Tuner Mode */
4801*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
4802*4882a593Smuzhiyun goto err;
4803*4882a593Smuzhiyun if (state->device == STV0900)
4804*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
4805*4882a593Smuzhiyun goto err;
4806*4882a593Smuzhiyun
4807*4882a593Smuzhiyun /* I2C repeater OFF */
4808*4882a593Smuzhiyun STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
4809*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4810*4882a593Smuzhiyun goto err;
4811*4882a593Smuzhiyun if (state->device == STV0900)
4812*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
4813*4882a593Smuzhiyun goto err;
4814*4882a593Smuzhiyun
4815*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4816*4882a593Smuzhiyun goto err;
4817*4882a593Smuzhiyun msleep(5);
4818*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4819*4882a593Smuzhiyun goto err;
4820*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4821*4882a593Smuzhiyun goto err;
4822*4882a593Smuzhiyun msleep(5);
4823*4882a593Smuzhiyun
4824*4882a593Smuzhiyun /* write initval */
4825*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Setting up initial values");
4826*4882a593Smuzhiyun for (i = 0; i < t1_size; i++) {
4827*4882a593Smuzhiyun if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4828*4882a593Smuzhiyun goto err;
4829*4882a593Smuzhiyun }
4830*4882a593Smuzhiyun
4831*4882a593Smuzhiyun state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
4832*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x20) {
4833*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4834*4882a593Smuzhiyun goto err;
4835*4882a593Smuzhiyun
4836*4882a593Smuzhiyun /* write cut20_val*/
4837*4882a593Smuzhiyun dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
4838*4882a593Smuzhiyun for (i = 0; i < t2_size; i++) {
4839*4882a593Smuzhiyun if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4840*4882a593Smuzhiyun goto err;
4841*4882a593Smuzhiyun }
4842*4882a593Smuzhiyun
4843*4882a593Smuzhiyun } else if (state->internal->dev_ver < 0x20) {
4844*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
4845*4882a593Smuzhiyun state->internal->dev_ver);
4846*4882a593Smuzhiyun
4847*4882a593Smuzhiyun goto err;
4848*4882a593Smuzhiyun } else if (state->internal->dev_ver > 0x30) {
4849*4882a593Smuzhiyun /* we shouldn't bail out from here */
4850*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
4851*4882a593Smuzhiyun state->internal->dev_ver);
4852*4882a593Smuzhiyun }
4853*4882a593Smuzhiyun
4854*4882a593Smuzhiyun /* ADC1 range */
4855*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4856*4882a593Smuzhiyun STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
4857*4882a593Smuzhiyun (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
4858*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4859*4882a593Smuzhiyun goto err;
4860*4882a593Smuzhiyun
4861*4882a593Smuzhiyun /* ADC2 range */
4862*4882a593Smuzhiyun reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4863*4882a593Smuzhiyun STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
4864*4882a593Smuzhiyun (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
4865*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4866*4882a593Smuzhiyun goto err;
4867*4882a593Smuzhiyun
4868*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4869*4882a593Smuzhiyun goto err;
4870*4882a593Smuzhiyun if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4871*4882a593Smuzhiyun goto err;
4872*4882a593Smuzhiyun
4873*4882a593Smuzhiyun return 0;
4874*4882a593Smuzhiyun err:
4875*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "I/O error");
4876*4882a593Smuzhiyun return -1;
4877*4882a593Smuzhiyun }
4878*4882a593Smuzhiyun
stv090x_set_gpio(struct dvb_frontend * fe,u8 gpio,u8 dir,u8 value,u8 xor_value)4879*4882a593Smuzhiyun static int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir,
4880*4882a593Smuzhiyun u8 value, u8 xor_value)
4881*4882a593Smuzhiyun {
4882*4882a593Smuzhiyun struct stv090x_state *state = fe->demodulator_priv;
4883*4882a593Smuzhiyun u8 reg = 0;
4884*4882a593Smuzhiyun
4885*4882a593Smuzhiyun STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir);
4886*4882a593Smuzhiyun STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value);
4887*4882a593Smuzhiyun STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value);
4888*4882a593Smuzhiyun
4889*4882a593Smuzhiyun return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);
4890*4882a593Smuzhiyun }
4891*4882a593Smuzhiyun
stv090x_setup_compound(struct stv090x_state * state)4892*4882a593Smuzhiyun static int stv090x_setup_compound(struct stv090x_state *state)
4893*4882a593Smuzhiyun {
4894*4882a593Smuzhiyun struct stv090x_dev *temp_int;
4895*4882a593Smuzhiyun
4896*4882a593Smuzhiyun temp_int = find_dev(state->i2c,
4897*4882a593Smuzhiyun state->config->address);
4898*4882a593Smuzhiyun
4899*4882a593Smuzhiyun if (temp_int && state->demod_mode == STV090x_DUAL) {
4900*4882a593Smuzhiyun state->internal = temp_int->internal;
4901*4882a593Smuzhiyun state->internal->num_used++;
4902*4882a593Smuzhiyun dprintk(FE_INFO, 1, "Found Internal Structure!");
4903*4882a593Smuzhiyun } else {
4904*4882a593Smuzhiyun state->internal = kmalloc(sizeof(*state->internal), GFP_KERNEL);
4905*4882a593Smuzhiyun if (!state->internal)
4906*4882a593Smuzhiyun goto error;
4907*4882a593Smuzhiyun temp_int = append_internal(state->internal);
4908*4882a593Smuzhiyun if (!temp_int) {
4909*4882a593Smuzhiyun kfree(state->internal);
4910*4882a593Smuzhiyun goto error;
4911*4882a593Smuzhiyun }
4912*4882a593Smuzhiyun state->internal->num_used = 1;
4913*4882a593Smuzhiyun state->internal->mclk = 0;
4914*4882a593Smuzhiyun state->internal->dev_ver = 0;
4915*4882a593Smuzhiyun state->internal->i2c_adap = state->i2c;
4916*4882a593Smuzhiyun state->internal->i2c_addr = state->config->address;
4917*4882a593Smuzhiyun dprintk(FE_INFO, 1, "Create New Internal Structure!");
4918*4882a593Smuzhiyun
4919*4882a593Smuzhiyun mutex_init(&state->internal->demod_lock);
4920*4882a593Smuzhiyun mutex_init(&state->internal->tuner_lock);
4921*4882a593Smuzhiyun
4922*4882a593Smuzhiyun if (stv090x_setup(&state->frontend) < 0) {
4923*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "Error setting up device");
4924*4882a593Smuzhiyun goto err_remove;
4925*4882a593Smuzhiyun }
4926*4882a593Smuzhiyun }
4927*4882a593Smuzhiyun
4928*4882a593Smuzhiyun if (state->internal->dev_ver >= 0x30)
4929*4882a593Smuzhiyun state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM;
4930*4882a593Smuzhiyun
4931*4882a593Smuzhiyun /* workaround for stuck DiSEqC output */
4932*4882a593Smuzhiyun if (state->config->diseqc_envelope_mode)
4933*4882a593Smuzhiyun stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A);
4934*4882a593Smuzhiyun
4935*4882a593Smuzhiyun state->config->set_gpio = stv090x_set_gpio;
4936*4882a593Smuzhiyun
4937*4882a593Smuzhiyun dprintk(FE_ERROR, 1, "Probing %s demodulator(%d) Cut=0x%02x",
4938*4882a593Smuzhiyun state->device == STV0900 ? "STV0900" : "STV0903",
4939*4882a593Smuzhiyun state->config->demod,
4940*4882a593Smuzhiyun state->internal->dev_ver);
4941*4882a593Smuzhiyun
4942*4882a593Smuzhiyun return 0;
4943*4882a593Smuzhiyun
4944*4882a593Smuzhiyun error:
4945*4882a593Smuzhiyun return -ENOMEM;
4946*4882a593Smuzhiyun err_remove:
4947*4882a593Smuzhiyun remove_dev(state->internal);
4948*4882a593Smuzhiyun kfree(state->internal);
4949*4882a593Smuzhiyun return -ENODEV;
4950*4882a593Smuzhiyun }
4951*4882a593Smuzhiyun
4952*4882a593Smuzhiyun static const struct dvb_frontend_ops stv090x_ops = {
4953*4882a593Smuzhiyun .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
4954*4882a593Smuzhiyun .info = {
4955*4882a593Smuzhiyun .name = "STV090x Multistandard",
4956*4882a593Smuzhiyun .frequency_min_hz = 950 * MHz,
4957*4882a593Smuzhiyun .frequency_max_hz = 2150 * MHz,
4958*4882a593Smuzhiyun .symbol_rate_min = 1000000,
4959*4882a593Smuzhiyun .symbol_rate_max = 45000000,
4960*4882a593Smuzhiyun .caps = FE_CAN_INVERSION_AUTO |
4961*4882a593Smuzhiyun FE_CAN_FEC_AUTO |
4962*4882a593Smuzhiyun FE_CAN_QPSK |
4963*4882a593Smuzhiyun FE_CAN_2G_MODULATION
4964*4882a593Smuzhiyun },
4965*4882a593Smuzhiyun
4966*4882a593Smuzhiyun .release = stv090x_release,
4967*4882a593Smuzhiyun .init = stv090x_init,
4968*4882a593Smuzhiyun
4969*4882a593Smuzhiyun .sleep = stv090x_sleep,
4970*4882a593Smuzhiyun .get_frontend_algo = stv090x_frontend_algo,
4971*4882a593Smuzhiyun
4972*4882a593Smuzhiyun .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
4973*4882a593Smuzhiyun .diseqc_send_burst = stv090x_send_diseqc_burst,
4974*4882a593Smuzhiyun .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4975*4882a593Smuzhiyun .set_tone = stv090x_set_tone,
4976*4882a593Smuzhiyun
4977*4882a593Smuzhiyun .search = stv090x_search,
4978*4882a593Smuzhiyun .read_status = stv090x_read_status,
4979*4882a593Smuzhiyun .read_ber = stv090x_read_per,
4980*4882a593Smuzhiyun .read_signal_strength = stv090x_read_signal_strength,
4981*4882a593Smuzhiyun .read_snr = stv090x_read_cnr,
4982*4882a593Smuzhiyun };
4983*4882a593Smuzhiyun
stv090x_get_dvb_frontend(struct i2c_client * client)4984*4882a593Smuzhiyun static struct dvb_frontend *stv090x_get_dvb_frontend(struct i2c_client *client)
4985*4882a593Smuzhiyun {
4986*4882a593Smuzhiyun struct stv090x_state *state = i2c_get_clientdata(client);
4987*4882a593Smuzhiyun
4988*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
4989*4882a593Smuzhiyun
4990*4882a593Smuzhiyun return &state->frontend;
4991*4882a593Smuzhiyun }
4992*4882a593Smuzhiyun
stv090x_probe(struct i2c_client * client,const struct i2c_device_id * id)4993*4882a593Smuzhiyun static int stv090x_probe(struct i2c_client *client,
4994*4882a593Smuzhiyun const struct i2c_device_id *id)
4995*4882a593Smuzhiyun {
4996*4882a593Smuzhiyun int ret = 0;
4997*4882a593Smuzhiyun struct stv090x_config *config = client->dev.platform_data;
4998*4882a593Smuzhiyun
4999*4882a593Smuzhiyun struct stv090x_state *state = NULL;
5000*4882a593Smuzhiyun
5001*4882a593Smuzhiyun state = kzalloc(sizeof(*state), GFP_KERNEL);
5002*4882a593Smuzhiyun if (!state) {
5003*4882a593Smuzhiyun ret = -ENOMEM;
5004*4882a593Smuzhiyun goto error;
5005*4882a593Smuzhiyun }
5006*4882a593Smuzhiyun
5007*4882a593Smuzhiyun state->verbose = &verbose;
5008*4882a593Smuzhiyun state->config = config;
5009*4882a593Smuzhiyun state->i2c = client->adapter;
5010*4882a593Smuzhiyun state->frontend.ops = stv090x_ops;
5011*4882a593Smuzhiyun state->frontend.demodulator_priv = state;
5012*4882a593Smuzhiyun state->demod = config->demod;
5013*4882a593Smuzhiyun /* Single or Dual mode */
5014*4882a593Smuzhiyun state->demod_mode = config->demod_mode;
5015*4882a593Smuzhiyun state->device = config->device;
5016*4882a593Smuzhiyun /* default */
5017*4882a593Smuzhiyun state->rolloff = STV090x_RO_35;
5018*4882a593Smuzhiyun
5019*4882a593Smuzhiyun ret = stv090x_setup_compound(state);
5020*4882a593Smuzhiyun if (ret)
5021*4882a593Smuzhiyun goto error;
5022*4882a593Smuzhiyun
5023*4882a593Smuzhiyun i2c_set_clientdata(client, state);
5024*4882a593Smuzhiyun
5025*4882a593Smuzhiyun /* setup callbacks */
5026*4882a593Smuzhiyun config->get_dvb_frontend = stv090x_get_dvb_frontend;
5027*4882a593Smuzhiyun
5028*4882a593Smuzhiyun return 0;
5029*4882a593Smuzhiyun
5030*4882a593Smuzhiyun error:
5031*4882a593Smuzhiyun kfree(state);
5032*4882a593Smuzhiyun return ret;
5033*4882a593Smuzhiyun }
5034*4882a593Smuzhiyun
stv090x_remove(struct i2c_client * client)5035*4882a593Smuzhiyun static int stv090x_remove(struct i2c_client *client)
5036*4882a593Smuzhiyun {
5037*4882a593Smuzhiyun struct stv090x_state *state = i2c_get_clientdata(client);
5038*4882a593Smuzhiyun
5039*4882a593Smuzhiyun stv090x_release(&state->frontend);
5040*4882a593Smuzhiyun return 0;
5041*4882a593Smuzhiyun }
5042*4882a593Smuzhiyun
stv090x_attach(struct stv090x_config * config,struct i2c_adapter * i2c,enum stv090x_demodulator demod)5043*4882a593Smuzhiyun struct dvb_frontend *stv090x_attach(struct stv090x_config *config,
5044*4882a593Smuzhiyun struct i2c_adapter *i2c,
5045*4882a593Smuzhiyun enum stv090x_demodulator demod)
5046*4882a593Smuzhiyun {
5047*4882a593Smuzhiyun int ret = 0;
5048*4882a593Smuzhiyun struct stv090x_state *state = NULL;
5049*4882a593Smuzhiyun
5050*4882a593Smuzhiyun state = kzalloc(sizeof(*state), GFP_KERNEL);
5051*4882a593Smuzhiyun if (!state)
5052*4882a593Smuzhiyun goto error;
5053*4882a593Smuzhiyun
5054*4882a593Smuzhiyun state->verbose = &verbose;
5055*4882a593Smuzhiyun state->config = config;
5056*4882a593Smuzhiyun state->i2c = i2c;
5057*4882a593Smuzhiyun state->frontend.ops = stv090x_ops;
5058*4882a593Smuzhiyun state->frontend.demodulator_priv = state;
5059*4882a593Smuzhiyun state->demod = demod;
5060*4882a593Smuzhiyun /* Single or Dual mode */
5061*4882a593Smuzhiyun state->demod_mode = config->demod_mode;
5062*4882a593Smuzhiyun state->device = config->device;
5063*4882a593Smuzhiyun /* default */
5064*4882a593Smuzhiyun state->rolloff = STV090x_RO_35;
5065*4882a593Smuzhiyun
5066*4882a593Smuzhiyun ret = stv090x_setup_compound(state);
5067*4882a593Smuzhiyun if (ret)
5068*4882a593Smuzhiyun goto error;
5069*4882a593Smuzhiyun
5070*4882a593Smuzhiyun return &state->frontend;
5071*4882a593Smuzhiyun
5072*4882a593Smuzhiyun error:
5073*4882a593Smuzhiyun kfree(state);
5074*4882a593Smuzhiyun return NULL;
5075*4882a593Smuzhiyun }
5076*4882a593Smuzhiyun EXPORT_SYMBOL(stv090x_attach);
5077*4882a593Smuzhiyun
5078*4882a593Smuzhiyun static const struct i2c_device_id stv090x_id_table[] = {
5079*4882a593Smuzhiyun {"stv090x", 0},
5080*4882a593Smuzhiyun {}
5081*4882a593Smuzhiyun };
5082*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, stv090x_id_table);
5083*4882a593Smuzhiyun
5084*4882a593Smuzhiyun static struct i2c_driver stv090x_driver = {
5085*4882a593Smuzhiyun .driver = {
5086*4882a593Smuzhiyun .name = "stv090x",
5087*4882a593Smuzhiyun .suppress_bind_attrs = true,
5088*4882a593Smuzhiyun },
5089*4882a593Smuzhiyun .probe = stv090x_probe,
5090*4882a593Smuzhiyun .remove = stv090x_remove,
5091*4882a593Smuzhiyun .id_table = stv090x_id_table,
5092*4882a593Smuzhiyun };
5093*4882a593Smuzhiyun
5094*4882a593Smuzhiyun module_i2c_driver(stv090x_driver);
5095*4882a593Smuzhiyun
5096*4882a593Smuzhiyun MODULE_PARM_DESC(verbose, "Set Verbosity level");
5097*4882a593Smuzhiyun MODULE_AUTHOR("Manu Abraham");
5098*4882a593Smuzhiyun MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
5099*4882a593Smuzhiyun MODULE_LICENSE("GPL");
5100