1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun STB0899 Multistandard Frontend driver 4*4882a593Smuzhiyun Copyright (C) Manu Abraham (abraham.manu@gmail.com) 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun Copyright (C) ST Microelectronics 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __STB0899_PRIV_H 11*4882a593Smuzhiyun #define __STB0899_PRIV_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <media/dvb_frontend.h> 14*4882a593Smuzhiyun #include "stb0899_drv.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define FE_ERROR 0 17*4882a593Smuzhiyun #define FE_NOTICE 1 18*4882a593Smuzhiyun #define FE_INFO 2 19*4882a593Smuzhiyun #define FE_DEBUG 3 20*4882a593Smuzhiyun #define FE_DEBUGREG 4 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define dprintk(x, y, z, format, arg...) do { \ 23*4882a593Smuzhiyun if (z) { \ 24*4882a593Smuzhiyun if ((*x > FE_ERROR) && (*x > y)) \ 25*4882a593Smuzhiyun printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \ 26*4882a593Smuzhiyun else if ((*x > FE_NOTICE) && (*x > y)) \ 27*4882a593Smuzhiyun printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \ 28*4882a593Smuzhiyun else if ((*x > FE_INFO) && (*x > y)) \ 29*4882a593Smuzhiyun printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \ 30*4882a593Smuzhiyun else if ((*x > FE_DEBUG) && (*x > y)) \ 31*4882a593Smuzhiyun printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \ 32*4882a593Smuzhiyun } else { \ 33*4882a593Smuzhiyun if (*x > y) \ 34*4882a593Smuzhiyun printk(format, ##arg); \ 35*4882a593Smuzhiyun } \ 36*4882a593Smuzhiyun } while(0) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define INRANGE(val, x, y) (((x <= val) && (val <= y)) || \ 39*4882a593Smuzhiyun ((y <= val) && (val <= x)) ? 1 : 0) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define BYTE0 0 42*4882a593Smuzhiyun #define BYTE1 8 43*4882a593Smuzhiyun #define BYTE2 16 44*4882a593Smuzhiyun #define BYTE3 24 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define GETBYTE(x, y) (((x) >> (y)) & 0xff) 47*4882a593Smuzhiyun #define MAKEWORD32(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) 48*4882a593Smuzhiyun #define MAKEWORD16(a, b) (((a) << 8) | (b)) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define LSB(x) ((x & 0xff)) 51*4882a593Smuzhiyun #define MSB(y) ((y >> 8) & 0xff) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define STB0899_GETFIELD(bitf, val) ((val >> STB0899_OFFST_##bitf) & ((1 << STB0899_WIDTH_##bitf) - 1)) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define STB0899_SETFIELD(mask, val, width, offset) (mask & (~(((1 << width) - 1) << \ 58*4882a593Smuzhiyun offset))) | ((val & \ 59*4882a593Smuzhiyun ((1 << width) - 1)) << offset) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define STB0899_SETFIELD_VAL(bitf, mask, val) (mask = (mask & (~(((1 << STB0899_WIDTH_##bitf) - 1) <<\ 62*4882a593Smuzhiyun STB0899_OFFST_##bitf))) | \ 63*4882a593Smuzhiyun (val << STB0899_OFFST_##bitf)) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun enum stb0899_status { 67*4882a593Smuzhiyun NOAGC1 = 0, 68*4882a593Smuzhiyun AGC1OK, 69*4882a593Smuzhiyun NOTIMING, 70*4882a593Smuzhiyun ANALOGCARRIER, 71*4882a593Smuzhiyun TIMINGOK, 72*4882a593Smuzhiyun NOAGC2, 73*4882a593Smuzhiyun AGC2OK, 74*4882a593Smuzhiyun NOCARRIER, 75*4882a593Smuzhiyun CARRIEROK, 76*4882a593Smuzhiyun NODATA, 77*4882a593Smuzhiyun FALSELOCK, 78*4882a593Smuzhiyun DATAOK, 79*4882a593Smuzhiyun OUTOFRANGE, 80*4882a593Smuzhiyun RANGEOK, 81*4882a593Smuzhiyun DVBS2_DEMOD_LOCK, 82*4882a593Smuzhiyun DVBS2_DEMOD_NOLOCK, 83*4882a593Smuzhiyun DVBS2_FEC_LOCK, 84*4882a593Smuzhiyun DVBS2_FEC_NOLOCK 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun enum stb0899_modcod { 88*4882a593Smuzhiyun STB0899_DUMMY_PLF, 89*4882a593Smuzhiyun STB0899_QPSK_14, 90*4882a593Smuzhiyun STB0899_QPSK_13, 91*4882a593Smuzhiyun STB0899_QPSK_25, 92*4882a593Smuzhiyun STB0899_QPSK_12, 93*4882a593Smuzhiyun STB0899_QPSK_35, 94*4882a593Smuzhiyun STB0899_QPSK_23, 95*4882a593Smuzhiyun STB0899_QPSK_34, 96*4882a593Smuzhiyun STB0899_QPSK_45, 97*4882a593Smuzhiyun STB0899_QPSK_56, 98*4882a593Smuzhiyun STB0899_QPSK_89, 99*4882a593Smuzhiyun STB0899_QPSK_910, 100*4882a593Smuzhiyun STB0899_8PSK_35, 101*4882a593Smuzhiyun STB0899_8PSK_23, 102*4882a593Smuzhiyun STB0899_8PSK_34, 103*4882a593Smuzhiyun STB0899_8PSK_56, 104*4882a593Smuzhiyun STB0899_8PSK_89, 105*4882a593Smuzhiyun STB0899_8PSK_910, 106*4882a593Smuzhiyun STB0899_16APSK_23, 107*4882a593Smuzhiyun STB0899_16APSK_34, 108*4882a593Smuzhiyun STB0899_16APSK_45, 109*4882a593Smuzhiyun STB0899_16APSK_56, 110*4882a593Smuzhiyun STB0899_16APSK_89, 111*4882a593Smuzhiyun STB0899_16APSK_910, 112*4882a593Smuzhiyun STB0899_32APSK_34, 113*4882a593Smuzhiyun STB0899_32APSK_45, 114*4882a593Smuzhiyun STB0899_32APSK_56, 115*4882a593Smuzhiyun STB0899_32APSK_89, 116*4882a593Smuzhiyun STB0899_32APSK_910 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun enum stb0899_frame { 120*4882a593Smuzhiyun STB0899_LONG_FRAME, 121*4882a593Smuzhiyun STB0899_SHORT_FRAME 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun enum stb0899_alpha { 125*4882a593Smuzhiyun RRC_20, 126*4882a593Smuzhiyun RRC_25, 127*4882a593Smuzhiyun RRC_35 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun struct stb0899_tab { 131*4882a593Smuzhiyun s32 real; 132*4882a593Smuzhiyun s32 read; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun enum stb0899_fec { 136*4882a593Smuzhiyun STB0899_FEC_1_2 = 13, 137*4882a593Smuzhiyun STB0899_FEC_2_3 = 18, 138*4882a593Smuzhiyun STB0899_FEC_3_4 = 21, 139*4882a593Smuzhiyun STB0899_FEC_5_6 = 24, 140*4882a593Smuzhiyun STB0899_FEC_6_7 = 25, 141*4882a593Smuzhiyun STB0899_FEC_7_8 = 26 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun struct stb0899_params { 145*4882a593Smuzhiyun u32 freq; /* Frequency */ 146*4882a593Smuzhiyun u32 srate; /* Symbol rate */ 147*4882a593Smuzhiyun enum fe_code_rate fecrate; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun struct stb0899_internal { 151*4882a593Smuzhiyun u32 master_clk; 152*4882a593Smuzhiyun u32 freq; /* Demod internal Frequency */ 153*4882a593Smuzhiyun u32 srate; /* Demod internal Symbol rate */ 154*4882a593Smuzhiyun enum stb0899_fec fecrate; /* Demod internal FEC rate */ 155*4882a593Smuzhiyun s32 srch_range; /* Demod internal Search Range */ 156*4882a593Smuzhiyun s32 sub_range; /* Demod current sub range (Hz) */ 157*4882a593Smuzhiyun s32 tuner_step; /* Tuner step (Hz) */ 158*4882a593Smuzhiyun s32 tuner_offst; /* Relative offset to carrier (Hz) */ 159*4882a593Smuzhiyun u32 tuner_bw; /* Current bandwidth of the tuner (Hz) */ 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun s32 mclk; /* Masterclock Divider factor (binary) */ 162*4882a593Smuzhiyun s32 rolloff; /* Current RollOff of the filter (x100) */ 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun s16 derot_freq; /* Current derotator frequency (Hz) */ 165*4882a593Smuzhiyun s16 derot_percent; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun s16 direction; /* Current derotator search direction */ 168*4882a593Smuzhiyun s16 derot_step; /* Derotator step (binary value) */ 169*4882a593Smuzhiyun s16 t_derot; /* Derotator time constant (ms) */ 170*4882a593Smuzhiyun s16 t_data; /* Data recovery time constant (ms) */ 171*4882a593Smuzhiyun s16 sub_dir; /* Direction of the next sub range */ 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun s16 t_agc1; /* Agc1 time constant (ms) */ 174*4882a593Smuzhiyun s16 t_agc2; /* Agc2 time constant (ms) */ 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun u32 lock; /* Demod internal lock state */ 177*4882a593Smuzhiyun enum stb0899_status status; /* Demod internal status */ 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* DVB-S2 */ 180*4882a593Smuzhiyun s32 agc_gain; /* RF AGC Gain */ 181*4882a593Smuzhiyun s32 center_freq; /* Nominal carrier frequency */ 182*4882a593Smuzhiyun s32 av_frame_coarse; /* Coarse carrier freq search frames */ 183*4882a593Smuzhiyun s32 av_frame_fine; /* Fine carrier freq search frames */ 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun s16 step_size; /* Carrier frequency search step size */ 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun enum stb0899_alpha rrc_alpha; 188*4882a593Smuzhiyun enum stb0899_inversion inversion; 189*4882a593Smuzhiyun enum stb0899_modcod modcod; 190*4882a593Smuzhiyun u8 pilots; /* Pilots found */ 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun enum stb0899_frame frame_length; 193*4882a593Smuzhiyun u8 v_status; /* VSTATUS */ 194*4882a593Smuzhiyun u8 err_ctrl; /* ERRCTRLn */ 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun struct stb0899_state { 198*4882a593Smuzhiyun struct i2c_adapter *i2c; 199*4882a593Smuzhiyun struct stb0899_config *config; 200*4882a593Smuzhiyun struct dvb_frontend frontend; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun u32 *verbose; /* Cached module verbosity level */ 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun struct stb0899_internal internal; /* Device internal parameters */ 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* cached params from API */ 207*4882a593Smuzhiyun enum fe_delivery_system delsys; 208*4882a593Smuzhiyun struct stb0899_params params; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun u32 rx_freq; /* DiSEqC 2.0 receiver freq */ 211*4882a593Smuzhiyun struct mutex search_lock; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun /* stb0899.c */ 214*4882a593Smuzhiyun extern int stb0899_read_reg(struct stb0899_state *state, 215*4882a593Smuzhiyun unsigned int reg); 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun extern u32 _stb0899_read_s2reg(struct stb0899_state *state, 218*4882a593Smuzhiyun u32 stb0899_i2cdev, 219*4882a593Smuzhiyun u32 stb0899_base_addr, 220*4882a593Smuzhiyun u16 stb0899_reg_offset); 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun extern int stb0899_read_regs(struct stb0899_state *state, 223*4882a593Smuzhiyun unsigned int reg, u8 *buf, 224*4882a593Smuzhiyun u32 count); 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun extern int stb0899_write_regs(struct stb0899_state *state, 227*4882a593Smuzhiyun unsigned int reg, u8 *data, 228*4882a593Smuzhiyun u32 count); 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun extern int stb0899_write_reg(struct stb0899_state *state, 231*4882a593Smuzhiyun unsigned int reg, 232*4882a593Smuzhiyun u8 data); 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun extern int stb0899_write_s2reg(struct stb0899_state *state, 235*4882a593Smuzhiyun u32 stb0899_i2cdev, 236*4882a593Smuzhiyun u32 stb0899_base_addr, 237*4882a593Smuzhiyun u16 stb0899_reg_offset, 238*4882a593Smuzhiyun u32 stb0899_data); 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun extern int stb0899_i2c_gate_ctrl(struct dvb_frontend *fe, int enable); 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun #define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG)) 244*4882a593Smuzhiyun //#define STB0899_WRITE_S2REG(DEVICE, REG, DATA) (_stb0899_write_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG, DATA)) 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* stb0899_algo.c */ 247*4882a593Smuzhiyun extern enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state); 248*4882a593Smuzhiyun extern enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state); 249*4882a593Smuzhiyun extern long stb0899_carr_width(struct stb0899_state *state); 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #endif //__STB0899_PRIV_H 252