1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun STB0899 Multistandard Frontend driver
4*4882a593Smuzhiyun Copyright (C) Manu Abraham (abraham.manu@gmail.com)
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun Copyright (C) ST Microelectronics
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/jiffies.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/string.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/dvb/frontend.h>
18*4882a593Smuzhiyun #include <media/dvb_frontend.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "stb0899_drv.h"
21*4882a593Smuzhiyun #include "stb0899_priv.h"
22*4882a593Smuzhiyun #include "stb0899_reg.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Max transfer size done by I2C transfer functions */
25*4882a593Smuzhiyun #define MAX_XFER_SIZE 64
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static unsigned int verbose = 0;//1;
28*4882a593Smuzhiyun module_param(verbose, int, 0644);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* C/N in dB/10, NIRM/NIRL */
31*4882a593Smuzhiyun static const struct stb0899_tab stb0899_cn_tab[] = {
32*4882a593Smuzhiyun { 200, 2600 },
33*4882a593Smuzhiyun { 190, 2700 },
34*4882a593Smuzhiyun { 180, 2860 },
35*4882a593Smuzhiyun { 170, 3020 },
36*4882a593Smuzhiyun { 160, 3210 },
37*4882a593Smuzhiyun { 150, 3440 },
38*4882a593Smuzhiyun { 140, 3710 },
39*4882a593Smuzhiyun { 130, 4010 },
40*4882a593Smuzhiyun { 120, 4360 },
41*4882a593Smuzhiyun { 110, 4740 },
42*4882a593Smuzhiyun { 100, 5190 },
43*4882a593Smuzhiyun { 90, 5670 },
44*4882a593Smuzhiyun { 80, 6200 },
45*4882a593Smuzhiyun { 70, 6770 },
46*4882a593Smuzhiyun { 60, 7360 },
47*4882a593Smuzhiyun { 50, 7970 },
48*4882a593Smuzhiyun { 40, 8250 },
49*4882a593Smuzhiyun { 30, 9000 },
50*4882a593Smuzhiyun { 20, 9450 },
51*4882a593Smuzhiyun { 15, 9600 },
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* DVB-S AGCIQ_VALUE vs. signal level in dBm/10.
55*4882a593Smuzhiyun * As measured, connected to a modulator.
56*4882a593Smuzhiyun * -8.0 to -50.0 dBm directly connected,
57*4882a593Smuzhiyun * -52.0 to -74.8 with extra attenuation.
58*4882a593Smuzhiyun * Cut-off to AGCIQ_VALUE = 0x80 below -74.8dBm.
59*4882a593Smuzhiyun * Crude linear extrapolation below -84.8dBm and above -8.0dBm.
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun static const struct stb0899_tab stb0899_dvbsrf_tab[] = {
62*4882a593Smuzhiyun { -750, -128 },
63*4882a593Smuzhiyun { -748, -94 },
64*4882a593Smuzhiyun { -745, -92 },
65*4882a593Smuzhiyun { -735, -90 },
66*4882a593Smuzhiyun { -720, -87 },
67*4882a593Smuzhiyun { -670, -77 },
68*4882a593Smuzhiyun { -640, -70 },
69*4882a593Smuzhiyun { -610, -62 },
70*4882a593Smuzhiyun { -600, -60 },
71*4882a593Smuzhiyun { -590, -56 },
72*4882a593Smuzhiyun { -560, -41 },
73*4882a593Smuzhiyun { -540, -25 },
74*4882a593Smuzhiyun { -530, -17 },
75*4882a593Smuzhiyun { -520, -11 },
76*4882a593Smuzhiyun { -500, 1 },
77*4882a593Smuzhiyun { -490, 6 },
78*4882a593Smuzhiyun { -480, 10 },
79*4882a593Smuzhiyun { -440, 22 },
80*4882a593Smuzhiyun { -420, 27 },
81*4882a593Smuzhiyun { -400, 31 },
82*4882a593Smuzhiyun { -380, 34 },
83*4882a593Smuzhiyun { -340, 40 },
84*4882a593Smuzhiyun { -320, 43 },
85*4882a593Smuzhiyun { -280, 48 },
86*4882a593Smuzhiyun { -250, 52 },
87*4882a593Smuzhiyun { -230, 55 },
88*4882a593Smuzhiyun { -180, 61 },
89*4882a593Smuzhiyun { -140, 66 },
90*4882a593Smuzhiyun { -90, 73 },
91*4882a593Smuzhiyun { -80, 74 },
92*4882a593Smuzhiyun { 500, 127 }
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* DVB-S2 IF_AGC_GAIN vs. signal level in dBm/10.
96*4882a593Smuzhiyun * As measured, connected to a modulator.
97*4882a593Smuzhiyun * -8.0 to -50.1 dBm directly connected,
98*4882a593Smuzhiyun * -53.0 to -76.6 with extra attenuation.
99*4882a593Smuzhiyun * Cut-off to IF_AGC_GAIN = 0x3fff below -76.6dBm.
100*4882a593Smuzhiyun * Crude linear extrapolation below -76.6dBm and above -8.0dBm.
101*4882a593Smuzhiyun */
102*4882a593Smuzhiyun static const struct stb0899_tab stb0899_dvbs2rf_tab[] = {
103*4882a593Smuzhiyun { 700, 0 },
104*4882a593Smuzhiyun { -80, 3217 },
105*4882a593Smuzhiyun { -150, 3893 },
106*4882a593Smuzhiyun { -190, 4217 },
107*4882a593Smuzhiyun { -240, 4621 },
108*4882a593Smuzhiyun { -280, 4945 },
109*4882a593Smuzhiyun { -320, 5273 },
110*4882a593Smuzhiyun { -350, 5545 },
111*4882a593Smuzhiyun { -370, 5741 },
112*4882a593Smuzhiyun { -410, 6147 },
113*4882a593Smuzhiyun { -450, 6671 },
114*4882a593Smuzhiyun { -490, 7413 },
115*4882a593Smuzhiyun { -501, 7665 },
116*4882a593Smuzhiyun { -530, 8767 },
117*4882a593Smuzhiyun { -560, 10219 },
118*4882a593Smuzhiyun { -580, 10939 },
119*4882a593Smuzhiyun { -590, 11518 },
120*4882a593Smuzhiyun { -600, 11723 },
121*4882a593Smuzhiyun { -650, 12659 },
122*4882a593Smuzhiyun { -690, 13219 },
123*4882a593Smuzhiyun { -730, 13645 },
124*4882a593Smuzhiyun { -750, 13909 },
125*4882a593Smuzhiyun { -766, 14153 },
126*4882a593Smuzhiyun { -950, 16383 }
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* DVB-S2 Es/N0 quant in dB/100 vs read value * 100*/
130*4882a593Smuzhiyun static struct stb0899_tab stb0899_quant_tab[] = {
131*4882a593Smuzhiyun { 0, 0 },
132*4882a593Smuzhiyun { 0, 100 },
133*4882a593Smuzhiyun { 600, 200 },
134*4882a593Smuzhiyun { 950, 299 },
135*4882a593Smuzhiyun { 1200, 398 },
136*4882a593Smuzhiyun { 1400, 501 },
137*4882a593Smuzhiyun { 1560, 603 },
138*4882a593Smuzhiyun { 1690, 700 },
139*4882a593Smuzhiyun { 1810, 804 },
140*4882a593Smuzhiyun { 1910, 902 },
141*4882a593Smuzhiyun { 2000, 1000 },
142*4882a593Smuzhiyun { 2080, 1096 },
143*4882a593Smuzhiyun { 2160, 1202 },
144*4882a593Smuzhiyun { 2230, 1303 },
145*4882a593Smuzhiyun { 2350, 1496 },
146*4882a593Smuzhiyun { 2410, 1603 },
147*4882a593Smuzhiyun { 2460, 1698 },
148*4882a593Smuzhiyun { 2510, 1799 },
149*4882a593Smuzhiyun { 2600, 1995 },
150*4882a593Smuzhiyun { 2650, 2113 },
151*4882a593Smuzhiyun { 2690, 2213 },
152*4882a593Smuzhiyun { 2720, 2291 },
153*4882a593Smuzhiyun { 2760, 2399 },
154*4882a593Smuzhiyun { 2800, 2512 },
155*4882a593Smuzhiyun { 2860, 2692 },
156*4882a593Smuzhiyun { 2930, 2917 },
157*4882a593Smuzhiyun { 2960, 3020 },
158*4882a593Smuzhiyun { 3010, 3199 },
159*4882a593Smuzhiyun { 3040, 3311 },
160*4882a593Smuzhiyun { 3060, 3388 },
161*4882a593Smuzhiyun { 3120, 3631 },
162*4882a593Smuzhiyun { 3190, 3936 },
163*4882a593Smuzhiyun { 3400, 5012 },
164*4882a593Smuzhiyun { 3610, 6383 },
165*4882a593Smuzhiyun { 3800, 7943 },
166*4882a593Smuzhiyun { 4210, 12735 },
167*4882a593Smuzhiyun { 4500, 17783 },
168*4882a593Smuzhiyun { 4690, 22131 },
169*4882a593Smuzhiyun { 4810, 25410 }
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /* DVB-S2 Es/N0 estimate in dB/100 vs read value */
173*4882a593Smuzhiyun static struct stb0899_tab stb0899_est_tab[] = {
174*4882a593Smuzhiyun { 0, 0 },
175*4882a593Smuzhiyun { 0, 1 },
176*4882a593Smuzhiyun { 301, 2 },
177*4882a593Smuzhiyun { 1204, 16 },
178*4882a593Smuzhiyun { 1806, 64 },
179*4882a593Smuzhiyun { 2408, 256 },
180*4882a593Smuzhiyun { 2709, 512 },
181*4882a593Smuzhiyun { 3010, 1023 },
182*4882a593Smuzhiyun { 3311, 2046 },
183*4882a593Smuzhiyun { 3612, 4093 },
184*4882a593Smuzhiyun { 3823, 6653 },
185*4882a593Smuzhiyun { 3913, 8185 },
186*4882a593Smuzhiyun { 4010, 10233 },
187*4882a593Smuzhiyun { 4107, 12794 },
188*4882a593Smuzhiyun { 4214, 16368 },
189*4882a593Smuzhiyun { 4266, 18450 },
190*4882a593Smuzhiyun { 4311, 20464 },
191*4882a593Smuzhiyun { 4353, 22542 },
192*4882a593Smuzhiyun { 4391, 24604 },
193*4882a593Smuzhiyun { 4425, 26607 },
194*4882a593Smuzhiyun { 4457, 28642 },
195*4882a593Smuzhiyun { 4487, 30690 },
196*4882a593Smuzhiyun { 4515, 32734 },
197*4882a593Smuzhiyun { 4612, 40926 },
198*4882a593Smuzhiyun { 4692, 49204 },
199*4882a593Smuzhiyun { 4816, 65464 },
200*4882a593Smuzhiyun { 4913, 81846 },
201*4882a593Smuzhiyun { 4993, 98401 },
202*4882a593Smuzhiyun { 5060, 114815 },
203*4882a593Smuzhiyun { 5118, 131220 },
204*4882a593Smuzhiyun { 5200, 158489 },
205*4882a593Smuzhiyun { 5300, 199526 },
206*4882a593Smuzhiyun { 5400, 251189 },
207*4882a593Smuzhiyun { 5500, 316228 },
208*4882a593Smuzhiyun { 5600, 398107 },
209*4882a593Smuzhiyun { 5720, 524807 },
210*4882a593Smuzhiyun { 5721, 526017 },
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun
_stb0899_read_reg(struct stb0899_state * state,unsigned int reg)213*4882a593Smuzhiyun static int _stb0899_read_reg(struct stb0899_state *state, unsigned int reg)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun int ret;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun u8 b0[] = { reg >> 8, reg & 0xff };
218*4882a593Smuzhiyun u8 buf;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun struct i2c_msg msg[] = {
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun .addr = state->config->demod_address,
223*4882a593Smuzhiyun .flags = 0,
224*4882a593Smuzhiyun .buf = b0,
225*4882a593Smuzhiyun .len = 2
226*4882a593Smuzhiyun },{
227*4882a593Smuzhiyun .addr = state->config->demod_address,
228*4882a593Smuzhiyun .flags = I2C_M_RD,
229*4882a593Smuzhiyun .buf = &buf,
230*4882a593Smuzhiyun .len = 1
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun ret = i2c_transfer(state->i2c, msg, 2);
235*4882a593Smuzhiyun if (ret != 2) {
236*4882a593Smuzhiyun if (ret != -ERESTARTSYS)
237*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1,
238*4882a593Smuzhiyun "Read error, Reg=[0x%02x], Status=%d",
239*4882a593Smuzhiyun reg, ret);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun return ret < 0 ? ret : -EREMOTEIO;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun if (unlikely(*state->verbose >= FE_DEBUGREG))
244*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
245*4882a593Smuzhiyun reg, buf);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun return (unsigned int)buf;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
stb0899_read_reg(struct stb0899_state * state,unsigned int reg)250*4882a593Smuzhiyun int stb0899_read_reg(struct stb0899_state *state, unsigned int reg)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun int result;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun result = _stb0899_read_reg(state, reg);
255*4882a593Smuzhiyun /*
256*4882a593Smuzhiyun * Bug ID 9:
257*4882a593Smuzhiyun * access to 0xf2xx/0xf6xx
258*4882a593Smuzhiyun * must be followed by read from 0xf2ff/0xf6ff.
259*4882a593Smuzhiyun */
260*4882a593Smuzhiyun if ((reg != 0xf2ff) && (reg != 0xf6ff) &&
261*4882a593Smuzhiyun (((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
262*4882a593Smuzhiyun _stb0899_read_reg(state, (reg | 0x00ff));
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun return result;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
_stb0899_read_s2reg(struct stb0899_state * state,u32 stb0899_i2cdev,u32 stb0899_base_addr,u16 stb0899_reg_offset)267*4882a593Smuzhiyun u32 _stb0899_read_s2reg(struct stb0899_state *state,
268*4882a593Smuzhiyun u32 stb0899_i2cdev,
269*4882a593Smuzhiyun u32 stb0899_base_addr,
270*4882a593Smuzhiyun u16 stb0899_reg_offset)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun int status;
273*4882a593Smuzhiyun u32 data;
274*4882a593Smuzhiyun u8 buf[7] = { 0 };
275*4882a593Smuzhiyun u16 tmpaddr;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun u8 buf_0[] = {
278*4882a593Smuzhiyun GETBYTE(stb0899_i2cdev, BYTE1), /* 0xf3 S2 Base Address (MSB) */
279*4882a593Smuzhiyun GETBYTE(stb0899_i2cdev, BYTE0), /* 0xfc S2 Base Address (LSB) */
280*4882a593Smuzhiyun GETBYTE(stb0899_base_addr, BYTE0), /* 0x00 Base Address (LSB) */
281*4882a593Smuzhiyun GETBYTE(stb0899_base_addr, BYTE1), /* 0x04 Base Address (LSB) */
282*4882a593Smuzhiyun GETBYTE(stb0899_base_addr, BYTE2), /* 0x00 Base Address (MSB) */
283*4882a593Smuzhiyun GETBYTE(stb0899_base_addr, BYTE3), /* 0x00 Base Address (MSB) */
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun u8 buf_1[] = {
286*4882a593Smuzhiyun 0x00, /* 0xf3 Reg Offset */
287*4882a593Smuzhiyun 0x00, /* 0x44 Reg Offset */
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun struct i2c_msg msg_0 = {
291*4882a593Smuzhiyun .addr = state->config->demod_address,
292*4882a593Smuzhiyun .flags = 0,
293*4882a593Smuzhiyun .buf = buf_0,
294*4882a593Smuzhiyun .len = 6
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun struct i2c_msg msg_1 = {
298*4882a593Smuzhiyun .addr = state->config->demod_address,
299*4882a593Smuzhiyun .flags = 0,
300*4882a593Smuzhiyun .buf = buf_1,
301*4882a593Smuzhiyun .len = 2
302*4882a593Smuzhiyun };
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun struct i2c_msg msg_r = {
305*4882a593Smuzhiyun .addr = state->config->demod_address,
306*4882a593Smuzhiyun .flags = I2C_M_RD,
307*4882a593Smuzhiyun .buf = buf,
308*4882a593Smuzhiyun .len = 4
309*4882a593Smuzhiyun };
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun tmpaddr = stb0899_reg_offset & 0xff00;
312*4882a593Smuzhiyun if (!(stb0899_reg_offset & 0x8))
313*4882a593Smuzhiyun tmpaddr = stb0899_reg_offset | 0x20;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun buf_1[0] = GETBYTE(tmpaddr, BYTE1);
316*4882a593Smuzhiyun buf_1[1] = GETBYTE(tmpaddr, BYTE0);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun status = i2c_transfer(state->i2c, &msg_0, 1);
319*4882a593Smuzhiyun if (status < 1) {
320*4882a593Smuzhiyun if (status != -ERESTARTSYS)
321*4882a593Smuzhiyun printk(KERN_ERR "%s ERR(1), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
322*4882a593Smuzhiyun __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun goto err;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /* Dummy */
328*4882a593Smuzhiyun status = i2c_transfer(state->i2c, &msg_1, 1);
329*4882a593Smuzhiyun if (status < 1)
330*4882a593Smuzhiyun goto err;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun status = i2c_transfer(state->i2c, &msg_r, 1);
333*4882a593Smuzhiyun if (status < 1)
334*4882a593Smuzhiyun goto err;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun buf_1[0] = GETBYTE(stb0899_reg_offset, BYTE1);
337*4882a593Smuzhiyun buf_1[1] = GETBYTE(stb0899_reg_offset, BYTE0);
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun /* Actual */
340*4882a593Smuzhiyun status = i2c_transfer(state->i2c, &msg_1, 1);
341*4882a593Smuzhiyun if (status < 1) {
342*4882a593Smuzhiyun if (status != -ERESTARTSYS)
343*4882a593Smuzhiyun printk(KERN_ERR "%s ERR(2), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
344*4882a593Smuzhiyun __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
345*4882a593Smuzhiyun goto err;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun status = i2c_transfer(state->i2c, &msg_r, 1);
349*4882a593Smuzhiyun if (status < 1) {
350*4882a593Smuzhiyun if (status != -ERESTARTSYS)
351*4882a593Smuzhiyun printk(KERN_ERR "%s ERR(3), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
352*4882a593Smuzhiyun __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
353*4882a593Smuzhiyun return status < 0 ? status : -EREMOTEIO;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun data = MAKEWORD32(buf[3], buf[2], buf[1], buf[0]);
357*4882a593Smuzhiyun if (unlikely(*state->verbose >= FE_DEBUGREG))
358*4882a593Smuzhiyun printk(KERN_DEBUG "%s Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Data=[0x%08x]\n",
359*4882a593Smuzhiyun __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, data);
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun return data;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun err:
364*4882a593Smuzhiyun return status < 0 ? status : -EREMOTEIO;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
stb0899_write_s2reg(struct stb0899_state * state,u32 stb0899_i2cdev,u32 stb0899_base_addr,u16 stb0899_reg_offset,u32 stb0899_data)367*4882a593Smuzhiyun int stb0899_write_s2reg(struct stb0899_state *state,
368*4882a593Smuzhiyun u32 stb0899_i2cdev,
369*4882a593Smuzhiyun u32 stb0899_base_addr,
370*4882a593Smuzhiyun u16 stb0899_reg_offset,
371*4882a593Smuzhiyun u32 stb0899_data)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun int status;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun /* Base Address Setup */
376*4882a593Smuzhiyun u8 buf_0[] = {
377*4882a593Smuzhiyun GETBYTE(stb0899_i2cdev, BYTE1), /* 0xf3 S2 Base Address (MSB) */
378*4882a593Smuzhiyun GETBYTE(stb0899_i2cdev, BYTE0), /* 0xfc S2 Base Address (LSB) */
379*4882a593Smuzhiyun GETBYTE(stb0899_base_addr, BYTE0), /* 0x00 Base Address (LSB) */
380*4882a593Smuzhiyun GETBYTE(stb0899_base_addr, BYTE1), /* 0x04 Base Address (LSB) */
381*4882a593Smuzhiyun GETBYTE(stb0899_base_addr, BYTE2), /* 0x00 Base Address (MSB) */
382*4882a593Smuzhiyun GETBYTE(stb0899_base_addr, BYTE3), /* 0x00 Base Address (MSB) */
383*4882a593Smuzhiyun };
384*4882a593Smuzhiyun u8 buf_1[] = {
385*4882a593Smuzhiyun 0x00, /* 0xf3 Reg Offset */
386*4882a593Smuzhiyun 0x00, /* 0x44 Reg Offset */
387*4882a593Smuzhiyun 0x00, /* data */
388*4882a593Smuzhiyun 0x00, /* data */
389*4882a593Smuzhiyun 0x00, /* data */
390*4882a593Smuzhiyun 0x00, /* data */
391*4882a593Smuzhiyun };
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun struct i2c_msg msg_0 = {
394*4882a593Smuzhiyun .addr = state->config->demod_address,
395*4882a593Smuzhiyun .flags = 0,
396*4882a593Smuzhiyun .buf = buf_0,
397*4882a593Smuzhiyun .len = 6
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun struct i2c_msg msg_1 = {
401*4882a593Smuzhiyun .addr = state->config->demod_address,
402*4882a593Smuzhiyun .flags = 0,
403*4882a593Smuzhiyun .buf = buf_1,
404*4882a593Smuzhiyun .len = 6
405*4882a593Smuzhiyun };
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun buf_1[0] = GETBYTE(stb0899_reg_offset, BYTE1);
408*4882a593Smuzhiyun buf_1[1] = GETBYTE(stb0899_reg_offset, BYTE0);
409*4882a593Smuzhiyun buf_1[2] = GETBYTE(stb0899_data, BYTE0);
410*4882a593Smuzhiyun buf_1[3] = GETBYTE(stb0899_data, BYTE1);
411*4882a593Smuzhiyun buf_1[4] = GETBYTE(stb0899_data, BYTE2);
412*4882a593Smuzhiyun buf_1[5] = GETBYTE(stb0899_data, BYTE3);
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun if (unlikely(*state->verbose >= FE_DEBUGREG))
415*4882a593Smuzhiyun printk(KERN_DEBUG "%s Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x]\n",
416*4882a593Smuzhiyun __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data);
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun status = i2c_transfer(state->i2c, &msg_0, 1);
419*4882a593Smuzhiyun if (unlikely(status < 1)) {
420*4882a593Smuzhiyun if (status != -ERESTARTSYS)
421*4882a593Smuzhiyun printk(KERN_ERR "%s ERR (1), Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x], status=%d\n",
422*4882a593Smuzhiyun __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data, status);
423*4882a593Smuzhiyun goto err;
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun status = i2c_transfer(state->i2c, &msg_1, 1);
426*4882a593Smuzhiyun if (unlikely(status < 1)) {
427*4882a593Smuzhiyun if (status != -ERESTARTSYS)
428*4882a593Smuzhiyun printk(KERN_ERR "%s ERR (2), Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x], status=%d\n",
429*4882a593Smuzhiyun __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data, status);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun return status < 0 ? status : -EREMOTEIO;
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun return 0;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun err:
437*4882a593Smuzhiyun return status < 0 ? status : -EREMOTEIO;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun
stb0899_read_regs(struct stb0899_state * state,unsigned int reg,u8 * buf,u32 count)440*4882a593Smuzhiyun int stb0899_read_regs(struct stb0899_state *state, unsigned int reg, u8 *buf, u32 count)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun int status;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun u8 b0[] = { reg >> 8, reg & 0xff };
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun struct i2c_msg msg[] = {
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun .addr = state->config->demod_address,
449*4882a593Smuzhiyun .flags = 0,
450*4882a593Smuzhiyun .buf = b0,
451*4882a593Smuzhiyun .len = 2
452*4882a593Smuzhiyun },{
453*4882a593Smuzhiyun .addr = state->config->demod_address,
454*4882a593Smuzhiyun .flags = I2C_M_RD,
455*4882a593Smuzhiyun .buf = buf,
456*4882a593Smuzhiyun .len = count
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun };
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun status = i2c_transfer(state->i2c, msg, 2);
461*4882a593Smuzhiyun if (status != 2) {
462*4882a593Smuzhiyun if (status != -ERESTARTSYS)
463*4882a593Smuzhiyun printk(KERN_ERR "%s Read error, Reg=[0x%04x], Count=%u, Status=%d\n",
464*4882a593Smuzhiyun __func__, reg, count, status);
465*4882a593Smuzhiyun goto err;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun /*
468*4882a593Smuzhiyun * Bug ID 9:
469*4882a593Smuzhiyun * access to 0xf2xx/0xf6xx
470*4882a593Smuzhiyun * must be followed by read from 0xf2ff/0xf6ff.
471*4882a593Smuzhiyun */
472*4882a593Smuzhiyun if ((reg != 0xf2ff) && (reg != 0xf6ff) &&
473*4882a593Smuzhiyun (((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
474*4882a593Smuzhiyun _stb0899_read_reg(state, (reg | 0x00ff));
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUGREG, 1,
477*4882a593Smuzhiyun "%s [0x%04x]: %*ph", __func__, reg, count, buf);
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun return 0;
480*4882a593Smuzhiyun err:
481*4882a593Smuzhiyun return status < 0 ? status : -EREMOTEIO;
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun
stb0899_write_regs(struct stb0899_state * state,unsigned int reg,u8 * data,u32 count)484*4882a593Smuzhiyun int stb0899_write_regs(struct stb0899_state *state, unsigned int reg, u8 *data, u32 count)
485*4882a593Smuzhiyun {
486*4882a593Smuzhiyun int ret;
487*4882a593Smuzhiyun u8 buf[MAX_XFER_SIZE];
488*4882a593Smuzhiyun struct i2c_msg i2c_msg = {
489*4882a593Smuzhiyun .addr = state->config->demod_address,
490*4882a593Smuzhiyun .flags = 0,
491*4882a593Smuzhiyun .buf = buf,
492*4882a593Smuzhiyun .len = 2 + count
493*4882a593Smuzhiyun };
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun if (2 + count > sizeof(buf)) {
496*4882a593Smuzhiyun printk(KERN_WARNING
497*4882a593Smuzhiyun "%s: i2c wr reg=%04x: len=%d is too big!\n",
498*4882a593Smuzhiyun KBUILD_MODNAME, reg, count);
499*4882a593Smuzhiyun return -EINVAL;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun buf[0] = reg >> 8;
503*4882a593Smuzhiyun buf[1] = reg & 0xff;
504*4882a593Smuzhiyun memcpy(&buf[2], data, count);
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUGREG, 1,
507*4882a593Smuzhiyun "%s [0x%04x]: %*ph", __func__, reg, count, data);
508*4882a593Smuzhiyun ret = i2c_transfer(state->i2c, &i2c_msg, 1);
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun /*
511*4882a593Smuzhiyun * Bug ID 9:
512*4882a593Smuzhiyun * access to 0xf2xx/0xf6xx
513*4882a593Smuzhiyun * must be followed by read from 0xf2ff/0xf6ff.
514*4882a593Smuzhiyun */
515*4882a593Smuzhiyun if ((((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
516*4882a593Smuzhiyun stb0899_read_reg(state, (reg | 0x00ff));
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun if (ret != 1) {
519*4882a593Smuzhiyun if (ret != -ERESTARTSYS)
520*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
521*4882a593Smuzhiyun reg, data[0], count, ret);
522*4882a593Smuzhiyun return ret < 0 ? ret : -EREMOTEIO;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun return 0;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
stb0899_write_reg(struct stb0899_state * state,unsigned int reg,u8 data)528*4882a593Smuzhiyun int stb0899_write_reg(struct stb0899_state *state, unsigned int reg, u8 data)
529*4882a593Smuzhiyun {
530*4882a593Smuzhiyun u8 tmp = data;
531*4882a593Smuzhiyun return stb0899_write_regs(state, reg, &tmp, 1);
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /*
535*4882a593Smuzhiyun * stb0899_get_mclk
536*4882a593Smuzhiyun * Get STB0899 master clock frequency
537*4882a593Smuzhiyun * ExtClk: external clock frequency (Hz)
538*4882a593Smuzhiyun */
stb0899_get_mclk(struct stb0899_state * state)539*4882a593Smuzhiyun static u32 stb0899_get_mclk(struct stb0899_state *state)
540*4882a593Smuzhiyun {
541*4882a593Smuzhiyun u32 mclk = 0, div = 0;
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun div = stb0899_read_reg(state, STB0899_NCOARSE);
544*4882a593Smuzhiyun mclk = (div + 1) * state->config->xtal_freq / 6;
545*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "div=%d, mclk=%d", div, mclk);
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun return mclk;
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun /*
551*4882a593Smuzhiyun * stb0899_set_mclk
552*4882a593Smuzhiyun * Set STB0899 master Clock frequency
553*4882a593Smuzhiyun * Mclk: demodulator master clock
554*4882a593Smuzhiyun * ExtClk: external clock frequency (Hz)
555*4882a593Smuzhiyun */
stb0899_set_mclk(struct stb0899_state * state,u32 Mclk)556*4882a593Smuzhiyun static void stb0899_set_mclk(struct stb0899_state *state, u32 Mclk)
557*4882a593Smuzhiyun {
558*4882a593Smuzhiyun struct stb0899_internal *internal = &state->internal;
559*4882a593Smuzhiyun u8 mdiv = 0;
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "state->config=%p", state->config);
562*4882a593Smuzhiyun mdiv = ((6 * Mclk) / state->config->xtal_freq) - 1;
563*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "mdiv=%d", mdiv);
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_NCOARSE, mdiv);
566*4882a593Smuzhiyun internal->master_clk = stb0899_get_mclk(state);
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "MasterCLOCK=%d", internal->master_clk);
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun
stb0899_postproc(struct stb0899_state * state,u8 ctl,int enable)571*4882a593Smuzhiyun static int stb0899_postproc(struct stb0899_state *state, u8 ctl, int enable)
572*4882a593Smuzhiyun {
573*4882a593Smuzhiyun struct stb0899_config *config = state->config;
574*4882a593Smuzhiyun const struct stb0899_postproc *postproc = config->postproc;
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun /* post process event */
577*4882a593Smuzhiyun if (postproc) {
578*4882a593Smuzhiyun if (enable) {
579*4882a593Smuzhiyun if (postproc[ctl].level == STB0899_GPIOPULLUP)
580*4882a593Smuzhiyun stb0899_write_reg(state, postproc[ctl].gpio, 0x02);
581*4882a593Smuzhiyun else
582*4882a593Smuzhiyun stb0899_write_reg(state, postproc[ctl].gpio, 0x82);
583*4882a593Smuzhiyun } else {
584*4882a593Smuzhiyun if (postproc[ctl].level == STB0899_GPIOPULLUP)
585*4882a593Smuzhiyun stb0899_write_reg(state, postproc[ctl].gpio, 0x82);
586*4882a593Smuzhiyun else
587*4882a593Smuzhiyun stb0899_write_reg(state, postproc[ctl].gpio, 0x02);
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun return 0;
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun
stb0899_detach(struct dvb_frontend * fe)593*4882a593Smuzhiyun static void stb0899_detach(struct dvb_frontend *fe)
594*4882a593Smuzhiyun {
595*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun /* post process event */
598*4882a593Smuzhiyun stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 0);
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun
stb0899_release(struct dvb_frontend * fe)601*4882a593Smuzhiyun static void stb0899_release(struct dvb_frontend *fe)
602*4882a593Smuzhiyun {
603*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Release Frontend");
606*4882a593Smuzhiyun kfree(state);
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun /*
610*4882a593Smuzhiyun * stb0899_get_alpha
611*4882a593Smuzhiyun * return: rolloff
612*4882a593Smuzhiyun */
stb0899_get_alpha(struct stb0899_state * state)613*4882a593Smuzhiyun static int stb0899_get_alpha(struct stb0899_state *state)
614*4882a593Smuzhiyun {
615*4882a593Smuzhiyun u8 mode_coeff;
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun mode_coeff = stb0899_read_reg(state, STB0899_DEMOD);
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun if (STB0899_GETFIELD(MODECOEFF, mode_coeff) == 1)
620*4882a593Smuzhiyun return 20;
621*4882a593Smuzhiyun else
622*4882a593Smuzhiyun return 35;
623*4882a593Smuzhiyun }
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun /*
626*4882a593Smuzhiyun * stb0899_init_calc
627*4882a593Smuzhiyun */
stb0899_init_calc(struct stb0899_state * state)628*4882a593Smuzhiyun static void stb0899_init_calc(struct stb0899_state *state)
629*4882a593Smuzhiyun {
630*4882a593Smuzhiyun struct stb0899_internal *internal = &state->internal;
631*4882a593Smuzhiyun int master_clk;
632*4882a593Smuzhiyun u8 agc[2];
633*4882a593Smuzhiyun u32 reg;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun /* Read registers (in burst mode) */
636*4882a593Smuzhiyun stb0899_read_regs(state, STB0899_AGC1REF, agc, 2); /* AGC1R and AGC2O */
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun /* Initial calculations */
639*4882a593Smuzhiyun master_clk = stb0899_get_mclk(state);
640*4882a593Smuzhiyun internal->t_agc1 = 0;
641*4882a593Smuzhiyun internal->t_agc2 = 0;
642*4882a593Smuzhiyun internal->master_clk = master_clk;
643*4882a593Smuzhiyun internal->mclk = master_clk / 65536L;
644*4882a593Smuzhiyun internal->rolloff = stb0899_get_alpha(state);
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun /* DVBS2 Initial calculations */
647*4882a593Smuzhiyun /* Set AGC value to the middle */
648*4882a593Smuzhiyun internal->agc_gain = 8154;
649*4882a593Smuzhiyun reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
650*4882a593Smuzhiyun STB0899_SETFIELD_VAL(IF_GAIN_INIT, reg, internal->agc_gain);
651*4882a593Smuzhiyun stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun reg = STB0899_READ_S2REG(STB0899_S2DEMOD, RRC_ALPHA);
654*4882a593Smuzhiyun internal->rrc_alpha = STB0899_GETFIELD(RRC_ALPHA, reg);
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun internal->center_freq = 0;
657*4882a593Smuzhiyun internal->av_frame_coarse = 10;
658*4882a593Smuzhiyun internal->av_frame_fine = 20;
659*4882a593Smuzhiyun internal->step_size = 2;
660*4882a593Smuzhiyun /*
661*4882a593Smuzhiyun if ((pParams->SpectralInv == FE_IQ_NORMAL) || (pParams->SpectralInv == FE_IQ_AUTO))
662*4882a593Smuzhiyun pParams->IQLocked = 0;
663*4882a593Smuzhiyun else
664*4882a593Smuzhiyun pParams->IQLocked = 1;
665*4882a593Smuzhiyun */
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun
stb0899_wait_diseqc_fifo_empty(struct stb0899_state * state,int timeout)668*4882a593Smuzhiyun static int stb0899_wait_diseqc_fifo_empty(struct stb0899_state *state, int timeout)
669*4882a593Smuzhiyun {
670*4882a593Smuzhiyun u8 reg = 0;
671*4882a593Smuzhiyun unsigned long start = jiffies;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun while (1) {
674*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISSTATUS);
675*4882a593Smuzhiyun if (!STB0899_GETFIELD(FIFOFULL, reg))
676*4882a593Smuzhiyun break;
677*4882a593Smuzhiyun if (time_after(jiffies, start + timeout)) {
678*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "timed out !!");
679*4882a593Smuzhiyun return -ETIMEDOUT;
680*4882a593Smuzhiyun }
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun return 0;
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun
stb0899_send_diseqc_msg(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)686*4882a593Smuzhiyun static int stb0899_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
689*4882a593Smuzhiyun u8 reg, i;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun if (cmd->msg_len > sizeof(cmd->msg))
692*4882a593Smuzhiyun return -EINVAL;
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun /* enable FIFO precharge */
695*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
696*4882a593Smuzhiyun STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 1);
697*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
698*4882a593Smuzhiyun for (i = 0; i < cmd->msg_len; i++) {
699*4882a593Smuzhiyun /* wait for FIFO empty */
700*4882a593Smuzhiyun if (stb0899_wait_diseqc_fifo_empty(state, 100) < 0)
701*4882a593Smuzhiyun return -ETIMEDOUT;
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISFIFO, cmd->msg[i]);
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
706*4882a593Smuzhiyun STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0);
707*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
708*4882a593Smuzhiyun msleep(100);
709*4882a593Smuzhiyun return 0;
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun
stb0899_wait_diseqc_rxidle(struct stb0899_state * state,int timeout)712*4882a593Smuzhiyun static int stb0899_wait_diseqc_rxidle(struct stb0899_state *state, int timeout)
713*4882a593Smuzhiyun {
714*4882a593Smuzhiyun u8 reg = 0;
715*4882a593Smuzhiyun unsigned long start = jiffies;
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun while (!STB0899_GETFIELD(RXEND, reg)) {
718*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISRX_ST0);
719*4882a593Smuzhiyun if (time_after(jiffies, start + timeout)) {
720*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "timed out!!");
721*4882a593Smuzhiyun return -ETIMEDOUT;
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun msleep(10);
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun return 0;
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun
stb0899_recv_slave_reply(struct dvb_frontend * fe,struct dvb_diseqc_slave_reply * reply)729*4882a593Smuzhiyun static int stb0899_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
730*4882a593Smuzhiyun {
731*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
732*4882a593Smuzhiyun u8 reg, length = 0, i;
733*4882a593Smuzhiyun int result;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun if (stb0899_wait_diseqc_rxidle(state, 100) < 0)
736*4882a593Smuzhiyun return -ETIMEDOUT;
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISRX_ST0);
739*4882a593Smuzhiyun if (STB0899_GETFIELD(RXEND, reg)) {
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISRX_ST1);
742*4882a593Smuzhiyun length = STB0899_GETFIELD(FIFOBYTENBR, reg);
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun if (length > sizeof (reply->msg)) {
745*4882a593Smuzhiyun result = -EOVERFLOW;
746*4882a593Smuzhiyun goto exit;
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun reply->msg_len = length;
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun /* extract data */
751*4882a593Smuzhiyun for (i = 0; i < length; i++)
752*4882a593Smuzhiyun reply->msg[i] = stb0899_read_reg(state, STB0899_DISFIFO);
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun return 0;
756*4882a593Smuzhiyun exit:
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun return result;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun
stb0899_wait_diseqc_txidle(struct stb0899_state * state,int timeout)761*4882a593Smuzhiyun static int stb0899_wait_diseqc_txidle(struct stb0899_state *state, int timeout)
762*4882a593Smuzhiyun {
763*4882a593Smuzhiyun u8 reg = 0;
764*4882a593Smuzhiyun unsigned long start = jiffies;
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun while (!STB0899_GETFIELD(TXIDLE, reg)) {
767*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISSTATUS);
768*4882a593Smuzhiyun if (time_after(jiffies, start + timeout)) {
769*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "timed out!!");
770*4882a593Smuzhiyun return -ETIMEDOUT;
771*4882a593Smuzhiyun }
772*4882a593Smuzhiyun msleep(10);
773*4882a593Smuzhiyun }
774*4882a593Smuzhiyun return 0;
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun
stb0899_send_diseqc_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd burst)777*4882a593Smuzhiyun static int stb0899_send_diseqc_burst(struct dvb_frontend *fe,
778*4882a593Smuzhiyun enum fe_sec_mini_cmd burst)
779*4882a593Smuzhiyun {
780*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
781*4882a593Smuzhiyun u8 reg, old_state;
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun /* wait for diseqc idle */
784*4882a593Smuzhiyun if (stb0899_wait_diseqc_txidle(state, 100) < 0)
785*4882a593Smuzhiyun return -ETIMEDOUT;
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
788*4882a593Smuzhiyun old_state = reg;
789*4882a593Smuzhiyun /* set to burst mode */
790*4882a593Smuzhiyun STB0899_SETFIELD_VAL(DISEQCMODE, reg, 0x03);
791*4882a593Smuzhiyun STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x01);
792*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
793*4882a593Smuzhiyun switch (burst) {
794*4882a593Smuzhiyun case SEC_MINI_A:
795*4882a593Smuzhiyun /* unmodulated */
796*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISFIFO, 0x00);
797*4882a593Smuzhiyun break;
798*4882a593Smuzhiyun case SEC_MINI_B:
799*4882a593Smuzhiyun /* modulated */
800*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISFIFO, 0xff);
801*4882a593Smuzhiyun break;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
804*4882a593Smuzhiyun STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x00);
805*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
806*4882a593Smuzhiyun /* wait for diseqc idle */
807*4882a593Smuzhiyun if (stb0899_wait_diseqc_txidle(state, 100) < 0)
808*4882a593Smuzhiyun return -ETIMEDOUT;
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun /* restore state */
811*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISCNTRL1, old_state);
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun return 0;
814*4882a593Smuzhiyun }
815*4882a593Smuzhiyun
stb0899_diseqc_init(struct stb0899_state * state)816*4882a593Smuzhiyun static int stb0899_diseqc_init(struct stb0899_state *state)
817*4882a593Smuzhiyun {
818*4882a593Smuzhiyun /*
819*4882a593Smuzhiyun struct dvb_diseqc_slave_reply rx_data;
820*4882a593Smuzhiyun */
821*4882a593Smuzhiyun u8 f22_tx, reg;
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun u32 mclk, tx_freq = 22000;/* count = 0, i; */
824*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISCNTRL2);
825*4882a593Smuzhiyun STB0899_SETFIELD_VAL(ONECHIP_TRX, reg, 0);
826*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISCNTRL2, reg);
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun /* disable Tx spy */
829*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
830*4882a593Smuzhiyun STB0899_SETFIELD_VAL(DISEQCRESET, reg, 1);
831*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
834*4882a593Smuzhiyun STB0899_SETFIELD_VAL(DISEQCRESET, reg, 0);
835*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun mclk = stb0899_get_mclk(state);
838*4882a593Smuzhiyun f22_tx = mclk / (tx_freq * 32);
839*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISF22, f22_tx); /* DiSEqC Tx freq */
840*4882a593Smuzhiyun state->rx_freq = 20000;
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun return 0;
843*4882a593Smuzhiyun }
844*4882a593Smuzhiyun
stb0899_sleep(struct dvb_frontend * fe)845*4882a593Smuzhiyun static int stb0899_sleep(struct dvb_frontend *fe)
846*4882a593Smuzhiyun {
847*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
848*4882a593Smuzhiyun /*
849*4882a593Smuzhiyun u8 reg;
850*4882a593Smuzhiyun */
851*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Going to Sleep .. (Really tired .. :-))");
852*4882a593Smuzhiyun /* post process event */
853*4882a593Smuzhiyun stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 0);
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun return 0;
856*4882a593Smuzhiyun }
857*4882a593Smuzhiyun
stb0899_wakeup(struct dvb_frontend * fe)858*4882a593Smuzhiyun static int stb0899_wakeup(struct dvb_frontend *fe)
859*4882a593Smuzhiyun {
860*4882a593Smuzhiyun int rc;
861*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun if ((rc = stb0899_write_reg(state, STB0899_SYNTCTRL, STB0899_SELOSCI)))
864*4882a593Smuzhiyun return rc;
865*4882a593Smuzhiyun /* Activate all clocks; DVB-S2 registers are inaccessible otherwise. */
866*4882a593Smuzhiyun if ((rc = stb0899_write_reg(state, STB0899_STOPCLK1, 0x00)))
867*4882a593Smuzhiyun return rc;
868*4882a593Smuzhiyun if ((rc = stb0899_write_reg(state, STB0899_STOPCLK2, 0x00)))
869*4882a593Smuzhiyun return rc;
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun /* post process event */
872*4882a593Smuzhiyun stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 1);
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun return 0;
875*4882a593Smuzhiyun }
876*4882a593Smuzhiyun
stb0899_init(struct dvb_frontend * fe)877*4882a593Smuzhiyun static int stb0899_init(struct dvb_frontend *fe)
878*4882a593Smuzhiyun {
879*4882a593Smuzhiyun int i;
880*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
881*4882a593Smuzhiyun struct stb0899_config *config = state->config;
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Initializing STB0899 ... ");
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun /* init device */
886*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "init device");
887*4882a593Smuzhiyun for (i = 0; config->init_dev[i].address != 0xffff; i++)
888*4882a593Smuzhiyun stb0899_write_reg(state, config->init_dev[i].address, config->init_dev[i].data);
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "init S2 demod");
891*4882a593Smuzhiyun /* init S2 demod */
892*4882a593Smuzhiyun for (i = 0; config->init_s2_demod[i].offset != 0xffff; i++)
893*4882a593Smuzhiyun stb0899_write_s2reg(state, STB0899_S2DEMOD,
894*4882a593Smuzhiyun config->init_s2_demod[i].base_address,
895*4882a593Smuzhiyun config->init_s2_demod[i].offset,
896*4882a593Smuzhiyun config->init_s2_demod[i].data);
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "init S1 demod");
899*4882a593Smuzhiyun /* init S1 demod */
900*4882a593Smuzhiyun for (i = 0; config->init_s1_demod[i].address != 0xffff; i++)
901*4882a593Smuzhiyun stb0899_write_reg(state, config->init_s1_demod[i].address, config->init_s1_demod[i].data);
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "init S2 FEC");
904*4882a593Smuzhiyun /* init S2 fec */
905*4882a593Smuzhiyun for (i = 0; config->init_s2_fec[i].offset != 0xffff; i++)
906*4882a593Smuzhiyun stb0899_write_s2reg(state, STB0899_S2FEC,
907*4882a593Smuzhiyun config->init_s2_fec[i].base_address,
908*4882a593Smuzhiyun config->init_s2_fec[i].offset,
909*4882a593Smuzhiyun config->init_s2_fec[i].data);
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "init TST");
912*4882a593Smuzhiyun /* init test */
913*4882a593Smuzhiyun for (i = 0; config->init_tst[i].address != 0xffff; i++)
914*4882a593Smuzhiyun stb0899_write_reg(state, config->init_tst[i].address, config->init_tst[i].data);
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun stb0899_init_calc(state);
917*4882a593Smuzhiyun stb0899_diseqc_init(state);
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun return 0;
920*4882a593Smuzhiyun }
921*4882a593Smuzhiyun
stb0899_table_lookup(const struct stb0899_tab * tab,int max,int val)922*4882a593Smuzhiyun static int stb0899_table_lookup(const struct stb0899_tab *tab, int max, int val)
923*4882a593Smuzhiyun {
924*4882a593Smuzhiyun int res = 0;
925*4882a593Smuzhiyun int min = 0, med;
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun if (val < tab[min].read)
928*4882a593Smuzhiyun res = tab[min].real;
929*4882a593Smuzhiyun else if (val >= tab[max].read)
930*4882a593Smuzhiyun res = tab[max].real;
931*4882a593Smuzhiyun else {
932*4882a593Smuzhiyun while ((max - min) > 1) {
933*4882a593Smuzhiyun med = (max + min) / 2;
934*4882a593Smuzhiyun if (val >= tab[min].read && val < tab[med].read)
935*4882a593Smuzhiyun max = med;
936*4882a593Smuzhiyun else
937*4882a593Smuzhiyun min = med;
938*4882a593Smuzhiyun }
939*4882a593Smuzhiyun res = ((val - tab[min].read) *
940*4882a593Smuzhiyun (tab[max].real - tab[min].real) /
941*4882a593Smuzhiyun (tab[max].read - tab[min].read)) +
942*4882a593Smuzhiyun tab[min].real;
943*4882a593Smuzhiyun }
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun return res;
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun
stb0899_read_signal_strength(struct dvb_frontend * fe,u16 * strength)948*4882a593Smuzhiyun static int stb0899_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
949*4882a593Smuzhiyun {
950*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
951*4882a593Smuzhiyun struct stb0899_internal *internal = &state->internal;
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun int val;
954*4882a593Smuzhiyun u32 reg;
955*4882a593Smuzhiyun *strength = 0;
956*4882a593Smuzhiyun switch (state->delsys) {
957*4882a593Smuzhiyun case SYS_DVBS:
958*4882a593Smuzhiyun case SYS_DSS:
959*4882a593Smuzhiyun if (internal->lock) {
960*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_VSTATUS);
961*4882a593Smuzhiyun if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_AGCIQIN);
964*4882a593Smuzhiyun val = (s32)(s8)STB0899_GETFIELD(AGCIQVALUE, reg);
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun *strength = stb0899_table_lookup(stb0899_dvbsrf_tab, ARRAY_SIZE(stb0899_dvbsrf_tab) - 1, val);
967*4882a593Smuzhiyun *strength += 750;
968*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "AGCIQVALUE = 0x%02x, C = %d * 0.1 dBm",
969*4882a593Smuzhiyun val & 0xff, *strength);
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun }
972*4882a593Smuzhiyun break;
973*4882a593Smuzhiyun case SYS_DVBS2:
974*4882a593Smuzhiyun if (internal->lock) {
975*4882a593Smuzhiyun reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_GAIN);
976*4882a593Smuzhiyun val = STB0899_GETFIELD(IF_AGC_GAIN, reg);
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun *strength = stb0899_table_lookup(stb0899_dvbs2rf_tab, ARRAY_SIZE(stb0899_dvbs2rf_tab) - 1, val);
979*4882a593Smuzhiyun *strength += 950;
980*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "IF_AGC_GAIN = 0x%04x, C = %d * 0.1 dBm",
981*4882a593Smuzhiyun val & 0x3fff, *strength);
982*4882a593Smuzhiyun }
983*4882a593Smuzhiyun break;
984*4882a593Smuzhiyun default:
985*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
986*4882a593Smuzhiyun return -EINVAL;
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun return 0;
990*4882a593Smuzhiyun }
991*4882a593Smuzhiyun
stb0899_read_snr(struct dvb_frontend * fe,u16 * snr)992*4882a593Smuzhiyun static int stb0899_read_snr(struct dvb_frontend *fe, u16 *snr)
993*4882a593Smuzhiyun {
994*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
995*4882a593Smuzhiyun struct stb0899_internal *internal = &state->internal;
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun unsigned int val, quant, quantn = -1, est, estn = -1;
998*4882a593Smuzhiyun u8 buf[2];
999*4882a593Smuzhiyun u32 reg;
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun *snr = 0;
1002*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_VSTATUS);
1003*4882a593Smuzhiyun switch (state->delsys) {
1004*4882a593Smuzhiyun case SYS_DVBS:
1005*4882a593Smuzhiyun case SYS_DSS:
1006*4882a593Smuzhiyun if (internal->lock) {
1007*4882a593Smuzhiyun if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun stb0899_read_regs(state, STB0899_NIRM, buf, 2);
1010*4882a593Smuzhiyun val = MAKEWORD16(buf[0], buf[1]);
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun *snr = stb0899_table_lookup(stb0899_cn_tab, ARRAY_SIZE(stb0899_cn_tab) - 1, val);
1013*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "NIR = 0x%02x%02x = %u, C/N = %d * 0.1 dBm\n",
1014*4882a593Smuzhiyun buf[0], buf[1], val, *snr);
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun }
1017*4882a593Smuzhiyun break;
1018*4882a593Smuzhiyun case SYS_DVBS2:
1019*4882a593Smuzhiyun if (internal->lock) {
1020*4882a593Smuzhiyun reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
1021*4882a593Smuzhiyun quant = STB0899_GETFIELD(UWP_ESN0_QUANT, reg);
1022*4882a593Smuzhiyun reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1023*4882a593Smuzhiyun est = STB0899_GETFIELD(ESN0_EST, reg);
1024*4882a593Smuzhiyun if (est == 1)
1025*4882a593Smuzhiyun val = 301; /* C/N = 30.1 dB */
1026*4882a593Smuzhiyun else if (est == 2)
1027*4882a593Smuzhiyun val = 270; /* C/N = 27.0 dB */
1028*4882a593Smuzhiyun else {
1029*4882a593Smuzhiyun /* quantn = 100 * log(quant^2) */
1030*4882a593Smuzhiyun quantn = stb0899_table_lookup(stb0899_quant_tab, ARRAY_SIZE(stb0899_quant_tab) - 1, quant * 100);
1031*4882a593Smuzhiyun /* estn = 100 * log(est) */
1032*4882a593Smuzhiyun estn = stb0899_table_lookup(stb0899_est_tab, ARRAY_SIZE(stb0899_est_tab) - 1, est);
1033*4882a593Smuzhiyun /* snr(dBm/10) = -10*(log(est)-log(quant^2)) => snr(dBm/10) = (100*log(quant^2)-100*log(est))/10 */
1034*4882a593Smuzhiyun val = (quantn - estn) / 10;
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun *snr = val;
1037*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Es/N0 quant = %d (%d) estimate = %u (%d), C/N = %d * 0.1 dBm",
1038*4882a593Smuzhiyun quant, quantn, est, estn, val);
1039*4882a593Smuzhiyun }
1040*4882a593Smuzhiyun break;
1041*4882a593Smuzhiyun default:
1042*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
1043*4882a593Smuzhiyun return -EINVAL;
1044*4882a593Smuzhiyun }
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun return 0;
1047*4882a593Smuzhiyun }
1048*4882a593Smuzhiyun
stb0899_read_status(struct dvb_frontend * fe,enum fe_status * status)1049*4882a593Smuzhiyun static int stb0899_read_status(struct dvb_frontend *fe, enum fe_status *status)
1050*4882a593Smuzhiyun {
1051*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
1052*4882a593Smuzhiyun struct stb0899_internal *internal = &state->internal;
1053*4882a593Smuzhiyun u8 reg;
1054*4882a593Smuzhiyun *status = 0;
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun switch (state->delsys) {
1057*4882a593Smuzhiyun case SYS_DVBS:
1058*4882a593Smuzhiyun case SYS_DSS:
1059*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Delivery system DVB-S/DSS");
1060*4882a593Smuzhiyun if (internal->lock) {
1061*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_VSTATUS);
1062*4882a593Smuzhiyun if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
1063*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "--------> FE_HAS_CARRIER | FE_HAS_LOCK");
1064*4882a593Smuzhiyun *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_LOCK;
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_PLPARM);
1067*4882a593Smuzhiyun if (STB0899_GETFIELD(VITCURPUN, reg)) {
1068*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "--------> FE_HAS_VITERBI | FE_HAS_SYNC");
1069*4882a593Smuzhiyun *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
1070*4882a593Smuzhiyun /* post process event */
1071*4882a593Smuzhiyun stb0899_postproc(state, STB0899_POSTPROC_GPIO_LOCK, 1);
1072*4882a593Smuzhiyun }
1073*4882a593Smuzhiyun }
1074*4882a593Smuzhiyun }
1075*4882a593Smuzhiyun break;
1076*4882a593Smuzhiyun case SYS_DVBS2:
1077*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Delivery system DVB-S2");
1078*4882a593Smuzhiyun if (internal->lock) {
1079*4882a593Smuzhiyun reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1080*4882a593Smuzhiyun if (STB0899_GETFIELD(UWP_LOCK, reg) && STB0899_GETFIELD(CSM_LOCK, reg)) {
1081*4882a593Smuzhiyun *status |= FE_HAS_CARRIER;
1082*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1,
1083*4882a593Smuzhiyun "UWP & CSM Lock ! ---> DVB-S2 FE_HAS_CARRIER");
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1086*4882a593Smuzhiyun if (STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg)) {
1087*4882a593Smuzhiyun *status |= FE_HAS_LOCK;
1088*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1,
1089*4882a593Smuzhiyun "Packet Delineator Locked ! -----> DVB-S2 FE_HAS_LOCK");
1090*4882a593Smuzhiyun
1091*4882a593Smuzhiyun }
1092*4882a593Smuzhiyun if (STB0899_GETFIELD(CONTINUOUS_STREAM, reg)) {
1093*4882a593Smuzhiyun *status |= FE_HAS_VITERBI;
1094*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1,
1095*4882a593Smuzhiyun "Packet Delineator found VITERBI ! -----> DVB-S2 FE_HAS_VITERBI");
1096*4882a593Smuzhiyun }
1097*4882a593Smuzhiyun if (STB0899_GETFIELD(ACCEPTED_STREAM, reg)) {
1098*4882a593Smuzhiyun *status |= FE_HAS_SYNC;
1099*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1,
1100*4882a593Smuzhiyun "Packet Delineator found SYNC ! -----> DVB-S2 FE_HAS_SYNC");
1101*4882a593Smuzhiyun /* post process event */
1102*4882a593Smuzhiyun stb0899_postproc(state, STB0899_POSTPROC_GPIO_LOCK, 1);
1103*4882a593Smuzhiyun }
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun }
1106*4882a593Smuzhiyun break;
1107*4882a593Smuzhiyun default:
1108*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
1109*4882a593Smuzhiyun return -EINVAL;
1110*4882a593Smuzhiyun }
1111*4882a593Smuzhiyun return 0;
1112*4882a593Smuzhiyun }
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun /*
1115*4882a593Smuzhiyun * stb0899_get_error
1116*4882a593Smuzhiyun * viterbi error for DVB-S/DSS
1117*4882a593Smuzhiyun * packet error for DVB-S2
1118*4882a593Smuzhiyun * Bit Error Rate or Packet Error Rate * 10 ^ 7
1119*4882a593Smuzhiyun */
stb0899_read_ber(struct dvb_frontend * fe,u32 * ber)1120*4882a593Smuzhiyun static int stb0899_read_ber(struct dvb_frontend *fe, u32 *ber)
1121*4882a593Smuzhiyun {
1122*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
1123*4882a593Smuzhiyun struct stb0899_internal *internal = &state->internal;
1124*4882a593Smuzhiyun
1125*4882a593Smuzhiyun u8 lsb, msb;
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun *ber = 0;
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun switch (state->delsys) {
1130*4882a593Smuzhiyun case SYS_DVBS:
1131*4882a593Smuzhiyun case SYS_DSS:
1132*4882a593Smuzhiyun if (internal->lock) {
1133*4882a593Smuzhiyun lsb = stb0899_read_reg(state, STB0899_ECNT1L);
1134*4882a593Smuzhiyun msb = stb0899_read_reg(state, STB0899_ECNT1M);
1135*4882a593Smuzhiyun *ber = MAKEWORD16(msb, lsb);
1136*4882a593Smuzhiyun /* Viterbi Check */
1137*4882a593Smuzhiyun if (STB0899_GETFIELD(VSTATUS_PRFVIT, internal->v_status)) {
1138*4882a593Smuzhiyun /* Error Rate */
1139*4882a593Smuzhiyun *ber *= 9766;
1140*4882a593Smuzhiyun /* ber = ber * 10 ^ 7 */
1141*4882a593Smuzhiyun *ber /= (-1 + (1 << (2 * STB0899_GETFIELD(NOE, internal->err_ctrl))));
1142*4882a593Smuzhiyun *ber /= 8;
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun }
1145*4882a593Smuzhiyun break;
1146*4882a593Smuzhiyun case SYS_DVBS2:
1147*4882a593Smuzhiyun if (internal->lock) {
1148*4882a593Smuzhiyun lsb = stb0899_read_reg(state, STB0899_ECNT1L);
1149*4882a593Smuzhiyun msb = stb0899_read_reg(state, STB0899_ECNT1M);
1150*4882a593Smuzhiyun *ber = MAKEWORD16(msb, lsb);
1151*4882a593Smuzhiyun /* ber = ber * 10 ^ 7 */
1152*4882a593Smuzhiyun *ber *= 10000000;
1153*4882a593Smuzhiyun *ber /= (-1 + (1 << (4 + 2 * STB0899_GETFIELD(NOE, internal->err_ctrl))));
1154*4882a593Smuzhiyun }
1155*4882a593Smuzhiyun break;
1156*4882a593Smuzhiyun default:
1157*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
1158*4882a593Smuzhiyun return -EINVAL;
1159*4882a593Smuzhiyun }
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun return 0;
1162*4882a593Smuzhiyun }
1163*4882a593Smuzhiyun
stb0899_set_voltage(struct dvb_frontend * fe,enum fe_sec_voltage voltage)1164*4882a593Smuzhiyun static int stb0899_set_voltage(struct dvb_frontend *fe,
1165*4882a593Smuzhiyun enum fe_sec_voltage voltage)
1166*4882a593Smuzhiyun {
1167*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun switch (voltage) {
1170*4882a593Smuzhiyun case SEC_VOLTAGE_13:
1171*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
1172*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
1173*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_GPIO02CFG, 0x00);
1174*4882a593Smuzhiyun break;
1175*4882a593Smuzhiyun case SEC_VOLTAGE_18:
1176*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_GPIO00CFG, 0x02);
1177*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
1178*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
1179*4882a593Smuzhiyun break;
1180*4882a593Smuzhiyun case SEC_VOLTAGE_OFF:
1181*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
1182*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_GPIO01CFG, 0x82);
1183*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
1184*4882a593Smuzhiyun break;
1185*4882a593Smuzhiyun default:
1186*4882a593Smuzhiyun return -EINVAL;
1187*4882a593Smuzhiyun }
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun return 0;
1190*4882a593Smuzhiyun }
1191*4882a593Smuzhiyun
stb0899_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)1192*4882a593Smuzhiyun static int stb0899_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
1193*4882a593Smuzhiyun {
1194*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
1195*4882a593Smuzhiyun struct stb0899_internal *internal = &state->internal;
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun u8 div, reg;
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun /* wait for diseqc idle */
1200*4882a593Smuzhiyun if (stb0899_wait_diseqc_txidle(state, 100) < 0)
1201*4882a593Smuzhiyun return -ETIMEDOUT;
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun switch (tone) {
1204*4882a593Smuzhiyun case SEC_TONE_ON:
1205*4882a593Smuzhiyun div = (internal->master_clk / 100) / 5632;
1206*4882a593Smuzhiyun div = (div + 5) / 10;
1207*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x66);
1208*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_ACRPRESC);
1209*4882a593Smuzhiyun STB0899_SETFIELD_VAL(ACRPRESC, reg, 0x03);
1210*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_ACRPRESC, reg);
1211*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_ACRDIV1, div);
1212*4882a593Smuzhiyun break;
1213*4882a593Smuzhiyun case SEC_TONE_OFF:
1214*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x20);
1215*4882a593Smuzhiyun break;
1216*4882a593Smuzhiyun default:
1217*4882a593Smuzhiyun return -EINVAL;
1218*4882a593Smuzhiyun }
1219*4882a593Smuzhiyun return 0;
1220*4882a593Smuzhiyun }
1221*4882a593Smuzhiyun
stb0899_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)1222*4882a593Smuzhiyun int stb0899_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
1223*4882a593Smuzhiyun {
1224*4882a593Smuzhiyun int i2c_stat;
1225*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun i2c_stat = stb0899_read_reg(state, STB0899_I2CRPT);
1228*4882a593Smuzhiyun if (i2c_stat < 0)
1229*4882a593Smuzhiyun goto err;
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun if (enable) {
1232*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Enabling I2C Repeater ...");
1233*4882a593Smuzhiyun i2c_stat |= STB0899_I2CTON;
1234*4882a593Smuzhiyun if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
1235*4882a593Smuzhiyun goto err;
1236*4882a593Smuzhiyun } else {
1237*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Disabling I2C Repeater ...");
1238*4882a593Smuzhiyun i2c_stat &= ~STB0899_I2CTON;
1239*4882a593Smuzhiyun if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
1240*4882a593Smuzhiyun goto err;
1241*4882a593Smuzhiyun }
1242*4882a593Smuzhiyun return 0;
1243*4882a593Smuzhiyun err:
1244*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "I2C Repeater control failed");
1245*4882a593Smuzhiyun return -EREMOTEIO;
1246*4882a593Smuzhiyun }
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun
CONVERT32(u32 x,char * str)1249*4882a593Smuzhiyun static inline void CONVERT32(u32 x, char *str)
1250*4882a593Smuzhiyun {
1251*4882a593Smuzhiyun *str++ = (x >> 24) & 0xff;
1252*4882a593Smuzhiyun *str++ = (x >> 16) & 0xff;
1253*4882a593Smuzhiyun *str++ = (x >> 8) & 0xff;
1254*4882a593Smuzhiyun *str++ = (x >> 0) & 0xff;
1255*4882a593Smuzhiyun *str = '\0';
1256*4882a593Smuzhiyun }
1257*4882a593Smuzhiyun
stb0899_get_dev_id(struct stb0899_state * state)1258*4882a593Smuzhiyun static int stb0899_get_dev_id(struct stb0899_state *state)
1259*4882a593Smuzhiyun {
1260*4882a593Smuzhiyun u8 chip_id, release;
1261*4882a593Smuzhiyun u16 id;
1262*4882a593Smuzhiyun u32 demod_ver = 0, fec_ver = 0;
1263*4882a593Smuzhiyun char demod_str[5] = { 0 };
1264*4882a593Smuzhiyun char fec_str[5] = { 0 };
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun id = stb0899_read_reg(state, STB0899_DEV_ID);
1267*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "ID reg=[0x%02x]", id);
1268*4882a593Smuzhiyun chip_id = STB0899_GETFIELD(CHIP_ID, id);
1269*4882a593Smuzhiyun release = STB0899_GETFIELD(CHIP_REL, id);
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "Device ID=[%d], Release=[%d]",
1272*4882a593Smuzhiyun chip_id, release);
1273*4882a593Smuzhiyun
1274*4882a593Smuzhiyun CONVERT32(STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CORE_ID), (char *)&demod_str);
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun demod_ver = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_VERSION_ID);
1277*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "Demodulator Core ID=[%s], Version=[%d]", (char *) &demod_str, demod_ver);
1278*4882a593Smuzhiyun CONVERT32(STB0899_READ_S2REG(STB0899_S2FEC, FEC_CORE_ID_REG), (char *)&fec_str);
1279*4882a593Smuzhiyun fec_ver = STB0899_READ_S2REG(STB0899_S2FEC, FEC_VER_ID_REG);
1280*4882a593Smuzhiyun if (! (chip_id > 0)) {
1281*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "couldn't find a STB 0899");
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun return -ENODEV;
1284*4882a593Smuzhiyun }
1285*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "FEC Core ID=[%s], Version=[%d]", (char*) &fec_str, fec_ver);
1286*4882a593Smuzhiyun
1287*4882a593Smuzhiyun return 0;
1288*4882a593Smuzhiyun }
1289*4882a593Smuzhiyun
stb0899_set_delivery(struct stb0899_state * state)1290*4882a593Smuzhiyun static void stb0899_set_delivery(struct stb0899_state *state)
1291*4882a593Smuzhiyun {
1292*4882a593Smuzhiyun u8 reg;
1293*4882a593Smuzhiyun u8 stop_clk[2];
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun stop_clk[0] = stb0899_read_reg(state, STB0899_STOPCLK1);
1296*4882a593Smuzhiyun stop_clk[1] = stb0899_read_reg(state, STB0899_STOPCLK2);
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun switch (state->delsys) {
1299*4882a593Smuzhiyun case SYS_DVBS:
1300*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Delivery System -- DVB-S");
1301*4882a593Smuzhiyun /* FECM/Viterbi ON */
1302*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_FECM);
1303*4882a593Smuzhiyun STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0);
1304*4882a593Smuzhiyun STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1);
1305*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_FECM, reg);
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_RSULC, 0xb1);
1308*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_TSULC, 0x40);
1309*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_RSLLC, 0x42);
1310*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_TSLPL, 0x12);
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_TSTRES);
1313*4882a593Smuzhiyun STB0899_SETFIELD_VAL(FRESLDPC, reg, 1);
1314*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_TSTRES, reg);
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
1317*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 1);
1318*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 1);
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 1);
1321*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 1);
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKINTBUF216, stop_clk[0], 1);
1324*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 1);
1327*4882a593Smuzhiyun break;
1328*4882a593Smuzhiyun case SYS_DVBS2:
1329*4882a593Smuzhiyun /* FECM/Viterbi OFF */
1330*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_FECM);
1331*4882a593Smuzhiyun STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0);
1332*4882a593Smuzhiyun STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 0);
1333*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_FECM, reg);
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_RSULC, 0xb1);
1336*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_TSULC, 0x42);
1337*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_RSLLC, 0x40);
1338*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_TSLPL, 0x02);
1339*4882a593Smuzhiyun
1340*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_TSTRES);
1341*4882a593Smuzhiyun STB0899_SETFIELD_VAL(FRESLDPC, reg, 0);
1342*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_TSTRES, reg);
1343*4882a593Smuzhiyun
1344*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
1345*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 0);
1346*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 0);
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 0);
1349*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 0);
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKINTBUF216, stop_clk[0], 0);
1352*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
1353*4882a593Smuzhiyun
1354*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 0);
1355*4882a593Smuzhiyun break;
1356*4882a593Smuzhiyun case SYS_DSS:
1357*4882a593Smuzhiyun /* FECM/Viterbi ON */
1358*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_FECM);
1359*4882a593Smuzhiyun STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 1);
1360*4882a593Smuzhiyun STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1);
1361*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_FECM, reg);
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_RSULC, 0xa1);
1364*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_TSULC, 0x61);
1365*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_RSLLC, 0x42);
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun reg = stb0899_read_reg(state, STB0899_TSTRES);
1368*4882a593Smuzhiyun STB0899_SETFIELD_VAL(FRESLDPC, reg, 1);
1369*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_TSTRES, reg);
1370*4882a593Smuzhiyun
1371*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
1372*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 1);
1373*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 1);
1374*4882a593Smuzhiyun
1375*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 1);
1376*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 1);
1377*4882a593Smuzhiyun
1378*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
1379*4882a593Smuzhiyun
1380*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 1);
1381*4882a593Smuzhiyun break;
1382*4882a593Smuzhiyun default:
1383*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "Unsupported delivery system");
1384*4882a593Smuzhiyun break;
1385*4882a593Smuzhiyun }
1386*4882a593Smuzhiyun STB0899_SETFIELD_VAL(STOP_CKADCI108, stop_clk[0], 0);
1387*4882a593Smuzhiyun stb0899_write_regs(state, STB0899_STOPCLK1, stop_clk, 2);
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun /*
1391*4882a593Smuzhiyun * stb0899_set_iterations
1392*4882a593Smuzhiyun * set the LDPC iteration scale function
1393*4882a593Smuzhiyun */
stb0899_set_iterations(struct stb0899_state * state)1394*4882a593Smuzhiyun static void stb0899_set_iterations(struct stb0899_state *state)
1395*4882a593Smuzhiyun {
1396*4882a593Smuzhiyun struct stb0899_internal *internal = &state->internal;
1397*4882a593Smuzhiyun struct stb0899_config *config = state->config;
1398*4882a593Smuzhiyun
1399*4882a593Smuzhiyun s32 iter_scale;
1400*4882a593Smuzhiyun u32 reg;
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun iter_scale = 17 * (internal->master_clk / 1000);
1403*4882a593Smuzhiyun iter_scale += 410000;
1404*4882a593Smuzhiyun iter_scale /= (internal->srate / 1000000);
1405*4882a593Smuzhiyun iter_scale /= 1000;
1406*4882a593Smuzhiyun
1407*4882a593Smuzhiyun if (iter_scale > config->ldpc_max_iter)
1408*4882a593Smuzhiyun iter_scale = config->ldpc_max_iter;
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun reg = STB0899_READ_S2REG(STB0899_S2FEC, MAX_ITER);
1411*4882a593Smuzhiyun STB0899_SETFIELD_VAL(MAX_ITERATIONS, reg, iter_scale);
1412*4882a593Smuzhiyun stb0899_write_s2reg(state, STB0899_S2FEC, STB0899_BASE_MAX_ITER, STB0899_OFF0_MAX_ITER, reg);
1413*4882a593Smuzhiyun }
1414*4882a593Smuzhiyun
stb0899_search(struct dvb_frontend * fe)1415*4882a593Smuzhiyun static enum dvbfe_search stb0899_search(struct dvb_frontend *fe)
1416*4882a593Smuzhiyun {
1417*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
1418*4882a593Smuzhiyun struct stb0899_params *i_params = &state->params;
1419*4882a593Smuzhiyun struct stb0899_internal *internal = &state->internal;
1420*4882a593Smuzhiyun struct stb0899_config *config = state->config;
1421*4882a593Smuzhiyun struct dtv_frontend_properties *props = &fe->dtv_property_cache;
1422*4882a593Smuzhiyun
1423*4882a593Smuzhiyun u32 SearchRange, gain;
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun i_params->freq = props->frequency;
1426*4882a593Smuzhiyun i_params->srate = props->symbol_rate;
1427*4882a593Smuzhiyun state->delsys = props->delivery_system;
1428*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "delivery system=%d", state->delsys);
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun SearchRange = 10000000;
1431*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Frequency=%d, Srate=%d", i_params->freq, i_params->srate);
1432*4882a593Smuzhiyun /* checking Search Range is meaningless for a fixed 3 Mhz */
1433*4882a593Smuzhiyun if (INRANGE(i_params->srate, 1000000, 45000000)) {
1434*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Parameters IN RANGE");
1435*4882a593Smuzhiyun stb0899_set_delivery(state);
1436*4882a593Smuzhiyun
1437*4882a593Smuzhiyun if (state->config->tuner_set_rfsiggain) {
1438*4882a593Smuzhiyun if (internal->srate > 15000000)
1439*4882a593Smuzhiyun gain = 8; /* 15Mb < srate < 45Mb, gain = 8dB */
1440*4882a593Smuzhiyun else if (internal->srate > 5000000)
1441*4882a593Smuzhiyun gain = 12; /* 5Mb < srate < 15Mb, gain = 12dB */
1442*4882a593Smuzhiyun else
1443*4882a593Smuzhiyun gain = 14; /* 1Mb < srate < 5Mb, gain = 14db */
1444*4882a593Smuzhiyun state->config->tuner_set_rfsiggain(fe, gain);
1445*4882a593Smuzhiyun }
1446*4882a593Smuzhiyun
1447*4882a593Smuzhiyun if (i_params->srate <= 5000000)
1448*4882a593Smuzhiyun stb0899_set_mclk(state, config->lo_clk);
1449*4882a593Smuzhiyun else
1450*4882a593Smuzhiyun stb0899_set_mclk(state, config->hi_clk);
1451*4882a593Smuzhiyun
1452*4882a593Smuzhiyun switch (state->delsys) {
1453*4882a593Smuzhiyun case SYS_DVBS:
1454*4882a593Smuzhiyun case SYS_DSS:
1455*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "DVB-S delivery system");
1456*4882a593Smuzhiyun internal->freq = i_params->freq;
1457*4882a593Smuzhiyun internal->srate = i_params->srate;
1458*4882a593Smuzhiyun /*
1459*4882a593Smuzhiyun * search = user search range +
1460*4882a593Smuzhiyun * 500Khz +
1461*4882a593Smuzhiyun * 2 * Tuner_step_size +
1462*4882a593Smuzhiyun * 10% of the symbol rate
1463*4882a593Smuzhiyun */
1464*4882a593Smuzhiyun internal->srch_range = SearchRange + 1500000 + (i_params->srate / 5);
1465*4882a593Smuzhiyun internal->derot_percent = 30;
1466*4882a593Smuzhiyun
1467*4882a593Smuzhiyun /* What to do for tuners having no bandwidth setup ? */
1468*4882a593Smuzhiyun /* enable tuner I/O */
1469*4882a593Smuzhiyun stb0899_i2c_gate_ctrl(&state->frontend, 1);
1470*4882a593Smuzhiyun
1471*4882a593Smuzhiyun if (state->config->tuner_set_bandwidth)
1472*4882a593Smuzhiyun state->config->tuner_set_bandwidth(fe, (13 * (stb0899_carr_width(state) + SearchRange)) / 10);
1473*4882a593Smuzhiyun if (state->config->tuner_get_bandwidth)
1474*4882a593Smuzhiyun state->config->tuner_get_bandwidth(fe, &internal->tuner_bw);
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun /* disable tuner I/O */
1477*4882a593Smuzhiyun stb0899_i2c_gate_ctrl(&state->frontend, 0);
1478*4882a593Smuzhiyun
1479*4882a593Smuzhiyun /* Set DVB-S1 AGC */
1480*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_AGCRFCFG, 0x11);
1481*4882a593Smuzhiyun
1482*4882a593Smuzhiyun /* Run the search algorithm */
1483*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "running DVB-S search algo ..");
1484*4882a593Smuzhiyun if (stb0899_dvbs_algo(state) == RANGEOK) {
1485*4882a593Smuzhiyun internal->lock = 1;
1486*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1,
1487*4882a593Smuzhiyun "-------------------------------------> DVB-S LOCK !");
1488*4882a593Smuzhiyun
1489*4882a593Smuzhiyun // stb0899_write_reg(state, STB0899_ERRCTRL1, 0x3d); /* Viterbi Errors */
1490*4882a593Smuzhiyun // internal->v_status = stb0899_read_reg(state, STB0899_VSTATUS);
1491*4882a593Smuzhiyun // internal->err_ctrl = stb0899_read_reg(state, STB0899_ERRCTRL1);
1492*4882a593Smuzhiyun // dprintk(state->verbose, FE_DEBUG, 1, "VSTATUS=0x%02x", internal->v_status);
1493*4882a593Smuzhiyun // dprintk(state->verbose, FE_DEBUG, 1, "ERR_CTRL=0x%02x", internal->err_ctrl);
1494*4882a593Smuzhiyun
1495*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_SUCCESS;
1496*4882a593Smuzhiyun } else {
1497*4882a593Smuzhiyun internal->lock = 0;
1498*4882a593Smuzhiyun
1499*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_FAILED;
1500*4882a593Smuzhiyun }
1501*4882a593Smuzhiyun break;
1502*4882a593Smuzhiyun case SYS_DVBS2:
1503*4882a593Smuzhiyun internal->freq = i_params->freq;
1504*4882a593Smuzhiyun internal->srate = i_params->srate;
1505*4882a593Smuzhiyun internal->srch_range = SearchRange;
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun /* enable tuner I/O */
1508*4882a593Smuzhiyun stb0899_i2c_gate_ctrl(&state->frontend, 1);
1509*4882a593Smuzhiyun
1510*4882a593Smuzhiyun if (state->config->tuner_set_bandwidth)
1511*4882a593Smuzhiyun state->config->tuner_set_bandwidth(fe, (stb0899_carr_width(state) + SearchRange));
1512*4882a593Smuzhiyun if (state->config->tuner_get_bandwidth)
1513*4882a593Smuzhiyun state->config->tuner_get_bandwidth(fe, &internal->tuner_bw);
1514*4882a593Smuzhiyun
1515*4882a593Smuzhiyun /* disable tuner I/O */
1516*4882a593Smuzhiyun stb0899_i2c_gate_ctrl(&state->frontend, 0);
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun // pParams->SpectralInv = pSearch->IQ_Inversion;
1519*4882a593Smuzhiyun
1520*4882a593Smuzhiyun /* Set DVB-S2 AGC */
1521*4882a593Smuzhiyun stb0899_write_reg(state, STB0899_AGCRFCFG, 0x1c);
1522*4882a593Smuzhiyun
1523*4882a593Smuzhiyun /* Set IterScale =f(MCLK,SYMB) */
1524*4882a593Smuzhiyun stb0899_set_iterations(state);
1525*4882a593Smuzhiyun
1526*4882a593Smuzhiyun /* Run the search algorithm */
1527*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "running DVB-S2 search algo ..");
1528*4882a593Smuzhiyun if (stb0899_dvbs2_algo(state) == DVBS2_FEC_LOCK) {
1529*4882a593Smuzhiyun internal->lock = 1;
1530*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1,
1531*4882a593Smuzhiyun "-------------------------------------> DVB-S2 LOCK !");
1532*4882a593Smuzhiyun
1533*4882a593Smuzhiyun // stb0899_write_reg(state, STB0899_ERRCTRL1, 0xb6); /* Packet Errors */
1534*4882a593Smuzhiyun // internal->v_status = stb0899_read_reg(state, STB0899_VSTATUS);
1535*4882a593Smuzhiyun // internal->err_ctrl = stb0899_read_reg(state, STB0899_ERRCTRL1);
1536*4882a593Smuzhiyun
1537*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_SUCCESS;
1538*4882a593Smuzhiyun } else {
1539*4882a593Smuzhiyun internal->lock = 0;
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_FAILED;
1542*4882a593Smuzhiyun }
1543*4882a593Smuzhiyun break;
1544*4882a593Smuzhiyun default:
1545*4882a593Smuzhiyun dprintk(state->verbose, FE_ERROR, 1, "Unsupported delivery system");
1546*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_INVALID;
1547*4882a593Smuzhiyun }
1548*4882a593Smuzhiyun }
1549*4882a593Smuzhiyun
1550*4882a593Smuzhiyun return DVBFE_ALGO_SEARCH_ERROR;
1551*4882a593Smuzhiyun }
1552*4882a593Smuzhiyun
stb0899_get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * p)1553*4882a593Smuzhiyun static int stb0899_get_frontend(struct dvb_frontend *fe,
1554*4882a593Smuzhiyun struct dtv_frontend_properties *p)
1555*4882a593Smuzhiyun {
1556*4882a593Smuzhiyun struct stb0899_state *state = fe->demodulator_priv;
1557*4882a593Smuzhiyun struct stb0899_internal *internal = &state->internal;
1558*4882a593Smuzhiyun
1559*4882a593Smuzhiyun dprintk(state->verbose, FE_DEBUG, 1, "Get params");
1560*4882a593Smuzhiyun p->symbol_rate = internal->srate;
1561*4882a593Smuzhiyun p->frequency = internal->freq;
1562*4882a593Smuzhiyun
1563*4882a593Smuzhiyun return 0;
1564*4882a593Smuzhiyun }
1565*4882a593Smuzhiyun
stb0899_frontend_algo(struct dvb_frontend * fe)1566*4882a593Smuzhiyun static enum dvbfe_algo stb0899_frontend_algo(struct dvb_frontend *fe)
1567*4882a593Smuzhiyun {
1568*4882a593Smuzhiyun return DVBFE_ALGO_CUSTOM;
1569*4882a593Smuzhiyun }
1570*4882a593Smuzhiyun
1571*4882a593Smuzhiyun static const struct dvb_frontend_ops stb0899_ops = {
1572*4882a593Smuzhiyun .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1573*4882a593Smuzhiyun .info = {
1574*4882a593Smuzhiyun .name = "STB0899 Multistandard",
1575*4882a593Smuzhiyun .frequency_min_hz = 950 * MHz,
1576*4882a593Smuzhiyun .frequency_max_hz = 2150 * MHz,
1577*4882a593Smuzhiyun .symbol_rate_min = 5000000,
1578*4882a593Smuzhiyun .symbol_rate_max = 45000000,
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun .caps = FE_CAN_INVERSION_AUTO |
1581*4882a593Smuzhiyun FE_CAN_FEC_AUTO |
1582*4882a593Smuzhiyun FE_CAN_2G_MODULATION |
1583*4882a593Smuzhiyun FE_CAN_QPSK
1584*4882a593Smuzhiyun },
1585*4882a593Smuzhiyun
1586*4882a593Smuzhiyun .detach = stb0899_detach,
1587*4882a593Smuzhiyun .release = stb0899_release,
1588*4882a593Smuzhiyun .init = stb0899_init,
1589*4882a593Smuzhiyun .sleep = stb0899_sleep,
1590*4882a593Smuzhiyun // .wakeup = stb0899_wakeup,
1591*4882a593Smuzhiyun
1592*4882a593Smuzhiyun .i2c_gate_ctrl = stb0899_i2c_gate_ctrl,
1593*4882a593Smuzhiyun
1594*4882a593Smuzhiyun .get_frontend_algo = stb0899_frontend_algo,
1595*4882a593Smuzhiyun .search = stb0899_search,
1596*4882a593Smuzhiyun .get_frontend = stb0899_get_frontend,
1597*4882a593Smuzhiyun
1598*4882a593Smuzhiyun
1599*4882a593Smuzhiyun .read_status = stb0899_read_status,
1600*4882a593Smuzhiyun .read_snr = stb0899_read_snr,
1601*4882a593Smuzhiyun .read_signal_strength = stb0899_read_signal_strength,
1602*4882a593Smuzhiyun .read_ber = stb0899_read_ber,
1603*4882a593Smuzhiyun
1604*4882a593Smuzhiyun .set_voltage = stb0899_set_voltage,
1605*4882a593Smuzhiyun .set_tone = stb0899_set_tone,
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun .diseqc_send_master_cmd = stb0899_send_diseqc_msg,
1608*4882a593Smuzhiyun .diseqc_recv_slave_reply = stb0899_recv_slave_reply,
1609*4882a593Smuzhiyun .diseqc_send_burst = stb0899_send_diseqc_burst,
1610*4882a593Smuzhiyun };
1611*4882a593Smuzhiyun
stb0899_attach(struct stb0899_config * config,struct i2c_adapter * i2c)1612*4882a593Smuzhiyun struct dvb_frontend *stb0899_attach(struct stb0899_config *config, struct i2c_adapter *i2c)
1613*4882a593Smuzhiyun {
1614*4882a593Smuzhiyun struct stb0899_state *state = NULL;
1615*4882a593Smuzhiyun
1616*4882a593Smuzhiyun state = kzalloc(sizeof (struct stb0899_state), GFP_KERNEL);
1617*4882a593Smuzhiyun if (state == NULL)
1618*4882a593Smuzhiyun goto error;
1619*4882a593Smuzhiyun
1620*4882a593Smuzhiyun state->verbose = &verbose;
1621*4882a593Smuzhiyun state->config = config;
1622*4882a593Smuzhiyun state->i2c = i2c;
1623*4882a593Smuzhiyun state->frontend.ops = stb0899_ops;
1624*4882a593Smuzhiyun state->frontend.demodulator_priv = state;
1625*4882a593Smuzhiyun /* use configured inversion as default -- we'll later autodetect inversion */
1626*4882a593Smuzhiyun state->internal.inversion = config->inversion;
1627*4882a593Smuzhiyun
1628*4882a593Smuzhiyun stb0899_wakeup(&state->frontend);
1629*4882a593Smuzhiyun if (stb0899_get_dev_id(state) == -ENODEV) {
1630*4882a593Smuzhiyun printk("%s: Exiting .. !\n", __func__);
1631*4882a593Smuzhiyun goto error;
1632*4882a593Smuzhiyun }
1633*4882a593Smuzhiyun
1634*4882a593Smuzhiyun printk("%s: Attaching STB0899 \n", __func__);
1635*4882a593Smuzhiyun return &state->frontend;
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun error:
1638*4882a593Smuzhiyun kfree(state);
1639*4882a593Smuzhiyun return NULL;
1640*4882a593Smuzhiyun }
1641*4882a593Smuzhiyun EXPORT_SYMBOL(stb0899_attach);
1642*4882a593Smuzhiyun MODULE_PARM_DESC(verbose, "Set Verbosity level");
1643*4882a593Smuzhiyun MODULE_AUTHOR("Manu Abraham");
1644*4882a593Smuzhiyun MODULE_DESCRIPTION("STB0899 Multi-Std frontend");
1645*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1646