1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * CIMaX SP2/HF CI driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Olli Salonen <olli.salonen@iki.fi> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef SP2_PRIV_H 9*4882a593Smuzhiyun #define SP2_PRIV_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "sp2.h" 12*4882a593Smuzhiyun #include <media/dvb_frontend.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* state struct */ 15*4882a593Smuzhiyun struct sp2 { 16*4882a593Smuzhiyun int status; 17*4882a593Smuzhiyun struct i2c_client *client; 18*4882a593Smuzhiyun struct dvb_adapter *dvb_adap; 19*4882a593Smuzhiyun struct dvb_ca_en50221 ca; 20*4882a593Smuzhiyun int module_access_type; 21*4882a593Smuzhiyun unsigned long next_status_checked_time; 22*4882a593Smuzhiyun void *priv; 23*4882a593Smuzhiyun void *ci_control; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define SP2_CI_ATTR_ACS 0x00 27*4882a593Smuzhiyun #define SP2_CI_IO_ACS 0x04 28*4882a593Smuzhiyun #define SP2_CI_WR 0 29*4882a593Smuzhiyun #define SP2_CI_RD 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Module control register (0x00 module A, 0x09 module B) bits */ 32*4882a593Smuzhiyun #define SP2_MOD_CTL_DET 0x01 33*4882a593Smuzhiyun #define SP2_MOD_CTL_AUTO 0x02 34*4882a593Smuzhiyun #define SP2_MOD_CTL_ACS0 0x04 35*4882a593Smuzhiyun #define SP2_MOD_CTL_ACS1 0x08 36*4882a593Smuzhiyun #define SP2_MOD_CTL_HAD 0x10 37*4882a593Smuzhiyun #define SP2_MOD_CTL_TSIEN 0x20 38*4882a593Smuzhiyun #define SP2_MOD_CTL_TSOEN 0x40 39*4882a593Smuzhiyun #define SP2_MOD_CTL_RST 0x80 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif 42