xref: /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/s921.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *   Sharp VA3A5JZ921 One Seg Broadcast Module driver
4*4882a593Smuzhiyun  *   This device is labeled as just S. 921 at the top of the frontend can
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  *   Copyright (C) 2009-2010 Mauro Carvalho Chehab
7*4882a593Smuzhiyun  *   Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  *   Developed for Leadership SBTVD 1seg device sold in Brazil
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  *   Frontend module based on cx24123 driver, getting some info from
12*4882a593Smuzhiyun  *	the old s921 driver.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *   FIXME: Need to port to DVB v5.2 API
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/kernel.h>
18*4882a593Smuzhiyun #include <asm/div64.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <media/dvb_frontend.h>
21*4882a593Smuzhiyun #include "s921.h"
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun static int debug = 1;
24*4882a593Smuzhiyun module_param(debug, int, 0644);
25*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define rc(args...)  do {						\
28*4882a593Smuzhiyun 	printk(KERN_ERR  "s921: " args);				\
29*4882a593Smuzhiyun } while (0)
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define dprintk(args...)						\
32*4882a593Smuzhiyun 	do {								\
33*4882a593Smuzhiyun 		if (debug) {						\
34*4882a593Smuzhiyun 			printk(KERN_DEBUG "s921: %s: ", __func__);	\
35*4882a593Smuzhiyun 			printk(args);					\
36*4882a593Smuzhiyun 		}							\
37*4882a593Smuzhiyun 	} while (0)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun struct s921_state {
40*4882a593Smuzhiyun 	struct i2c_adapter *i2c;
41*4882a593Smuzhiyun 	const struct s921_config *config;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	struct dvb_frontend frontend;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	/* The Demod can't easily provide these, we cache them */
46*4882a593Smuzhiyun 	u32 currentfreq;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun /*
50*4882a593Smuzhiyun  * Various tuner defaults need to be established for a given frequency kHz.
51*4882a593Smuzhiyun  * fixme: The bounds on the bands do not match the doc in real life.
52*4882a593Smuzhiyun  * fixme: Some of them have been moved, other might need adjustment.
53*4882a593Smuzhiyun  */
54*4882a593Smuzhiyun static struct s921_bandselect_val {
55*4882a593Smuzhiyun 	u32 freq_low;
56*4882a593Smuzhiyun 	u8  band_reg;
57*4882a593Smuzhiyun } s921_bandselect[] = {
58*4882a593Smuzhiyun 	{         0, 0x7b },
59*4882a593Smuzhiyun 	{ 485140000, 0x5b },
60*4882a593Smuzhiyun 	{ 515140000, 0x3b },
61*4882a593Smuzhiyun 	{ 545140000, 0x1b },
62*4882a593Smuzhiyun 	{ 599140000, 0xfb },
63*4882a593Smuzhiyun 	{ 623140000, 0xdb },
64*4882a593Smuzhiyun 	{ 659140000, 0xbb },
65*4882a593Smuzhiyun 	{ 713140000, 0x9b },
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun struct regdata {
69*4882a593Smuzhiyun 	u8 reg;
70*4882a593Smuzhiyun 	u8 data;
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun static struct regdata s921_init[] = {
74*4882a593Smuzhiyun 	{ 0x01, 0x80 },		/* Probably, a reset sequence */
75*4882a593Smuzhiyun 	{ 0x01, 0x40 },
76*4882a593Smuzhiyun 	{ 0x01, 0x80 },
77*4882a593Smuzhiyun 	{ 0x01, 0x40 },
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	{ 0x02, 0x00 },
80*4882a593Smuzhiyun 	{ 0x03, 0x40 },
81*4882a593Smuzhiyun 	{ 0x04, 0x01 },
82*4882a593Smuzhiyun 	{ 0x05, 0x00 },
83*4882a593Smuzhiyun 	{ 0x06, 0x00 },
84*4882a593Smuzhiyun 	{ 0x07, 0x00 },
85*4882a593Smuzhiyun 	{ 0x08, 0x00 },
86*4882a593Smuzhiyun 	{ 0x09, 0x00 },
87*4882a593Smuzhiyun 	{ 0x0a, 0x00 },
88*4882a593Smuzhiyun 	{ 0x0b, 0x5a },
89*4882a593Smuzhiyun 	{ 0x0c, 0x00 },
90*4882a593Smuzhiyun 	{ 0x0d, 0x00 },
91*4882a593Smuzhiyun 	{ 0x0f, 0x00 },
92*4882a593Smuzhiyun 	{ 0x13, 0x1b },
93*4882a593Smuzhiyun 	{ 0x14, 0x80 },
94*4882a593Smuzhiyun 	{ 0x15, 0x40 },
95*4882a593Smuzhiyun 	{ 0x17, 0x70 },
96*4882a593Smuzhiyun 	{ 0x18, 0x01 },
97*4882a593Smuzhiyun 	{ 0x19, 0x12 },
98*4882a593Smuzhiyun 	{ 0x1a, 0x01 },
99*4882a593Smuzhiyun 	{ 0x1b, 0x12 },
100*4882a593Smuzhiyun 	{ 0x1c, 0xa0 },
101*4882a593Smuzhiyun 	{ 0x1d, 0x00 },
102*4882a593Smuzhiyun 	{ 0x1e, 0x0a },
103*4882a593Smuzhiyun 	{ 0x1f, 0x08 },
104*4882a593Smuzhiyun 	{ 0x20, 0x40 },
105*4882a593Smuzhiyun 	{ 0x21, 0xff },
106*4882a593Smuzhiyun 	{ 0x22, 0x4c },
107*4882a593Smuzhiyun 	{ 0x23, 0x4e },
108*4882a593Smuzhiyun 	{ 0x24, 0x4c },
109*4882a593Smuzhiyun 	{ 0x25, 0x00 },
110*4882a593Smuzhiyun 	{ 0x26, 0x00 },
111*4882a593Smuzhiyun 	{ 0x27, 0xf4 },
112*4882a593Smuzhiyun 	{ 0x28, 0x60 },
113*4882a593Smuzhiyun 	{ 0x29, 0x88 },
114*4882a593Smuzhiyun 	{ 0x2a, 0x40 },
115*4882a593Smuzhiyun 	{ 0x2b, 0x40 },
116*4882a593Smuzhiyun 	{ 0x2c, 0xff },
117*4882a593Smuzhiyun 	{ 0x2d, 0x00 },
118*4882a593Smuzhiyun 	{ 0x2e, 0xff },
119*4882a593Smuzhiyun 	{ 0x2f, 0x00 },
120*4882a593Smuzhiyun 	{ 0x30, 0x20 },
121*4882a593Smuzhiyun 	{ 0x31, 0x06 },
122*4882a593Smuzhiyun 	{ 0x32, 0x0c },
123*4882a593Smuzhiyun 	{ 0x34, 0x0f },
124*4882a593Smuzhiyun 	{ 0x37, 0xfe },
125*4882a593Smuzhiyun 	{ 0x38, 0x00 },
126*4882a593Smuzhiyun 	{ 0x39, 0x63 },
127*4882a593Smuzhiyun 	{ 0x3a, 0x10 },
128*4882a593Smuzhiyun 	{ 0x3b, 0x10 },
129*4882a593Smuzhiyun 	{ 0x47, 0x00 },
130*4882a593Smuzhiyun 	{ 0x49, 0xe5 },
131*4882a593Smuzhiyun 	{ 0x4b, 0x00 },
132*4882a593Smuzhiyun 	{ 0x50, 0xc0 },
133*4882a593Smuzhiyun 	{ 0x52, 0x20 },
134*4882a593Smuzhiyun 	{ 0x54, 0x5a },
135*4882a593Smuzhiyun 	{ 0x55, 0x5b },
136*4882a593Smuzhiyun 	{ 0x56, 0x40 },
137*4882a593Smuzhiyun 	{ 0x57, 0x70 },
138*4882a593Smuzhiyun 	{ 0x5c, 0x50 },
139*4882a593Smuzhiyun 	{ 0x5d, 0x00 },
140*4882a593Smuzhiyun 	{ 0x62, 0x17 },
141*4882a593Smuzhiyun 	{ 0x63, 0x2f },
142*4882a593Smuzhiyun 	{ 0x64, 0x6f },
143*4882a593Smuzhiyun 	{ 0x68, 0x00 },
144*4882a593Smuzhiyun 	{ 0x69, 0x89 },
145*4882a593Smuzhiyun 	{ 0x6a, 0x00 },
146*4882a593Smuzhiyun 	{ 0x6b, 0x00 },
147*4882a593Smuzhiyun 	{ 0x6c, 0x00 },
148*4882a593Smuzhiyun 	{ 0x6d, 0x00 },
149*4882a593Smuzhiyun 	{ 0x6e, 0x00 },
150*4882a593Smuzhiyun 	{ 0x70, 0x10 },
151*4882a593Smuzhiyun 	{ 0x71, 0x00 },
152*4882a593Smuzhiyun 	{ 0x75, 0x00 },
153*4882a593Smuzhiyun 	{ 0x76, 0x30 },
154*4882a593Smuzhiyun 	{ 0x77, 0x01 },
155*4882a593Smuzhiyun 	{ 0xaf, 0x00 },
156*4882a593Smuzhiyun 	{ 0xb0, 0xa0 },
157*4882a593Smuzhiyun 	{ 0xb2, 0x3d },
158*4882a593Smuzhiyun 	{ 0xb3, 0x25 },
159*4882a593Smuzhiyun 	{ 0xb4, 0x8b },
160*4882a593Smuzhiyun 	{ 0xb5, 0x4b },
161*4882a593Smuzhiyun 	{ 0xb6, 0x3f },
162*4882a593Smuzhiyun 	{ 0xb7, 0xff },
163*4882a593Smuzhiyun 	{ 0xb8, 0xff },
164*4882a593Smuzhiyun 	{ 0xb9, 0xfc },
165*4882a593Smuzhiyun 	{ 0xba, 0x00 },
166*4882a593Smuzhiyun 	{ 0xbb, 0x00 },
167*4882a593Smuzhiyun 	{ 0xbc, 0x00 },
168*4882a593Smuzhiyun 	{ 0xd0, 0x30 },
169*4882a593Smuzhiyun 	{ 0xe4, 0x84 },
170*4882a593Smuzhiyun 	{ 0xf0, 0x48 },
171*4882a593Smuzhiyun 	{ 0xf1, 0x19 },
172*4882a593Smuzhiyun 	{ 0xf2, 0x5a },
173*4882a593Smuzhiyun 	{ 0xf3, 0x8e },
174*4882a593Smuzhiyun 	{ 0xf4, 0x2d },
175*4882a593Smuzhiyun 	{ 0xf5, 0x07 },
176*4882a593Smuzhiyun 	{ 0xf6, 0x5a },
177*4882a593Smuzhiyun 	{ 0xf7, 0xba },
178*4882a593Smuzhiyun 	{ 0xf8, 0xd7 },
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun static struct regdata s921_prefreq[] = {
182*4882a593Smuzhiyun 	{ 0x47, 0x60 },
183*4882a593Smuzhiyun 	{ 0x68, 0x00 },
184*4882a593Smuzhiyun 	{ 0x69, 0x89 },
185*4882a593Smuzhiyun 	{ 0xf0, 0x48 },
186*4882a593Smuzhiyun 	{ 0xf1, 0x19 },
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun static struct regdata s921_postfreq[] = {
190*4882a593Smuzhiyun 	{ 0xf5, 0xae },
191*4882a593Smuzhiyun 	{ 0xf6, 0xb7 },
192*4882a593Smuzhiyun 	{ 0xf7, 0xba },
193*4882a593Smuzhiyun 	{ 0xf8, 0xd7 },
194*4882a593Smuzhiyun 	{ 0x68, 0x0a },
195*4882a593Smuzhiyun 	{ 0x69, 0x09 },
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
s921_i2c_writereg(struct s921_state * state,u8 i2c_addr,int reg,int data)198*4882a593Smuzhiyun static int s921_i2c_writereg(struct s921_state *state,
199*4882a593Smuzhiyun 			     u8 i2c_addr, int reg, int data)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun 	u8 buf[] = { reg, data };
202*4882a593Smuzhiyun 	struct i2c_msg msg = {
203*4882a593Smuzhiyun 		.addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
204*4882a593Smuzhiyun 	};
205*4882a593Smuzhiyun 	int rc;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	rc = i2c_transfer(state->i2c, &msg, 1);
208*4882a593Smuzhiyun 	if (rc != 1) {
209*4882a593Smuzhiyun 		printk("%s: writereg rcor(rc == %i, reg == 0x%02x, data == 0x%02x)\n",
210*4882a593Smuzhiyun 		       __func__, rc, reg, data);
211*4882a593Smuzhiyun 		return rc;
212*4882a593Smuzhiyun 	}
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	return 0;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun 
s921_i2c_writeregdata(struct s921_state * state,u8 i2c_addr,struct regdata * rd,int size)217*4882a593Smuzhiyun static int s921_i2c_writeregdata(struct s921_state *state, u8 i2c_addr,
218*4882a593Smuzhiyun 				 struct regdata *rd, int size)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	int i, rc;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	for (i = 0; i < size; i++) {
223*4882a593Smuzhiyun 		rc = s921_i2c_writereg(state, i2c_addr, rd[i].reg, rd[i].data);
224*4882a593Smuzhiyun 		if (rc < 0)
225*4882a593Smuzhiyun 			return rc;
226*4882a593Smuzhiyun 	}
227*4882a593Smuzhiyun 	return 0;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun 
s921_i2c_readreg(struct s921_state * state,u8 i2c_addr,u8 reg)230*4882a593Smuzhiyun static int s921_i2c_readreg(struct s921_state *state, u8 i2c_addr, u8 reg)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun 	u8 val;
233*4882a593Smuzhiyun 	int rc;
234*4882a593Smuzhiyun 	struct i2c_msg msg[] = {
235*4882a593Smuzhiyun 		{ .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
236*4882a593Smuzhiyun 		{ .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
237*4882a593Smuzhiyun 	};
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	rc = i2c_transfer(state->i2c, msg, 2);
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	if (rc != 2) {
242*4882a593Smuzhiyun 		rc("%s: reg=0x%x (rcor=%d)\n", __func__, reg, rc);
243*4882a593Smuzhiyun 		return rc;
244*4882a593Smuzhiyun 	}
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	return val;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun #define s921_readreg(state, reg) \
250*4882a593Smuzhiyun 	s921_i2c_readreg(state, state->config->demod_address, reg)
251*4882a593Smuzhiyun #define s921_writereg(state, reg, val) \
252*4882a593Smuzhiyun 	s921_i2c_writereg(state, state->config->demod_address, reg, val)
253*4882a593Smuzhiyun #define s921_writeregdata(state, regdata) \
254*4882a593Smuzhiyun 	s921_i2c_writeregdata(state, state->config->demod_address, \
255*4882a593Smuzhiyun 	regdata, ARRAY_SIZE(regdata))
256*4882a593Smuzhiyun 
s921_pll_tune(struct dvb_frontend * fe)257*4882a593Smuzhiyun static int s921_pll_tune(struct dvb_frontend *fe)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
260*4882a593Smuzhiyun 	struct s921_state *state = fe->demodulator_priv;
261*4882a593Smuzhiyun 	int band, rc, i;
262*4882a593Smuzhiyun 	unsigned long f_offset;
263*4882a593Smuzhiyun 	u8 f_switch;
264*4882a593Smuzhiyun 	u64 offset;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	dprintk("frequency=%i\n", p->frequency);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	for (band = 0; band < ARRAY_SIZE(s921_bandselect); band++)
269*4882a593Smuzhiyun 		if (p->frequency < s921_bandselect[band].freq_low)
270*4882a593Smuzhiyun 			break;
271*4882a593Smuzhiyun 	band--;
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	if (band < 0) {
274*4882a593Smuzhiyun 		rc("%s: frequency out of range\n", __func__);
275*4882a593Smuzhiyun 		return -EINVAL;
276*4882a593Smuzhiyun 	}
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	f_switch = s921_bandselect[band].band_reg;
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	offset = ((u64)p->frequency) * 258;
281*4882a593Smuzhiyun 	do_div(offset, 6000000);
282*4882a593Smuzhiyun 	f_offset = ((unsigned long)offset) + 2321;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	rc = s921_writeregdata(state, s921_prefreq);
285*4882a593Smuzhiyun 	if (rc < 0)
286*4882a593Smuzhiyun 		return rc;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	rc = s921_writereg(state, 0xf2, (f_offset >> 8) & 0xff);
289*4882a593Smuzhiyun 	if (rc < 0)
290*4882a593Smuzhiyun 		return rc;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	rc = s921_writereg(state, 0xf3, f_offset & 0xff);
293*4882a593Smuzhiyun 	if (rc < 0)
294*4882a593Smuzhiyun 		return rc;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	rc = s921_writereg(state, 0xf4, f_switch);
297*4882a593Smuzhiyun 	if (rc < 0)
298*4882a593Smuzhiyun 		return rc;
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	rc = s921_writeregdata(state, s921_postfreq);
301*4882a593Smuzhiyun 	if (rc < 0)
302*4882a593Smuzhiyun 		return rc;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	for (i = 0 ; i < 6; i++) {
305*4882a593Smuzhiyun 		rc = s921_readreg(state, 0x80);
306*4882a593Smuzhiyun 		dprintk("status 0x80: %02x\n", rc);
307*4882a593Smuzhiyun 	}
308*4882a593Smuzhiyun 	rc = s921_writereg(state, 0x01, 0x40);
309*4882a593Smuzhiyun 	if (rc < 0)
310*4882a593Smuzhiyun 		return rc;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	rc = s921_readreg(state, 0x01);
313*4882a593Smuzhiyun 	dprintk("status 0x01: %02x\n", rc);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	rc = s921_readreg(state, 0x80);
316*4882a593Smuzhiyun 	dprintk("status 0x80: %02x\n", rc);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	rc = s921_readreg(state, 0x80);
319*4882a593Smuzhiyun 	dprintk("status 0x80: %02x\n", rc);
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	rc = s921_readreg(state, 0x32);
322*4882a593Smuzhiyun 	dprintk("status 0x32: %02x\n", rc);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	dprintk("pll tune band=%d, pll=%d\n", f_switch, (int)f_offset);
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	return 0;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun 
s921_initfe(struct dvb_frontend * fe)329*4882a593Smuzhiyun static int s921_initfe(struct dvb_frontend *fe)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun 	struct s921_state *state = fe->demodulator_priv;
332*4882a593Smuzhiyun 	int rc;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	dprintk("\n");
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	rc = s921_writeregdata(state, s921_init);
337*4882a593Smuzhiyun 	if (rc < 0)
338*4882a593Smuzhiyun 		return rc;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	return 0;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun 
s921_read_status(struct dvb_frontend * fe,enum fe_status * status)343*4882a593Smuzhiyun static int s921_read_status(struct dvb_frontend *fe, enum fe_status *status)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun 	struct s921_state *state = fe->demodulator_priv;
346*4882a593Smuzhiyun 	int regstatus, rc;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	*status = 0;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	rc = s921_readreg(state, 0x81);
351*4882a593Smuzhiyun 	if (rc < 0)
352*4882a593Smuzhiyun 		return rc;
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	regstatus = rc << 8;
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	rc = s921_readreg(state, 0x82);
357*4882a593Smuzhiyun 	if (rc < 0)
358*4882a593Smuzhiyun 		return rc;
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	regstatus |= rc;
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	dprintk("status = %04x\n", regstatus);
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	/* Full Sync - We don't know what each bit means on regs 0x81/0x82 */
365*4882a593Smuzhiyun 	if ((regstatus & 0xff) == 0x40) {
366*4882a593Smuzhiyun 		*status = FE_HAS_SIGNAL  |
367*4882a593Smuzhiyun 			  FE_HAS_CARRIER |
368*4882a593Smuzhiyun 			  FE_HAS_VITERBI |
369*4882a593Smuzhiyun 			  FE_HAS_SYNC    |
370*4882a593Smuzhiyun 			  FE_HAS_LOCK;
371*4882a593Smuzhiyun 	} else if (regstatus & 0x40) {
372*4882a593Smuzhiyun 		/* This is close to Full Sync, but not enough to get useful info */
373*4882a593Smuzhiyun 		*status = FE_HAS_SIGNAL  |
374*4882a593Smuzhiyun 			  FE_HAS_CARRIER |
375*4882a593Smuzhiyun 			  FE_HAS_VITERBI |
376*4882a593Smuzhiyun 			  FE_HAS_SYNC;
377*4882a593Smuzhiyun 	}
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	return 0;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun 
s921_read_signal_strength(struct dvb_frontend * fe,u16 * strength)382*4882a593Smuzhiyun static int s921_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun 	enum fe_status	status;
385*4882a593Smuzhiyun 	struct s921_state *state = fe->demodulator_priv;
386*4882a593Smuzhiyun 	int rc;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	/* FIXME: Use the proper register for it... 0x80? */
389*4882a593Smuzhiyun 	rc = s921_read_status(fe, &status);
390*4882a593Smuzhiyun 	if (rc < 0)
391*4882a593Smuzhiyun 		return rc;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	*strength = (status & FE_HAS_LOCK) ? 0xffff : 0;
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	dprintk("strength = 0x%04x\n", *strength);
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	rc = s921_readreg(state, 0x01);
398*4882a593Smuzhiyun 	dprintk("status 0x01: %02x\n", rc);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	rc = s921_readreg(state, 0x80);
401*4882a593Smuzhiyun 	dprintk("status 0x80: %02x\n", rc);
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	rc = s921_readreg(state, 0x32);
404*4882a593Smuzhiyun 	dprintk("status 0x32: %02x\n", rc);
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	return 0;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun 
s921_set_frontend(struct dvb_frontend * fe)409*4882a593Smuzhiyun static int s921_set_frontend(struct dvb_frontend *fe)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
412*4882a593Smuzhiyun 	struct s921_state *state = fe->demodulator_priv;
413*4882a593Smuzhiyun 	int rc;
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	dprintk("\n");
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	/* FIXME: We don't know how to use non-auto mode */
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	rc = s921_pll_tune(fe);
420*4882a593Smuzhiyun 	if (rc < 0)
421*4882a593Smuzhiyun 		return rc;
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	state->currentfreq = p->frequency;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	return 0;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun 
s921_get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * p)428*4882a593Smuzhiyun static int s921_get_frontend(struct dvb_frontend *fe,
429*4882a593Smuzhiyun 			     struct dtv_frontend_properties *p)
430*4882a593Smuzhiyun {
431*4882a593Smuzhiyun 	struct s921_state *state = fe->demodulator_priv;
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	/* FIXME: Probably it is possible to get it from regs f1 and f2 */
434*4882a593Smuzhiyun 	p->frequency = state->currentfreq;
435*4882a593Smuzhiyun 	p->delivery_system = SYS_ISDBT;
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	return 0;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
s921_tune(struct dvb_frontend * fe,bool re_tune,unsigned int mode_flags,unsigned int * delay,enum fe_status * status)440*4882a593Smuzhiyun static int s921_tune(struct dvb_frontend *fe,
441*4882a593Smuzhiyun 			bool re_tune,
442*4882a593Smuzhiyun 			unsigned int mode_flags,
443*4882a593Smuzhiyun 			unsigned int *delay,
444*4882a593Smuzhiyun 			enum fe_status *status)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun 	int rc = 0;
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	dprintk("\n");
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	if (re_tune)
451*4882a593Smuzhiyun 		rc = s921_set_frontend(fe);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
454*4882a593Smuzhiyun 		s921_read_status(fe, status);
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	return rc;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun 
s921_get_algo(struct dvb_frontend * fe)459*4882a593Smuzhiyun static enum dvbfe_algo s921_get_algo(struct dvb_frontend *fe)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun 	return DVBFE_ALGO_HW;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun 
s921_release(struct dvb_frontend * fe)464*4882a593Smuzhiyun static void s921_release(struct dvb_frontend *fe)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun 	struct s921_state *state = fe->demodulator_priv;
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	dprintk("\n");
469*4882a593Smuzhiyun 	kfree(state);
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun static const struct dvb_frontend_ops s921_ops;
473*4882a593Smuzhiyun 
s921_attach(const struct s921_config * config,struct i2c_adapter * i2c)474*4882a593Smuzhiyun struct dvb_frontend *s921_attach(const struct s921_config *config,
475*4882a593Smuzhiyun 				    struct i2c_adapter *i2c)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun 	/* allocate memory for the internal state */
478*4882a593Smuzhiyun 	struct s921_state *state =
479*4882a593Smuzhiyun 		kzalloc(sizeof(struct s921_state), GFP_KERNEL);
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	dprintk("\n");
482*4882a593Smuzhiyun 	if (!state) {
483*4882a593Smuzhiyun 		rc("Unable to kzalloc\n");
484*4882a593Smuzhiyun 		return NULL;
485*4882a593Smuzhiyun 	}
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun 	/* setup the state */
488*4882a593Smuzhiyun 	state->config = config;
489*4882a593Smuzhiyun 	state->i2c = i2c;
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	/* create dvb_frontend */
492*4882a593Smuzhiyun 	memcpy(&state->frontend.ops, &s921_ops,
493*4882a593Smuzhiyun 		sizeof(struct dvb_frontend_ops));
494*4882a593Smuzhiyun 	state->frontend.demodulator_priv = state;
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	return &state->frontend;
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun EXPORT_SYMBOL(s921_attach);
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun static const struct dvb_frontend_ops s921_ops = {
501*4882a593Smuzhiyun 	.delsys = { SYS_ISDBT },
502*4882a593Smuzhiyun 	/* Use dib8000 values per default */
503*4882a593Smuzhiyun 	.info = {
504*4882a593Smuzhiyun 		.name = "Sharp S921",
505*4882a593Smuzhiyun 		.frequency_min_hz = 470 * MHz,
506*4882a593Smuzhiyun 		/*
507*4882a593Smuzhiyun 		 * Max should be 770MHz instead, according with Sharp docs,
508*4882a593Smuzhiyun 		 * but Leadership doc says it works up to 806 MHz. This is
509*4882a593Smuzhiyun 		 * required to get channel 69, used in Brazil
510*4882a593Smuzhiyun 		 */
511*4882a593Smuzhiyun 		.frequency_max_hz = 806 * MHz,
512*4882a593Smuzhiyun 		.caps =  FE_CAN_INVERSION_AUTO |
513*4882a593Smuzhiyun 			 FE_CAN_FEC_1_2  | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
514*4882a593Smuzhiyun 			 FE_CAN_FEC_5_6  | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
515*4882a593Smuzhiyun 			 FE_CAN_QPSK     | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
516*4882a593Smuzhiyun 			 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
517*4882a593Smuzhiyun 			 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
518*4882a593Smuzhiyun 			 FE_CAN_HIERARCHY_AUTO,
519*4882a593Smuzhiyun 	},
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	.release = s921_release,
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 	.init = s921_initfe,
524*4882a593Smuzhiyun 	.set_frontend = s921_set_frontend,
525*4882a593Smuzhiyun 	.get_frontend = s921_get_frontend,
526*4882a593Smuzhiyun 	.read_status = s921_read_status,
527*4882a593Smuzhiyun 	.read_signal_strength = s921_read_signal_strength,
528*4882a593Smuzhiyun 	.tune = s921_tune,
529*4882a593Smuzhiyun 	.get_frontend_algo = s921_get_algo,
530*4882a593Smuzhiyun };
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun MODULE_DESCRIPTION("DVB Frontend module for Sharp S921 hardware");
533*4882a593Smuzhiyun MODULE_AUTHOR("Mauro Carvalho Chehab");
534*4882a593Smuzhiyun MODULE_AUTHOR("Douglas Landgraf <dougsland@redhat.com>");
535*4882a593Smuzhiyun MODULE_LICENSE("GPL");
536