1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Realtek RTL2830 DVB-T demodulator driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include "rtl2830_priv.h"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /* Our regmap is bypassing I2C adapter lock, thus we do it! */
rtl2830_bulk_write(struct i2c_client * client,unsigned int reg,const void * val,size_t val_count)11*4882a593Smuzhiyun static int rtl2830_bulk_write(struct i2c_client *client, unsigned int reg,
12*4882a593Smuzhiyun const void *val, size_t val_count)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
15*4882a593Smuzhiyun int ret;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
18*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
19*4882a593Smuzhiyun i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
20*4882a593Smuzhiyun return ret;
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
rtl2830_update_bits(struct i2c_client * client,unsigned int reg,unsigned int mask,unsigned int val)23*4882a593Smuzhiyun static int rtl2830_update_bits(struct i2c_client *client, unsigned int reg,
24*4882a593Smuzhiyun unsigned int mask, unsigned int val)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
27*4882a593Smuzhiyun int ret;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
30*4882a593Smuzhiyun ret = regmap_update_bits(dev->regmap, reg, mask, val);
31*4882a593Smuzhiyun i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
32*4882a593Smuzhiyun return ret;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
rtl2830_bulk_read(struct i2c_client * client,unsigned int reg,void * val,size_t val_count)35*4882a593Smuzhiyun static int rtl2830_bulk_read(struct i2c_client *client, unsigned int reg,
36*4882a593Smuzhiyun void *val, size_t val_count)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
39*4882a593Smuzhiyun int ret;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
42*4882a593Smuzhiyun ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
43*4882a593Smuzhiyun i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
44*4882a593Smuzhiyun return ret;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
rtl2830_init(struct dvb_frontend * fe)47*4882a593Smuzhiyun static int rtl2830_init(struct dvb_frontend *fe)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
50*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
51*4882a593Smuzhiyun struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
52*4882a593Smuzhiyun int ret, i;
53*4882a593Smuzhiyun struct rtl2830_reg_val_mask tab[] = {
54*4882a593Smuzhiyun {0x00d, 0x01, 0x03},
55*4882a593Smuzhiyun {0x00d, 0x10, 0x10},
56*4882a593Smuzhiyun {0x104, 0x00, 0x1e},
57*4882a593Smuzhiyun {0x105, 0x80, 0x80},
58*4882a593Smuzhiyun {0x110, 0x02, 0x03},
59*4882a593Smuzhiyun {0x110, 0x08, 0x0c},
60*4882a593Smuzhiyun {0x17b, 0x00, 0x40},
61*4882a593Smuzhiyun {0x17d, 0x05, 0x0f},
62*4882a593Smuzhiyun {0x17d, 0x50, 0xf0},
63*4882a593Smuzhiyun {0x18c, 0x08, 0x0f},
64*4882a593Smuzhiyun {0x18d, 0x00, 0xc0},
65*4882a593Smuzhiyun {0x188, 0x05, 0x0f},
66*4882a593Smuzhiyun {0x189, 0x00, 0xfc},
67*4882a593Smuzhiyun {0x2d5, 0x02, 0x02},
68*4882a593Smuzhiyun {0x2f1, 0x02, 0x06},
69*4882a593Smuzhiyun {0x2f1, 0x20, 0xf8},
70*4882a593Smuzhiyun {0x16d, 0x00, 0x01},
71*4882a593Smuzhiyun {0x1a6, 0x00, 0x80},
72*4882a593Smuzhiyun {0x106, dev->pdata->vtop, 0x3f},
73*4882a593Smuzhiyun {0x107, dev->pdata->krf, 0x3f},
74*4882a593Smuzhiyun {0x112, 0x28, 0xff},
75*4882a593Smuzhiyun {0x103, dev->pdata->agc_targ_val, 0xff},
76*4882a593Smuzhiyun {0x00a, 0x02, 0x07},
77*4882a593Smuzhiyun {0x140, 0x0c, 0x3c},
78*4882a593Smuzhiyun {0x140, 0x40, 0xc0},
79*4882a593Smuzhiyun {0x15b, 0x05, 0x07},
80*4882a593Smuzhiyun {0x15b, 0x28, 0x38},
81*4882a593Smuzhiyun {0x15c, 0x05, 0x07},
82*4882a593Smuzhiyun {0x15c, 0x28, 0x38},
83*4882a593Smuzhiyun {0x115, dev->pdata->spec_inv, 0x01},
84*4882a593Smuzhiyun {0x16f, 0x01, 0x07},
85*4882a593Smuzhiyun {0x170, 0x18, 0x38},
86*4882a593Smuzhiyun {0x172, 0x0f, 0x0f},
87*4882a593Smuzhiyun {0x173, 0x08, 0x38},
88*4882a593Smuzhiyun {0x175, 0x01, 0x07},
89*4882a593Smuzhiyun {0x176, 0x00, 0xc0},
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(tab); i++) {
93*4882a593Smuzhiyun ret = rtl2830_update_bits(client, tab[i].reg, tab[i].mask,
94*4882a593Smuzhiyun tab[i].val);
95*4882a593Smuzhiyun if (ret)
96*4882a593Smuzhiyun goto err;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun ret = rtl2830_bulk_write(client, 0x18f, "\x28\x00", 2);
100*4882a593Smuzhiyun if (ret)
101*4882a593Smuzhiyun goto err;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun ret = rtl2830_bulk_write(client, 0x195,
104*4882a593Smuzhiyun "\x04\x06\x0a\x12\x0a\x12\x1e\x28", 8);
105*4882a593Smuzhiyun if (ret)
106*4882a593Smuzhiyun goto err;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* TODO: spec init */
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* soft reset */
111*4882a593Smuzhiyun ret = rtl2830_update_bits(client, 0x101, 0x04, 0x04);
112*4882a593Smuzhiyun if (ret)
113*4882a593Smuzhiyun goto err;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun ret = rtl2830_update_bits(client, 0x101, 0x04, 0x00);
116*4882a593Smuzhiyun if (ret)
117*4882a593Smuzhiyun goto err;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* init stats here in order signal app which stats are supported */
120*4882a593Smuzhiyun c->strength.len = 1;
121*4882a593Smuzhiyun c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
122*4882a593Smuzhiyun c->cnr.len = 1;
123*4882a593Smuzhiyun c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
124*4882a593Smuzhiyun c->post_bit_error.len = 1;
125*4882a593Smuzhiyun c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
126*4882a593Smuzhiyun c->post_bit_count.len = 1;
127*4882a593Smuzhiyun c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun dev->sleeping = false;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return ret;
132*4882a593Smuzhiyun err:
133*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
134*4882a593Smuzhiyun return ret;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
rtl2830_sleep(struct dvb_frontend * fe)137*4882a593Smuzhiyun static int rtl2830_sleep(struct dvb_frontend *fe)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
140*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun dev->sleeping = true;
143*4882a593Smuzhiyun dev->fe_status = 0;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
rtl2830_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * s)148*4882a593Smuzhiyun static int rtl2830_get_tune_settings(struct dvb_frontend *fe,
149*4882a593Smuzhiyun struct dvb_frontend_tune_settings *s)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun s->min_delay_ms = 500;
152*4882a593Smuzhiyun s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
153*4882a593Smuzhiyun s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
rtl2830_set_frontend(struct dvb_frontend * fe)158*4882a593Smuzhiyun static int rtl2830_set_frontend(struct dvb_frontend *fe)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
161*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
162*4882a593Smuzhiyun struct dtv_frontend_properties *c = &fe->dtv_property_cache;
163*4882a593Smuzhiyun int ret, i;
164*4882a593Smuzhiyun u64 num;
165*4882a593Smuzhiyun u8 buf[3], u8tmp;
166*4882a593Smuzhiyun u32 if_ctl, if_frequency;
167*4882a593Smuzhiyun static const u8 bw_params1[3][34] = {
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun 0x1f, 0xf0, 0x1f, 0xf0, 0x1f, 0xfa, 0x00, 0x17, 0x00, 0x41,
170*4882a593Smuzhiyun 0x00, 0x64, 0x00, 0x67, 0x00, 0x38, 0x1f, 0xde, 0x1f, 0x7a,
171*4882a593Smuzhiyun 0x1f, 0x47, 0x1f, 0x7c, 0x00, 0x30, 0x01, 0x4b, 0x02, 0x82,
172*4882a593Smuzhiyun 0x03, 0x73, 0x03, 0xcf, /* 6 MHz */
173*4882a593Smuzhiyun }, {
174*4882a593Smuzhiyun 0x1f, 0xfa, 0x1f, 0xda, 0x1f, 0xc1, 0x1f, 0xb3, 0x1f, 0xca,
175*4882a593Smuzhiyun 0x00, 0x07, 0x00, 0x4d, 0x00, 0x6d, 0x00, 0x40, 0x1f, 0xca,
176*4882a593Smuzhiyun 0x1f, 0x4d, 0x1f, 0x2a, 0x1f, 0xb2, 0x00, 0xec, 0x02, 0x7e,
177*4882a593Smuzhiyun 0x03, 0xd0, 0x04, 0x53, /* 7 MHz */
178*4882a593Smuzhiyun }, {
179*4882a593Smuzhiyun 0x00, 0x10, 0x00, 0x0e, 0x1f, 0xf7, 0x1f, 0xc9, 0x1f, 0xa0,
180*4882a593Smuzhiyun 0x1f, 0xa6, 0x1f, 0xec, 0x00, 0x4e, 0x00, 0x7d, 0x00, 0x3a,
181*4882a593Smuzhiyun 0x1f, 0x98, 0x1f, 0x10, 0x1f, 0x40, 0x00, 0x75, 0x02, 0x5f,
182*4882a593Smuzhiyun 0x04, 0x24, 0x04, 0xdb, /* 8 MHz */
183*4882a593Smuzhiyun },
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun static const u8 bw_params2[3][6] = {
186*4882a593Smuzhiyun {0xc3, 0x0c, 0x44, 0x33, 0x33, 0x30}, /* 6 MHz */
187*4882a593Smuzhiyun {0xb8, 0xe3, 0x93, 0x99, 0x99, 0x98}, /* 7 MHz */
188*4882a593Smuzhiyun {0xae, 0xba, 0xf3, 0x26, 0x66, 0x64}, /* 8 MHz */
189*4882a593Smuzhiyun };
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
192*4882a593Smuzhiyun c->frequency, c->bandwidth_hz, c->inversion);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* program tuner */
195*4882a593Smuzhiyun if (fe->ops.tuner_ops.set_params)
196*4882a593Smuzhiyun fe->ops.tuner_ops.set_params(fe);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun switch (c->bandwidth_hz) {
199*4882a593Smuzhiyun case 6000000:
200*4882a593Smuzhiyun i = 0;
201*4882a593Smuzhiyun break;
202*4882a593Smuzhiyun case 7000000:
203*4882a593Smuzhiyun i = 1;
204*4882a593Smuzhiyun break;
205*4882a593Smuzhiyun case 8000000:
206*4882a593Smuzhiyun i = 2;
207*4882a593Smuzhiyun break;
208*4882a593Smuzhiyun default:
209*4882a593Smuzhiyun dev_err(&client->dev, "invalid bandwidth_hz %u\n",
210*4882a593Smuzhiyun c->bandwidth_hz);
211*4882a593Smuzhiyun return -EINVAL;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun ret = rtl2830_update_bits(client, 0x008, 0x06, i << 1);
215*4882a593Smuzhiyun if (ret)
216*4882a593Smuzhiyun goto err;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* program if frequency */
219*4882a593Smuzhiyun if (fe->ops.tuner_ops.get_if_frequency)
220*4882a593Smuzhiyun ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
221*4882a593Smuzhiyun else
222*4882a593Smuzhiyun ret = -EINVAL;
223*4882a593Smuzhiyun if (ret)
224*4882a593Smuzhiyun goto err;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun num = if_frequency % dev->pdata->clk;
227*4882a593Smuzhiyun num *= 0x400000;
228*4882a593Smuzhiyun num = div_u64(num, dev->pdata->clk);
229*4882a593Smuzhiyun num = -num;
230*4882a593Smuzhiyun if_ctl = num & 0x3fffff;
231*4882a593Smuzhiyun dev_dbg(&client->dev, "if_frequency=%d if_ctl=%08x\n",
232*4882a593Smuzhiyun if_frequency, if_ctl);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun buf[0] = (if_ctl >> 16) & 0x3f;
235*4882a593Smuzhiyun buf[1] = (if_ctl >> 8) & 0xff;
236*4882a593Smuzhiyun buf[2] = (if_ctl >> 0) & 0xff;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun ret = rtl2830_bulk_read(client, 0x119, &u8tmp, 1);
239*4882a593Smuzhiyun if (ret)
240*4882a593Smuzhiyun goto err;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun buf[0] |= u8tmp & 0xc0; /* [7:6] */
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun ret = rtl2830_bulk_write(client, 0x119, buf, 3);
245*4882a593Smuzhiyun if (ret)
246*4882a593Smuzhiyun goto err;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* 1/2 split I2C write */
249*4882a593Smuzhiyun ret = rtl2830_bulk_write(client, 0x11c, &bw_params1[i][0], 17);
250*4882a593Smuzhiyun if (ret)
251*4882a593Smuzhiyun goto err;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /* 2/2 split I2C write */
254*4882a593Smuzhiyun ret = rtl2830_bulk_write(client, 0x12d, &bw_params1[i][17], 17);
255*4882a593Smuzhiyun if (ret)
256*4882a593Smuzhiyun goto err;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun ret = rtl2830_bulk_write(client, 0x19d, bw_params2[i], 6);
259*4882a593Smuzhiyun if (ret)
260*4882a593Smuzhiyun goto err;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun return ret;
263*4882a593Smuzhiyun err:
264*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
265*4882a593Smuzhiyun return ret;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
rtl2830_get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * c)268*4882a593Smuzhiyun static int rtl2830_get_frontend(struct dvb_frontend *fe,
269*4882a593Smuzhiyun struct dtv_frontend_properties *c)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
272*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
273*4882a593Smuzhiyun int ret;
274*4882a593Smuzhiyun u8 buf[3];
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun if (dev->sleeping)
277*4882a593Smuzhiyun return 0;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun ret = rtl2830_bulk_read(client, 0x33c, buf, 2);
280*4882a593Smuzhiyun if (ret)
281*4882a593Smuzhiyun goto err;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun ret = rtl2830_bulk_read(client, 0x351, &buf[2], 1);
284*4882a593Smuzhiyun if (ret)
285*4882a593Smuzhiyun goto err;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun switch ((buf[0] >> 2) & 3) {
290*4882a593Smuzhiyun case 0:
291*4882a593Smuzhiyun c->modulation = QPSK;
292*4882a593Smuzhiyun break;
293*4882a593Smuzhiyun case 1:
294*4882a593Smuzhiyun c->modulation = QAM_16;
295*4882a593Smuzhiyun break;
296*4882a593Smuzhiyun case 2:
297*4882a593Smuzhiyun c->modulation = QAM_64;
298*4882a593Smuzhiyun break;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun switch ((buf[2] >> 2) & 1) {
302*4882a593Smuzhiyun case 0:
303*4882a593Smuzhiyun c->transmission_mode = TRANSMISSION_MODE_2K;
304*4882a593Smuzhiyun break;
305*4882a593Smuzhiyun case 1:
306*4882a593Smuzhiyun c->transmission_mode = TRANSMISSION_MODE_8K;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun switch ((buf[2] >> 0) & 3) {
310*4882a593Smuzhiyun case 0:
311*4882a593Smuzhiyun c->guard_interval = GUARD_INTERVAL_1_32;
312*4882a593Smuzhiyun break;
313*4882a593Smuzhiyun case 1:
314*4882a593Smuzhiyun c->guard_interval = GUARD_INTERVAL_1_16;
315*4882a593Smuzhiyun break;
316*4882a593Smuzhiyun case 2:
317*4882a593Smuzhiyun c->guard_interval = GUARD_INTERVAL_1_8;
318*4882a593Smuzhiyun break;
319*4882a593Smuzhiyun case 3:
320*4882a593Smuzhiyun c->guard_interval = GUARD_INTERVAL_1_4;
321*4882a593Smuzhiyun break;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun switch ((buf[0] >> 4) & 7) {
325*4882a593Smuzhiyun case 0:
326*4882a593Smuzhiyun c->hierarchy = HIERARCHY_NONE;
327*4882a593Smuzhiyun break;
328*4882a593Smuzhiyun case 1:
329*4882a593Smuzhiyun c->hierarchy = HIERARCHY_1;
330*4882a593Smuzhiyun break;
331*4882a593Smuzhiyun case 2:
332*4882a593Smuzhiyun c->hierarchy = HIERARCHY_2;
333*4882a593Smuzhiyun break;
334*4882a593Smuzhiyun case 3:
335*4882a593Smuzhiyun c->hierarchy = HIERARCHY_4;
336*4882a593Smuzhiyun break;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun switch ((buf[1] >> 3) & 7) {
340*4882a593Smuzhiyun case 0:
341*4882a593Smuzhiyun c->code_rate_HP = FEC_1_2;
342*4882a593Smuzhiyun break;
343*4882a593Smuzhiyun case 1:
344*4882a593Smuzhiyun c->code_rate_HP = FEC_2_3;
345*4882a593Smuzhiyun break;
346*4882a593Smuzhiyun case 2:
347*4882a593Smuzhiyun c->code_rate_HP = FEC_3_4;
348*4882a593Smuzhiyun break;
349*4882a593Smuzhiyun case 3:
350*4882a593Smuzhiyun c->code_rate_HP = FEC_5_6;
351*4882a593Smuzhiyun break;
352*4882a593Smuzhiyun case 4:
353*4882a593Smuzhiyun c->code_rate_HP = FEC_7_8;
354*4882a593Smuzhiyun break;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun switch ((buf[1] >> 0) & 7) {
358*4882a593Smuzhiyun case 0:
359*4882a593Smuzhiyun c->code_rate_LP = FEC_1_2;
360*4882a593Smuzhiyun break;
361*4882a593Smuzhiyun case 1:
362*4882a593Smuzhiyun c->code_rate_LP = FEC_2_3;
363*4882a593Smuzhiyun break;
364*4882a593Smuzhiyun case 2:
365*4882a593Smuzhiyun c->code_rate_LP = FEC_3_4;
366*4882a593Smuzhiyun break;
367*4882a593Smuzhiyun case 3:
368*4882a593Smuzhiyun c->code_rate_LP = FEC_5_6;
369*4882a593Smuzhiyun break;
370*4882a593Smuzhiyun case 4:
371*4882a593Smuzhiyun c->code_rate_LP = FEC_7_8;
372*4882a593Smuzhiyun break;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun return 0;
376*4882a593Smuzhiyun err:
377*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
378*4882a593Smuzhiyun return ret;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
rtl2830_read_status(struct dvb_frontend * fe,enum fe_status * status)381*4882a593Smuzhiyun static int rtl2830_read_status(struct dvb_frontend *fe, enum fe_status *status)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
384*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
385*4882a593Smuzhiyun struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
386*4882a593Smuzhiyun int ret, stmp;
387*4882a593Smuzhiyun unsigned int utmp;
388*4882a593Smuzhiyun u8 u8tmp, buf[2];
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun *status = 0;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun if (dev->sleeping)
393*4882a593Smuzhiyun return 0;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun ret = rtl2830_bulk_read(client, 0x351, &u8tmp, 1);
396*4882a593Smuzhiyun if (ret)
397*4882a593Smuzhiyun goto err;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun u8tmp = (u8tmp >> 3) & 0x0f; /* [6:3] */
400*4882a593Smuzhiyun if (u8tmp == 11) {
401*4882a593Smuzhiyun *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
402*4882a593Smuzhiyun FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
403*4882a593Smuzhiyun } else if (u8tmp == 10) {
404*4882a593Smuzhiyun *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
405*4882a593Smuzhiyun FE_HAS_VITERBI;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun dev->fe_status = *status;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun /* Signal strength */
411*4882a593Smuzhiyun if (dev->fe_status & FE_HAS_SIGNAL) {
412*4882a593Smuzhiyun /* Read IF AGC */
413*4882a593Smuzhiyun ret = rtl2830_bulk_read(client, 0x359, buf, 2);
414*4882a593Smuzhiyun if (ret)
415*4882a593Smuzhiyun goto err;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun stmp = buf[0] << 8 | buf[1] << 0;
418*4882a593Smuzhiyun stmp = sign_extend32(stmp, 13);
419*4882a593Smuzhiyun utmp = clamp_val(-4 * stmp + 32767, 0x0000, 0xffff);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun dev_dbg(&client->dev, "IF AGC=%d\n", stmp);
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun c->strength.stat[0].scale = FE_SCALE_RELATIVE;
424*4882a593Smuzhiyun c->strength.stat[0].uvalue = utmp;
425*4882a593Smuzhiyun } else {
426*4882a593Smuzhiyun c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun /* CNR */
430*4882a593Smuzhiyun if (dev->fe_status & FE_HAS_VITERBI) {
431*4882a593Smuzhiyun unsigned int hierarchy, constellation;
432*4882a593Smuzhiyun #define CONSTELLATION_NUM 3
433*4882a593Smuzhiyun #define HIERARCHY_NUM 4
434*4882a593Smuzhiyun static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
435*4882a593Smuzhiyun {70705899, 70705899, 70705899, 70705899},
436*4882a593Smuzhiyun {82433173, 82433173, 87483115, 94445660},
437*4882a593Smuzhiyun {92888734, 92888734, 95487525, 99770748},
438*4882a593Smuzhiyun };
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun ret = rtl2830_bulk_read(client, 0x33c, &u8tmp, 1);
441*4882a593Smuzhiyun if (ret)
442*4882a593Smuzhiyun goto err;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
445*4882a593Smuzhiyun if (constellation > CONSTELLATION_NUM - 1)
446*4882a593Smuzhiyun goto err;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
449*4882a593Smuzhiyun if (hierarchy > HIERARCHY_NUM - 1)
450*4882a593Smuzhiyun goto err;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun ret = rtl2830_bulk_read(client, 0x40c, buf, 2);
453*4882a593Smuzhiyun if (ret)
454*4882a593Smuzhiyun goto err;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun utmp = buf[0] << 8 | buf[1] << 0;
457*4882a593Smuzhiyun if (utmp)
458*4882a593Smuzhiyun stmp = (constant[constellation][hierarchy] -
459*4882a593Smuzhiyun intlog10(utmp)) / ((1 << 24) / 10000);
460*4882a593Smuzhiyun else
461*4882a593Smuzhiyun stmp = 0;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun dev_dbg(&client->dev, "CNR raw=%u\n", utmp);
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
466*4882a593Smuzhiyun c->cnr.stat[0].svalue = stmp;
467*4882a593Smuzhiyun } else {
468*4882a593Smuzhiyun c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun /* BER */
472*4882a593Smuzhiyun if (dev->fe_status & FE_HAS_LOCK) {
473*4882a593Smuzhiyun ret = rtl2830_bulk_read(client, 0x34e, buf, 2);
474*4882a593Smuzhiyun if (ret)
475*4882a593Smuzhiyun goto err;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun utmp = buf[0] << 8 | buf[1] << 0;
478*4882a593Smuzhiyun dev->post_bit_error += utmp;
479*4882a593Smuzhiyun dev->post_bit_count += 1000000;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun dev_dbg(&client->dev, "BER errors=%u total=1000000\n", utmp);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
484*4882a593Smuzhiyun c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
485*4882a593Smuzhiyun c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
486*4882a593Smuzhiyun c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
487*4882a593Smuzhiyun } else {
488*4882a593Smuzhiyun c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
489*4882a593Smuzhiyun c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun return ret;
494*4882a593Smuzhiyun err:
495*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
496*4882a593Smuzhiyun return ret;
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun
rtl2830_read_snr(struct dvb_frontend * fe,u16 * snr)499*4882a593Smuzhiyun static int rtl2830_read_snr(struct dvb_frontend *fe, u16 *snr)
500*4882a593Smuzhiyun {
501*4882a593Smuzhiyun struct dtv_frontend_properties *c = &fe->dtv_property_cache;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
504*4882a593Smuzhiyun *snr = div_s64(c->cnr.stat[0].svalue, 100);
505*4882a593Smuzhiyun else
506*4882a593Smuzhiyun *snr = 0;
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun return 0;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
rtl2830_read_ber(struct dvb_frontend * fe,u32 * ber)511*4882a593Smuzhiyun static int rtl2830_read_ber(struct dvb_frontend *fe, u32 *ber)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
514*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun *ber = (dev->post_bit_error - dev->post_bit_error_prev);
517*4882a593Smuzhiyun dev->post_bit_error_prev = dev->post_bit_error;
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun return 0;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
rtl2830_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)522*4882a593Smuzhiyun static int rtl2830_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
523*4882a593Smuzhiyun {
524*4882a593Smuzhiyun *ucblocks = 0;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun return 0;
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
rtl2830_read_signal_strength(struct dvb_frontend * fe,u16 * strength)529*4882a593Smuzhiyun static int rtl2830_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun struct dtv_frontend_properties *c = &fe->dtv_property_cache;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun if (c->strength.stat[0].scale == FE_SCALE_RELATIVE)
534*4882a593Smuzhiyun *strength = c->strength.stat[0].uvalue;
535*4882a593Smuzhiyun else
536*4882a593Smuzhiyun *strength = 0;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun return 0;
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun static const struct dvb_frontend_ops rtl2830_ops = {
542*4882a593Smuzhiyun .delsys = {SYS_DVBT},
543*4882a593Smuzhiyun .info = {
544*4882a593Smuzhiyun .name = "Realtek RTL2830 (DVB-T)",
545*4882a593Smuzhiyun .caps = FE_CAN_FEC_1_2 |
546*4882a593Smuzhiyun FE_CAN_FEC_2_3 |
547*4882a593Smuzhiyun FE_CAN_FEC_3_4 |
548*4882a593Smuzhiyun FE_CAN_FEC_5_6 |
549*4882a593Smuzhiyun FE_CAN_FEC_7_8 |
550*4882a593Smuzhiyun FE_CAN_FEC_AUTO |
551*4882a593Smuzhiyun FE_CAN_QPSK |
552*4882a593Smuzhiyun FE_CAN_QAM_16 |
553*4882a593Smuzhiyun FE_CAN_QAM_64 |
554*4882a593Smuzhiyun FE_CAN_QAM_AUTO |
555*4882a593Smuzhiyun FE_CAN_TRANSMISSION_MODE_AUTO |
556*4882a593Smuzhiyun FE_CAN_GUARD_INTERVAL_AUTO |
557*4882a593Smuzhiyun FE_CAN_HIERARCHY_AUTO |
558*4882a593Smuzhiyun FE_CAN_RECOVER |
559*4882a593Smuzhiyun FE_CAN_MUTE_TS
560*4882a593Smuzhiyun },
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun .init = rtl2830_init,
563*4882a593Smuzhiyun .sleep = rtl2830_sleep,
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun .get_tune_settings = rtl2830_get_tune_settings,
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun .set_frontend = rtl2830_set_frontend,
568*4882a593Smuzhiyun .get_frontend = rtl2830_get_frontend,
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun .read_status = rtl2830_read_status,
571*4882a593Smuzhiyun .read_snr = rtl2830_read_snr,
572*4882a593Smuzhiyun .read_ber = rtl2830_read_ber,
573*4882a593Smuzhiyun .read_ucblocks = rtl2830_read_ucblocks,
574*4882a593Smuzhiyun .read_signal_strength = rtl2830_read_signal_strength,
575*4882a593Smuzhiyun };
576*4882a593Smuzhiyun
rtl2830_pid_filter_ctrl(struct dvb_frontend * fe,int onoff)577*4882a593Smuzhiyun static int rtl2830_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
578*4882a593Smuzhiyun {
579*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
580*4882a593Smuzhiyun int ret;
581*4882a593Smuzhiyun u8 u8tmp;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun dev_dbg(&client->dev, "onoff=%d\n", onoff);
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun /* enable / disable PID filter */
586*4882a593Smuzhiyun if (onoff)
587*4882a593Smuzhiyun u8tmp = 0x80;
588*4882a593Smuzhiyun else
589*4882a593Smuzhiyun u8tmp = 0x00;
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun ret = rtl2830_update_bits(client, 0x061, 0x80, u8tmp);
592*4882a593Smuzhiyun if (ret)
593*4882a593Smuzhiyun goto err;
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun return 0;
596*4882a593Smuzhiyun err:
597*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
598*4882a593Smuzhiyun return ret;
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun
rtl2830_pid_filter(struct dvb_frontend * fe,u8 index,u16 pid,int onoff)601*4882a593Smuzhiyun static int rtl2830_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid, int onoff)
602*4882a593Smuzhiyun {
603*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
604*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
605*4882a593Smuzhiyun int ret;
606*4882a593Smuzhiyun u8 buf[4];
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
609*4882a593Smuzhiyun index, pid, onoff);
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun /* skip invalid PIDs (0x2000) */
612*4882a593Smuzhiyun if (pid > 0x1fff || index > 32)
613*4882a593Smuzhiyun return 0;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun if (onoff)
616*4882a593Smuzhiyun set_bit(index, &dev->filters);
617*4882a593Smuzhiyun else
618*4882a593Smuzhiyun clear_bit(index, &dev->filters);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun /* enable / disable PIDs */
621*4882a593Smuzhiyun buf[0] = (dev->filters >> 0) & 0xff;
622*4882a593Smuzhiyun buf[1] = (dev->filters >> 8) & 0xff;
623*4882a593Smuzhiyun buf[2] = (dev->filters >> 16) & 0xff;
624*4882a593Smuzhiyun buf[3] = (dev->filters >> 24) & 0xff;
625*4882a593Smuzhiyun ret = rtl2830_bulk_write(client, 0x062, buf, 4);
626*4882a593Smuzhiyun if (ret)
627*4882a593Smuzhiyun goto err;
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun /* add PID */
630*4882a593Smuzhiyun buf[0] = (pid >> 8) & 0xff;
631*4882a593Smuzhiyun buf[1] = (pid >> 0) & 0xff;
632*4882a593Smuzhiyun ret = rtl2830_bulk_write(client, 0x066 + 2 * index, buf, 2);
633*4882a593Smuzhiyun if (ret)
634*4882a593Smuzhiyun goto err;
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun return 0;
637*4882a593Smuzhiyun err:
638*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
639*4882a593Smuzhiyun return ret;
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun /*
643*4882a593Smuzhiyun * I2C gate/mux/repeater logic
644*4882a593Smuzhiyun * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
645*4882a593Smuzhiyun * adapter lock is already taken by tuner driver.
646*4882a593Smuzhiyun * Gate is closed automatically after single I2C transfer.
647*4882a593Smuzhiyun */
rtl2830_select(struct i2c_mux_core * muxc,u32 chan_id)648*4882a593Smuzhiyun static int rtl2830_select(struct i2c_mux_core *muxc, u32 chan_id)
649*4882a593Smuzhiyun {
650*4882a593Smuzhiyun struct i2c_client *client = i2c_mux_priv(muxc);
651*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
652*4882a593Smuzhiyun int ret;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun /* open I2C repeater for 1 transfer, closes automatically */
657*4882a593Smuzhiyun /* XXX: regmap_update_bits() does not lock I2C adapter */
658*4882a593Smuzhiyun ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
659*4882a593Smuzhiyun if (ret)
660*4882a593Smuzhiyun goto err;
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun return 0;
663*4882a593Smuzhiyun err:
664*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
665*4882a593Smuzhiyun return ret;
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun
rtl2830_get_dvb_frontend(struct i2c_client * client)668*4882a593Smuzhiyun static struct dvb_frontend *rtl2830_get_dvb_frontend(struct i2c_client *client)
669*4882a593Smuzhiyun {
670*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun return &dev->fe;
675*4882a593Smuzhiyun }
676*4882a593Smuzhiyun
rtl2830_get_i2c_adapter(struct i2c_client * client)677*4882a593Smuzhiyun static struct i2c_adapter *rtl2830_get_i2c_adapter(struct i2c_client *client)
678*4882a593Smuzhiyun {
679*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun return dev->muxc->adapter[0];
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun /*
687*4882a593Smuzhiyun * We implement own I2C access routines for regmap in order to get manual access
688*4882a593Smuzhiyun * to I2C adapter lock, which is needed for I2C mux adapter.
689*4882a593Smuzhiyun */
rtl2830_regmap_read(void * context,const void * reg_buf,size_t reg_size,void * val_buf,size_t val_size)690*4882a593Smuzhiyun static int rtl2830_regmap_read(void *context, const void *reg_buf,
691*4882a593Smuzhiyun size_t reg_size, void *val_buf, size_t val_size)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun struct i2c_client *client = context;
694*4882a593Smuzhiyun int ret;
695*4882a593Smuzhiyun struct i2c_msg msg[2] = {
696*4882a593Smuzhiyun {
697*4882a593Smuzhiyun .addr = client->addr,
698*4882a593Smuzhiyun .flags = 0,
699*4882a593Smuzhiyun .len = reg_size,
700*4882a593Smuzhiyun .buf = (u8 *)reg_buf,
701*4882a593Smuzhiyun }, {
702*4882a593Smuzhiyun .addr = client->addr,
703*4882a593Smuzhiyun .flags = I2C_M_RD,
704*4882a593Smuzhiyun .len = val_size,
705*4882a593Smuzhiyun .buf = val_buf,
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun };
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun ret = __i2c_transfer(client->adapter, msg, 2);
710*4882a593Smuzhiyun if (ret != 2) {
711*4882a593Smuzhiyun dev_warn(&client->dev, "i2c reg read failed %d\n", ret);
712*4882a593Smuzhiyun if (ret >= 0)
713*4882a593Smuzhiyun ret = -EREMOTEIO;
714*4882a593Smuzhiyun return ret;
715*4882a593Smuzhiyun }
716*4882a593Smuzhiyun return 0;
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun
rtl2830_regmap_write(void * context,const void * data,size_t count)719*4882a593Smuzhiyun static int rtl2830_regmap_write(void *context, const void *data, size_t count)
720*4882a593Smuzhiyun {
721*4882a593Smuzhiyun struct i2c_client *client = context;
722*4882a593Smuzhiyun int ret;
723*4882a593Smuzhiyun struct i2c_msg msg[1] = {
724*4882a593Smuzhiyun {
725*4882a593Smuzhiyun .addr = client->addr,
726*4882a593Smuzhiyun .flags = 0,
727*4882a593Smuzhiyun .len = count,
728*4882a593Smuzhiyun .buf = (u8 *)data,
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun };
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun ret = __i2c_transfer(client->adapter, msg, 1);
733*4882a593Smuzhiyun if (ret != 1) {
734*4882a593Smuzhiyun dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
735*4882a593Smuzhiyun if (ret >= 0)
736*4882a593Smuzhiyun ret = -EREMOTEIO;
737*4882a593Smuzhiyun return ret;
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun return 0;
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun
rtl2830_regmap_gather_write(void * context,const void * reg,size_t reg_len,const void * val,size_t val_len)742*4882a593Smuzhiyun static int rtl2830_regmap_gather_write(void *context, const void *reg,
743*4882a593Smuzhiyun size_t reg_len, const void *val,
744*4882a593Smuzhiyun size_t val_len)
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun struct i2c_client *client = context;
747*4882a593Smuzhiyun int ret;
748*4882a593Smuzhiyun u8 buf[256];
749*4882a593Smuzhiyun struct i2c_msg msg[1] = {
750*4882a593Smuzhiyun {
751*4882a593Smuzhiyun .addr = client->addr,
752*4882a593Smuzhiyun .flags = 0,
753*4882a593Smuzhiyun .len = 1 + val_len,
754*4882a593Smuzhiyun .buf = buf,
755*4882a593Smuzhiyun }
756*4882a593Smuzhiyun };
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun buf[0] = *(u8 const *)reg;
759*4882a593Smuzhiyun memcpy(&buf[1], val, val_len);
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun ret = __i2c_transfer(client->adapter, msg, 1);
762*4882a593Smuzhiyun if (ret != 1) {
763*4882a593Smuzhiyun dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
764*4882a593Smuzhiyun if (ret >= 0)
765*4882a593Smuzhiyun ret = -EREMOTEIO;
766*4882a593Smuzhiyun return ret;
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun return 0;
769*4882a593Smuzhiyun }
770*4882a593Smuzhiyun
rtl2830_probe(struct i2c_client * client,const struct i2c_device_id * id)771*4882a593Smuzhiyun static int rtl2830_probe(struct i2c_client *client,
772*4882a593Smuzhiyun const struct i2c_device_id *id)
773*4882a593Smuzhiyun {
774*4882a593Smuzhiyun struct rtl2830_platform_data *pdata = client->dev.platform_data;
775*4882a593Smuzhiyun struct rtl2830_dev *dev;
776*4882a593Smuzhiyun int ret;
777*4882a593Smuzhiyun u8 u8tmp;
778*4882a593Smuzhiyun static const struct regmap_bus regmap_bus = {
779*4882a593Smuzhiyun .read = rtl2830_regmap_read,
780*4882a593Smuzhiyun .write = rtl2830_regmap_write,
781*4882a593Smuzhiyun .gather_write = rtl2830_regmap_gather_write,
782*4882a593Smuzhiyun .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
783*4882a593Smuzhiyun };
784*4882a593Smuzhiyun static const struct regmap_range_cfg regmap_range_cfg[] = {
785*4882a593Smuzhiyun {
786*4882a593Smuzhiyun .selector_reg = 0x00,
787*4882a593Smuzhiyun .selector_mask = 0xff,
788*4882a593Smuzhiyun .selector_shift = 0,
789*4882a593Smuzhiyun .window_start = 0,
790*4882a593Smuzhiyun .window_len = 0x100,
791*4882a593Smuzhiyun .range_min = 0 * 0x100,
792*4882a593Smuzhiyun .range_max = 5 * 0x100,
793*4882a593Smuzhiyun },
794*4882a593Smuzhiyun };
795*4882a593Smuzhiyun static const struct regmap_config regmap_config = {
796*4882a593Smuzhiyun .reg_bits = 8,
797*4882a593Smuzhiyun .val_bits = 8,
798*4882a593Smuzhiyun .max_register = 5 * 0x100,
799*4882a593Smuzhiyun .ranges = regmap_range_cfg,
800*4882a593Smuzhiyun .num_ranges = ARRAY_SIZE(regmap_range_cfg),
801*4882a593Smuzhiyun };
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun if (pdata == NULL) {
806*4882a593Smuzhiyun ret = -EINVAL;
807*4882a593Smuzhiyun goto err;
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun /* allocate memory for the internal state */
811*4882a593Smuzhiyun dev = kzalloc(sizeof(*dev), GFP_KERNEL);
812*4882a593Smuzhiyun if (dev == NULL) {
813*4882a593Smuzhiyun ret = -ENOMEM;
814*4882a593Smuzhiyun goto err;
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun /* setup the state */
818*4882a593Smuzhiyun i2c_set_clientdata(client, dev);
819*4882a593Smuzhiyun dev->client = client;
820*4882a593Smuzhiyun dev->pdata = client->dev.platform_data;
821*4882a593Smuzhiyun dev->sleeping = true;
822*4882a593Smuzhiyun dev->regmap = regmap_init(&client->dev, ®map_bus, client,
823*4882a593Smuzhiyun ®map_config);
824*4882a593Smuzhiyun if (IS_ERR(dev->regmap)) {
825*4882a593Smuzhiyun ret = PTR_ERR(dev->regmap);
826*4882a593Smuzhiyun goto err_kfree;
827*4882a593Smuzhiyun }
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun /* check if the demod is there */
830*4882a593Smuzhiyun ret = rtl2830_bulk_read(client, 0x000, &u8tmp, 1);
831*4882a593Smuzhiyun if (ret)
832*4882a593Smuzhiyun goto err_regmap_exit;
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun /* create muxed i2c adapter for tuner */
835*4882a593Smuzhiyun dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
836*4882a593Smuzhiyun rtl2830_select, NULL);
837*4882a593Smuzhiyun if (!dev->muxc) {
838*4882a593Smuzhiyun ret = -ENOMEM;
839*4882a593Smuzhiyun goto err_regmap_exit;
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun dev->muxc->priv = client;
842*4882a593Smuzhiyun ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
843*4882a593Smuzhiyun if (ret)
844*4882a593Smuzhiyun goto err_regmap_exit;
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun /* create dvb frontend */
847*4882a593Smuzhiyun memcpy(&dev->fe.ops, &rtl2830_ops, sizeof(dev->fe.ops));
848*4882a593Smuzhiyun dev->fe.demodulator_priv = client;
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun /* setup callbacks */
851*4882a593Smuzhiyun pdata->get_dvb_frontend = rtl2830_get_dvb_frontend;
852*4882a593Smuzhiyun pdata->get_i2c_adapter = rtl2830_get_i2c_adapter;
853*4882a593Smuzhiyun pdata->pid_filter = rtl2830_pid_filter;
854*4882a593Smuzhiyun pdata->pid_filter_ctrl = rtl2830_pid_filter_ctrl;
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun dev_info(&client->dev, "Realtek RTL2830 successfully attached\n");
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun return 0;
859*4882a593Smuzhiyun err_regmap_exit:
860*4882a593Smuzhiyun regmap_exit(dev->regmap);
861*4882a593Smuzhiyun err_kfree:
862*4882a593Smuzhiyun kfree(dev);
863*4882a593Smuzhiyun err:
864*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
865*4882a593Smuzhiyun return ret;
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun
rtl2830_remove(struct i2c_client * client)868*4882a593Smuzhiyun static int rtl2830_remove(struct i2c_client *client)
869*4882a593Smuzhiyun {
870*4882a593Smuzhiyun struct rtl2830_dev *dev = i2c_get_clientdata(client);
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun i2c_mux_del_adapters(dev->muxc);
875*4882a593Smuzhiyun regmap_exit(dev->regmap);
876*4882a593Smuzhiyun kfree(dev);
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun return 0;
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun static const struct i2c_device_id rtl2830_id_table[] = {
882*4882a593Smuzhiyun {"rtl2830", 0},
883*4882a593Smuzhiyun {}
884*4882a593Smuzhiyun };
885*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, rtl2830_id_table);
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun static struct i2c_driver rtl2830_driver = {
888*4882a593Smuzhiyun .driver = {
889*4882a593Smuzhiyun .name = "rtl2830",
890*4882a593Smuzhiyun .suppress_bind_attrs = true,
891*4882a593Smuzhiyun },
892*4882a593Smuzhiyun .probe = rtl2830_probe,
893*4882a593Smuzhiyun .remove = rtl2830_remove,
894*4882a593Smuzhiyun .id_table = rtl2830_id_table,
895*4882a593Smuzhiyun };
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun module_i2c_driver(rtl2830_driver);
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
900*4882a593Smuzhiyun MODULE_DESCRIPTION("Realtek RTL2830 DVB-T demodulator driver");
901*4882a593Smuzhiyun MODULE_LICENSE("GPL");
902