xref: /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/nxt6000_priv.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Public Include File for DRV6000 users
4*4882a593Smuzhiyun  * (ie. NxtWave Communications - NXT6000 demodulator driver)
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2001 NxtWave Communications, Inc.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /*  Nxt6000 Register Addresses and Bit Masks */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun /* Maximum Register Number */
13*4882a593Smuzhiyun #define MAXNXT6000REG          (0x9A)
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /* 0x1B A_VIT_BER_0  aka 0x3A */
16*4882a593Smuzhiyun #define A_VIT_BER_0            (0x1B)
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* 0x1D A_VIT_BER_TIMER_0 aka 0x38 */
19*4882a593Smuzhiyun #define A_VIT_BER_TIMER_0      (0x1D)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* 0x21 RS_COR_STAT */
22*4882a593Smuzhiyun #define RS_COR_STAT            (0x21)
23*4882a593Smuzhiyun #define RSCORESTATUS           (0x03)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /* 0x22 RS_COR_INTEN */
26*4882a593Smuzhiyun #define RS_COR_INTEN           (0x22)
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /* 0x23 RS_COR_INSTAT */
29*4882a593Smuzhiyun #define RS_COR_INSTAT          (0x23)
30*4882a593Smuzhiyun #define INSTAT_ERROR           (0x04)
31*4882a593Smuzhiyun #define LOCK_LOSS_BITS         (0x03)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* 0x24 RS_COR_SYNC_PARAM */
34*4882a593Smuzhiyun #define RS_COR_SYNC_PARAM      (0x24)
35*4882a593Smuzhiyun #define SYNC_PARAM             (0x03)
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* 0x25 BER_CTRL */
38*4882a593Smuzhiyun #define BER_CTRL               (0x25)
39*4882a593Smuzhiyun #define BER_ENABLE             (0x02)
40*4882a593Smuzhiyun #define BER_RESET              (0x01)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* 0x26 BER_PAY */
43*4882a593Smuzhiyun #define BER_PAY                (0x26)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* 0x27 BER_PKT_L */
46*4882a593Smuzhiyun #define BER_PKT_L              (0x27)
47*4882a593Smuzhiyun #define BER_PKTOVERFLOW        (0x80)
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun /* 0x30 VIT_COR_CTL */
50*4882a593Smuzhiyun #define VIT_COR_CTL            (0x30)
51*4882a593Smuzhiyun #define BER_CONTROL            (0x02)
52*4882a593Smuzhiyun #define VIT_COR_MASK           (0x82)
53*4882a593Smuzhiyun #define VIT_COR_RESYNC         (0x80)
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* 0x32 VIT_SYNC_STATUS */
57*4882a593Smuzhiyun #define VIT_SYNC_STATUS        (0x32)
58*4882a593Smuzhiyun #define VITINSYNC              (0x80)
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /* 0x33 VIT_COR_INTEN */
61*4882a593Smuzhiyun #define VIT_COR_INTEN          (0x33)
62*4882a593Smuzhiyun #define GLOBAL_ENABLE          (0x80)
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun /* 0x34 VIT_COR_INTSTAT */
65*4882a593Smuzhiyun #define VIT_COR_INTSTAT        (0x34)
66*4882a593Smuzhiyun #define BER_DONE               (0x08)
67*4882a593Smuzhiyun #define BER_OVERFLOW           (0x10)
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /* 0x38 VIT_BERTIME_2 */
70*4882a593Smuzhiyun #define VIT_BERTIME_2      (0x38)
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* 0x39 VIT_BERTIME_1 */
73*4882a593Smuzhiyun #define VIT_BERTIME_1      (0x39)
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* 0x3A VIT_BERTIME_0 */
76*4882a593Smuzhiyun #define VIT_BERTIME_0      (0x3a)
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 			     /* 0x38 OFDM_BERTimer *//* Use the alias registers */
79*4882a593Smuzhiyun #define A_VIT_BER_TIMER_0      (0x1D)
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 			     /* 0x3A VIT_BER_TIMER_0 *//* Use the alias registers */
82*4882a593Smuzhiyun #define A_VIT_BER_0            (0x1B)
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /* 0x3B VIT_BER_1 */
85*4882a593Smuzhiyun #define VIT_BER_1              (0x3b)
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /* 0x3C VIT_BER_0 */
88*4882a593Smuzhiyun #define VIT_BER_0              (0x3c)
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /* 0x40 OFDM_COR_CTL */
91*4882a593Smuzhiyun #define OFDM_COR_CTL           (0x40)
92*4882a593Smuzhiyun #define COREACT                (0x20)
93*4882a593Smuzhiyun #define HOLDSM                 (0x10)
94*4882a593Smuzhiyun #define WAIT_AGC               (0x02)
95*4882a593Smuzhiyun #define WAIT_SYR               (0x03)
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /* 0x41 OFDM_COR_STAT */
98*4882a593Smuzhiyun #define OFDM_COR_STAT          (0x41)
99*4882a593Smuzhiyun #define COR_STATUS             (0x0F)
100*4882a593Smuzhiyun #define MONITOR_TPS            (0x06)
101*4882a593Smuzhiyun #define TPSLOCKED              (0x40)
102*4882a593Smuzhiyun #define AGCLOCKED              (0x10)
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun /* 0x42 OFDM_COR_INTEN */
105*4882a593Smuzhiyun #define OFDM_COR_INTEN         (0x42)
106*4882a593Smuzhiyun #define TPSRCVBAD              (0x04)
107*4882a593Smuzhiyun #define TPSRCVCHANGED         (0x02)
108*4882a593Smuzhiyun #define TPSRCVUPDATE           (0x01)
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun /* 0x43 OFDM_COR_INSTAT */
111*4882a593Smuzhiyun #define OFDM_COR_INSTAT        (0x43)
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /* 0x44 OFDM_COR_MODEGUARD */
114*4882a593Smuzhiyun #define OFDM_COR_MODEGUARD     (0x44)
115*4882a593Smuzhiyun #define FORCEMODE              (0x08)
116*4882a593Smuzhiyun #define FORCEMODE8K			   (0x04)
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun /* 0x45 OFDM_AGC_CTL */
119*4882a593Smuzhiyun #define OFDM_AGC_CTL           (0x45)
120*4882a593Smuzhiyun #define INITIAL_AGC_BW		   (0x08)
121*4882a593Smuzhiyun #define AGCNEG                 (0x02)
122*4882a593Smuzhiyun #define AGCLAST				   (0x10)
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun /* 0x48 OFDM_AGC_TARGET */
125*4882a593Smuzhiyun #define OFDM_AGC_TARGET		   (0x48)
126*4882a593Smuzhiyun #define OFDM_AGC_TARGET_DEFAULT (0x28)
127*4882a593Smuzhiyun #define OFDM_AGC_TARGET_IMPULSE (0x38)
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /* 0x49 OFDM_AGC_GAIN_1 */
130*4882a593Smuzhiyun #define OFDM_AGC_GAIN_1        (0x49)
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun /* 0x4B OFDM_ITB_CTL */
133*4882a593Smuzhiyun #define OFDM_ITB_CTL           (0x4B)
134*4882a593Smuzhiyun #define ITBINV                 (0x01)
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun /* 0x49 AGC_GAIN_1 */
137*4882a593Smuzhiyun #define AGC_GAIN_1             (0x49)
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun /* 0x4A AGC_GAIN_2 */
140*4882a593Smuzhiyun #define AGC_GAIN_2             (0x4A)
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /* 0x4C OFDM_ITB_FREQ_1 */
143*4882a593Smuzhiyun #define OFDM_ITB_FREQ_1        (0x4C)
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /* 0x4D OFDM_ITB_FREQ_2 */
146*4882a593Smuzhiyun #define OFDM_ITB_FREQ_2        (0x4D)
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun /* 0x4E  OFDM_CAS_CTL */
149*4882a593Smuzhiyun #define OFDM_CAS_CTL           (0x4E)
150*4882a593Smuzhiyun #define ACSDIS                 (0x40)
151*4882a593Smuzhiyun #define CCSEN                  (0x80)
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun /* 0x4F CAS_FREQ */
154*4882a593Smuzhiyun #define CAS_FREQ               (0x4F)
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun /* 0x51 OFDM_SYR_CTL */
157*4882a593Smuzhiyun #define OFDM_SYR_CTL           (0x51)
158*4882a593Smuzhiyun #define SIXTH_ENABLE           (0x80)
159*4882a593Smuzhiyun #define SYR_TRACKING_DISABLE   (0x01)
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun /* 0x52 OFDM_SYR_STAT */
162*4882a593Smuzhiyun #define OFDM_SYR_STAT		   (0x52)
163*4882a593Smuzhiyun #define GI14_2K_SYR_LOCK	   (0x13)
164*4882a593Smuzhiyun #define GI14_8K_SYR_LOCK	   (0x17)
165*4882a593Smuzhiyun #define GI14_SYR_LOCK		   (0x10)
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun /* 0x55 OFDM_SYR_OFFSET_1 */
168*4882a593Smuzhiyun #define OFDM_SYR_OFFSET_1      (0x55)
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /* 0x56 OFDM_SYR_OFFSET_2 */
171*4882a593Smuzhiyun #define OFDM_SYR_OFFSET_2      (0x56)
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /* 0x58 OFDM_SCR_CTL */
174*4882a593Smuzhiyun #define OFDM_SCR_CTL           (0x58)
175*4882a593Smuzhiyun #define SYR_ADJ_DECAY_MASK     (0x70)
176*4882a593Smuzhiyun #define SYR_ADJ_DECAY          (0x30)
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun /* 0x59 OFDM_PPM_CTL_1 */
179*4882a593Smuzhiyun #define OFDM_PPM_CTL_1         (0x59)
180*4882a593Smuzhiyun #define PPMMAX_MASK            (0x30)
181*4882a593Smuzhiyun #define PPM256				   (0x30)
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun /* 0x5B OFDM_TRL_NOMINALRATE_1 */
184*4882a593Smuzhiyun #define OFDM_TRL_NOMINALRATE_1 (0x5B)
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun /* 0x5C OFDM_TRL_NOMINALRATE_2 */
187*4882a593Smuzhiyun #define OFDM_TRL_NOMINALRATE_2 (0x5C)
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /* 0x5D OFDM_TRL_TIME_1 */
190*4882a593Smuzhiyun #define OFDM_TRL_TIME_1        (0x5D)
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun /* 0x60 OFDM_CRL_FREQ_1 */
193*4882a593Smuzhiyun #define OFDM_CRL_FREQ_1        (0x60)
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun /* 0x63 OFDM_CHC_CTL_1 */
196*4882a593Smuzhiyun #define OFDM_CHC_CTL_1         (0x63)
197*4882a593Smuzhiyun #define MANMEAN1               (0xF0);
198*4882a593Smuzhiyun #define CHCFIR                 (0x01)
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun /* 0x64 OFDM_CHC_SNR */
201*4882a593Smuzhiyun #define OFDM_CHC_SNR           (0x64)
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun /* 0x65 OFDM_BDI_CTL */
204*4882a593Smuzhiyun #define OFDM_BDI_CTL           (0x65)
205*4882a593Smuzhiyun #define LP_SELECT              (0x02)
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun /* 0x67 OFDM_TPS_RCVD_1 */
208*4882a593Smuzhiyun #define OFDM_TPS_RCVD_1        (0x67)
209*4882a593Smuzhiyun #define TPSFRAME               (0x03)
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /* 0x68 OFDM_TPS_RCVD_2 */
212*4882a593Smuzhiyun #define OFDM_TPS_RCVD_2        (0x68)
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun /* 0x69 OFDM_TPS_RCVD_3 */
215*4882a593Smuzhiyun #define OFDM_TPS_RCVD_3        (0x69)
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun /* 0x6A OFDM_TPS_RCVD_4 */
218*4882a593Smuzhiyun #define OFDM_TPS_RCVD_4        (0x6A)
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun /* 0x6B OFDM_TPS_RESERVED_1 */
221*4882a593Smuzhiyun #define OFDM_TPS_RESERVED_1    (0x6B)
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun /* 0x6C OFDM_TPS_RESERVED_2 */
224*4882a593Smuzhiyun #define OFDM_TPS_RESERVED_2    (0x6C)
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun /* 0x73 OFDM_MSC_REV */
227*4882a593Smuzhiyun #define OFDM_MSC_REV           (0x73)
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun /* 0x76 OFDM_SNR_CARRIER_2 */
230*4882a593Smuzhiyun #define OFDM_SNR_CARRIER_2     (0x76)
231*4882a593Smuzhiyun #define MEAN_MASK              (0x80)
232*4882a593Smuzhiyun #define MEANBIT                (0x80)
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun /* 0x80 ANALOG_CONTROL_0 */
235*4882a593Smuzhiyun #define ANALOG_CONTROL_0       (0x80)
236*4882a593Smuzhiyun #define POWER_DOWN_ADC         (0x40)
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun /* 0x81 ENABLE_TUNER_IIC */
239*4882a593Smuzhiyun #define ENABLE_TUNER_IIC       (0x81)
240*4882a593Smuzhiyun #define ENABLE_TUNER_BIT       (0x01)
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun /* 0x82 EN_DMD_RACQ */
243*4882a593Smuzhiyun #define EN_DMD_RACQ            (0x82)
244*4882a593Smuzhiyun #define EN_DMD_RACQ_REG_VAL    (0x81)
245*4882a593Smuzhiyun #define EN_DMD_RACQ_REG_VAL_14 (0x01)
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun /* 0x84 SNR_COMMAND */
248*4882a593Smuzhiyun #define SNR_COMMAND            (0x84)
249*4882a593Smuzhiyun #define SNRStat                (0x80)
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun /* 0x85 SNRCARRIERNUMBER_LSB */
252*4882a593Smuzhiyun #define SNRCARRIERNUMBER_LSB   (0x85)
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun /* 0x87 SNRMINTHRESHOLD_LSB */
255*4882a593Smuzhiyun #define SNRMINTHRESHOLD_LSB    (0x87)
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun /* 0x89 SNR_PER_CARRIER_LSB */
258*4882a593Smuzhiyun #define SNR_PER_CARRIER_LSB    (0x89)
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun /* 0x8B SNRBELOWTHRESHOLD_LSB */
261*4882a593Smuzhiyun #define SNRBELOWTHRESHOLD_LSB  (0x8B)
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun /* 0x91 RF_AGC_VAL_1 */
264*4882a593Smuzhiyun #define RF_AGC_VAL_1           (0x91)
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun /* 0x92 RF_AGC_STATUS */
267*4882a593Smuzhiyun #define RF_AGC_STATUS          (0x92)
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun /* 0x98 DIAG_CONFIG */
270*4882a593Smuzhiyun #define DIAG_CONFIG            (0x98)
271*4882a593Smuzhiyun #define DIAG_MASK              (0x70)
272*4882a593Smuzhiyun #define TB_SET                 (0x10)
273*4882a593Smuzhiyun #define TRAN_SELECT            (0x07)
274*4882a593Smuzhiyun #define SERIAL_SELECT          (0x01)
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun /* 0x99 SUB_DIAG_MODE_SEL */
277*4882a593Smuzhiyun #define SUB_DIAG_MODE_SEL      (0x99)
278*4882a593Smuzhiyun #define CLKINVERSION           (0x01)
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun /* 0x9A TS_FORMAT */
281*4882a593Smuzhiyun #define TS_FORMAT              (0x9A)
282*4882a593Smuzhiyun #define ERROR_SENSE            (0x08)
283*4882a593Smuzhiyun #define VALID_SENSE            (0x04)
284*4882a593Smuzhiyun #define SYNC_SENSE             (0x02)
285*4882a593Smuzhiyun #define GATED_CLOCK            (0x01)
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun #define NXT6000ASICDEVICE      (0x0b)
288