xref: /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/nxt6000.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun 	NxtWave Communications - NXT6000 demodulator driver
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun     Copyright (C) 2002-2003 Florian Schirmer <jolt@tuxbox.org>
6*4882a593Smuzhiyun     Copyright (C) 2003 Paul Andreassen <paul@andreassen.com.au>
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/string.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <media/dvb_frontend.h>
19*4882a593Smuzhiyun #include "nxt6000_priv.h"
20*4882a593Smuzhiyun #include "nxt6000.h"
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun struct nxt6000_state {
25*4882a593Smuzhiyun 	struct i2c_adapter* i2c;
26*4882a593Smuzhiyun 	/* configuration settings */
27*4882a593Smuzhiyun 	const struct nxt6000_config* config;
28*4882a593Smuzhiyun 	struct dvb_frontend frontend;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun static int debug;
32*4882a593Smuzhiyun #define dprintk(fmt, arg...) do {					\
33*4882a593Smuzhiyun 	if (debug)							\
34*4882a593Smuzhiyun 		printk(KERN_DEBUG pr_fmt("%s: " fmt),			\
35*4882a593Smuzhiyun 		       __func__, ##arg);				\
36*4882a593Smuzhiyun } while (0)
37*4882a593Smuzhiyun 
nxt6000_writereg(struct nxt6000_state * state,u8 reg,u8 data)38*4882a593Smuzhiyun static int nxt6000_writereg(struct nxt6000_state* state, u8 reg, u8 data)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	u8 buf[] = { reg, data };
41*4882a593Smuzhiyun 	struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
42*4882a593Smuzhiyun 	int ret;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
45*4882a593Smuzhiyun 		dprintk("nxt6000: nxt6000_write error (reg: 0x%02X, data: 0x%02X, ret: %d)\n", reg, data, ret);
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	return (ret != 1) ? -EIO : 0;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun 
nxt6000_readreg(struct nxt6000_state * state,u8 reg)50*4882a593Smuzhiyun static u8 nxt6000_readreg(struct nxt6000_state* state, u8 reg)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	int ret;
53*4882a593Smuzhiyun 	u8 b0[] = { reg };
54*4882a593Smuzhiyun 	u8 b1[] = { 0 };
55*4882a593Smuzhiyun 	struct i2c_msg msgs[] = {
56*4882a593Smuzhiyun 		{.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
57*4882a593Smuzhiyun 		{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
58*4882a593Smuzhiyun 	};
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	ret = i2c_transfer(state->i2c, msgs, 2);
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	if (ret != 2)
63*4882a593Smuzhiyun 		dprintk("nxt6000: nxt6000_read error (reg: 0x%02X, ret: %d)\n", reg, ret);
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	return b1[0];
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun 
nxt6000_reset(struct nxt6000_state * state)68*4882a593Smuzhiyun static void nxt6000_reset(struct nxt6000_state* state)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun 	u8 val;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	val = nxt6000_readreg(state, OFDM_COR_CTL);
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_COR_CTL, val & ~COREACT);
75*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_COR_CTL, val | COREACT);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun 
nxt6000_set_bandwidth(struct nxt6000_state * state,u32 bandwidth)78*4882a593Smuzhiyun static int nxt6000_set_bandwidth(struct nxt6000_state *state, u32 bandwidth)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun 	u16 nominal_rate;
81*4882a593Smuzhiyun 	int result;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	switch (bandwidth) {
84*4882a593Smuzhiyun 	case 6000000:
85*4882a593Smuzhiyun 		nominal_rate = 0x55B7;
86*4882a593Smuzhiyun 		break;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	case 7000000:
89*4882a593Smuzhiyun 		nominal_rate = 0x6400;
90*4882a593Smuzhiyun 		break;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	case 8000000:
93*4882a593Smuzhiyun 		nominal_rate = 0x7249;
94*4882a593Smuzhiyun 		break;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	default:
97*4882a593Smuzhiyun 		return -EINVAL;
98*4882a593Smuzhiyun 	}
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	if ((result = nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_1, nominal_rate & 0xFF)) < 0)
101*4882a593Smuzhiyun 		return result;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	return nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_2, (nominal_rate >> 8) & 0xFF);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
nxt6000_set_guard_interval(struct nxt6000_state * state,enum fe_guard_interval guard_interval)106*4882a593Smuzhiyun static int nxt6000_set_guard_interval(struct nxt6000_state *state,
107*4882a593Smuzhiyun 				      enum fe_guard_interval guard_interval)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	switch (guard_interval) {
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	case GUARD_INTERVAL_1_32:
112*4882a593Smuzhiyun 		return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x00 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	case GUARD_INTERVAL_1_16:
115*4882a593Smuzhiyun 		return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x01 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	case GUARD_INTERVAL_AUTO:
118*4882a593Smuzhiyun 	case GUARD_INTERVAL_1_8:
119*4882a593Smuzhiyun 		return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x02 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	case GUARD_INTERVAL_1_4:
122*4882a593Smuzhiyun 		return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x03 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	default:
125*4882a593Smuzhiyun 		return -EINVAL;
126*4882a593Smuzhiyun 	}
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
nxt6000_set_inversion(struct nxt6000_state * state,enum fe_spectral_inversion inversion)129*4882a593Smuzhiyun static int nxt6000_set_inversion(struct nxt6000_state *state,
130*4882a593Smuzhiyun 				 enum fe_spectral_inversion inversion)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun 	switch (inversion) {
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	case INVERSION_OFF:
135*4882a593Smuzhiyun 		return nxt6000_writereg(state, OFDM_ITB_CTL, 0x00);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	case INVERSION_ON:
138*4882a593Smuzhiyun 		return nxt6000_writereg(state, OFDM_ITB_CTL, ITBINV);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	default:
141*4882a593Smuzhiyun 		return -EINVAL;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	}
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun static int
nxt6000_set_transmission_mode(struct nxt6000_state * state,enum fe_transmit_mode transmission_mode)147*4882a593Smuzhiyun nxt6000_set_transmission_mode(struct nxt6000_state *state,
148*4882a593Smuzhiyun 			      enum fe_transmit_mode transmission_mode)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun 	int result;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	switch (transmission_mode) {
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	case TRANSMISSION_MODE_2K:
155*4882a593Smuzhiyun 		if ((result = nxt6000_writereg(state, EN_DMD_RACQ, 0x00 | (nxt6000_readreg(state, EN_DMD_RACQ) & ~0x03))) < 0)
156*4882a593Smuzhiyun 			return result;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 		return nxt6000_writereg(state, OFDM_COR_MODEGUARD, (0x00 << 2) | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x04));
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	case TRANSMISSION_MODE_8K:
161*4882a593Smuzhiyun 	case TRANSMISSION_MODE_AUTO:
162*4882a593Smuzhiyun 		if ((result = nxt6000_writereg(state, EN_DMD_RACQ, 0x02 | (nxt6000_readreg(state, EN_DMD_RACQ) & ~0x03))) < 0)
163*4882a593Smuzhiyun 			return result;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 		return nxt6000_writereg(state, OFDM_COR_MODEGUARD, (0x01 << 2) | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x04));
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	default:
168*4882a593Smuzhiyun 		return -EINVAL;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	}
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
nxt6000_setup(struct dvb_frontend * fe)173*4882a593Smuzhiyun static void nxt6000_setup(struct dvb_frontend* fe)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	struct nxt6000_state* state = fe->demodulator_priv;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	nxt6000_writereg(state, RS_COR_SYNC_PARAM, SYNC_PARAM);
178*4882a593Smuzhiyun 	nxt6000_writereg(state, BER_CTRL, /*(1 << 2) | */ (0x01 << 1) | 0x01);
179*4882a593Smuzhiyun 	nxt6000_writereg(state, VIT_BERTIME_2, 0x00);  // BER Timer = 0x000200 * 256 = 131072 bits
180*4882a593Smuzhiyun 	nxt6000_writereg(state, VIT_BERTIME_1, 0x02);  //
181*4882a593Smuzhiyun 	nxt6000_writereg(state, VIT_BERTIME_0, 0x00);  //
182*4882a593Smuzhiyun 	nxt6000_writereg(state, VIT_COR_INTEN, 0x98); // Enable BER interrupts
183*4882a593Smuzhiyun 	nxt6000_writereg(state, VIT_COR_CTL, 0x82);   // Enable BER measurement
184*4882a593Smuzhiyun 	nxt6000_writereg(state, VIT_COR_CTL, VIT_COR_RESYNC | 0x02 );
185*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_COR_CTL, (0x01 << 5) | (nxt6000_readreg(state, OFDM_COR_CTL) & 0x0F));
186*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_COR_MODEGUARD, FORCEMODE8K | 0x02);
187*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_AGC_CTL, AGCLAST | INITIAL_AGC_BW);
188*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_ITB_FREQ_1, 0x06);
189*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_ITB_FREQ_2, 0x31);
190*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_CAS_CTL, (0x01 << 7) | (0x02 << 3) | 0x04);
191*4882a593Smuzhiyun 	nxt6000_writereg(state, CAS_FREQ, 0xBB);	/* CHECKME */
192*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_SYR_CTL, 1 << 2);
193*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_PPM_CTL_1, PPM256);
194*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_1, 0x49);
195*4882a593Smuzhiyun 	nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_2, 0x72);
196*4882a593Smuzhiyun 	nxt6000_writereg(state, ANALOG_CONTROL_0, 1 << 5);
197*4882a593Smuzhiyun 	nxt6000_writereg(state, EN_DMD_RACQ, (1 << 7) | (3 << 4) | 2);
198*4882a593Smuzhiyun 	nxt6000_writereg(state, DIAG_CONFIG, TB_SET);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	if (state->config->clock_inversion)
201*4882a593Smuzhiyun 		nxt6000_writereg(state, SUB_DIAG_MODE_SEL, CLKINVERSION);
202*4882a593Smuzhiyun 	else
203*4882a593Smuzhiyun 		nxt6000_writereg(state, SUB_DIAG_MODE_SEL, 0);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	nxt6000_writereg(state, TS_FORMAT, 0);
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
nxt6000_dump_status(struct nxt6000_state * state)208*4882a593Smuzhiyun static void nxt6000_dump_status(struct nxt6000_state *state)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	u8 val;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun #if 0
213*4882a593Smuzhiyun 	pr_info("RS_COR_STAT: 0x%02X\n",
214*4882a593Smuzhiyun 		nxt6000_readreg(fe, RS_COR_STAT));
215*4882a593Smuzhiyun 	pr_info("VIT_SYNC_STATUS: 0x%02X\n",
216*4882a593Smuzhiyun 		nxt6000_readreg(fe, VIT_SYNC_STATUS));
217*4882a593Smuzhiyun 	pr_info("OFDM_COR_STAT: 0x%02X\n",
218*4882a593Smuzhiyun 		nxt6000_readreg(fe, OFDM_COR_STAT));
219*4882a593Smuzhiyun 	pr_info("OFDM_SYR_STAT: 0x%02X\n",
220*4882a593Smuzhiyun 		nxt6000_readreg(fe, OFDM_SYR_STAT));
221*4882a593Smuzhiyun 	pr_info("OFDM_TPS_RCVD_1: 0x%02X\n",
222*4882a593Smuzhiyun 		nxt6000_readreg(fe, OFDM_TPS_RCVD_1));
223*4882a593Smuzhiyun 	pr_info("OFDM_TPS_RCVD_2: 0x%02X\n",
224*4882a593Smuzhiyun 		nxt6000_readreg(fe, OFDM_TPS_RCVD_2));
225*4882a593Smuzhiyun 	pr_info("OFDM_TPS_RCVD_3: 0x%02X\n",
226*4882a593Smuzhiyun 		nxt6000_readreg(fe, OFDM_TPS_RCVD_3));
227*4882a593Smuzhiyun 	pr_info("OFDM_TPS_RCVD_4: 0x%02X\n",
228*4882a593Smuzhiyun 		nxt6000_readreg(fe, OFDM_TPS_RCVD_4));
229*4882a593Smuzhiyun 	pr_info("OFDM_TPS_RESERVED_1: 0x%02X\n",
230*4882a593Smuzhiyun 		nxt6000_readreg(fe, OFDM_TPS_RESERVED_1));
231*4882a593Smuzhiyun 	pr_info("OFDM_TPS_RESERVED_2: 0x%02X\n",
232*4882a593Smuzhiyun 		nxt6000_readreg(fe, OFDM_TPS_RESERVED_2));
233*4882a593Smuzhiyun #endif
234*4882a593Smuzhiyun 	pr_info("NXT6000 status:");
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	val = nxt6000_readreg(state, RS_COR_STAT);
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	pr_cont(" DATA DESCR LOCK: %d,", val & 0x01);
239*4882a593Smuzhiyun 	pr_cont(" DATA SYNC LOCK: %d,", (val >> 1) & 0x01);
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	val = nxt6000_readreg(state, VIT_SYNC_STATUS);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	pr_cont(" VITERBI LOCK: %d,", (val >> 7) & 0x01);
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	switch ((val >> 4) & 0x07) {
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	case 0x00:
248*4882a593Smuzhiyun 		pr_cont(" VITERBI CODERATE: 1/2,");
249*4882a593Smuzhiyun 		break;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	case 0x01:
252*4882a593Smuzhiyun 		pr_cont(" VITERBI CODERATE: 2/3,");
253*4882a593Smuzhiyun 		break;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	case 0x02:
256*4882a593Smuzhiyun 		pr_cont(" VITERBI CODERATE: 3/4,");
257*4882a593Smuzhiyun 		break;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	case 0x03:
260*4882a593Smuzhiyun 		pr_cont(" VITERBI CODERATE: 5/6,");
261*4882a593Smuzhiyun 		break;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	case 0x04:
264*4882a593Smuzhiyun 		pr_cont(" VITERBI CODERATE: 7/8,");
265*4882a593Smuzhiyun 		break;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	default:
268*4882a593Smuzhiyun 		pr_cont(" VITERBI CODERATE: Reserved,");
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	}
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	val = nxt6000_readreg(state, OFDM_COR_STAT);
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	pr_cont(" CHCTrack: %d,", (val >> 7) & 0x01);
275*4882a593Smuzhiyun 	pr_cont(" TPSLock: %d,", (val >> 6) & 0x01);
276*4882a593Smuzhiyun 	pr_cont(" SYRLock: %d,", (val >> 5) & 0x01);
277*4882a593Smuzhiyun 	pr_cont(" AGCLock: %d,", (val >> 4) & 0x01);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	switch (val & 0x0F) {
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	case 0x00:
282*4882a593Smuzhiyun 		pr_cont(" CoreState: IDLE,");
283*4882a593Smuzhiyun 		break;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	case 0x02:
286*4882a593Smuzhiyun 		pr_cont(" CoreState: WAIT_AGC,");
287*4882a593Smuzhiyun 		break;
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	case 0x03:
290*4882a593Smuzhiyun 		pr_cont(" CoreState: WAIT_SYR,");
291*4882a593Smuzhiyun 		break;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	case 0x04:
294*4882a593Smuzhiyun 		pr_cont(" CoreState: WAIT_PPM,");
295*4882a593Smuzhiyun 		break;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	case 0x01:
298*4882a593Smuzhiyun 		pr_cont(" CoreState: WAIT_TRL,");
299*4882a593Smuzhiyun 		break;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	case 0x05:
302*4882a593Smuzhiyun 		pr_cont(" CoreState: WAIT_TPS,");
303*4882a593Smuzhiyun 		break;
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	case 0x06:
306*4882a593Smuzhiyun 		pr_cont(" CoreState: MONITOR_TPS,");
307*4882a593Smuzhiyun 		break;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	default:
310*4882a593Smuzhiyun 		pr_cont(" CoreState: Reserved,");
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	}
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	val = nxt6000_readreg(state, OFDM_SYR_STAT);
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	pr_cont(" SYRLock: %d,", (val >> 4) & 0x01);
317*4882a593Smuzhiyun 	pr_cont(" SYRMode: %s,", (val >> 2) & 0x01 ? "8K" : "2K");
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	switch ((val >> 4) & 0x03) {
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	case 0x00:
322*4882a593Smuzhiyun 		pr_cont(" SYRGuard: 1/32,");
323*4882a593Smuzhiyun 		break;
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	case 0x01:
326*4882a593Smuzhiyun 		pr_cont(" SYRGuard: 1/16,");
327*4882a593Smuzhiyun 		break;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	case 0x02:
330*4882a593Smuzhiyun 		pr_cont(" SYRGuard: 1/8,");
331*4882a593Smuzhiyun 		break;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	case 0x03:
334*4882a593Smuzhiyun 		pr_cont(" SYRGuard: 1/4,");
335*4882a593Smuzhiyun 		break;
336*4882a593Smuzhiyun 	}
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	val = nxt6000_readreg(state, OFDM_TPS_RCVD_3);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	switch ((val >> 4) & 0x07) {
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	case 0x00:
343*4882a593Smuzhiyun 		pr_cont(" TPSLP: 1/2,");
344*4882a593Smuzhiyun 		break;
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	case 0x01:
347*4882a593Smuzhiyun 		pr_cont(" TPSLP: 2/3,");
348*4882a593Smuzhiyun 		break;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	case 0x02:
351*4882a593Smuzhiyun 		pr_cont(" TPSLP: 3/4,");
352*4882a593Smuzhiyun 		break;
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	case 0x03:
355*4882a593Smuzhiyun 		pr_cont(" TPSLP: 5/6,");
356*4882a593Smuzhiyun 		break;
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	case 0x04:
359*4882a593Smuzhiyun 		pr_cont(" TPSLP: 7/8,");
360*4882a593Smuzhiyun 		break;
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	default:
363*4882a593Smuzhiyun 		pr_cont(" TPSLP: Reserved,");
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	}
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	switch (val & 0x07) {
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	case 0x00:
370*4882a593Smuzhiyun 		pr_cont(" TPSHP: 1/2,");
371*4882a593Smuzhiyun 		break;
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	case 0x01:
374*4882a593Smuzhiyun 		pr_cont(" TPSHP: 2/3,");
375*4882a593Smuzhiyun 		break;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	case 0x02:
378*4882a593Smuzhiyun 		pr_cont(" TPSHP: 3/4,");
379*4882a593Smuzhiyun 		break;
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	case 0x03:
382*4882a593Smuzhiyun 		pr_cont(" TPSHP: 5/6,");
383*4882a593Smuzhiyun 		break;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	case 0x04:
386*4882a593Smuzhiyun 		pr_cont(" TPSHP: 7/8,");
387*4882a593Smuzhiyun 		break;
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	default:
390*4882a593Smuzhiyun 		pr_cont(" TPSHP: Reserved,");
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	}
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	val = nxt6000_readreg(state, OFDM_TPS_RCVD_4);
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	pr_cont(" TPSMode: %s,", val & 0x01 ? "8K" : "2K");
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	switch ((val >> 4) & 0x03) {
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	case 0x00:
401*4882a593Smuzhiyun 		pr_cont(" TPSGuard: 1/32,");
402*4882a593Smuzhiyun 		break;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	case 0x01:
405*4882a593Smuzhiyun 		pr_cont(" TPSGuard: 1/16,");
406*4882a593Smuzhiyun 		break;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	case 0x02:
409*4882a593Smuzhiyun 		pr_cont(" TPSGuard: 1/8,");
410*4882a593Smuzhiyun 		break;
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	case 0x03:
413*4882a593Smuzhiyun 		pr_cont(" TPSGuard: 1/4,");
414*4882a593Smuzhiyun 		break;
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	}
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 	/* Strange magic required to gain access to RF_AGC_STATUS */
419*4882a593Smuzhiyun 	nxt6000_readreg(state, RF_AGC_VAL_1);
420*4882a593Smuzhiyun 	val = nxt6000_readreg(state, RF_AGC_STATUS);
421*4882a593Smuzhiyun 	val = nxt6000_readreg(state, RF_AGC_STATUS);
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	pr_cont(" RF AGC LOCK: %d,", (val >> 4) & 0x01);
424*4882a593Smuzhiyun 	pr_cont("\n");
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun 
nxt6000_read_status(struct dvb_frontend * fe,enum fe_status * status)427*4882a593Smuzhiyun static int nxt6000_read_status(struct dvb_frontend *fe, enum fe_status *status)
428*4882a593Smuzhiyun {
429*4882a593Smuzhiyun 	u8 core_status;
430*4882a593Smuzhiyun 	struct nxt6000_state* state = fe->demodulator_priv;
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	*status = 0;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	core_status = nxt6000_readreg(state, OFDM_COR_STAT);
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	if (core_status & AGCLOCKED)
437*4882a593Smuzhiyun 		*status |= FE_HAS_SIGNAL;
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	if (nxt6000_readreg(state, OFDM_SYR_STAT) & GI14_SYR_LOCK)
440*4882a593Smuzhiyun 		*status |= FE_HAS_CARRIER;
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	if (nxt6000_readreg(state, VIT_SYNC_STATUS) & VITINSYNC)
443*4882a593Smuzhiyun 		*status |= FE_HAS_VITERBI;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	if (nxt6000_readreg(state, RS_COR_STAT) & RSCORESTATUS)
446*4882a593Smuzhiyun 		*status |= FE_HAS_SYNC;
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	if ((core_status & TPSLOCKED) && (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)))
449*4882a593Smuzhiyun 		*status |= FE_HAS_LOCK;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	if (debug)
452*4882a593Smuzhiyun 		nxt6000_dump_status(state);
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	return 0;
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun 
nxt6000_init(struct dvb_frontend * fe)457*4882a593Smuzhiyun static int nxt6000_init(struct dvb_frontend* fe)
458*4882a593Smuzhiyun {
459*4882a593Smuzhiyun 	struct nxt6000_state* state = fe->demodulator_priv;
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	nxt6000_reset(state);
462*4882a593Smuzhiyun 	nxt6000_setup(fe);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	return 0;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun 
nxt6000_set_frontend(struct dvb_frontend * fe)467*4882a593Smuzhiyun static int nxt6000_set_frontend(struct dvb_frontend *fe)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
470*4882a593Smuzhiyun 	struct nxt6000_state* state = fe->demodulator_priv;
471*4882a593Smuzhiyun 	int result;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	if (fe->ops.tuner_ops.set_params) {
474*4882a593Smuzhiyun 		fe->ops.tuner_ops.set_params(fe);
475*4882a593Smuzhiyun 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
476*4882a593Smuzhiyun 	}
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	result = nxt6000_set_bandwidth(state, p->bandwidth_hz);
479*4882a593Smuzhiyun 	if (result < 0)
480*4882a593Smuzhiyun 		return result;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	result = nxt6000_set_guard_interval(state, p->guard_interval);
483*4882a593Smuzhiyun 	if (result < 0)
484*4882a593Smuzhiyun 		return result;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	result = nxt6000_set_transmission_mode(state, p->transmission_mode);
487*4882a593Smuzhiyun 	if (result < 0)
488*4882a593Smuzhiyun 		return result;
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	result = nxt6000_set_inversion(state, p->inversion);
491*4882a593Smuzhiyun 	if (result < 0)
492*4882a593Smuzhiyun 		return result;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	msleep(500);
495*4882a593Smuzhiyun 	return 0;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun 
nxt6000_release(struct dvb_frontend * fe)498*4882a593Smuzhiyun static void nxt6000_release(struct dvb_frontend* fe)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun 	struct nxt6000_state* state = fe->demodulator_priv;
501*4882a593Smuzhiyun 	kfree(state);
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun 
nxt6000_read_snr(struct dvb_frontend * fe,u16 * snr)504*4882a593Smuzhiyun static int nxt6000_read_snr(struct dvb_frontend* fe, u16* snr)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun 	struct nxt6000_state* state = fe->demodulator_priv;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	*snr = nxt6000_readreg( state, OFDM_CHC_SNR) / 8;
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 	return 0;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun 
nxt6000_read_ber(struct dvb_frontend * fe,u32 * ber)513*4882a593Smuzhiyun static int nxt6000_read_ber(struct dvb_frontend* fe, u32* ber)
514*4882a593Smuzhiyun {
515*4882a593Smuzhiyun 	struct nxt6000_state* state = fe->demodulator_priv;
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun 	nxt6000_writereg( state, VIT_COR_INTSTAT, 0x18 );
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	*ber = (nxt6000_readreg( state, VIT_BER_1 ) << 8 ) |
520*4882a593Smuzhiyun 		nxt6000_readreg( state, VIT_BER_0 );
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	nxt6000_writereg( state, VIT_COR_INTSTAT, 0x18); // Clear BER Done interrupts
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	return 0;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun 
nxt6000_read_signal_strength(struct dvb_frontend * fe,u16 * signal_strength)527*4882a593Smuzhiyun static int nxt6000_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun 	struct nxt6000_state* state = fe->demodulator_priv;
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 	*signal_strength = (short) (511 -
532*4882a593Smuzhiyun 		(nxt6000_readreg(state, AGC_GAIN_1) +
533*4882a593Smuzhiyun 		((nxt6000_readreg(state, AGC_GAIN_2) & 0x03) << 8)));
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	return 0;
536*4882a593Smuzhiyun }
537*4882a593Smuzhiyun 
nxt6000_fe_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * tune)538*4882a593Smuzhiyun static int nxt6000_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
539*4882a593Smuzhiyun {
540*4882a593Smuzhiyun 	tune->min_delay_ms = 500;
541*4882a593Smuzhiyun 	return 0;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun 
nxt6000_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)544*4882a593Smuzhiyun static int nxt6000_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun 	struct nxt6000_state* state = fe->demodulator_priv;
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	if (enable) {
549*4882a593Smuzhiyun 		return nxt6000_writereg(state, ENABLE_TUNER_IIC, 0x01);
550*4882a593Smuzhiyun 	} else {
551*4882a593Smuzhiyun 		return nxt6000_writereg(state, ENABLE_TUNER_IIC, 0x00);
552*4882a593Smuzhiyun 	}
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun static const struct dvb_frontend_ops nxt6000_ops;
556*4882a593Smuzhiyun 
nxt6000_attach(const struct nxt6000_config * config,struct i2c_adapter * i2c)557*4882a593Smuzhiyun struct dvb_frontend* nxt6000_attach(const struct nxt6000_config* config,
558*4882a593Smuzhiyun 				    struct i2c_adapter* i2c)
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun 	struct nxt6000_state* state = NULL;
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 	/* allocate memory for the internal state */
563*4882a593Smuzhiyun 	state = kzalloc(sizeof(struct nxt6000_state), GFP_KERNEL);
564*4882a593Smuzhiyun 	if (state == NULL) goto error;
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	/* setup the state */
567*4882a593Smuzhiyun 	state->config = config;
568*4882a593Smuzhiyun 	state->i2c = i2c;
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	/* check if the demod is there */
571*4882a593Smuzhiyun 	if (nxt6000_readreg(state, OFDM_MSC_REV) != NXT6000ASICDEVICE) goto error;
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	/* create dvb_frontend */
574*4882a593Smuzhiyun 	memcpy(&state->frontend.ops, &nxt6000_ops, sizeof(struct dvb_frontend_ops));
575*4882a593Smuzhiyun 	state->frontend.demodulator_priv = state;
576*4882a593Smuzhiyun 	return &state->frontend;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun error:
579*4882a593Smuzhiyun 	kfree(state);
580*4882a593Smuzhiyun 	return NULL;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun static const struct dvb_frontend_ops nxt6000_ops = {
584*4882a593Smuzhiyun 	.delsys = { SYS_DVBT },
585*4882a593Smuzhiyun 	.info = {
586*4882a593Smuzhiyun 		.name = "NxtWave NXT6000 DVB-T",
587*4882a593Smuzhiyun 		.frequency_min_hz = 0,
588*4882a593Smuzhiyun 		.frequency_max_hz = 863250 * kHz,
589*4882a593Smuzhiyun 		.frequency_stepsize_hz = 62500,
590*4882a593Smuzhiyun 		/*.frequency_tolerance = *//* FIXME: 12% of SR */
591*4882a593Smuzhiyun 		.symbol_rate_min = 0,	/* FIXME */
592*4882a593Smuzhiyun 		.symbol_rate_max = 9360000,	/* FIXME */
593*4882a593Smuzhiyun 		.symbol_rate_tolerance = 4000,
594*4882a593Smuzhiyun 		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
595*4882a593Smuzhiyun 			FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
596*4882a593Smuzhiyun 			FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
597*4882a593Smuzhiyun 			FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
598*4882a593Smuzhiyun 			FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
599*4882a593Smuzhiyun 			FE_CAN_HIERARCHY_AUTO,
600*4882a593Smuzhiyun 	},
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	.release = nxt6000_release,
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 	.init = nxt6000_init,
605*4882a593Smuzhiyun 	.i2c_gate_ctrl = nxt6000_i2c_gate_ctrl,
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	.get_tune_settings = nxt6000_fe_get_tune_settings,
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	.set_frontend = nxt6000_set_frontend,
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	.read_status = nxt6000_read_status,
612*4882a593Smuzhiyun 	.read_ber = nxt6000_read_ber,
613*4882a593Smuzhiyun 	.read_signal_strength = nxt6000_read_signal_strength,
614*4882a593Smuzhiyun 	.read_snr = nxt6000_read_snr,
615*4882a593Smuzhiyun };
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun module_param(debug, int, 0644);
618*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun MODULE_DESCRIPTION("NxtWave NXT6000 DVB-T demodulator driver");
621*4882a593Smuzhiyun MODULE_AUTHOR("Florian Schirmer");
622*4882a593Smuzhiyun MODULE_LICENSE("GPL");
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun EXPORT_SYMBOL(nxt6000_attach);
625