xref: /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/mt352_priv.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Driver for Zarlink DVB-T MT352 demodulator
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Written by Holger Waechtler <holger@qanu.de>
6*4882a593Smuzhiyun  *	 and Daniel Mack <daniel@qanu.de>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  *  AVerMedia AVerTV DVB-T 771 support by
9*4882a593Smuzhiyun  *       Wolfram Joost <dbox2@frokaschwei.de>
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  *  Support for Samsung TDTC9251DH01C(M) tuner
12*4882a593Smuzhiyun  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
13*4882a593Smuzhiyun  *                     Amauri  Celani  <acelani@essegi.net>
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
16*4882a593Smuzhiyun  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #ifndef _MT352_PRIV_
20*4882a593Smuzhiyun #define _MT352_PRIV_
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define ID_MT352        0x13
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define msb(x) (((x) >> 8) & 0xff)
25*4882a593Smuzhiyun #define lsb(x) ((x) & 0xff)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun enum mt352_reg_addr {
28*4882a593Smuzhiyun 	STATUS_0           = 0x00,
29*4882a593Smuzhiyun 	STATUS_1           = 0x01,
30*4882a593Smuzhiyun 	STATUS_2           = 0x02,
31*4882a593Smuzhiyun 	STATUS_3           = 0x03,
32*4882a593Smuzhiyun 	STATUS_4           = 0x04,
33*4882a593Smuzhiyun 	INTERRUPT_0        = 0x05,
34*4882a593Smuzhiyun 	INTERRUPT_1        = 0x06,
35*4882a593Smuzhiyun 	INTERRUPT_2        = 0x07,
36*4882a593Smuzhiyun 	INTERRUPT_3        = 0x08,
37*4882a593Smuzhiyun 	SNR                = 0x09,
38*4882a593Smuzhiyun 	VIT_ERR_CNT_2      = 0x0A,
39*4882a593Smuzhiyun 	VIT_ERR_CNT_1      = 0x0B,
40*4882a593Smuzhiyun 	VIT_ERR_CNT_0      = 0x0C,
41*4882a593Smuzhiyun 	RS_ERR_CNT_2       = 0x0D,
42*4882a593Smuzhiyun 	RS_ERR_CNT_1       = 0x0E,
43*4882a593Smuzhiyun 	RS_ERR_CNT_0       = 0x0F,
44*4882a593Smuzhiyun 	RS_UBC_1           = 0x10,
45*4882a593Smuzhiyun 	RS_UBC_0           = 0x11,
46*4882a593Smuzhiyun 	AGC_GAIN_3         = 0x12,
47*4882a593Smuzhiyun 	AGC_GAIN_2         = 0x13,
48*4882a593Smuzhiyun 	AGC_GAIN_1         = 0x14,
49*4882a593Smuzhiyun 	AGC_GAIN_0         = 0x15,
50*4882a593Smuzhiyun 	FREQ_OFFSET_2      = 0x17,
51*4882a593Smuzhiyun 	FREQ_OFFSET_1      = 0x18,
52*4882a593Smuzhiyun 	FREQ_OFFSET_0      = 0x19,
53*4882a593Smuzhiyun 	TIMING_OFFSET_1    = 0x1A,
54*4882a593Smuzhiyun 	TIMING_OFFSET_0    = 0x1B,
55*4882a593Smuzhiyun 	CHAN_FREQ_1        = 0x1C,
56*4882a593Smuzhiyun 	CHAN_FREQ_0        = 0x1D,
57*4882a593Smuzhiyun 	TPS_RECEIVED_1     = 0x1E,
58*4882a593Smuzhiyun 	TPS_RECEIVED_0     = 0x1F,
59*4882a593Smuzhiyun 	TPS_CURRENT_1      = 0x20,
60*4882a593Smuzhiyun 	TPS_CURRENT_0      = 0x21,
61*4882a593Smuzhiyun 	TPS_CELL_ID_1      = 0x22,
62*4882a593Smuzhiyun 	TPS_CELL_ID_0      = 0x23,
63*4882a593Smuzhiyun 	TPS_MISC_DATA_2    = 0x24,
64*4882a593Smuzhiyun 	TPS_MISC_DATA_1    = 0x25,
65*4882a593Smuzhiyun 	TPS_MISC_DATA_0    = 0x26,
66*4882a593Smuzhiyun 	RESET              = 0x50,
67*4882a593Smuzhiyun 	TPS_GIVEN_1        = 0x51,
68*4882a593Smuzhiyun 	TPS_GIVEN_0        = 0x52,
69*4882a593Smuzhiyun 	ACQ_CTL            = 0x53,
70*4882a593Smuzhiyun 	TRL_NOMINAL_RATE_1 = 0x54,
71*4882a593Smuzhiyun 	TRL_NOMINAL_RATE_0 = 0x55,
72*4882a593Smuzhiyun 	INPUT_FREQ_1       = 0x56,
73*4882a593Smuzhiyun 	INPUT_FREQ_0       = 0x57,
74*4882a593Smuzhiyun 	TUNER_ADDR         = 0x58,
75*4882a593Smuzhiyun 	CHAN_START_1       = 0x59,
76*4882a593Smuzhiyun 	CHAN_START_0       = 0x5A,
77*4882a593Smuzhiyun 	CONT_1             = 0x5B,
78*4882a593Smuzhiyun 	CONT_0             = 0x5C,
79*4882a593Smuzhiyun 	TUNER_GO           = 0x5D,
80*4882a593Smuzhiyun 	STATUS_EN_0        = 0x5F,
81*4882a593Smuzhiyun 	STATUS_EN_1        = 0x60,
82*4882a593Smuzhiyun 	INTERRUPT_EN_0     = 0x61,
83*4882a593Smuzhiyun 	INTERRUPT_EN_1     = 0x62,
84*4882a593Smuzhiyun 	INTERRUPT_EN_2     = 0x63,
85*4882a593Smuzhiyun 	INTERRUPT_EN_3     = 0x64,
86*4882a593Smuzhiyun 	AGC_TARGET         = 0x67,
87*4882a593Smuzhiyun 	AGC_CTL            = 0x68,
88*4882a593Smuzhiyun 	CAPT_RANGE         = 0x75,
89*4882a593Smuzhiyun 	SNR_SELECT_1       = 0x79,
90*4882a593Smuzhiyun 	SNR_SELECT_0       = 0x7A,
91*4882a593Smuzhiyun 	RS_ERR_PER_1       = 0x7C,
92*4882a593Smuzhiyun 	RS_ERR_PER_0       = 0x7D,
93*4882a593Smuzhiyun 	CHIP_ID            = 0x7F,
94*4882a593Smuzhiyun 	CHAN_STOP_1        = 0x80,
95*4882a593Smuzhiyun 	CHAN_STOP_0        = 0x81,
96*4882a593Smuzhiyun 	CHAN_STEP_1        = 0x82,
97*4882a593Smuzhiyun 	CHAN_STEP_0        = 0x83,
98*4882a593Smuzhiyun 	FEC_LOCK_TIME      = 0x85,
99*4882a593Smuzhiyun 	OFDM_LOCK_TIME     = 0x86,
100*4882a593Smuzhiyun 	ACQ_DELAY          = 0x87,
101*4882a593Smuzhiyun 	SCAN_CTL           = 0x88,
102*4882a593Smuzhiyun 	CLOCK_CTL          = 0x89,
103*4882a593Smuzhiyun 	CONFIG             = 0x8A,
104*4882a593Smuzhiyun 	MCLK_RATIO         = 0x8B,
105*4882a593Smuzhiyun 	GPP_CTL            = 0x8C,
106*4882a593Smuzhiyun 	ADC_CTL_1          = 0x8E,
107*4882a593Smuzhiyun 	ADC_CTL_0          = 0x8F
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun /* here we assume 1/6MHz == 166.66kHz stepsize */
111*4882a593Smuzhiyun #define IF_FREQUENCYx6 217    /* 6 * 36.16666666667MHz */
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun #endif                          /* _MT352_PRIV_ */
114