1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Panasonic MN88473 DVB-T/T2/C demodulator driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Antti Palosaari <crope@iki.fi>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include "mn88473_priv.h"
9*4882a593Smuzhiyun
mn88473_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * s)10*4882a593Smuzhiyun static int mn88473_get_tune_settings(struct dvb_frontend *fe,
11*4882a593Smuzhiyun struct dvb_frontend_tune_settings *s)
12*4882a593Smuzhiyun {
13*4882a593Smuzhiyun s->min_delay_ms = 1000;
14*4882a593Smuzhiyun return 0;
15*4882a593Smuzhiyun }
16*4882a593Smuzhiyun
mn88473_set_frontend(struct dvb_frontend * fe)17*4882a593Smuzhiyun static int mn88473_set_frontend(struct dvb_frontend *fe)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
20*4882a593Smuzhiyun struct mn88473_dev *dev = i2c_get_clientdata(client);
21*4882a593Smuzhiyun struct dtv_frontend_properties *c = &fe->dtv_property_cache;
22*4882a593Smuzhiyun int ret, i;
23*4882a593Smuzhiyun unsigned int uitmp;
24*4882a593Smuzhiyun u32 if_frequency;
25*4882a593Smuzhiyun u8 delivery_system_val, if_val[3], *conf_val_ptr;
26*4882a593Smuzhiyun u8 reg_bank2_2d_val, reg_bank0_d2_val;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun dev_dbg(&client->dev,
29*4882a593Smuzhiyun "delivery_system=%u modulation=%u frequency=%u bandwidth_hz=%u symbol_rate=%u inversion=%d stream_id=%d\n",
30*4882a593Smuzhiyun c->delivery_system, c->modulation, c->frequency,
31*4882a593Smuzhiyun c->bandwidth_hz, c->symbol_rate, c->inversion, c->stream_id);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun if (!dev->active) {
34*4882a593Smuzhiyun ret = -EAGAIN;
35*4882a593Smuzhiyun goto err;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun switch (c->delivery_system) {
39*4882a593Smuzhiyun case SYS_DVBT:
40*4882a593Smuzhiyun delivery_system_val = 0x02;
41*4882a593Smuzhiyun reg_bank2_2d_val = 0x23;
42*4882a593Smuzhiyun reg_bank0_d2_val = 0x2a;
43*4882a593Smuzhiyun break;
44*4882a593Smuzhiyun case SYS_DVBT2:
45*4882a593Smuzhiyun delivery_system_val = 0x03;
46*4882a593Smuzhiyun reg_bank2_2d_val = 0x3b;
47*4882a593Smuzhiyun reg_bank0_d2_val = 0x29;
48*4882a593Smuzhiyun break;
49*4882a593Smuzhiyun case SYS_DVBC_ANNEX_A:
50*4882a593Smuzhiyun delivery_system_val = 0x04;
51*4882a593Smuzhiyun reg_bank2_2d_val = 0x3b;
52*4882a593Smuzhiyun reg_bank0_d2_val = 0x29;
53*4882a593Smuzhiyun break;
54*4882a593Smuzhiyun default:
55*4882a593Smuzhiyun ret = -EINVAL;
56*4882a593Smuzhiyun goto err;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun switch (c->delivery_system) {
60*4882a593Smuzhiyun case SYS_DVBT:
61*4882a593Smuzhiyun case SYS_DVBT2:
62*4882a593Smuzhiyun switch (c->bandwidth_hz) {
63*4882a593Smuzhiyun case 6000000:
64*4882a593Smuzhiyun conf_val_ptr = "\xe9\x55\x55\x1c\x29\x1c\x29";
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun case 7000000:
67*4882a593Smuzhiyun conf_val_ptr = "\xc8\x00\x00\x17\x0a\x17\x0a";
68*4882a593Smuzhiyun break;
69*4882a593Smuzhiyun case 8000000:
70*4882a593Smuzhiyun conf_val_ptr = "\xaf\x00\x00\x11\xec\x11\xec";
71*4882a593Smuzhiyun break;
72*4882a593Smuzhiyun default:
73*4882a593Smuzhiyun ret = -EINVAL;
74*4882a593Smuzhiyun goto err;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun break;
77*4882a593Smuzhiyun case SYS_DVBC_ANNEX_A:
78*4882a593Smuzhiyun conf_val_ptr = "\x10\xab\x0d\xae\x1d\x9d";
79*4882a593Smuzhiyun break;
80*4882a593Smuzhiyun default:
81*4882a593Smuzhiyun break;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Program tuner */
85*4882a593Smuzhiyun if (fe->ops.tuner_ops.set_params) {
86*4882a593Smuzhiyun ret = fe->ops.tuner_ops.set_params(fe);
87*4882a593Smuzhiyun if (ret)
88*4882a593Smuzhiyun goto err;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (fe->ops.tuner_ops.get_if_frequency) {
92*4882a593Smuzhiyun ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
93*4882a593Smuzhiyun if (ret)
94*4882a593Smuzhiyun goto err;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun dev_dbg(&client->dev, "get_if_frequency=%u\n", if_frequency);
97*4882a593Smuzhiyun } else {
98*4882a593Smuzhiyun ret = -EINVAL;
99*4882a593Smuzhiyun goto err;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Calculate IF registers */
103*4882a593Smuzhiyun uitmp = DIV_ROUND_CLOSEST_ULL((u64) if_frequency * 0x1000000, dev->clk);
104*4882a593Smuzhiyun if_val[0] = (uitmp >> 16) & 0xff;
105*4882a593Smuzhiyun if_val[1] = (uitmp >> 8) & 0xff;
106*4882a593Smuzhiyun if_val[2] = (uitmp >> 0) & 0xff;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x05, 0x00);
109*4882a593Smuzhiyun if (ret)
110*4882a593Smuzhiyun goto err;
111*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0xfb, 0x13);
112*4882a593Smuzhiyun if (ret)
113*4882a593Smuzhiyun goto err;
114*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0xef, 0x13);
115*4882a593Smuzhiyun if (ret)
116*4882a593Smuzhiyun goto err;
117*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0xf9, 0x13);
118*4882a593Smuzhiyun if (ret)
119*4882a593Smuzhiyun goto err;
120*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x00, 0x18);
121*4882a593Smuzhiyun if (ret)
122*4882a593Smuzhiyun goto err;
123*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x01, 0x01);
124*4882a593Smuzhiyun if (ret)
125*4882a593Smuzhiyun goto err;
126*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x02, 0x21);
127*4882a593Smuzhiyun if (ret)
128*4882a593Smuzhiyun goto err;
129*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x03, delivery_system_val);
130*4882a593Smuzhiyun if (ret)
131*4882a593Smuzhiyun goto err;
132*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x0b, 0x00);
133*4882a593Smuzhiyun if (ret)
134*4882a593Smuzhiyun goto err;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun for (i = 0; i < sizeof(if_val); i++) {
137*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x10 + i, if_val[i]);
138*4882a593Smuzhiyun if (ret)
139*4882a593Smuzhiyun goto err;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun switch (c->delivery_system) {
143*4882a593Smuzhiyun case SYS_DVBT:
144*4882a593Smuzhiyun case SYS_DVBT2:
145*4882a593Smuzhiyun for (i = 0; i < 7; i++) {
146*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x13 + i,
147*4882a593Smuzhiyun conf_val_ptr[i]);
148*4882a593Smuzhiyun if (ret)
149*4882a593Smuzhiyun goto err;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun break;
152*4882a593Smuzhiyun case SYS_DVBC_ANNEX_A:
153*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap[1], 0x10, conf_val_ptr, 6);
154*4882a593Smuzhiyun if (ret)
155*4882a593Smuzhiyun goto err;
156*4882a593Smuzhiyun break;
157*4882a593Smuzhiyun default:
158*4882a593Smuzhiyun break;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x2d, reg_bank2_2d_val);
162*4882a593Smuzhiyun if (ret)
163*4882a593Smuzhiyun goto err;
164*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x2e, 0x00);
165*4882a593Smuzhiyun if (ret)
166*4882a593Smuzhiyun goto err;
167*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x56, 0x0d);
168*4882a593Smuzhiyun if (ret)
169*4882a593Smuzhiyun goto err;
170*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap[0], 0x01,
171*4882a593Smuzhiyun "\xba\x13\x80\xba\x91\xdd\xe7\x28", 8);
172*4882a593Smuzhiyun if (ret)
173*4882a593Smuzhiyun goto err;
174*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0x0a, 0x1a);
175*4882a593Smuzhiyun if (ret)
176*4882a593Smuzhiyun goto err;
177*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0x13, 0x1f);
178*4882a593Smuzhiyun if (ret)
179*4882a593Smuzhiyun goto err;
180*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0x19, 0x03);
181*4882a593Smuzhiyun if (ret)
182*4882a593Smuzhiyun goto err;
183*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0x1d, 0xb0);
184*4882a593Smuzhiyun if (ret)
185*4882a593Smuzhiyun goto err;
186*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0x2a, 0x72);
187*4882a593Smuzhiyun if (ret)
188*4882a593Smuzhiyun goto err;
189*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0x2d, 0x00);
190*4882a593Smuzhiyun if (ret)
191*4882a593Smuzhiyun goto err;
192*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0x3c, 0x00);
193*4882a593Smuzhiyun if (ret)
194*4882a593Smuzhiyun goto err;
195*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0x3f, 0xf8);
196*4882a593Smuzhiyun if (ret)
197*4882a593Smuzhiyun goto err;
198*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap[0], 0x40, "\xf4\x08", 2);
199*4882a593Smuzhiyun if (ret)
200*4882a593Smuzhiyun goto err;
201*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0xd2, reg_bank0_d2_val);
202*4882a593Smuzhiyun if (ret)
203*4882a593Smuzhiyun goto err;
204*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0xd4, 0x55);
205*4882a593Smuzhiyun if (ret)
206*4882a593Smuzhiyun goto err;
207*4882a593Smuzhiyun ret = regmap_write(dev->regmap[1], 0xbe, 0x08);
208*4882a593Smuzhiyun if (ret)
209*4882a593Smuzhiyun goto err;
210*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0xb2, 0x37);
211*4882a593Smuzhiyun if (ret)
212*4882a593Smuzhiyun goto err;
213*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0xd7, 0x04);
214*4882a593Smuzhiyun if (ret)
215*4882a593Smuzhiyun goto err;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* PLP */
218*4882a593Smuzhiyun if (c->delivery_system == SYS_DVBT2) {
219*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x36,
220*4882a593Smuzhiyun (c->stream_id == NO_STREAM_ID_FILTER) ? 0 :
221*4882a593Smuzhiyun c->stream_id );
222*4882a593Smuzhiyun if (ret)
223*4882a593Smuzhiyun goto err;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* Reset FSM */
227*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0xf8, 0x9f);
228*4882a593Smuzhiyun if (ret)
229*4882a593Smuzhiyun goto err;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun return 0;
232*4882a593Smuzhiyun err:
233*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
234*4882a593Smuzhiyun return ret;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
mn88473_read_status(struct dvb_frontend * fe,enum fe_status * status)237*4882a593Smuzhiyun static int mn88473_read_status(struct dvb_frontend *fe, enum fe_status *status)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
240*4882a593Smuzhiyun struct mn88473_dev *dev = i2c_get_clientdata(client);
241*4882a593Smuzhiyun struct dtv_frontend_properties *c = &fe->dtv_property_cache;
242*4882a593Smuzhiyun int ret, i, stmp;
243*4882a593Smuzhiyun unsigned int utmp, utmp1, utmp2;
244*4882a593Smuzhiyun u8 buf[5];
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (!dev->active) {
247*4882a593Smuzhiyun ret = -EAGAIN;
248*4882a593Smuzhiyun goto err;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /* Lock detection */
252*4882a593Smuzhiyun switch (c->delivery_system) {
253*4882a593Smuzhiyun case SYS_DVBT:
254*4882a593Smuzhiyun ret = regmap_read(dev->regmap[0], 0x62, &utmp);
255*4882a593Smuzhiyun if (ret)
256*4882a593Smuzhiyun goto err;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun if (!(utmp & 0xa0)) {
259*4882a593Smuzhiyun if ((utmp & 0x0f) >= 0x09)
260*4882a593Smuzhiyun *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
261*4882a593Smuzhiyun FE_HAS_VITERBI | FE_HAS_SYNC |
262*4882a593Smuzhiyun FE_HAS_LOCK;
263*4882a593Smuzhiyun else if ((utmp & 0x0f) >= 0x03)
264*4882a593Smuzhiyun *status = FE_HAS_SIGNAL | FE_HAS_CARRIER;
265*4882a593Smuzhiyun } else {
266*4882a593Smuzhiyun *status = 0;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun break;
269*4882a593Smuzhiyun case SYS_DVBT2:
270*4882a593Smuzhiyun ret = regmap_read(dev->regmap[2], 0x8b, &utmp);
271*4882a593Smuzhiyun if (ret)
272*4882a593Smuzhiyun goto err;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (!(utmp & 0x40)) {
275*4882a593Smuzhiyun if ((utmp & 0x0f) >= 0x0d)
276*4882a593Smuzhiyun *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
277*4882a593Smuzhiyun FE_HAS_VITERBI | FE_HAS_SYNC |
278*4882a593Smuzhiyun FE_HAS_LOCK;
279*4882a593Smuzhiyun else if ((utmp & 0x0f) >= 0x0a)
280*4882a593Smuzhiyun *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
281*4882a593Smuzhiyun FE_HAS_VITERBI;
282*4882a593Smuzhiyun else if ((utmp & 0x0f) >= 0x07)
283*4882a593Smuzhiyun *status = FE_HAS_SIGNAL | FE_HAS_CARRIER;
284*4882a593Smuzhiyun } else {
285*4882a593Smuzhiyun *status = 0;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun break;
288*4882a593Smuzhiyun case SYS_DVBC_ANNEX_A:
289*4882a593Smuzhiyun ret = regmap_read(dev->regmap[1], 0x85, &utmp);
290*4882a593Smuzhiyun if (ret)
291*4882a593Smuzhiyun goto err;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun if (!(utmp & 0x40)) {
294*4882a593Smuzhiyun ret = regmap_read(dev->regmap[1], 0x89, &utmp);
295*4882a593Smuzhiyun if (ret)
296*4882a593Smuzhiyun goto err;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun if (utmp & 0x01)
299*4882a593Smuzhiyun *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
300*4882a593Smuzhiyun FE_HAS_VITERBI | FE_HAS_SYNC |
301*4882a593Smuzhiyun FE_HAS_LOCK;
302*4882a593Smuzhiyun } else {
303*4882a593Smuzhiyun *status = 0;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun break;
306*4882a593Smuzhiyun default:
307*4882a593Smuzhiyun ret = -EINVAL;
308*4882a593Smuzhiyun goto err;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /* Signal strength */
312*4882a593Smuzhiyun if (*status & FE_HAS_SIGNAL) {
313*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
314*4882a593Smuzhiyun ret = regmap_bulk_read(dev->regmap[2], 0x86 + i,
315*4882a593Smuzhiyun &buf[i], 1);
316*4882a593Smuzhiyun if (ret)
317*4882a593Smuzhiyun goto err;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun /* AGCRD[15:6] gives us a 10bit value ([5:0] are always 0) */
321*4882a593Smuzhiyun utmp1 = buf[0] << 8 | buf[1] << 0 | buf[0] >> 2;
322*4882a593Smuzhiyun dev_dbg(&client->dev, "strength=%u\n", utmp1);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun c->strength.stat[0].scale = FE_SCALE_RELATIVE;
325*4882a593Smuzhiyun c->strength.stat[0].uvalue = utmp1;
326*4882a593Smuzhiyun } else {
327*4882a593Smuzhiyun c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun /* CNR */
331*4882a593Smuzhiyun if (*status & FE_HAS_VITERBI && c->delivery_system == SYS_DVBT) {
332*4882a593Smuzhiyun /* DVB-T CNR */
333*4882a593Smuzhiyun ret = regmap_bulk_read(dev->regmap[0], 0x8f, buf, 2);
334*4882a593Smuzhiyun if (ret)
335*4882a593Smuzhiyun goto err;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun utmp = buf[0] << 8 | buf[1] << 0;
338*4882a593Smuzhiyun if (utmp) {
339*4882a593Smuzhiyun /* CNR[dB]: 10 * (log10(65536 / value) + 0.2) */
340*4882a593Smuzhiyun /* log10(65536) = 80807124, 0.2 = 3355443 */
341*4882a593Smuzhiyun stmp = div_u64(((u64)80807124 - intlog10(utmp)
342*4882a593Smuzhiyun + 3355443) * 10000, 1 << 24);
343*4882a593Smuzhiyun dev_dbg(&client->dev, "cnr=%d value=%u\n", stmp, utmp);
344*4882a593Smuzhiyun } else {
345*4882a593Smuzhiyun stmp = 0;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun c->cnr.stat[0].svalue = stmp;
349*4882a593Smuzhiyun c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
350*4882a593Smuzhiyun } else if (*status & FE_HAS_VITERBI &&
351*4882a593Smuzhiyun c->delivery_system == SYS_DVBT2) {
352*4882a593Smuzhiyun /* DVB-T2 CNR */
353*4882a593Smuzhiyun for (i = 0; i < 3; i++) {
354*4882a593Smuzhiyun ret = regmap_bulk_read(dev->regmap[2], 0xb7 + i,
355*4882a593Smuzhiyun &buf[i], 1);
356*4882a593Smuzhiyun if (ret)
357*4882a593Smuzhiyun goto err;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun utmp = buf[1] << 8 | buf[2] << 0;
361*4882a593Smuzhiyun utmp1 = (buf[0] >> 2) & 0x01; /* 0=SISO, 1=MISO */
362*4882a593Smuzhiyun if (utmp) {
363*4882a593Smuzhiyun if (utmp1) {
364*4882a593Smuzhiyun /* CNR[dB]: 10 * (log10(16384 / value) - 0.6) */
365*4882a593Smuzhiyun /* log10(16384) = 70706234, 0.6 = 10066330 */
366*4882a593Smuzhiyun stmp = div_u64(((u64)70706234 - intlog10(utmp)
367*4882a593Smuzhiyun - 10066330) * 10000, 1 << 24);
368*4882a593Smuzhiyun dev_dbg(&client->dev, "cnr=%d value=%u MISO\n",
369*4882a593Smuzhiyun stmp, utmp);
370*4882a593Smuzhiyun } else {
371*4882a593Smuzhiyun /* CNR[dB]: 10 * (log10(65536 / value) + 0.2) */
372*4882a593Smuzhiyun /* log10(65536) = 80807124, 0.2 = 3355443 */
373*4882a593Smuzhiyun stmp = div_u64(((u64)80807124 - intlog10(utmp)
374*4882a593Smuzhiyun + 3355443) * 10000, 1 << 24);
375*4882a593Smuzhiyun dev_dbg(&client->dev, "cnr=%d value=%u SISO\n",
376*4882a593Smuzhiyun stmp, utmp);
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun } else {
379*4882a593Smuzhiyun stmp = 0;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun c->cnr.stat[0].svalue = stmp;
383*4882a593Smuzhiyun c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
384*4882a593Smuzhiyun } else if (*status & FE_HAS_VITERBI &&
385*4882a593Smuzhiyun c->delivery_system == SYS_DVBC_ANNEX_A) {
386*4882a593Smuzhiyun /* DVB-C CNR */
387*4882a593Smuzhiyun ret = regmap_bulk_read(dev->regmap[1], 0xa1, buf, 4);
388*4882a593Smuzhiyun if (ret)
389*4882a593Smuzhiyun goto err;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun utmp1 = buf[0] << 8 | buf[1] << 0; /* signal */
392*4882a593Smuzhiyun utmp2 = buf[2] << 8 | buf[3] << 0; /* noise */
393*4882a593Smuzhiyun if (utmp1 && utmp2) {
394*4882a593Smuzhiyun /* CNR[dB]: 10 * log10(8 * (signal / noise)) */
395*4882a593Smuzhiyun /* log10(8) = 15151336 */
396*4882a593Smuzhiyun stmp = div_u64(((u64)15151336 + intlog10(utmp1)
397*4882a593Smuzhiyun - intlog10(utmp2)) * 10000, 1 << 24);
398*4882a593Smuzhiyun dev_dbg(&client->dev, "cnr=%d signal=%u noise=%u\n",
399*4882a593Smuzhiyun stmp, utmp1, utmp2);
400*4882a593Smuzhiyun } else {
401*4882a593Smuzhiyun stmp = 0;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun c->cnr.stat[0].svalue = stmp;
405*4882a593Smuzhiyun c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
406*4882a593Smuzhiyun } else {
407*4882a593Smuzhiyun c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun /* BER */
411*4882a593Smuzhiyun if (*status & FE_HAS_LOCK && (c->delivery_system == SYS_DVBT ||
412*4882a593Smuzhiyun c->delivery_system == SYS_DVBC_ANNEX_A)) {
413*4882a593Smuzhiyun /* DVB-T & DVB-C BER */
414*4882a593Smuzhiyun ret = regmap_bulk_read(dev->regmap[0], 0x92, buf, 5);
415*4882a593Smuzhiyun if (ret)
416*4882a593Smuzhiyun goto err;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun utmp1 = buf[0] << 16 | buf[1] << 8 | buf[2] << 0;
419*4882a593Smuzhiyun utmp2 = buf[3] << 8 | buf[4] << 0;
420*4882a593Smuzhiyun utmp2 = utmp2 * 8 * 204;
421*4882a593Smuzhiyun dev_dbg(&client->dev, "post_bit_error=%u post_bit_count=%u\n",
422*4882a593Smuzhiyun utmp1, utmp2);
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
425*4882a593Smuzhiyun c->post_bit_error.stat[0].uvalue += utmp1;
426*4882a593Smuzhiyun c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
427*4882a593Smuzhiyun c->post_bit_count.stat[0].uvalue += utmp2;
428*4882a593Smuzhiyun } else {
429*4882a593Smuzhiyun c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
430*4882a593Smuzhiyun c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun /* PER */
434*4882a593Smuzhiyun if (*status & FE_HAS_LOCK) {
435*4882a593Smuzhiyun ret = regmap_bulk_read(dev->regmap[0], 0xdd, buf, 4);
436*4882a593Smuzhiyun if (ret)
437*4882a593Smuzhiyun goto err;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun utmp1 = buf[0] << 8 | buf[1] << 0;
440*4882a593Smuzhiyun utmp2 = buf[2] << 8 | buf[3] << 0;
441*4882a593Smuzhiyun dev_dbg(&client->dev, "block_error=%u block_count=%u\n",
442*4882a593Smuzhiyun utmp1, utmp2);
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun c->block_error.stat[0].scale = FE_SCALE_COUNTER;
445*4882a593Smuzhiyun c->block_error.stat[0].uvalue += utmp1;
446*4882a593Smuzhiyun c->block_count.stat[0].scale = FE_SCALE_COUNTER;
447*4882a593Smuzhiyun c->block_count.stat[0].uvalue += utmp2;
448*4882a593Smuzhiyun } else {
449*4882a593Smuzhiyun c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
450*4882a593Smuzhiyun c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun return 0;
454*4882a593Smuzhiyun err:
455*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
456*4882a593Smuzhiyun return ret;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
mn88473_init(struct dvb_frontend * fe)459*4882a593Smuzhiyun static int mn88473_init(struct dvb_frontend *fe)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
462*4882a593Smuzhiyun struct mn88473_dev *dev = i2c_get_clientdata(client);
463*4882a593Smuzhiyun struct dtv_frontend_properties *c = &fe->dtv_property_cache;
464*4882a593Smuzhiyun int ret, len, remain;
465*4882a593Smuzhiyun unsigned int uitmp;
466*4882a593Smuzhiyun const struct firmware *fw;
467*4882a593Smuzhiyun const char *name = MN88473_FIRMWARE;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun /* Check if firmware is already running */
472*4882a593Smuzhiyun ret = regmap_read(dev->regmap[0], 0xf5, &uitmp);
473*4882a593Smuzhiyun if (ret)
474*4882a593Smuzhiyun goto err;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun if (!(uitmp & 0x01))
477*4882a593Smuzhiyun goto warm;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun /* Request the firmware, this will block and timeout */
480*4882a593Smuzhiyun ret = request_firmware(&fw, name, &client->dev);
481*4882a593Smuzhiyun if (ret) {
482*4882a593Smuzhiyun dev_err(&client->dev, "firmware file '%s' not found\n", name);
483*4882a593Smuzhiyun goto err;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0xf5, 0x03);
489*4882a593Smuzhiyun if (ret)
490*4882a593Smuzhiyun goto err_release_firmware;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun for (remain = fw->size; remain > 0; remain -= (dev->i2c_wr_max - 1)) {
493*4882a593Smuzhiyun len = min(dev->i2c_wr_max - 1, remain);
494*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap[0], 0xf6,
495*4882a593Smuzhiyun &fw->data[fw->size - remain], len);
496*4882a593Smuzhiyun if (ret) {
497*4882a593Smuzhiyun dev_err(&client->dev, "firmware download failed %d\n",
498*4882a593Smuzhiyun ret);
499*4882a593Smuzhiyun goto err_release_firmware;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun release_firmware(fw);
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun /* Parity check of firmware */
506*4882a593Smuzhiyun ret = regmap_read(dev->regmap[0], 0xf8, &uitmp);
507*4882a593Smuzhiyun if (ret)
508*4882a593Smuzhiyun goto err;
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun if (uitmp & 0x10) {
511*4882a593Smuzhiyun dev_err(&client->dev, "firmware parity check failed\n");
512*4882a593Smuzhiyun ret = -EINVAL;
513*4882a593Smuzhiyun goto err;
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun ret = regmap_write(dev->regmap[0], 0xf5, 0x00);
517*4882a593Smuzhiyun if (ret)
518*4882a593Smuzhiyun goto err;
519*4882a593Smuzhiyun warm:
520*4882a593Smuzhiyun /* TS config */
521*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x09, 0x08);
522*4882a593Smuzhiyun if (ret)
523*4882a593Smuzhiyun goto err;
524*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x08, 0x1d);
525*4882a593Smuzhiyun if (ret)
526*4882a593Smuzhiyun goto err;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun dev->active = true;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun /* init stats here to indicate which stats are supported */
531*4882a593Smuzhiyun c->strength.len = 1;
532*4882a593Smuzhiyun c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
533*4882a593Smuzhiyun c->cnr.len = 1;
534*4882a593Smuzhiyun c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
535*4882a593Smuzhiyun c->post_bit_error.len = 1;
536*4882a593Smuzhiyun c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
537*4882a593Smuzhiyun c->post_bit_count.len = 1;
538*4882a593Smuzhiyun c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
539*4882a593Smuzhiyun c->block_error.len = 1;
540*4882a593Smuzhiyun c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
541*4882a593Smuzhiyun c->block_count.len = 1;
542*4882a593Smuzhiyun c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun return 0;
545*4882a593Smuzhiyun err_release_firmware:
546*4882a593Smuzhiyun release_firmware(fw);
547*4882a593Smuzhiyun err:
548*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
549*4882a593Smuzhiyun return ret;
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun
mn88473_sleep(struct dvb_frontend * fe)552*4882a593Smuzhiyun static int mn88473_sleep(struct dvb_frontend *fe)
553*4882a593Smuzhiyun {
554*4882a593Smuzhiyun struct i2c_client *client = fe->demodulator_priv;
555*4882a593Smuzhiyun struct mn88473_dev *dev = i2c_get_clientdata(client);
556*4882a593Smuzhiyun int ret;
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun dev->active = false;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
563*4882a593Smuzhiyun if (ret)
564*4882a593Smuzhiyun goto err;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun return 0;
567*4882a593Smuzhiyun err:
568*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
569*4882a593Smuzhiyun return ret;
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun static const struct dvb_frontend_ops mn88473_ops = {
573*4882a593Smuzhiyun .delsys = {SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A},
574*4882a593Smuzhiyun .info = {
575*4882a593Smuzhiyun .name = "Panasonic MN88473",
576*4882a593Smuzhiyun .symbol_rate_min = 1000000,
577*4882a593Smuzhiyun .symbol_rate_max = 7200000,
578*4882a593Smuzhiyun .caps = FE_CAN_FEC_1_2 |
579*4882a593Smuzhiyun FE_CAN_FEC_2_3 |
580*4882a593Smuzhiyun FE_CAN_FEC_3_4 |
581*4882a593Smuzhiyun FE_CAN_FEC_5_6 |
582*4882a593Smuzhiyun FE_CAN_FEC_7_8 |
583*4882a593Smuzhiyun FE_CAN_FEC_AUTO |
584*4882a593Smuzhiyun FE_CAN_QPSK |
585*4882a593Smuzhiyun FE_CAN_QAM_16 |
586*4882a593Smuzhiyun FE_CAN_QAM_32 |
587*4882a593Smuzhiyun FE_CAN_QAM_64 |
588*4882a593Smuzhiyun FE_CAN_QAM_128 |
589*4882a593Smuzhiyun FE_CAN_QAM_256 |
590*4882a593Smuzhiyun FE_CAN_QAM_AUTO |
591*4882a593Smuzhiyun FE_CAN_TRANSMISSION_MODE_AUTO |
592*4882a593Smuzhiyun FE_CAN_GUARD_INTERVAL_AUTO |
593*4882a593Smuzhiyun FE_CAN_HIERARCHY_AUTO |
594*4882a593Smuzhiyun FE_CAN_MUTE_TS |
595*4882a593Smuzhiyun FE_CAN_2G_MODULATION |
596*4882a593Smuzhiyun FE_CAN_MULTISTREAM
597*4882a593Smuzhiyun },
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun .get_tune_settings = mn88473_get_tune_settings,
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun .init = mn88473_init,
602*4882a593Smuzhiyun .sleep = mn88473_sleep,
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun .set_frontend = mn88473_set_frontend,
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun .read_status = mn88473_read_status,
607*4882a593Smuzhiyun };
608*4882a593Smuzhiyun
mn88473_probe(struct i2c_client * client,const struct i2c_device_id * id)609*4882a593Smuzhiyun static int mn88473_probe(struct i2c_client *client,
610*4882a593Smuzhiyun const struct i2c_device_id *id)
611*4882a593Smuzhiyun {
612*4882a593Smuzhiyun struct mn88473_config *config = client->dev.platform_data;
613*4882a593Smuzhiyun struct mn88473_dev *dev;
614*4882a593Smuzhiyun int ret;
615*4882a593Smuzhiyun unsigned int uitmp;
616*4882a593Smuzhiyun static const struct regmap_config regmap_config = {
617*4882a593Smuzhiyun .reg_bits = 8,
618*4882a593Smuzhiyun .val_bits = 8,
619*4882a593Smuzhiyun };
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun /* Caller really need to provide pointer for frontend we create */
624*4882a593Smuzhiyun if (config->fe == NULL) {
625*4882a593Smuzhiyun dev_err(&client->dev, "frontend pointer not defined\n");
626*4882a593Smuzhiyun ret = -EINVAL;
627*4882a593Smuzhiyun goto err;
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun dev = kzalloc(sizeof(*dev), GFP_KERNEL);
631*4882a593Smuzhiyun if (dev == NULL) {
632*4882a593Smuzhiyun ret = -ENOMEM;
633*4882a593Smuzhiyun goto err;
634*4882a593Smuzhiyun }
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun if (config->i2c_wr_max)
637*4882a593Smuzhiyun dev->i2c_wr_max = config->i2c_wr_max;
638*4882a593Smuzhiyun else
639*4882a593Smuzhiyun dev->i2c_wr_max = ~0;
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun if (config->xtal)
642*4882a593Smuzhiyun dev->clk = config->xtal;
643*4882a593Smuzhiyun else
644*4882a593Smuzhiyun dev->clk = 25000000;
645*4882a593Smuzhiyun dev->client[0] = client;
646*4882a593Smuzhiyun dev->regmap[0] = regmap_init_i2c(dev->client[0], ®map_config);
647*4882a593Smuzhiyun if (IS_ERR(dev->regmap[0])) {
648*4882a593Smuzhiyun ret = PTR_ERR(dev->regmap[0]);
649*4882a593Smuzhiyun goto err_kfree;
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun /*
653*4882a593Smuzhiyun * Chip has three I2C addresses for different register banks. Used
654*4882a593Smuzhiyun * addresses are 0x18, 0x1a and 0x1c. We register two dummy clients,
655*4882a593Smuzhiyun * 0x1a and 0x1c, in order to get own I2C client for each register bank.
656*4882a593Smuzhiyun *
657*4882a593Smuzhiyun * Also, register bank 2 do not support sequential I/O. Only single
658*4882a593Smuzhiyun * register write or read is allowed to that bank.
659*4882a593Smuzhiyun */
660*4882a593Smuzhiyun dev->client[1] = i2c_new_dummy_device(client->adapter, 0x1a);
661*4882a593Smuzhiyun if (IS_ERR(dev->client[1])) {
662*4882a593Smuzhiyun ret = PTR_ERR(dev->client[1]);
663*4882a593Smuzhiyun dev_err(&client->dev, "I2C registration failed\n");
664*4882a593Smuzhiyun goto err_regmap_0_regmap_exit;
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun dev->regmap[1] = regmap_init_i2c(dev->client[1], ®map_config);
667*4882a593Smuzhiyun if (IS_ERR(dev->regmap[1])) {
668*4882a593Smuzhiyun ret = PTR_ERR(dev->regmap[1]);
669*4882a593Smuzhiyun goto err_client_1_i2c_unregister_device;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun i2c_set_clientdata(dev->client[1], dev);
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun dev->client[2] = i2c_new_dummy_device(client->adapter, 0x1c);
674*4882a593Smuzhiyun if (IS_ERR(dev->client[2])) {
675*4882a593Smuzhiyun ret = PTR_ERR(dev->client[2]);
676*4882a593Smuzhiyun dev_err(&client->dev, "2nd I2C registration failed\n");
677*4882a593Smuzhiyun goto err_regmap_1_regmap_exit;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun dev->regmap[2] = regmap_init_i2c(dev->client[2], ®map_config);
680*4882a593Smuzhiyun if (IS_ERR(dev->regmap[2])) {
681*4882a593Smuzhiyun ret = PTR_ERR(dev->regmap[2]);
682*4882a593Smuzhiyun goto err_client_2_i2c_unregister_device;
683*4882a593Smuzhiyun }
684*4882a593Smuzhiyun i2c_set_clientdata(dev->client[2], dev);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun /* Check demod answers with correct chip id */
687*4882a593Smuzhiyun ret = regmap_read(dev->regmap[2], 0xff, &uitmp);
688*4882a593Smuzhiyun if (ret)
689*4882a593Smuzhiyun goto err_regmap_2_regmap_exit;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun dev_dbg(&client->dev, "chip id=%02x\n", uitmp);
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun if (uitmp != 0x03) {
694*4882a593Smuzhiyun ret = -ENODEV;
695*4882a593Smuzhiyun goto err_regmap_2_regmap_exit;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun /* Sleep because chip is active by default */
699*4882a593Smuzhiyun ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
700*4882a593Smuzhiyun if (ret)
701*4882a593Smuzhiyun goto err_regmap_2_regmap_exit;
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun /* Create dvb frontend */
704*4882a593Smuzhiyun memcpy(&dev->frontend.ops, &mn88473_ops, sizeof(dev->frontend.ops));
705*4882a593Smuzhiyun dev->frontend.demodulator_priv = client;
706*4882a593Smuzhiyun *config->fe = &dev->frontend;
707*4882a593Smuzhiyun i2c_set_clientdata(client, dev);
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun dev_info(&client->dev, "Panasonic MN88473 successfully identified\n");
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun return 0;
712*4882a593Smuzhiyun err_regmap_2_regmap_exit:
713*4882a593Smuzhiyun regmap_exit(dev->regmap[2]);
714*4882a593Smuzhiyun err_client_2_i2c_unregister_device:
715*4882a593Smuzhiyun i2c_unregister_device(dev->client[2]);
716*4882a593Smuzhiyun err_regmap_1_regmap_exit:
717*4882a593Smuzhiyun regmap_exit(dev->regmap[1]);
718*4882a593Smuzhiyun err_client_1_i2c_unregister_device:
719*4882a593Smuzhiyun i2c_unregister_device(dev->client[1]);
720*4882a593Smuzhiyun err_regmap_0_regmap_exit:
721*4882a593Smuzhiyun regmap_exit(dev->regmap[0]);
722*4882a593Smuzhiyun err_kfree:
723*4882a593Smuzhiyun kfree(dev);
724*4882a593Smuzhiyun err:
725*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
726*4882a593Smuzhiyun return ret;
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun
mn88473_remove(struct i2c_client * client)729*4882a593Smuzhiyun static int mn88473_remove(struct i2c_client *client)
730*4882a593Smuzhiyun {
731*4882a593Smuzhiyun struct mn88473_dev *dev = i2c_get_clientdata(client);
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun regmap_exit(dev->regmap[2]);
736*4882a593Smuzhiyun i2c_unregister_device(dev->client[2]);
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun regmap_exit(dev->regmap[1]);
739*4882a593Smuzhiyun i2c_unregister_device(dev->client[1]);
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun regmap_exit(dev->regmap[0]);
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun kfree(dev);
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun return 0;
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun static const struct i2c_device_id mn88473_id_table[] = {
749*4882a593Smuzhiyun {"mn88473", 0},
750*4882a593Smuzhiyun {}
751*4882a593Smuzhiyun };
752*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mn88473_id_table);
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun static struct i2c_driver mn88473_driver = {
755*4882a593Smuzhiyun .driver = {
756*4882a593Smuzhiyun .name = "mn88473",
757*4882a593Smuzhiyun .suppress_bind_attrs = true,
758*4882a593Smuzhiyun },
759*4882a593Smuzhiyun .probe = mn88473_probe,
760*4882a593Smuzhiyun .remove = mn88473_remove,
761*4882a593Smuzhiyun .id_table = mn88473_id_table,
762*4882a593Smuzhiyun };
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun module_i2c_driver(mn88473_driver);
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
767*4882a593Smuzhiyun MODULE_DESCRIPTION("Panasonic MN88473 DVB-T/T2/C demodulator driver");
768*4882a593Smuzhiyun MODULE_LICENSE("GPL");
769*4882a593Smuzhiyun MODULE_FIRMWARE(MN88473_FIRMWARE);
770