xref: /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/mn88472.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Panasonic MN88472 DVB-T/T2/C demodulator driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include "mn88472_priv.h"
9*4882a593Smuzhiyun 
mn88472_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * s)10*4882a593Smuzhiyun static int mn88472_get_tune_settings(struct dvb_frontend *fe,
11*4882a593Smuzhiyun 				     struct dvb_frontend_tune_settings *s)
12*4882a593Smuzhiyun {
13*4882a593Smuzhiyun 	s->min_delay_ms = 1000;
14*4882a593Smuzhiyun 	return 0;
15*4882a593Smuzhiyun }
16*4882a593Smuzhiyun 
mn88472_read_status(struct dvb_frontend * fe,enum fe_status * status)17*4882a593Smuzhiyun static int mn88472_read_status(struct dvb_frontend *fe, enum fe_status *status)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun 	struct i2c_client *client = fe->demodulator_priv;
20*4882a593Smuzhiyun 	struct mn88472_dev *dev = i2c_get_clientdata(client);
21*4882a593Smuzhiyun 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
22*4882a593Smuzhiyun 	int ret, i, stmp;
23*4882a593Smuzhiyun 	unsigned int utmp, utmp1, utmp2;
24*4882a593Smuzhiyun 	u8 buf[5];
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 	if (!dev->active) {
27*4882a593Smuzhiyun 		ret = -EAGAIN;
28*4882a593Smuzhiyun 		goto err;
29*4882a593Smuzhiyun 	}
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	switch (c->delivery_system) {
32*4882a593Smuzhiyun 	case SYS_DVBT:
33*4882a593Smuzhiyun 		ret = regmap_read(dev->regmap[0], 0x7f, &utmp);
34*4882a593Smuzhiyun 		if (ret)
35*4882a593Smuzhiyun 			goto err;
36*4882a593Smuzhiyun 		if ((utmp & 0x0f) >= 0x09)
37*4882a593Smuzhiyun 			*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
38*4882a593Smuzhiyun 				  FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
39*4882a593Smuzhiyun 		else
40*4882a593Smuzhiyun 			*status = 0;
41*4882a593Smuzhiyun 		break;
42*4882a593Smuzhiyun 	case SYS_DVBT2:
43*4882a593Smuzhiyun 		ret = regmap_read(dev->regmap[2], 0x92, &utmp);
44*4882a593Smuzhiyun 		if (ret)
45*4882a593Smuzhiyun 			goto err;
46*4882a593Smuzhiyun 		if ((utmp & 0x0f) >= 0x0d)
47*4882a593Smuzhiyun 			*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
48*4882a593Smuzhiyun 				  FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
49*4882a593Smuzhiyun 		else if ((utmp & 0x0f) >= 0x0a)
50*4882a593Smuzhiyun 			*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
51*4882a593Smuzhiyun 				  FE_HAS_VITERBI;
52*4882a593Smuzhiyun 		else if ((utmp & 0x0f) >= 0x07)
53*4882a593Smuzhiyun 			*status = FE_HAS_SIGNAL | FE_HAS_CARRIER;
54*4882a593Smuzhiyun 		else
55*4882a593Smuzhiyun 			*status = 0;
56*4882a593Smuzhiyun 		break;
57*4882a593Smuzhiyun 	case SYS_DVBC_ANNEX_A:
58*4882a593Smuzhiyun 		ret = regmap_read(dev->regmap[1], 0x84, &utmp);
59*4882a593Smuzhiyun 		if (ret)
60*4882a593Smuzhiyun 			goto err;
61*4882a593Smuzhiyun 		if ((utmp & 0x0f) >= 0x08)
62*4882a593Smuzhiyun 			*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
63*4882a593Smuzhiyun 				  FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
64*4882a593Smuzhiyun 		else
65*4882a593Smuzhiyun 			*status = 0;
66*4882a593Smuzhiyun 		break;
67*4882a593Smuzhiyun 	default:
68*4882a593Smuzhiyun 		ret = -EINVAL;
69*4882a593Smuzhiyun 		goto err;
70*4882a593Smuzhiyun 	}
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	/* Signal strength */
73*4882a593Smuzhiyun 	if (*status & FE_HAS_SIGNAL) {
74*4882a593Smuzhiyun 		for (i = 0; i < 2; i++) {
75*4882a593Smuzhiyun 			ret = regmap_bulk_read(dev->regmap[2], 0x8e + i,
76*4882a593Smuzhiyun 					       &buf[i], 1);
77*4882a593Smuzhiyun 			if (ret)
78*4882a593Smuzhiyun 				goto err;
79*4882a593Smuzhiyun 		}
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 		utmp1 = buf[0] << 8 | buf[1] << 0 | buf[0] >> 2;
82*4882a593Smuzhiyun 		dev_dbg(&client->dev, "strength=%u\n", utmp1);
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 		c->strength.stat[0].scale = FE_SCALE_RELATIVE;
85*4882a593Smuzhiyun 		c->strength.stat[0].uvalue = utmp1;
86*4882a593Smuzhiyun 	} else {
87*4882a593Smuzhiyun 		c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
88*4882a593Smuzhiyun 	}
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	/* CNR */
91*4882a593Smuzhiyun 	if (*status & FE_HAS_VITERBI && c->delivery_system == SYS_DVBT) {
92*4882a593Smuzhiyun 		/* DVB-T CNR */
93*4882a593Smuzhiyun 		ret = regmap_bulk_read(dev->regmap[0], 0x9c, buf, 2);
94*4882a593Smuzhiyun 		if (ret)
95*4882a593Smuzhiyun 			goto err;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 		utmp = buf[0] << 8 | buf[1] << 0;
98*4882a593Smuzhiyun 		if (utmp) {
99*4882a593Smuzhiyun 			/* CNR[dB]: 10 * log10(65536 / value) + 2 */
100*4882a593Smuzhiyun 			/* log10(65536) = 80807124, 0.2 = 3355443 */
101*4882a593Smuzhiyun 			stmp = ((u64)80807124 - intlog10(utmp) + 3355443)
102*4882a593Smuzhiyun 			       * 10000 >> 24;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 			dev_dbg(&client->dev, "cnr=%d value=%u\n", stmp, utmp);
105*4882a593Smuzhiyun 		} else {
106*4882a593Smuzhiyun 			stmp = 0;
107*4882a593Smuzhiyun 		}
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 		c->cnr.stat[0].svalue = stmp;
110*4882a593Smuzhiyun 		c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
111*4882a593Smuzhiyun 	} else if (*status & FE_HAS_VITERBI &&
112*4882a593Smuzhiyun 		   c->delivery_system == SYS_DVBT2) {
113*4882a593Smuzhiyun 		/* DVB-T2 CNR */
114*4882a593Smuzhiyun 		for (i = 0; i < 3; i++) {
115*4882a593Smuzhiyun 			ret = regmap_bulk_read(dev->regmap[2], 0xbc + i,
116*4882a593Smuzhiyun 					       &buf[i], 1);
117*4882a593Smuzhiyun 			if (ret)
118*4882a593Smuzhiyun 				goto err;
119*4882a593Smuzhiyun 		}
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 		utmp = buf[1] << 8 | buf[2] << 0;
122*4882a593Smuzhiyun 		utmp1 = (buf[0] >> 2) & 0x01; /* 0=SISO, 1=MISO */
123*4882a593Smuzhiyun 		if (utmp) {
124*4882a593Smuzhiyun 			if (utmp1) {
125*4882a593Smuzhiyun 				/* CNR[dB]: 10 * log10(16384 / value) - 6 */
126*4882a593Smuzhiyun 				/* log10(16384) = 70706234, 0.6 = 10066330 */
127*4882a593Smuzhiyun 				stmp = ((u64)70706234 - intlog10(utmp)
128*4882a593Smuzhiyun 				       - 10066330) * 10000 >> 24;
129*4882a593Smuzhiyun 				dev_dbg(&client->dev, "cnr=%d value=%u MISO\n",
130*4882a593Smuzhiyun 					stmp, utmp);
131*4882a593Smuzhiyun 			} else {
132*4882a593Smuzhiyun 				/* CNR[dB]: 10 * log10(65536 / value) + 2 */
133*4882a593Smuzhiyun 				/* log10(65536) = 80807124, 0.2 = 3355443 */
134*4882a593Smuzhiyun 				stmp = ((u64)80807124 - intlog10(utmp)
135*4882a593Smuzhiyun 				       + 3355443) * 10000 >> 24;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 				dev_dbg(&client->dev, "cnr=%d value=%u SISO\n",
138*4882a593Smuzhiyun 					stmp, utmp);
139*4882a593Smuzhiyun 			}
140*4882a593Smuzhiyun 		} else {
141*4882a593Smuzhiyun 			stmp = 0;
142*4882a593Smuzhiyun 		}
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 		c->cnr.stat[0].svalue = stmp;
145*4882a593Smuzhiyun 		c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
146*4882a593Smuzhiyun 	} else if (*status & FE_HAS_VITERBI &&
147*4882a593Smuzhiyun 		   c->delivery_system == SYS_DVBC_ANNEX_A) {
148*4882a593Smuzhiyun 		/* DVB-C CNR */
149*4882a593Smuzhiyun 		ret = regmap_bulk_read(dev->regmap[1], 0xa1, buf, 4);
150*4882a593Smuzhiyun 		if (ret)
151*4882a593Smuzhiyun 			goto err;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 		utmp1 = buf[0] << 8 | buf[1] << 0; /* signal */
154*4882a593Smuzhiyun 		utmp2 = buf[2] << 8 | buf[3] << 0; /* noise */
155*4882a593Smuzhiyun 		if (utmp1 && utmp2) {
156*4882a593Smuzhiyun 			/* CNR[dB]: 10 * log10(8 * (signal / noise)) */
157*4882a593Smuzhiyun 			/* log10(8) = 15151336 */
158*4882a593Smuzhiyun 			stmp = ((u64)15151336 + intlog10(utmp1)
159*4882a593Smuzhiyun 			       - intlog10(utmp2)) * 10000 >> 24;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 			dev_dbg(&client->dev, "cnr=%d signal=%u noise=%u\n",
162*4882a593Smuzhiyun 				stmp, utmp1, utmp2);
163*4882a593Smuzhiyun 		} else {
164*4882a593Smuzhiyun 			stmp = 0;
165*4882a593Smuzhiyun 		}
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 		c->cnr.stat[0].svalue = stmp;
168*4882a593Smuzhiyun 		c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
169*4882a593Smuzhiyun 	} else {
170*4882a593Smuzhiyun 		c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
171*4882a593Smuzhiyun 	}
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	/* PER */
174*4882a593Smuzhiyun 	if (*status & FE_HAS_SYNC) {
175*4882a593Smuzhiyun 		ret = regmap_bulk_read(dev->regmap[0], 0xe1, buf, 4);
176*4882a593Smuzhiyun 		if (ret)
177*4882a593Smuzhiyun 			goto err;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 		utmp1 = buf[0] << 8 | buf[1] << 0;
180*4882a593Smuzhiyun 		utmp2 = buf[2] << 8 | buf[3] << 0;
181*4882a593Smuzhiyun 		dev_dbg(&client->dev, "block_error=%u block_count=%u\n",
182*4882a593Smuzhiyun 			utmp1, utmp2);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 		c->block_error.stat[0].scale = FE_SCALE_COUNTER;
185*4882a593Smuzhiyun 		c->block_error.stat[0].uvalue += utmp1;
186*4882a593Smuzhiyun 		c->block_count.stat[0].scale = FE_SCALE_COUNTER;
187*4882a593Smuzhiyun 		c->block_count.stat[0].uvalue += utmp2;
188*4882a593Smuzhiyun 	} else {
189*4882a593Smuzhiyun 		c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
190*4882a593Smuzhiyun 		c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
191*4882a593Smuzhiyun 	}
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	return 0;
194*4882a593Smuzhiyun err:
195*4882a593Smuzhiyun 	dev_dbg(&client->dev, "failed=%d\n", ret);
196*4882a593Smuzhiyun 	return ret;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun 
mn88472_set_frontend(struct dvb_frontend * fe)199*4882a593Smuzhiyun static int mn88472_set_frontend(struct dvb_frontend *fe)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun 	struct i2c_client *client = fe->demodulator_priv;
202*4882a593Smuzhiyun 	struct mn88472_dev *dev = i2c_get_clientdata(client);
203*4882a593Smuzhiyun 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
204*4882a593Smuzhiyun 	int ret, i;
205*4882a593Smuzhiyun 	unsigned int utmp;
206*4882a593Smuzhiyun 	u32 if_frequency;
207*4882a593Smuzhiyun 	u8 buf[3], delivery_system_val, bandwidth_val, *bandwidth_vals_ptr;
208*4882a593Smuzhiyun 	u8 reg_bank0_b4_val, reg_bank0_cd_val, reg_bank0_d4_val;
209*4882a593Smuzhiyun 	u8 reg_bank0_d6_val;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	dev_dbg(&client->dev,
212*4882a593Smuzhiyun 		"delivery_system=%u modulation=%u frequency=%u bandwidth_hz=%u symbol_rate=%u inversion=%d stream_id=%d\n",
213*4882a593Smuzhiyun 		c->delivery_system, c->modulation, c->frequency,
214*4882a593Smuzhiyun 		c->bandwidth_hz, c->symbol_rate, c->inversion, c->stream_id);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	if (!dev->active) {
217*4882a593Smuzhiyun 		ret = -EAGAIN;
218*4882a593Smuzhiyun 		goto err;
219*4882a593Smuzhiyun 	}
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	switch (c->delivery_system) {
222*4882a593Smuzhiyun 	case SYS_DVBT:
223*4882a593Smuzhiyun 		delivery_system_val = 0x02;
224*4882a593Smuzhiyun 		reg_bank0_b4_val = 0x00;
225*4882a593Smuzhiyun 		reg_bank0_cd_val = 0x1f;
226*4882a593Smuzhiyun 		reg_bank0_d4_val = 0x0a;
227*4882a593Smuzhiyun 		reg_bank0_d6_val = 0x48;
228*4882a593Smuzhiyun 		break;
229*4882a593Smuzhiyun 	case SYS_DVBT2:
230*4882a593Smuzhiyun 		delivery_system_val = 0x03;
231*4882a593Smuzhiyun 		reg_bank0_b4_val = 0xf6;
232*4882a593Smuzhiyun 		reg_bank0_cd_val = 0x01;
233*4882a593Smuzhiyun 		reg_bank0_d4_val = 0x09;
234*4882a593Smuzhiyun 		reg_bank0_d6_val = 0x46;
235*4882a593Smuzhiyun 		break;
236*4882a593Smuzhiyun 	case SYS_DVBC_ANNEX_A:
237*4882a593Smuzhiyun 		delivery_system_val = 0x04;
238*4882a593Smuzhiyun 		reg_bank0_b4_val = 0x00;
239*4882a593Smuzhiyun 		reg_bank0_cd_val = 0x17;
240*4882a593Smuzhiyun 		reg_bank0_d4_val = 0x09;
241*4882a593Smuzhiyun 		reg_bank0_d6_val = 0x48;
242*4882a593Smuzhiyun 		break;
243*4882a593Smuzhiyun 	default:
244*4882a593Smuzhiyun 		ret = -EINVAL;
245*4882a593Smuzhiyun 		goto err;
246*4882a593Smuzhiyun 	}
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	switch (c->delivery_system) {
249*4882a593Smuzhiyun 	case SYS_DVBT:
250*4882a593Smuzhiyun 	case SYS_DVBT2:
251*4882a593Smuzhiyun 		switch (c->bandwidth_hz) {
252*4882a593Smuzhiyun 		case 5000000:
253*4882a593Smuzhiyun 			bandwidth_vals_ptr = "\xe5\x99\x9a\x1b\xa9\x1b\xa9";
254*4882a593Smuzhiyun 			bandwidth_val = 0x03;
255*4882a593Smuzhiyun 			break;
256*4882a593Smuzhiyun 		case 6000000:
257*4882a593Smuzhiyun 			bandwidth_vals_ptr = "\xbf\x55\x55\x15\x6b\x15\x6b";
258*4882a593Smuzhiyun 			bandwidth_val = 0x02;
259*4882a593Smuzhiyun 			break;
260*4882a593Smuzhiyun 		case 7000000:
261*4882a593Smuzhiyun 			bandwidth_vals_ptr = "\xa4\x00\x00\x0f\x2c\x0f\x2c";
262*4882a593Smuzhiyun 			bandwidth_val = 0x01;
263*4882a593Smuzhiyun 			break;
264*4882a593Smuzhiyun 		case 8000000:
265*4882a593Smuzhiyun 			bandwidth_vals_ptr = "\x8f\x80\x00\x08\xee\x08\xee";
266*4882a593Smuzhiyun 			bandwidth_val = 0x00;
267*4882a593Smuzhiyun 			break;
268*4882a593Smuzhiyun 		default:
269*4882a593Smuzhiyun 			ret = -EINVAL;
270*4882a593Smuzhiyun 			goto err;
271*4882a593Smuzhiyun 		}
272*4882a593Smuzhiyun 		break;
273*4882a593Smuzhiyun 	case SYS_DVBC_ANNEX_A:
274*4882a593Smuzhiyun 		bandwidth_vals_ptr = NULL;
275*4882a593Smuzhiyun 		bandwidth_val = 0x00;
276*4882a593Smuzhiyun 		break;
277*4882a593Smuzhiyun 	default:
278*4882a593Smuzhiyun 		break;
279*4882a593Smuzhiyun 	}
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	/* Program tuner */
282*4882a593Smuzhiyun 	if (fe->ops.tuner_ops.set_params) {
283*4882a593Smuzhiyun 		ret = fe->ops.tuner_ops.set_params(fe);
284*4882a593Smuzhiyun 		if (ret)
285*4882a593Smuzhiyun 			goto err;
286*4882a593Smuzhiyun 	}
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	if (fe->ops.tuner_ops.get_if_frequency) {
289*4882a593Smuzhiyun 		ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
290*4882a593Smuzhiyun 		if (ret)
291*4882a593Smuzhiyun 			goto err;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 		dev_dbg(&client->dev, "get_if_frequency=%d\n", if_frequency);
294*4882a593Smuzhiyun 	} else {
295*4882a593Smuzhiyun 		ret = -EINVAL;
296*4882a593Smuzhiyun 		goto err;
297*4882a593Smuzhiyun 	}
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x00, 0x66);
300*4882a593Smuzhiyun 	if (ret)
301*4882a593Smuzhiyun 		goto err;
302*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x01, 0x00);
303*4882a593Smuzhiyun 	if (ret)
304*4882a593Smuzhiyun 		goto err;
305*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x02, 0x01);
306*4882a593Smuzhiyun 	if (ret)
307*4882a593Smuzhiyun 		goto err;
308*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x03, delivery_system_val);
309*4882a593Smuzhiyun 	if (ret)
310*4882a593Smuzhiyun 		goto err;
311*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x04, bandwidth_val);
312*4882a593Smuzhiyun 	if (ret)
313*4882a593Smuzhiyun 		goto err;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	/* IF */
316*4882a593Smuzhiyun 	utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, dev->clk);
317*4882a593Smuzhiyun 	buf[0] = (utmp >> 16) & 0xff;
318*4882a593Smuzhiyun 	buf[1] = (utmp >>  8) & 0xff;
319*4882a593Smuzhiyun 	buf[2] = (utmp >>  0) & 0xff;
320*4882a593Smuzhiyun 	for (i = 0; i < 3; i++) {
321*4882a593Smuzhiyun 		ret = regmap_write(dev->regmap[2], 0x10 + i, buf[i]);
322*4882a593Smuzhiyun 		if (ret)
323*4882a593Smuzhiyun 			goto err;
324*4882a593Smuzhiyun 	}
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	/* Bandwidth */
327*4882a593Smuzhiyun 	if (bandwidth_vals_ptr) {
328*4882a593Smuzhiyun 		for (i = 0; i < 7; i++) {
329*4882a593Smuzhiyun 			ret = regmap_write(dev->regmap[2], 0x13 + i,
330*4882a593Smuzhiyun 					   bandwidth_vals_ptr[i]);
331*4882a593Smuzhiyun 			if (ret)
332*4882a593Smuzhiyun 				goto err;
333*4882a593Smuzhiyun 		}
334*4882a593Smuzhiyun 	}
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[0], 0xb4, reg_bank0_b4_val);
337*4882a593Smuzhiyun 	if (ret)
338*4882a593Smuzhiyun 		goto err;
339*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[0], 0xcd, reg_bank0_cd_val);
340*4882a593Smuzhiyun 	if (ret)
341*4882a593Smuzhiyun 		goto err;
342*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[0], 0xd4, reg_bank0_d4_val);
343*4882a593Smuzhiyun 	if (ret)
344*4882a593Smuzhiyun 		goto err;
345*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[0], 0xd6, reg_bank0_d6_val);
346*4882a593Smuzhiyun 	if (ret)
347*4882a593Smuzhiyun 		goto err;
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	switch (c->delivery_system) {
350*4882a593Smuzhiyun 	case SYS_DVBT:
351*4882a593Smuzhiyun 		ret = regmap_write(dev->regmap[0], 0x07, 0x26);
352*4882a593Smuzhiyun 		if (ret)
353*4882a593Smuzhiyun 			goto err;
354*4882a593Smuzhiyun 		ret = regmap_write(dev->regmap[0], 0x00, 0xba);
355*4882a593Smuzhiyun 		if (ret)
356*4882a593Smuzhiyun 			goto err;
357*4882a593Smuzhiyun 		ret = regmap_write(dev->regmap[0], 0x01, 0x13);
358*4882a593Smuzhiyun 		if (ret)
359*4882a593Smuzhiyun 			goto err;
360*4882a593Smuzhiyun 		break;
361*4882a593Smuzhiyun 	case SYS_DVBT2:
362*4882a593Smuzhiyun 		ret = regmap_write(dev->regmap[2], 0x2b, 0x13);
363*4882a593Smuzhiyun 		if (ret)
364*4882a593Smuzhiyun 			goto err;
365*4882a593Smuzhiyun 		ret = regmap_write(dev->regmap[2], 0x4f, 0x05);
366*4882a593Smuzhiyun 		if (ret)
367*4882a593Smuzhiyun 			goto err;
368*4882a593Smuzhiyun 		ret = regmap_write(dev->regmap[1], 0xf6, 0x05);
369*4882a593Smuzhiyun 		if (ret)
370*4882a593Smuzhiyun 			goto err;
371*4882a593Smuzhiyun 		ret = regmap_write(dev->regmap[2], 0x32,
372*4882a593Smuzhiyun 				(c->stream_id == NO_STREAM_ID_FILTER) ? 0 :
373*4882a593Smuzhiyun 				c->stream_id );
374*4882a593Smuzhiyun 		if (ret)
375*4882a593Smuzhiyun 			goto err;
376*4882a593Smuzhiyun 		break;
377*4882a593Smuzhiyun 	case SYS_DVBC_ANNEX_A:
378*4882a593Smuzhiyun 		break;
379*4882a593Smuzhiyun 	default:
380*4882a593Smuzhiyun 		break;
381*4882a593Smuzhiyun 	}
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	/* Reset FSM */
384*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0xf8, 0x9f);
385*4882a593Smuzhiyun 	if (ret)
386*4882a593Smuzhiyun 		goto err;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	return 0;
389*4882a593Smuzhiyun err:
390*4882a593Smuzhiyun 	dev_dbg(&client->dev, "failed=%d\n", ret);
391*4882a593Smuzhiyun 	return ret;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun 
mn88472_init(struct dvb_frontend * fe)394*4882a593Smuzhiyun static int mn88472_init(struct dvb_frontend *fe)
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun 	struct i2c_client *client = fe->demodulator_priv;
397*4882a593Smuzhiyun 	struct mn88472_dev *dev = i2c_get_clientdata(client);
398*4882a593Smuzhiyun 	int ret, len, rem;
399*4882a593Smuzhiyun 	unsigned int utmp;
400*4882a593Smuzhiyun 	const struct firmware *firmware;
401*4882a593Smuzhiyun 	const char *name = MN88472_FIRMWARE;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	dev_dbg(&client->dev, "\n");
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	/* Power up */
406*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x05, 0x00);
407*4882a593Smuzhiyun 	if (ret)
408*4882a593Smuzhiyun 		goto err;
409*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x0b, 0x00);
410*4882a593Smuzhiyun 	if (ret)
411*4882a593Smuzhiyun 		goto err;
412*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x0c, 0x00);
413*4882a593Smuzhiyun 	if (ret)
414*4882a593Smuzhiyun 		goto err;
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	/* Check if firmware is already running */
417*4882a593Smuzhiyun 	ret = regmap_read(dev->regmap[0], 0xf5, &utmp);
418*4882a593Smuzhiyun 	if (ret)
419*4882a593Smuzhiyun 		goto err;
420*4882a593Smuzhiyun 	if (!(utmp & 0x01))
421*4882a593Smuzhiyun 		goto warm;
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	ret = request_firmware(&firmware, name, &client->dev);
424*4882a593Smuzhiyun 	if (ret) {
425*4882a593Smuzhiyun 		dev_err(&client->dev, "firmware file '%s' not found\n", name);
426*4882a593Smuzhiyun 		goto err;
427*4882a593Smuzhiyun 	}
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[0], 0xf5, 0x03);
432*4882a593Smuzhiyun 	if (ret)
433*4882a593Smuzhiyun 		goto err_release_firmware;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	for (rem = firmware->size; rem > 0; rem -= (dev->i2c_write_max - 1)) {
436*4882a593Smuzhiyun 		len = min(dev->i2c_write_max - 1, rem);
437*4882a593Smuzhiyun 		ret = regmap_bulk_write(dev->regmap[0], 0xf6,
438*4882a593Smuzhiyun 					&firmware->data[firmware->size - rem],
439*4882a593Smuzhiyun 					len);
440*4882a593Smuzhiyun 		if (ret) {
441*4882a593Smuzhiyun 			dev_err(&client->dev, "firmware download failed %d\n",
442*4882a593Smuzhiyun 				ret);
443*4882a593Smuzhiyun 			goto err_release_firmware;
444*4882a593Smuzhiyun 		}
445*4882a593Smuzhiyun 	}
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	/* Parity check of firmware */
448*4882a593Smuzhiyun 	ret = regmap_read(dev->regmap[0], 0xf8, &utmp);
449*4882a593Smuzhiyun 	if (ret)
450*4882a593Smuzhiyun 		goto err_release_firmware;
451*4882a593Smuzhiyun 	if (utmp & 0x10) {
452*4882a593Smuzhiyun 		ret = -EINVAL;
453*4882a593Smuzhiyun 		dev_err(&client->dev, "firmware did not run\n");
454*4882a593Smuzhiyun 		goto err_release_firmware;
455*4882a593Smuzhiyun 	}
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[0], 0xf5, 0x00);
458*4882a593Smuzhiyun 	if (ret)
459*4882a593Smuzhiyun 		goto err_release_firmware;
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	release_firmware(firmware);
462*4882a593Smuzhiyun warm:
463*4882a593Smuzhiyun 	/* TS config */
464*4882a593Smuzhiyun 	switch (dev->ts_mode) {
465*4882a593Smuzhiyun 	case SERIAL_TS_MODE:
466*4882a593Smuzhiyun 		utmp = 0x1d;
467*4882a593Smuzhiyun 		break;
468*4882a593Smuzhiyun 	case PARALLEL_TS_MODE:
469*4882a593Smuzhiyun 		utmp = 0x00;
470*4882a593Smuzhiyun 		break;
471*4882a593Smuzhiyun 	default:
472*4882a593Smuzhiyun 		ret = -EINVAL;
473*4882a593Smuzhiyun 		goto err;
474*4882a593Smuzhiyun 	}
475*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x08, utmp);
476*4882a593Smuzhiyun 	if (ret)
477*4882a593Smuzhiyun 		goto err;
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	switch (dev->ts_clk) {
480*4882a593Smuzhiyun 	case VARIABLE_TS_CLOCK:
481*4882a593Smuzhiyun 		utmp = 0xe3;
482*4882a593Smuzhiyun 		break;
483*4882a593Smuzhiyun 	case FIXED_TS_CLOCK:
484*4882a593Smuzhiyun 		utmp = 0xe1;
485*4882a593Smuzhiyun 		break;
486*4882a593Smuzhiyun 	default:
487*4882a593Smuzhiyun 		ret = -EINVAL;
488*4882a593Smuzhiyun 		goto err;
489*4882a593Smuzhiyun 	}
490*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[0], 0xd9, utmp);
491*4882a593Smuzhiyun 	if (ret)
492*4882a593Smuzhiyun 		goto err;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	dev->active = true;
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	return 0;
497*4882a593Smuzhiyun err_release_firmware:
498*4882a593Smuzhiyun 	release_firmware(firmware);
499*4882a593Smuzhiyun err:
500*4882a593Smuzhiyun 	dev_dbg(&client->dev, "failed=%d\n", ret);
501*4882a593Smuzhiyun 	return ret;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun 
mn88472_sleep(struct dvb_frontend * fe)504*4882a593Smuzhiyun static int mn88472_sleep(struct dvb_frontend *fe)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun 	struct i2c_client *client = fe->demodulator_priv;
507*4882a593Smuzhiyun 	struct mn88472_dev *dev = i2c_get_clientdata(client);
508*4882a593Smuzhiyun 	int ret;
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 	dev_dbg(&client->dev, "\n");
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	/* Power down */
513*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x0c, 0x30);
514*4882a593Smuzhiyun 	if (ret)
515*4882a593Smuzhiyun 		goto err;
516*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x0b, 0x30);
517*4882a593Smuzhiyun 	if (ret)
518*4882a593Smuzhiyun 		goto err;
519*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
520*4882a593Smuzhiyun 	if (ret)
521*4882a593Smuzhiyun 		goto err;
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 	return 0;
524*4882a593Smuzhiyun err:
525*4882a593Smuzhiyun 	dev_dbg(&client->dev, "failed=%d\n", ret);
526*4882a593Smuzhiyun 	return ret;
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun static const struct dvb_frontend_ops mn88472_ops = {
530*4882a593Smuzhiyun 	.delsys = {SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A},
531*4882a593Smuzhiyun 	.info = {
532*4882a593Smuzhiyun 		.name = "Panasonic MN88472",
533*4882a593Smuzhiyun 		.symbol_rate_min = 1000000,
534*4882a593Smuzhiyun 		.symbol_rate_max = 7200000,
535*4882a593Smuzhiyun 		.caps =	FE_CAN_FEC_1_2                 |
536*4882a593Smuzhiyun 			FE_CAN_FEC_2_3                 |
537*4882a593Smuzhiyun 			FE_CAN_FEC_3_4                 |
538*4882a593Smuzhiyun 			FE_CAN_FEC_5_6                 |
539*4882a593Smuzhiyun 			FE_CAN_FEC_7_8                 |
540*4882a593Smuzhiyun 			FE_CAN_FEC_AUTO                |
541*4882a593Smuzhiyun 			FE_CAN_QPSK                    |
542*4882a593Smuzhiyun 			FE_CAN_QAM_16                  |
543*4882a593Smuzhiyun 			FE_CAN_QAM_32                  |
544*4882a593Smuzhiyun 			FE_CAN_QAM_64                  |
545*4882a593Smuzhiyun 			FE_CAN_QAM_128                 |
546*4882a593Smuzhiyun 			FE_CAN_QAM_256                 |
547*4882a593Smuzhiyun 			FE_CAN_QAM_AUTO                |
548*4882a593Smuzhiyun 			FE_CAN_TRANSMISSION_MODE_AUTO  |
549*4882a593Smuzhiyun 			FE_CAN_GUARD_INTERVAL_AUTO     |
550*4882a593Smuzhiyun 			FE_CAN_HIERARCHY_AUTO          |
551*4882a593Smuzhiyun 			FE_CAN_MUTE_TS                 |
552*4882a593Smuzhiyun 			FE_CAN_2G_MODULATION           |
553*4882a593Smuzhiyun 			FE_CAN_MULTISTREAM
554*4882a593Smuzhiyun 	},
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	.get_tune_settings = mn88472_get_tune_settings,
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	.init = mn88472_init,
559*4882a593Smuzhiyun 	.sleep = mn88472_sleep,
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	.set_frontend = mn88472_set_frontend,
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 	.read_status = mn88472_read_status,
564*4882a593Smuzhiyun };
565*4882a593Smuzhiyun 
mn88472_get_dvb_frontend(struct i2c_client * client)566*4882a593Smuzhiyun static struct dvb_frontend *mn88472_get_dvb_frontend(struct i2c_client *client)
567*4882a593Smuzhiyun {
568*4882a593Smuzhiyun 	struct mn88472_dev *dev = i2c_get_clientdata(client);
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	dev_dbg(&client->dev, "\n");
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	return &dev->fe;
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun 
mn88472_probe(struct i2c_client * client,const struct i2c_device_id * id)575*4882a593Smuzhiyun static int mn88472_probe(struct i2c_client *client,
576*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun 	struct mn88472_config *pdata = client->dev.platform_data;
579*4882a593Smuzhiyun 	struct mn88472_dev *dev;
580*4882a593Smuzhiyun 	struct dtv_frontend_properties *c;
581*4882a593Smuzhiyun 	int ret;
582*4882a593Smuzhiyun 	unsigned int utmp;
583*4882a593Smuzhiyun 	static const struct regmap_config regmap_config = {
584*4882a593Smuzhiyun 		.reg_bits = 8,
585*4882a593Smuzhiyun 		.val_bits = 8,
586*4882a593Smuzhiyun 	};
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	dev_dbg(&client->dev, "\n");
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
591*4882a593Smuzhiyun 	if (!dev) {
592*4882a593Smuzhiyun 		ret = -ENOMEM;
593*4882a593Smuzhiyun 		goto err;
594*4882a593Smuzhiyun 	}
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	dev->i2c_write_max = pdata->i2c_wr_max ? pdata->i2c_wr_max : ~0;
597*4882a593Smuzhiyun 	dev->clk = pdata->xtal;
598*4882a593Smuzhiyun 	dev->ts_mode = pdata->ts_mode;
599*4882a593Smuzhiyun 	dev->ts_clk = pdata->ts_clock;
600*4882a593Smuzhiyun 	dev->client[0] = client;
601*4882a593Smuzhiyun 	dev->regmap[0] = regmap_init_i2c(dev->client[0], &regmap_config);
602*4882a593Smuzhiyun 	if (IS_ERR(dev->regmap[0])) {
603*4882a593Smuzhiyun 		ret = PTR_ERR(dev->regmap[0]);
604*4882a593Smuzhiyun 		goto err_kfree;
605*4882a593Smuzhiyun 	}
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	/*
608*4882a593Smuzhiyun 	 * Chip has three I2C addresses for different register banks. Used
609*4882a593Smuzhiyun 	 * addresses are 0x18, 0x1a and 0x1c. We register two dummy clients,
610*4882a593Smuzhiyun 	 * 0x1a and 0x1c, in order to get own I2C client for each register bank.
611*4882a593Smuzhiyun 	 *
612*4882a593Smuzhiyun 	 * Also, register bank 2 do not support sequential I/O. Only single
613*4882a593Smuzhiyun 	 * register write or read is allowed to that bank.
614*4882a593Smuzhiyun 	 */
615*4882a593Smuzhiyun 	dev->client[1] = i2c_new_dummy_device(client->adapter, 0x1a);
616*4882a593Smuzhiyun 	if (IS_ERR(dev->client[1])) {
617*4882a593Smuzhiyun 		ret = PTR_ERR(dev->client[1]);
618*4882a593Smuzhiyun 		dev_err(&client->dev, "I2C registration failed\n");
619*4882a593Smuzhiyun 		goto err_regmap_0_regmap_exit;
620*4882a593Smuzhiyun 	}
621*4882a593Smuzhiyun 	dev->regmap[1] = regmap_init_i2c(dev->client[1], &regmap_config);
622*4882a593Smuzhiyun 	if (IS_ERR(dev->regmap[1])) {
623*4882a593Smuzhiyun 		ret = PTR_ERR(dev->regmap[1]);
624*4882a593Smuzhiyun 		goto err_client_1_i2c_unregister_device;
625*4882a593Smuzhiyun 	}
626*4882a593Smuzhiyun 	i2c_set_clientdata(dev->client[1], dev);
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 	dev->client[2] = i2c_new_dummy_device(client->adapter, 0x1c);
629*4882a593Smuzhiyun 	if (IS_ERR(dev->client[2])) {
630*4882a593Smuzhiyun 		ret = PTR_ERR(dev->client[2]);
631*4882a593Smuzhiyun 		dev_err(&client->dev, "2nd I2C registration failed\n");
632*4882a593Smuzhiyun 		goto err_regmap_1_regmap_exit;
633*4882a593Smuzhiyun 	}
634*4882a593Smuzhiyun 	dev->regmap[2] = regmap_init_i2c(dev->client[2], &regmap_config);
635*4882a593Smuzhiyun 	if (IS_ERR(dev->regmap[2])) {
636*4882a593Smuzhiyun 		ret = PTR_ERR(dev->regmap[2]);
637*4882a593Smuzhiyun 		goto err_client_2_i2c_unregister_device;
638*4882a593Smuzhiyun 	}
639*4882a593Smuzhiyun 	i2c_set_clientdata(dev->client[2], dev);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	/* Check demod answers with correct chip id */
642*4882a593Smuzhiyun 	ret = regmap_read(dev->regmap[2], 0xff, &utmp);
643*4882a593Smuzhiyun 	if (ret)
644*4882a593Smuzhiyun 		goto err_regmap_2_regmap_exit;
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun 	dev_dbg(&client->dev, "chip id=%02x\n", utmp);
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	if (utmp != 0x02) {
649*4882a593Smuzhiyun 		ret = -ENODEV;
650*4882a593Smuzhiyun 		goto err_regmap_2_regmap_exit;
651*4882a593Smuzhiyun 	}
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	/* Sleep because chip is active by default */
654*4882a593Smuzhiyun 	ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
655*4882a593Smuzhiyun 	if (ret)
656*4882a593Smuzhiyun 		goto err_regmap_2_regmap_exit;
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	/* Create dvb frontend */
659*4882a593Smuzhiyun 	memcpy(&dev->fe.ops, &mn88472_ops, sizeof(struct dvb_frontend_ops));
660*4882a593Smuzhiyun 	dev->fe.demodulator_priv = client;
661*4882a593Smuzhiyun 	*pdata->fe = &dev->fe;
662*4882a593Smuzhiyun 	i2c_set_clientdata(client, dev);
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	/* Init stats to indicate which stats are supported */
665*4882a593Smuzhiyun 	c = &dev->fe.dtv_property_cache;
666*4882a593Smuzhiyun 	c->strength.len = 1;
667*4882a593Smuzhiyun 	c->cnr.len = 1;
668*4882a593Smuzhiyun 	c->block_error.len = 1;
669*4882a593Smuzhiyun 	c->block_count.len = 1;
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	/* Setup callbacks */
672*4882a593Smuzhiyun 	pdata->get_dvb_frontend = mn88472_get_dvb_frontend;
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun 	dev_info(&client->dev, "Panasonic MN88472 successfully identified\n");
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	return 0;
677*4882a593Smuzhiyun err_regmap_2_regmap_exit:
678*4882a593Smuzhiyun 	regmap_exit(dev->regmap[2]);
679*4882a593Smuzhiyun err_client_2_i2c_unregister_device:
680*4882a593Smuzhiyun 	i2c_unregister_device(dev->client[2]);
681*4882a593Smuzhiyun err_regmap_1_regmap_exit:
682*4882a593Smuzhiyun 	regmap_exit(dev->regmap[1]);
683*4882a593Smuzhiyun err_client_1_i2c_unregister_device:
684*4882a593Smuzhiyun 	i2c_unregister_device(dev->client[1]);
685*4882a593Smuzhiyun err_regmap_0_regmap_exit:
686*4882a593Smuzhiyun 	regmap_exit(dev->regmap[0]);
687*4882a593Smuzhiyun err_kfree:
688*4882a593Smuzhiyun 	kfree(dev);
689*4882a593Smuzhiyun err:
690*4882a593Smuzhiyun 	dev_dbg(&client->dev, "failed=%d\n", ret);
691*4882a593Smuzhiyun 	return ret;
692*4882a593Smuzhiyun }
693*4882a593Smuzhiyun 
mn88472_remove(struct i2c_client * client)694*4882a593Smuzhiyun static int mn88472_remove(struct i2c_client *client)
695*4882a593Smuzhiyun {
696*4882a593Smuzhiyun 	struct mn88472_dev *dev = i2c_get_clientdata(client);
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun 	dev_dbg(&client->dev, "\n");
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	regmap_exit(dev->regmap[2]);
701*4882a593Smuzhiyun 	i2c_unregister_device(dev->client[2]);
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	regmap_exit(dev->regmap[1]);
704*4882a593Smuzhiyun 	i2c_unregister_device(dev->client[1]);
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	regmap_exit(dev->regmap[0]);
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 	kfree(dev);
709*4882a593Smuzhiyun 
710*4882a593Smuzhiyun 	return 0;
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun static const struct i2c_device_id mn88472_id_table[] = {
714*4882a593Smuzhiyun 	{"mn88472", 0},
715*4882a593Smuzhiyun 	{}
716*4882a593Smuzhiyun };
717*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mn88472_id_table);
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun static struct i2c_driver mn88472_driver = {
720*4882a593Smuzhiyun 	.driver = {
721*4882a593Smuzhiyun 		.name = "mn88472",
722*4882a593Smuzhiyun 		.suppress_bind_attrs = true,
723*4882a593Smuzhiyun 	},
724*4882a593Smuzhiyun 	.probe    = mn88472_probe,
725*4882a593Smuzhiyun 	.remove   = mn88472_remove,
726*4882a593Smuzhiyun 	.id_table = mn88472_id_table,
727*4882a593Smuzhiyun };
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun module_i2c_driver(mn88472_driver);
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
732*4882a593Smuzhiyun MODULE_DESCRIPTION("Panasonic MN88472 DVB-T/T2/C demodulator driver");
733*4882a593Smuzhiyun MODULE_LICENSE("GPL");
734*4882a593Smuzhiyun MODULE_FIRMWARE(MN88472_FIRMWARE);
735