1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Support for Legend Silicon GB20600 (a.k.a DMB-TH) demodulator 4*4882a593Smuzhiyun * LGS8913, LGS8GL5, LGS8G75 5*4882a593Smuzhiyun * experimental support LGS8G42, LGS8G52 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2007-2009 David T.L. Wong <davidtlwong@gmail.com> 8*4882a593Smuzhiyun * Copyright (C) 2008 Sirius International (Hong Kong) Limited 9*4882a593Smuzhiyun * Timothy Lee <timothy.lee@siriushk.com> (for initial work on LGS8GL5) 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef LGS8913_PRIV_H 13*4882a593Smuzhiyun #define LGS8913_PRIV_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct lgs8gxx_state { 16*4882a593Smuzhiyun struct i2c_adapter *i2c; 17*4882a593Smuzhiyun /* configuration settings */ 18*4882a593Smuzhiyun const struct lgs8gxx_config *config; 19*4882a593Smuzhiyun struct dvb_frontend frontend; 20*4882a593Smuzhiyun u16 curr_gi; /* current guard interval */ 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define SC_MASK 0x1C /* Sub-Carrier Modulation Mask */ 24*4882a593Smuzhiyun #define SC_QAM64 0x10 /* 64QAM modulation */ 25*4882a593Smuzhiyun #define SC_QAM32 0x0C /* 32QAM modulation */ 26*4882a593Smuzhiyun #define SC_QAM16 0x08 /* 16QAM modulation */ 27*4882a593Smuzhiyun #define SC_QAM4NR 0x04 /* 4QAM-NR modulation */ 28*4882a593Smuzhiyun #define SC_QAM4 0x00 /* 4QAM modulation */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define LGS_FEC_MASK 0x03 /* FEC Rate Mask */ 31*4882a593Smuzhiyun #define LGS_FEC_0_4 0x00 /* FEC Rate 0.4 */ 32*4882a593Smuzhiyun #define LGS_FEC_0_6 0x01 /* FEC Rate 0.6 */ 33*4882a593Smuzhiyun #define LGS_FEC_0_8 0x02 /* FEC Rate 0.8 */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define TIM_MASK 0x20 /* Time Interleave Length Mask */ 36*4882a593Smuzhiyun #define TIM_LONG 0x20 /* Time Interleave Length = 720 */ 37*4882a593Smuzhiyun #define TIM_MIDDLE 0x00 /* Time Interleave Length = 240 */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CF_MASK 0x80 /* Control Frame Mask */ 40*4882a593Smuzhiyun #define CF_EN 0x80 /* Control Frame On */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define GI_MASK 0x03 /* Guard Interval Mask */ 43*4882a593Smuzhiyun #define GI_420 0x00 /* 1/9 Guard Interval */ 44*4882a593Smuzhiyun #define GI_595 0x01 /* */ 45*4882a593Smuzhiyun #define GI_945 0x02 /* 1/4 Guard Interval */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define TS_PARALLEL 0x00 /* Parallel TS Output a.k.a. SPI */ 49*4882a593Smuzhiyun #define TS_SERIAL 0x01 /* Serial TS Output a.k.a. SSI */ 50*4882a593Smuzhiyun #define TS_CLK_NORMAL 0x00 /* MPEG Clock Normal */ 51*4882a593Smuzhiyun #define TS_CLK_INVERTED 0x02 /* MPEG Clock Inverted */ 52*4882a593Smuzhiyun #define TS_CLK_GATED 0x00 /* MPEG clock gated */ 53*4882a593Smuzhiyun #define TS_CLK_FREERUN 0x04 /* MPEG clock free running*/ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif 57