1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * gp8psk_fe driver 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef GP8PSK_FE_H 7*4882a593Smuzhiyun #define GP8PSK_FE_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/types.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* gp8psk commands */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define GET_8PSK_CONFIG 0x80 /* in */ 14*4882a593Smuzhiyun #define SET_8PSK_CONFIG 0x81 15*4882a593Smuzhiyun #define I2C_WRITE 0x83 16*4882a593Smuzhiyun #define I2C_READ 0x84 17*4882a593Smuzhiyun #define ARM_TRANSFER 0x85 18*4882a593Smuzhiyun #define TUNE_8PSK 0x86 19*4882a593Smuzhiyun #define GET_SIGNAL_STRENGTH 0x87 /* in */ 20*4882a593Smuzhiyun #define LOAD_BCM4500 0x88 21*4882a593Smuzhiyun #define BOOT_8PSK 0x89 /* in */ 22*4882a593Smuzhiyun #define START_INTERSIL 0x8A /* in */ 23*4882a593Smuzhiyun #define SET_LNB_VOLTAGE 0x8B 24*4882a593Smuzhiyun #define SET_22KHZ_TONE 0x8C 25*4882a593Smuzhiyun #define SEND_DISEQC_COMMAND 0x8D 26*4882a593Smuzhiyun #define SET_DVB_MODE 0x8E 27*4882a593Smuzhiyun #define SET_DN_SWITCH 0x8F 28*4882a593Smuzhiyun #define GET_SIGNAL_LOCK 0x90 /* in */ 29*4882a593Smuzhiyun #define GET_FW_VERS 0x92 30*4882a593Smuzhiyun #define GET_SERIAL_NUMBER 0x93 /* in */ 31*4882a593Smuzhiyun #define USE_EXTRA_VOLT 0x94 32*4882a593Smuzhiyun #define GET_FPGA_VERS 0x95 33*4882a593Smuzhiyun #define CW3K_INIT 0x9d 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* PSK_configuration bits */ 36*4882a593Smuzhiyun #define bm8pskStarted 0x01 37*4882a593Smuzhiyun #define bm8pskFW_Loaded 0x02 38*4882a593Smuzhiyun #define bmIntersilOn 0x04 39*4882a593Smuzhiyun #define bmDVBmode 0x08 40*4882a593Smuzhiyun #define bm22kHz 0x10 41*4882a593Smuzhiyun #define bmSEL18V 0x20 42*4882a593Smuzhiyun #define bmDCtuned 0x40 43*4882a593Smuzhiyun #define bmArmed 0x80 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Satellite modulation modes */ 46*4882a593Smuzhiyun #define ADV_MOD_DVB_QPSK 0 /* DVB-S QPSK */ 47*4882a593Smuzhiyun #define ADV_MOD_TURBO_QPSK 1 /* Turbo QPSK */ 48*4882a593Smuzhiyun #define ADV_MOD_TURBO_8PSK 2 /* Turbo 8PSK (also used for Trellis 8PSK) */ 49*4882a593Smuzhiyun #define ADV_MOD_TURBO_16QAM 3 /* Turbo 16QAM (also used for Trellis 8PSK) */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define ADV_MOD_DCII_C_QPSK 4 /* Digicipher II Combo */ 52*4882a593Smuzhiyun #define ADV_MOD_DCII_I_QPSK 5 /* Digicipher II I-stream */ 53*4882a593Smuzhiyun #define ADV_MOD_DCII_Q_QPSK 6 /* Digicipher II Q-stream */ 54*4882a593Smuzhiyun #define ADV_MOD_DCII_C_OQPSK 7 /* Digicipher II offset QPSK */ 55*4882a593Smuzhiyun #define ADV_MOD_DSS_QPSK 8 /* DSS (DIRECTV) QPSK */ 56*4882a593Smuzhiyun #define ADV_MOD_DVB_BPSK 9 /* DVB-S BPSK */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* firmware revision id's */ 59*4882a593Smuzhiyun #define GP8PSK_FW_REV1 0x020604 60*4882a593Smuzhiyun #define GP8PSK_FW_REV2 0x020704 61*4882a593Smuzhiyun #define GP8PSK_FW_VERS(_fw_vers) \ 62*4882a593Smuzhiyun ((_fw_vers)[2]<<0x10 | (_fw_vers)[1]<<0x08 | (_fw_vers)[0]) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct gp8psk_fe_ops { 65*4882a593Smuzhiyun int (*in)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen); 66*4882a593Smuzhiyun int (*out)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen); 67*4882a593Smuzhiyun int (*reload)(void *priv); 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct dvb_frontend *gp8psk_fe_attach(const struct gp8psk_fe_ops *ops, 71*4882a593Smuzhiyun void *priv, bool is_rev1); 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif 74