1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * E3C EC100 demodulator driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <media/dvb_frontend.h>
9*4882a593Smuzhiyun #include "ec100.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun struct ec100_state {
12*4882a593Smuzhiyun struct i2c_adapter *i2c;
13*4882a593Smuzhiyun struct dvb_frontend frontend;
14*4882a593Smuzhiyun struct ec100_config config;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun u16 ber;
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* write single register */
ec100_write_reg(struct ec100_state * state,u8 reg,u8 val)20*4882a593Smuzhiyun static int ec100_write_reg(struct ec100_state *state, u8 reg, u8 val)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun int ret;
23*4882a593Smuzhiyun u8 buf[2] = {reg, val};
24*4882a593Smuzhiyun struct i2c_msg msg[1] = {
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun .addr = state->config.demod_address,
27*4882a593Smuzhiyun .flags = 0,
28*4882a593Smuzhiyun .len = sizeof(buf),
29*4882a593Smuzhiyun .buf = buf,
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun ret = i2c_transfer(state->i2c, msg, 1);
34*4882a593Smuzhiyun if (ret == 1) {
35*4882a593Smuzhiyun ret = 0;
36*4882a593Smuzhiyun } else {
37*4882a593Smuzhiyun dev_warn(&state->i2c->dev, "%s: i2c wr failed=%d reg=%02x\n",
38*4882a593Smuzhiyun KBUILD_MODNAME, ret, reg);
39*4882a593Smuzhiyun ret = -EREMOTEIO;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return ret;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* read single register */
ec100_read_reg(struct ec100_state * state,u8 reg,u8 * val)46*4882a593Smuzhiyun static int ec100_read_reg(struct ec100_state *state, u8 reg, u8 *val)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun int ret;
49*4882a593Smuzhiyun struct i2c_msg msg[2] = {
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun .addr = state->config.demod_address,
52*4882a593Smuzhiyun .flags = 0,
53*4882a593Smuzhiyun .len = 1,
54*4882a593Smuzhiyun .buf = ®
55*4882a593Smuzhiyun }, {
56*4882a593Smuzhiyun .addr = state->config.demod_address,
57*4882a593Smuzhiyun .flags = I2C_M_RD,
58*4882a593Smuzhiyun .len = 1,
59*4882a593Smuzhiyun .buf = val
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun ret = i2c_transfer(state->i2c, msg, 2);
64*4882a593Smuzhiyun if (ret == 2) {
65*4882a593Smuzhiyun ret = 0;
66*4882a593Smuzhiyun } else {
67*4882a593Smuzhiyun dev_warn(&state->i2c->dev, "%s: i2c rd failed=%d reg=%02x\n",
68*4882a593Smuzhiyun KBUILD_MODNAME, ret, reg);
69*4882a593Smuzhiyun ret = -EREMOTEIO;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return ret;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
ec100_set_frontend(struct dvb_frontend * fe)75*4882a593Smuzhiyun static int ec100_set_frontend(struct dvb_frontend *fe)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct dtv_frontend_properties *c = &fe->dtv_property_cache;
78*4882a593Smuzhiyun struct ec100_state *state = fe->demodulator_priv;
79*4882a593Smuzhiyun int ret;
80*4882a593Smuzhiyun u8 tmp, tmp2;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n",
83*4882a593Smuzhiyun __func__, c->frequency, c->bandwidth_hz);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* program tuner */
86*4882a593Smuzhiyun if (fe->ops.tuner_ops.set_params)
87*4882a593Smuzhiyun fe->ops.tuner_ops.set_params(fe);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun ret = ec100_write_reg(state, 0x04, 0x06);
90*4882a593Smuzhiyun if (ret)
91*4882a593Smuzhiyun goto error;
92*4882a593Smuzhiyun ret = ec100_write_reg(state, 0x67, 0x58);
93*4882a593Smuzhiyun if (ret)
94*4882a593Smuzhiyun goto error;
95*4882a593Smuzhiyun ret = ec100_write_reg(state, 0x05, 0x18);
96*4882a593Smuzhiyun if (ret)
97*4882a593Smuzhiyun goto error;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* reg/bw | 6 | 7 | 8
100*4882a593Smuzhiyun -------+------+------+------
101*4882a593Smuzhiyun A 0x1b | 0xa1 | 0xe7 | 0x2c
102*4882a593Smuzhiyun A 0x1c | 0x55 | 0x63 | 0x72
103*4882a593Smuzhiyun -------+------+------+------
104*4882a593Smuzhiyun B 0x1b | 0xb7 | 0x00 | 0x49
105*4882a593Smuzhiyun B 0x1c | 0x55 | 0x64 | 0x72 */
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun switch (c->bandwidth_hz) {
108*4882a593Smuzhiyun case 6000000:
109*4882a593Smuzhiyun tmp = 0xb7;
110*4882a593Smuzhiyun tmp2 = 0x55;
111*4882a593Smuzhiyun break;
112*4882a593Smuzhiyun case 7000000:
113*4882a593Smuzhiyun tmp = 0x00;
114*4882a593Smuzhiyun tmp2 = 0x64;
115*4882a593Smuzhiyun break;
116*4882a593Smuzhiyun case 8000000:
117*4882a593Smuzhiyun default:
118*4882a593Smuzhiyun tmp = 0x49;
119*4882a593Smuzhiyun tmp2 = 0x72;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun ret = ec100_write_reg(state, 0x1b, tmp);
123*4882a593Smuzhiyun if (ret)
124*4882a593Smuzhiyun goto error;
125*4882a593Smuzhiyun ret = ec100_write_reg(state, 0x1c, tmp2);
126*4882a593Smuzhiyun if (ret)
127*4882a593Smuzhiyun goto error;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun ret = ec100_write_reg(state, 0x0c, 0xbb); /* if freq */
130*4882a593Smuzhiyun if (ret)
131*4882a593Smuzhiyun goto error;
132*4882a593Smuzhiyun ret = ec100_write_reg(state, 0x0d, 0x31); /* if freq */
133*4882a593Smuzhiyun if (ret)
134*4882a593Smuzhiyun goto error;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun ret = ec100_write_reg(state, 0x08, 0x24);
137*4882a593Smuzhiyun if (ret)
138*4882a593Smuzhiyun goto error;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun ret = ec100_write_reg(state, 0x00, 0x00); /* go */
141*4882a593Smuzhiyun if (ret)
142*4882a593Smuzhiyun goto error;
143*4882a593Smuzhiyun ret = ec100_write_reg(state, 0x00, 0x20); /* go */
144*4882a593Smuzhiyun if (ret)
145*4882a593Smuzhiyun goto error;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return ret;
148*4882a593Smuzhiyun error:
149*4882a593Smuzhiyun dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
150*4882a593Smuzhiyun return ret;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
ec100_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * fesettings)153*4882a593Smuzhiyun static int ec100_get_tune_settings(struct dvb_frontend *fe,
154*4882a593Smuzhiyun struct dvb_frontend_tune_settings *fesettings)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun fesettings->min_delay_ms = 300;
157*4882a593Smuzhiyun fesettings->step_size = 0;
158*4882a593Smuzhiyun fesettings->max_drift = 0;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun return 0;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
ec100_read_status(struct dvb_frontend * fe,enum fe_status * status)163*4882a593Smuzhiyun static int ec100_read_status(struct dvb_frontend *fe, enum fe_status *status)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun struct ec100_state *state = fe->demodulator_priv;
166*4882a593Smuzhiyun int ret;
167*4882a593Smuzhiyun u8 tmp;
168*4882a593Smuzhiyun *status = 0;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun ret = ec100_read_reg(state, 0x42, &tmp);
171*4882a593Smuzhiyun if (ret)
172*4882a593Smuzhiyun goto error;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun if (tmp & 0x80) {
175*4882a593Smuzhiyun /* bit7 set - have lock */
176*4882a593Smuzhiyun *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
177*4882a593Smuzhiyun FE_HAS_SYNC | FE_HAS_LOCK;
178*4882a593Smuzhiyun } else {
179*4882a593Smuzhiyun ret = ec100_read_reg(state, 0x01, &tmp);
180*4882a593Smuzhiyun if (ret)
181*4882a593Smuzhiyun goto error;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun if (tmp & 0x10) {
184*4882a593Smuzhiyun /* bit4 set - have signal */
185*4882a593Smuzhiyun *status |= FE_HAS_SIGNAL;
186*4882a593Smuzhiyun if (!(tmp & 0x01)) {
187*4882a593Smuzhiyun /* bit0 clear - have ~valid signal */
188*4882a593Smuzhiyun *status |= FE_HAS_CARRIER | FE_HAS_VITERBI;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun error:
195*4882a593Smuzhiyun dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
196*4882a593Smuzhiyun return ret;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
ec100_read_ber(struct dvb_frontend * fe,u32 * ber)199*4882a593Smuzhiyun static int ec100_read_ber(struct dvb_frontend *fe, u32 *ber)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun struct ec100_state *state = fe->demodulator_priv;
202*4882a593Smuzhiyun int ret;
203*4882a593Smuzhiyun u8 tmp, tmp2;
204*4882a593Smuzhiyun u16 ber2;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun *ber = 0;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun ret = ec100_read_reg(state, 0x65, &tmp);
209*4882a593Smuzhiyun if (ret)
210*4882a593Smuzhiyun goto error;
211*4882a593Smuzhiyun ret = ec100_read_reg(state, 0x66, &tmp2);
212*4882a593Smuzhiyun if (ret)
213*4882a593Smuzhiyun goto error;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun ber2 = (tmp2 << 8) | tmp;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* if counter overflow or clear */
218*4882a593Smuzhiyun if (ber2 < state->ber)
219*4882a593Smuzhiyun *ber = ber2;
220*4882a593Smuzhiyun else
221*4882a593Smuzhiyun *ber = ber2 - state->ber;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun state->ber = ber2;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun return ret;
226*4882a593Smuzhiyun error:
227*4882a593Smuzhiyun dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
228*4882a593Smuzhiyun return ret;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
ec100_read_signal_strength(struct dvb_frontend * fe,u16 * strength)231*4882a593Smuzhiyun static int ec100_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun struct ec100_state *state = fe->demodulator_priv;
234*4882a593Smuzhiyun int ret;
235*4882a593Smuzhiyun u8 tmp;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun ret = ec100_read_reg(state, 0x24, &tmp);
238*4882a593Smuzhiyun if (ret) {
239*4882a593Smuzhiyun *strength = 0;
240*4882a593Smuzhiyun goto error;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun *strength = ((tmp << 8) | tmp);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun return ret;
246*4882a593Smuzhiyun error:
247*4882a593Smuzhiyun dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
248*4882a593Smuzhiyun return ret;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
ec100_read_snr(struct dvb_frontend * fe,u16 * snr)251*4882a593Smuzhiyun static int ec100_read_snr(struct dvb_frontend *fe, u16 *snr)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun *snr = 0;
254*4882a593Smuzhiyun return 0;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
ec100_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)257*4882a593Smuzhiyun static int ec100_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun *ucblocks = 0;
260*4882a593Smuzhiyun return 0;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
ec100_release(struct dvb_frontend * fe)263*4882a593Smuzhiyun static void ec100_release(struct dvb_frontend *fe)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun struct ec100_state *state = fe->demodulator_priv;
266*4882a593Smuzhiyun kfree(state);
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun static const struct dvb_frontend_ops ec100_ops;
270*4882a593Smuzhiyun
ec100_attach(const struct ec100_config * config,struct i2c_adapter * i2c)271*4882a593Smuzhiyun struct dvb_frontend *ec100_attach(const struct ec100_config *config,
272*4882a593Smuzhiyun struct i2c_adapter *i2c)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun int ret;
275*4882a593Smuzhiyun struct ec100_state *state = NULL;
276*4882a593Smuzhiyun u8 tmp;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun /* allocate memory for the internal state */
279*4882a593Smuzhiyun state = kzalloc(sizeof(struct ec100_state), GFP_KERNEL);
280*4882a593Smuzhiyun if (state == NULL)
281*4882a593Smuzhiyun goto error;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun /* setup the state */
284*4882a593Smuzhiyun state->i2c = i2c;
285*4882a593Smuzhiyun memcpy(&state->config, config, sizeof(struct ec100_config));
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun /* check if the demod is there */
288*4882a593Smuzhiyun ret = ec100_read_reg(state, 0x33, &tmp);
289*4882a593Smuzhiyun if (ret || tmp != 0x0b)
290*4882a593Smuzhiyun goto error;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun /* create dvb_frontend */
293*4882a593Smuzhiyun memcpy(&state->frontend.ops, &ec100_ops,
294*4882a593Smuzhiyun sizeof(struct dvb_frontend_ops));
295*4882a593Smuzhiyun state->frontend.demodulator_priv = state;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun return &state->frontend;
298*4882a593Smuzhiyun error:
299*4882a593Smuzhiyun kfree(state);
300*4882a593Smuzhiyun return NULL;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun EXPORT_SYMBOL(ec100_attach);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun static const struct dvb_frontend_ops ec100_ops = {
305*4882a593Smuzhiyun .delsys = { SYS_DVBT },
306*4882a593Smuzhiyun .info = {
307*4882a593Smuzhiyun .name = "E3C EC100 DVB-T",
308*4882a593Smuzhiyun .caps =
309*4882a593Smuzhiyun FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
310*4882a593Smuzhiyun FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
311*4882a593Smuzhiyun FE_CAN_QPSK | FE_CAN_QAM_16 |
312*4882a593Smuzhiyun FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
313*4882a593Smuzhiyun FE_CAN_TRANSMISSION_MODE_AUTO |
314*4882a593Smuzhiyun FE_CAN_GUARD_INTERVAL_AUTO |
315*4882a593Smuzhiyun FE_CAN_HIERARCHY_AUTO |
316*4882a593Smuzhiyun FE_CAN_MUTE_TS
317*4882a593Smuzhiyun },
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun .release = ec100_release,
320*4882a593Smuzhiyun .set_frontend = ec100_set_frontend,
321*4882a593Smuzhiyun .get_tune_settings = ec100_get_tune_settings,
322*4882a593Smuzhiyun .read_status = ec100_read_status,
323*4882a593Smuzhiyun .read_ber = ec100_read_ber,
324*4882a593Smuzhiyun .read_signal_strength = ec100_read_signal_strength,
325*4882a593Smuzhiyun .read_snr = ec100_read_snr,
326*4882a593Smuzhiyun .read_ucblocks = ec100_read_ucblocks,
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
330*4882a593Smuzhiyun MODULE_DESCRIPTION("E3C EC100 DVB-T demodulator driver");
331*4882a593Smuzhiyun MODULE_LICENSE("GPL");
332