1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #define AUD_COMM_EXEC__A 0x1000000 3*4882a593Smuzhiyun #define AUD_COMM_EXEC_STOP 0x0 4*4882a593Smuzhiyun #define FEC_COMM_EXEC__A 0x1C00000 5*4882a593Smuzhiyun #define FEC_COMM_EXEC_STOP 0x0 6*4882a593Smuzhiyun #define FEC_COMM_EXEC_ACTIVE 0x1 7*4882a593Smuzhiyun #define FEC_DI_COMM_EXEC__A 0x1C20000 8*4882a593Smuzhiyun #define FEC_DI_COMM_EXEC_STOP 0x0 9*4882a593Smuzhiyun #define FEC_DI_INPUT_CTL__A 0x1C20016 10*4882a593Smuzhiyun #define FEC_RS_COMM_EXEC__A 0x1C30000 11*4882a593Smuzhiyun #define FEC_RS_COMM_EXEC_STOP 0x0 12*4882a593Smuzhiyun #define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 13*4882a593Smuzhiyun #define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 14*4882a593Smuzhiyun #define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 15*4882a593Smuzhiyun #define FEC_OC_MODE__A 0x1C40011 16*4882a593Smuzhiyun #define FEC_OC_MODE_PARITY__M 0x1 17*4882a593Smuzhiyun #define FEC_OC_DTO_MODE__A 0x1C40014 18*4882a593Smuzhiyun #define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 19*4882a593Smuzhiyun #define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 20*4882a593Smuzhiyun #define FEC_OC_DTO_PERIOD__A 0x1C40015 21*4882a593Smuzhiyun #define FEC_OC_DTO_BURST_LEN__A 0x1C40018 22*4882a593Smuzhiyun #define FEC_OC_FCT_MODE__A 0x1C4001A 23*4882a593Smuzhiyun #define FEC_OC_FCT_MODE__PRE 0x0 24*4882a593Smuzhiyun #define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 25*4882a593Smuzhiyun #define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 26*4882a593Smuzhiyun #define FEC_OC_TMD_MODE__A 0x1C4001E 27*4882a593Smuzhiyun #define FEC_OC_TMD_COUNT__A 0x1C4001F 28*4882a593Smuzhiyun #define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 29*4882a593Smuzhiyun #define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 30*4882a593Smuzhiyun #define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 31*4882a593Smuzhiyun #define FEC_OC_AVR_PARM_A__A 0x1C40026 32*4882a593Smuzhiyun #define FEC_OC_AVR_PARM_B__A 0x1C40027 33*4882a593Smuzhiyun #define FEC_OC_RCN_GAIN__A 0x1C4002E 34*4882a593Smuzhiyun #define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 35*4882a593Smuzhiyun #define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 36*4882a593Smuzhiyun #define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 37*4882a593Smuzhiyun #define FEC_OC_SNC_MODE__A 0x1C40040 38*4882a593Smuzhiyun #define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 39*4882a593Smuzhiyun #define FEC_OC_SNC_LWM__A 0x1C40041 40*4882a593Smuzhiyun #define FEC_OC_SNC_HWM__A 0x1C40042 41*4882a593Smuzhiyun #define FEC_OC_SNC_UNLOCK__A 0x1C40043 42*4882a593Smuzhiyun #define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 43*4882a593Smuzhiyun #define FEC_OC_IPR_MODE__A 0x1C40048 44*4882a593Smuzhiyun #define FEC_OC_IPR_MODE_SERIAL__M 0x1 45*4882a593Smuzhiyun #define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 46*4882a593Smuzhiyun #define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 47*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT__A 0x1C40049 48*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MD0__M 0x1 49*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MD1__M 0x2 50*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MD2__M 0x4 51*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MD3__M 0x8 52*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MD4__M 0x10 53*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MD5__M 0x20 54*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MD6__M 0x40 55*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MD7__M 0x80 56*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MERR__M 0x100 57*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MSTRT__M 0x200 58*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MVAL__M 0x400 59*4882a593Smuzhiyun #define FEC_OC_IPR_INVERT_MCLK__M 0x800 60*4882a593Smuzhiyun #define FEC_OC_OCR_INVERT__A 0x1C40052 61*4882a593Smuzhiyun #define IQM_COMM_EXEC__A 0x1800000 62*4882a593Smuzhiyun #define IQM_COMM_EXEC_B_STOP 0x0 63*4882a593Smuzhiyun #define IQM_COMM_EXEC_B_ACTIVE 0x1 64*4882a593Smuzhiyun #define IQM_FS_RATE_OFS_LO__A 0x1820010 65*4882a593Smuzhiyun #define IQM_FS_ADJ_SEL__A 0x1820014 66*4882a593Smuzhiyun #define IQM_FS_ADJ_SEL_B_OFF 0x0 67*4882a593Smuzhiyun #define IQM_FS_ADJ_SEL_B_QAM 0x1 68*4882a593Smuzhiyun #define IQM_FS_ADJ_SEL_B_VSB 0x2 69*4882a593Smuzhiyun #define IQM_FD_RATESEL__A 0x1830010 70*4882a593Smuzhiyun #define IQM_RC_RATE_OFS_LO__A 0x1840010 71*4882a593Smuzhiyun #define IQM_RC_RATE_OFS_LO__W 16 72*4882a593Smuzhiyun #define IQM_RC_RATE_OFS_LO__M 0xFFFF 73*4882a593Smuzhiyun #define IQM_RC_RATE_OFS_HI__M 0xFF 74*4882a593Smuzhiyun #define IQM_RC_ADJ_SEL__A 0x1840014 75*4882a593Smuzhiyun #define IQM_RC_ADJ_SEL_B_OFF 0x0 76*4882a593Smuzhiyun #define IQM_RC_ADJ_SEL_B_QAM 0x1 77*4882a593Smuzhiyun #define IQM_RC_ADJ_SEL_B_VSB 0x2 78*4882a593Smuzhiyun #define IQM_RC_STRETCH__A 0x1840016 79*4882a593Smuzhiyun #define IQM_CF_COMM_INT_MSK__A 0x1860006 80*4882a593Smuzhiyun #define IQM_CF_SYMMETRIC__A 0x1860010 81*4882a593Smuzhiyun #define IQM_CF_MIDTAP__A 0x1860011 82*4882a593Smuzhiyun #define IQM_CF_MIDTAP_RE__B 0 83*4882a593Smuzhiyun #define IQM_CF_MIDTAP_IM__B 1 84*4882a593Smuzhiyun #define IQM_CF_OUT_ENA__A 0x1860012 85*4882a593Smuzhiyun #define IQM_CF_OUT_ENA_QAM__B 1 86*4882a593Smuzhiyun #define IQM_CF_OUT_ENA_OFDM__M 0x4 87*4882a593Smuzhiyun #define IQM_CF_ADJ_SEL__A 0x1860013 88*4882a593Smuzhiyun #define IQM_CF_SCALE__A 0x1860014 89*4882a593Smuzhiyun #define IQM_CF_SCALE_SH__A 0x1860015 90*4882a593Smuzhiyun #define IQM_CF_SCALE_SH__PRE 0x0 91*4882a593Smuzhiyun #define IQM_CF_POW_MEAS_LEN__A 0x1860017 92*4882a593Smuzhiyun #define IQM_CF_DS_ENA__A 0x1860019 93*4882a593Smuzhiyun #define IQM_CF_TAP_RE0__A 0x1860020 94*4882a593Smuzhiyun #define IQM_CF_TAP_IM0__A 0x1860040 95*4882a593Smuzhiyun #define IQM_CF_CLP_VAL__A 0x1860060 96*4882a593Smuzhiyun #define IQM_CF_DATATH__A 0x1860061 97*4882a593Smuzhiyun #define IQM_CF_PKDTH__A 0x1860062 98*4882a593Smuzhiyun #define IQM_CF_WND_LEN__A 0x1860063 99*4882a593Smuzhiyun #define IQM_CF_DET_LCT__A 0x1860064 100*4882a593Smuzhiyun #define IQM_CF_BYPASSDET__A 0x1860067 101*4882a593Smuzhiyun #define IQM_AF_COMM_EXEC__A 0x1870000 102*4882a593Smuzhiyun #define IQM_AF_COMM_EXEC_ACTIVE 0x1 103*4882a593Smuzhiyun #define IQM_AF_CLKNEG__A 0x1870012 104*4882a593Smuzhiyun #define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 105*4882a593Smuzhiyun #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 106*4882a593Smuzhiyun #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 107*4882a593Smuzhiyun #define IQM_AF_START_LOCK__A 0x187001B 108*4882a593Smuzhiyun #define IQM_AF_PHASE0__A 0x187001C 109*4882a593Smuzhiyun #define IQM_AF_PHASE1__A 0x187001D 110*4882a593Smuzhiyun #define IQM_AF_PHASE2__A 0x187001E 111*4882a593Smuzhiyun #define IQM_AF_CLP_LEN__A 0x1870023 112*4882a593Smuzhiyun #define IQM_AF_CLP_TH__A 0x1870024 113*4882a593Smuzhiyun #define IQM_AF_SNS_LEN__A 0x1870026 114*4882a593Smuzhiyun #define IQM_AF_AGC_IF__A 0x1870028 115*4882a593Smuzhiyun #define IQM_AF_AGC_RF__A 0x1870029 116*4882a593Smuzhiyun #define IQM_AF_PDREF__A 0x187002B 117*4882a593Smuzhiyun #define IQM_AF_PDREF__M 0x1F 118*4882a593Smuzhiyun #define IQM_AF_STDBY__A 0x187002C 119*4882a593Smuzhiyun #define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 120*4882a593Smuzhiyun #define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 121*4882a593Smuzhiyun #define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 122*4882a593Smuzhiyun #define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 123*4882a593Smuzhiyun #define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 124*4882a593Smuzhiyun #define IQM_AF_AMUX__A 0x187002D 125*4882a593Smuzhiyun #define IQM_AF_AMUX_SIGNAL2ADC 0x1 126*4882a593Smuzhiyun #define IQM_AF_UPD_SEL__A 0x187002F 127*4882a593Smuzhiyun #define IQM_AF_INC_LCT__A 0x1870034 128*4882a593Smuzhiyun #define IQM_AF_INC_BYPASS__A 0x1870036 129*4882a593Smuzhiyun #define OFDM_CP_COMM_EXEC__A 0x2800000 130*4882a593Smuzhiyun #define OFDM_CP_COMM_EXEC_STOP 0x0 131*4882a593Smuzhiyun #define OFDM_EC_SB_PRIOR__A 0x3410013 132*4882a593Smuzhiyun #define OFDM_EC_SB_PRIOR_HI 0x0 133*4882a593Smuzhiyun #define OFDM_EC_SB_PRIOR_LO 0x1 134*4882a593Smuzhiyun #define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 135*4882a593Smuzhiyun #define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 136*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 137*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 138*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 139*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 140*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 141*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 142*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E 143*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F 144*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 145*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 146*4882a593Smuzhiyun #define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 147*4882a593Smuzhiyun #define OFDM_LC_COMM_EXEC__A 0x3800000 148*4882a593Smuzhiyun #define OFDM_LC_COMM_EXEC_STOP 0x0 149*4882a593Smuzhiyun #define OFDM_SC_COMM_EXEC__A 0x3C00000 150*4882a593Smuzhiyun #define OFDM_SC_COMM_EXEC_STOP 0x0 151*4882a593Smuzhiyun #define OFDM_SC_COMM_STATE__A 0x3C00001 152*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 153*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 154*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 155*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CMD__A 0x3C20043 156*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CMD_NULL 0x0 157*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 158*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 159*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 160*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 161*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 162*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 163*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 164*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 165*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 166*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 167*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 168*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 169*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 170*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 171*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 172*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 173*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC 174*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 175*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 176*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 177*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 178*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 179*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 180*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 181*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 182*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 183*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 184*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 185*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 186*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 187*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 188*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 189*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 190*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 191*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 192*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 193*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B 194*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 195*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 196*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 197*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 198*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D 199*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E 200*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F 201*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 202*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF 203*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 204*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 205*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 206*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 207*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D 208*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 209*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 210*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 211*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 212*4882a593Smuzhiyun #define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 213*4882a593Smuzhiyun #define QAM_COMM_EXEC__A 0x1400000 214*4882a593Smuzhiyun #define QAM_COMM_EXEC_STOP 0x0 215*4882a593Smuzhiyun #define QAM_COMM_EXEC_ACTIVE 0x1 216*4882a593Smuzhiyun #define QAM_TOP_ANNEX_A 0x0 217*4882a593Smuzhiyun #define QAM_TOP_ANNEX_C 0x2 218*4882a593Smuzhiyun #define QAM_SL_ERR_POWER__A 0x1430017 219*4882a593Smuzhiyun #define QAM_DQ_QUAL_FUN0__A 0x1440018 220*4882a593Smuzhiyun #define QAM_DQ_QUAL_FUN1__A 0x1440019 221*4882a593Smuzhiyun #define QAM_DQ_QUAL_FUN2__A 0x144001A 222*4882a593Smuzhiyun #define QAM_DQ_QUAL_FUN3__A 0x144001B 223*4882a593Smuzhiyun #define QAM_DQ_QUAL_FUN4__A 0x144001C 224*4882a593Smuzhiyun #define QAM_DQ_QUAL_FUN5__A 0x144001D 225*4882a593Smuzhiyun #define QAM_LC_MODE__A 0x1450010 226*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB0__A 0x1450018 227*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB1__A 0x1450019 228*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB2__A 0x145001A 229*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB3__A 0x145001B 230*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB4__A 0x145001C 231*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB5__A 0x145001D 232*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB6__A 0x145001E 233*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB8__A 0x145001F 234*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB9__A 0x1450020 235*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB10__A 0x1450021 236*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB12__A 0x1450022 237*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB15__A 0x1450023 238*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB16__A 0x1450024 239*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB20__A 0x1450025 240*4882a593Smuzhiyun #define QAM_LC_QUAL_TAB25__A 0x1450026 241*4882a593Smuzhiyun #define QAM_LC_LPF_FACTORP__A 0x1450028 242*4882a593Smuzhiyun #define QAM_LC_LPF_FACTORI__A 0x1450029 243*4882a593Smuzhiyun #define QAM_LC_RATE_LIMIT__A 0x145002A 244*4882a593Smuzhiyun #define QAM_LC_SYMBOL_FREQ__A 0x145002B 245*4882a593Smuzhiyun #define QAM_SY_TIMEOUT__A 0x1470011 246*4882a593Smuzhiyun #define QAM_SY_TIMEOUT__PRE 0x3A98 247*4882a593Smuzhiyun #define QAM_SY_SYNC_LWM__A 0x1470012 248*4882a593Smuzhiyun #define QAM_SY_SYNC_AWM__A 0x1470013 249*4882a593Smuzhiyun #define QAM_SY_SYNC_HWM__A 0x1470014 250*4882a593Smuzhiyun #define QAM_SY_SP_INV__A 0x1470017 251*4882a593Smuzhiyun #define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 252*4882a593Smuzhiyun #define SCU_COMM_EXEC__A 0x800000 253*4882a593Smuzhiyun #define SCU_COMM_EXEC_STOP 0x0 254*4882a593Smuzhiyun #define SCU_COMM_EXEC_ACTIVE 0x1 255*4882a593Smuzhiyun #define SCU_COMM_EXEC_HOLD 0x2 256*4882a593Smuzhiyun #define SCU_RAM_DRIVER_DEBUG__A 0x831EBF 257*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 258*4882a593Smuzhiyun #define SCU_RAM_GPIO__A 0x831EC7 259*4882a593Smuzhiyun #define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 260*4882a593Smuzhiyun #define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 261*4882a593Smuzhiyun #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB 262*4882a593Smuzhiyun #define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 263*4882a593Smuzhiyun #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 264*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 265*4882a593Smuzhiyun #define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 266*4882a593Smuzhiyun #define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 267*4882a593Smuzhiyun #define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A 268*4882a593Smuzhiyun #define SCU_RAM_AGC_RF_MAX__A 0x831F1B 269*4882a593Smuzhiyun #define SCU_RAM_AGC_CONFIG__A 0x831F24 270*4882a593Smuzhiyun #define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 271*4882a593Smuzhiyun #define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 272*4882a593Smuzhiyun #define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 273*4882a593Smuzhiyun #define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 274*4882a593Smuzhiyun #define SCU_RAM_AGC_KI__A 0x831F25 275*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_RF__B 4 276*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_RF__M 0xF0 277*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_IF__B 8 278*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_IF__M 0xF00 279*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_RED__A 0x831F26 280*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 281*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC 282*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 283*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 284*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 285*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 286*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 287*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A 288*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_MIN__A 0x831F2B 289*4882a593Smuzhiyun #define SCU_RAM_AGC_KI_MAX__A 0x831F2C 290*4882a593Smuzhiyun #define SCU_RAM_AGC_CLP_SUM__A 0x831F2D 291*4882a593Smuzhiyun #define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E 292*4882a593Smuzhiyun #define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F 293*4882a593Smuzhiyun #define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 294*4882a593Smuzhiyun #define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 295*4882a593Smuzhiyun #define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 296*4882a593Smuzhiyun #define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 297*4882a593Smuzhiyun #define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 298*4882a593Smuzhiyun #define SCU_RAM_AGC_SNS_SUM__A 0x831F35 299*4882a593Smuzhiyun #define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 300*4882a593Smuzhiyun #define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 301*4882a593Smuzhiyun #define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 302*4882a593Smuzhiyun #define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 303*4882a593Smuzhiyun #define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A 304*4882a593Smuzhiyun #define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B 305*4882a593Smuzhiyun #define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D 306*4882a593Smuzhiyun #define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E 307*4882a593Smuzhiyun #define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F 308*4882a593Smuzhiyun #define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 309*4882a593Smuzhiyun #define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 310*4882a593Smuzhiyun #define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 311*4882a593Smuzhiyun #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 312*4882a593Smuzhiyun #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 313*4882a593Smuzhiyun #define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 314*4882a593Smuzhiyun #define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 315*4882a593Smuzhiyun #define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 316*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 317*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 318*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 319*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 320*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 321*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 322*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A 323*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_RTH__A 0x831F8E 324*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_FTH__A 0x831F8F 325*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_PTH__A 0x831F90 326*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_MTH__A 0x831F91 327*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_CTH__A 0x831F92 328*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_QTH__A 0x831F93 329*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 330*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 331*4882a593Smuzhiyun #define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 332*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 333*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 334*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A 335*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B 336*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C 337*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D 338*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E 339*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F 340*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 341*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 342*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 343*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 344*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 345*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 346*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 347*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 348*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 349*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 350*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA 351*4882a593Smuzhiyun #define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB 352*4882a593Smuzhiyun #define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC 353*4882a593Smuzhiyun #define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD 354*4882a593Smuzhiyun #define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE 355*4882a593Smuzhiyun #define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF 356*4882a593Smuzhiyun #define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 357*4882a593Smuzhiyun #define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 358*4882a593Smuzhiyun #define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 359*4882a593Smuzhiyun #define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 360*4882a593Smuzhiyun #define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 361*4882a593Smuzhiyun #define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 362*4882a593Smuzhiyun #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA 363*4882a593Smuzhiyun #define SCU_RAM_DRIVER_VER_HI__A 0x831FEB 364*4882a593Smuzhiyun #define SCU_RAM_DRIVER_VER_LO__A 0x831FEC 365*4882a593Smuzhiyun #define SCU_RAM_PARAM_15__A 0x831FED 366*4882a593Smuzhiyun #define SCU_RAM_PARAM_0__A 0x831FFC 367*4882a593Smuzhiyun #define SCU_RAM_COMMAND__A 0x831FFD 368*4882a593Smuzhiyun #define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 369*4882a593Smuzhiyun #define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 370*4882a593Smuzhiyun #define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 371*4882a593Smuzhiyun #define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 372*4882a593Smuzhiyun #define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 373*4882a593Smuzhiyun #define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 374*4882a593Smuzhiyun #define SCU_RAM_COMMAND_STANDARD_QAM 0x200 375*4882a593Smuzhiyun #define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 376*4882a593Smuzhiyun #define SIO_TOP_COMM_KEY__A 0x41000F 377*4882a593Smuzhiyun #define SIO_TOP_COMM_KEY_KEY 0xFABA 378*4882a593Smuzhiyun #define SIO_TOP_JTAGID_LO__A 0x410012 379*4882a593Smuzhiyun #define SIO_HI_RA_RAM_RES__A 0x420031 380*4882a593Smuzhiyun #define SIO_HI_RA_RAM_CMD__A 0x420032 381*4882a593Smuzhiyun #define SIO_HI_RA_RAM_CMD_RESET 0x2 382*4882a593Smuzhiyun #define SIO_HI_RA_RAM_CMD_CONFIG 0x3 383*4882a593Smuzhiyun #define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 384*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_1__A 0x420033 385*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 386*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_2__A 0x420034 387*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F 388*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 389*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 390*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_3__A 0x420035 391*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F 392*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 393*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 394*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 395*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_4__A 0x420036 396*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_5__A 0x420037 397*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 398*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 399*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 400*4882a593Smuzhiyun #define SIO_HI_RA_RAM_PAR_6__A 0x420038 401*4882a593Smuzhiyun #define SIO_CC_PLL_LOCK__A 0x450012 402*4882a593Smuzhiyun #define SIO_CC_PWD_MODE__A 0x450015 403*4882a593Smuzhiyun #define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 404*4882a593Smuzhiyun #define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 405*4882a593Smuzhiyun #define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 406*4882a593Smuzhiyun #define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 407*4882a593Smuzhiyun #define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 408*4882a593Smuzhiyun #define SIO_CC_SOFT_RST__A 0x450016 409*4882a593Smuzhiyun #define SIO_CC_SOFT_RST_OFDM__M 0x1 410*4882a593Smuzhiyun #define SIO_CC_SOFT_RST_SYS__M 0x2 411*4882a593Smuzhiyun #define SIO_CC_SOFT_RST_OSC__M 0x4 412*4882a593Smuzhiyun #define SIO_CC_UPDATE__A 0x450017 413*4882a593Smuzhiyun #define SIO_CC_UPDATE_KEY 0xFABA 414*4882a593Smuzhiyun #define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 415*4882a593Smuzhiyun #define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 416*4882a593Smuzhiyun #define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 417*4882a593Smuzhiyun #define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 418*4882a593Smuzhiyun #define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 419*4882a593Smuzhiyun #define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 420*4882a593Smuzhiyun #define SIO_BL_COMM_EXEC__A 0x480000 421*4882a593Smuzhiyun #define SIO_BL_COMM_EXEC_ACTIVE 0x1 422*4882a593Smuzhiyun #define SIO_BL_STATUS__A 0x480010 423*4882a593Smuzhiyun #define SIO_BL_MODE__A 0x480011 424*4882a593Smuzhiyun #define SIO_BL_MODE_DIRECT 0x0 425*4882a593Smuzhiyun #define SIO_BL_MODE_CHAIN 0x1 426*4882a593Smuzhiyun #define SIO_BL_ENABLE__A 0x480012 427*4882a593Smuzhiyun #define SIO_BL_ENABLE_ON 0x1 428*4882a593Smuzhiyun #define SIO_BL_TGT_HDR__A 0x480014 429*4882a593Smuzhiyun #define SIO_BL_TGT_ADDR__A 0x480015 430*4882a593Smuzhiyun #define SIO_BL_SRC_ADDR__A 0x480016 431*4882a593Smuzhiyun #define SIO_BL_SRC_LEN__A 0x480017 432*4882a593Smuzhiyun #define SIO_BL_CHAIN_ADDR__A 0x480018 433*4882a593Smuzhiyun #define SIO_BL_CHAIN_LEN__A 0x480019 434*4882a593Smuzhiyun #define SIO_PDR_MON_CFG__A 0x7F0010 435*4882a593Smuzhiyun #define SIO_PDR_UIO_IN_HI__A 0x7F0015 436*4882a593Smuzhiyun #define SIO_PDR_UIO_OUT_LO__A 0x7F0016 437*4882a593Smuzhiyun #define SIO_PDR_OHW_CFG__A 0x7F001F 438*4882a593Smuzhiyun #define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 439*4882a593Smuzhiyun #define SIO_PDR_GPIO_CFG__A 0x7F0021 440*4882a593Smuzhiyun #define SIO_PDR_MSTRT_CFG__A 0x7F0025 441*4882a593Smuzhiyun #define SIO_PDR_MERR_CFG__A 0x7F0026 442*4882a593Smuzhiyun #define SIO_PDR_MCLK_CFG__A 0x7F0028 443*4882a593Smuzhiyun #define SIO_PDR_MCLK_CFG_DRIVE__B 3 444*4882a593Smuzhiyun #define SIO_PDR_MVAL_CFG__A 0x7F0029 445*4882a593Smuzhiyun #define SIO_PDR_MD0_CFG__A 0x7F002A 446*4882a593Smuzhiyun #define SIO_PDR_MD0_CFG_DRIVE__B 3 447*4882a593Smuzhiyun #define SIO_PDR_MD1_CFG__A 0x7F002B 448*4882a593Smuzhiyun #define SIO_PDR_MD2_CFG__A 0x7F002C 449*4882a593Smuzhiyun #define SIO_PDR_MD3_CFG__A 0x7F002D 450*4882a593Smuzhiyun #define SIO_PDR_MD4_CFG__A 0x7F002F 451*4882a593Smuzhiyun #define SIO_PDR_MD5_CFG__A 0x7F0030 452*4882a593Smuzhiyun #define SIO_PDR_MD6_CFG__A 0x7F0031 453*4882a593Smuzhiyun #define SIO_PDR_MD7_CFG__A 0x7F0032 454*4882a593Smuzhiyun #define SIO_PDR_SMA_RX_CFG__A 0x7F0037 455*4882a593Smuzhiyun #define SIO_PDR_SMA_TX_CFG__A 0x7F0038 456