1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * drx3973d_map_firm.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2006-2007 Micronas 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DRX3973D_MAP__H__ 9*4882a593Smuzhiyun #define __DRX3973D_MAP__H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Note: originally, this file contained 12000+ lines of data 13*4882a593Smuzhiyun * Probably a few lines for every firwmare assembler instruction. However, 14*4882a593Smuzhiyun * only a few defines were actually used. So, removed all uneeded lines. 15*4882a593Smuzhiyun * If ever needed, the other lines can be easily obtained via git history. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define HI_COMM_EXEC__A 0x400000 19*4882a593Smuzhiyun #define HI_COMM_MB__A 0x400002 20*4882a593Smuzhiyun #define HI_CT_REG_COMM_STATE__A 0x410001 21*4882a593Smuzhiyun #define HI_RA_RAM_SRV_RES__A 0x420031 22*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CMD__A 0x420032 23*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CMD_RESET 0x2 24*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CMD_CONFIG 0x3 25*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 26*4882a593Smuzhiyun #define HI_RA_RAM_SRV_RST_KEY__A 0x420033 27*4882a593Smuzhiyun #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 28*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 29*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 30*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 31*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 32*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 33*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 34*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 35*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 36*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 37*4882a593Smuzhiyun #define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 38*4882a593Smuzhiyun #define HI_RA_RAM_USR_BEGIN__A 0x420040 39*4882a593Smuzhiyun #define HI_IF_RAM_TRP_BPT0__AX 0x430000 40*4882a593Smuzhiyun #define HI_IF_RAM_USR_BEGIN__A 0x430200 41*4882a593Smuzhiyun #define SC_COMM_EXEC__A 0x800000 42*4882a593Smuzhiyun #define SC_COMM_EXEC_CTL_STOP 0x0 43*4882a593Smuzhiyun #define SC_COMM_STATE__A 0x800001 44*4882a593Smuzhiyun #define SC_RA_RAM_PARAM0__A 0x820040 45*4882a593Smuzhiyun #define SC_RA_RAM_PARAM1__A 0x820041 46*4882a593Smuzhiyun #define SC_RA_RAM_CMD_ADDR__A 0x820042 47*4882a593Smuzhiyun #define SC_RA_RAM_CMD__A 0x820043 48*4882a593Smuzhiyun #define SC_RA_RAM_CMD_PROC_START 0x1 49*4882a593Smuzhiyun #define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 50*4882a593Smuzhiyun #define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 51*4882a593Smuzhiyun #define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 52*4882a593Smuzhiyun #define SC_RA_RAM_LOCKTRACK_MIN 0x1 53*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 54*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 55*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 56*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 57*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 58*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_GUARD_4 0xC 59*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 60*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 61*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 62*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 63*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 64*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 65*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 66*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 67*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 68*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 69*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 70*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 71*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 72*4882a593Smuzhiyun #define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 73*4882a593Smuzhiyun #define SC_RA_RAM_OP_AUTO_MODE__M 0x1 74*4882a593Smuzhiyun #define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 75*4882a593Smuzhiyun #define SC_RA_RAM_OP_AUTO_CONST__M 0x4 76*4882a593Smuzhiyun #define SC_RA_RAM_OP_AUTO_HIER__M 0x8 77*4882a593Smuzhiyun #define SC_RA_RAM_OP_AUTO_RATE__M 0x10 78*4882a593Smuzhiyun #define SC_RA_RAM_LOCK__A 0x82004B 79*4882a593Smuzhiyun #define SC_RA_RAM_LOCK_DEMOD__M 0x1 80*4882a593Smuzhiyun #define SC_RA_RAM_LOCK_FEC__M 0x2 81*4882a593Smuzhiyun #define SC_RA_RAM_LOCK_MPEG__M 0x4 82*4882a593Smuzhiyun #define SC_RA_RAM_BE_OPT_ENA__A 0x82004C 83*4882a593Smuzhiyun #define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 84*4882a593Smuzhiyun #define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D 85*4882a593Smuzhiyun #define SC_RA_RAM_CONFIG__A 0x820050 86*4882a593Smuzhiyun #define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 87*4882a593Smuzhiyun #define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 88*4882a593Smuzhiyun #define SC_RA_RAM_CONFIG_SLAVE__M 0x20 89*4882a593Smuzhiyun #define SC_RA_RAM_IF_SAVE__AX 0x82008E 90*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 91*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 92*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 93*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 94*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 95*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 96*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 97*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 98*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 99*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 100*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 101*4882a593Smuzhiyun #define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 102*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 103*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 104*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 105*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 106*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 107*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 108*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA 109*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB 110*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB 111*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 112*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC 113*4882a593Smuzhiyun #define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 114*4882a593Smuzhiyun #define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD 115*4882a593Smuzhiyun #define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 116*4882a593Smuzhiyun #define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 117*4882a593Smuzhiyun #define SC_RA_RAM_BAND__A 0x8200EC 118*4882a593Smuzhiyun #define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 119*4882a593Smuzhiyun #define SC_RA_RAM_LC_ABS_2K__PRE 0x1F 120*4882a593Smuzhiyun #define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 121*4882a593Smuzhiyun #define SC_RA_RAM_LC_ABS_8K__PRE 0x1F 122*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 123*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 124*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB 125*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 126*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF 127*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 128*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E 129*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 130*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A 131*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 132*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB 133*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 134*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F 135*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 136*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 137*4882a593Smuzhiyun #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 138*4882a593Smuzhiyun #define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE 139*4882a593Smuzhiyun #define SC_RA_RAM_PROC_LOCKTRACK 0x0 140*4882a593Smuzhiyun #define FE_COMM_EXEC__A 0xC00000 141*4882a593Smuzhiyun #define FE_AD_REG_COMM_EXEC__A 0xC10000 142*4882a593Smuzhiyun #define FE_AD_REG_FDB_IN__A 0xC10012 143*4882a593Smuzhiyun #define FE_AD_REG_PD__A 0xC10013 144*4882a593Smuzhiyun #define FE_AD_REG_INVEXT__A 0xC10014 145*4882a593Smuzhiyun #define FE_AD_REG_CLKNEG__A 0xC10015 146*4882a593Smuzhiyun #define FE_AG_REG_COMM_EXEC__A 0xC20000 147*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP__A 0xC20010 148*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 149*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 150*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 151*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 152*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 153*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 154*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 155*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 156*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 157*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 158*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 159*4882a593Smuzhiyun #define FE_AG_REG_AG_MODE_HIP__A 0xC20011 160*4882a593Smuzhiyun #define FE_AG_REG_AG_PGA_MODE__A 0xC20012 161*4882a593Smuzhiyun #define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 162*4882a593Smuzhiyun #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 163*4882a593Smuzhiyun #define FE_AG_REG_AG_AGC_SIO__A 0xC20013 164*4882a593Smuzhiyun #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 165*4882a593Smuzhiyun #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 166*4882a593Smuzhiyun #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 167*4882a593Smuzhiyun #define FE_AG_REG_AG_PWD__A 0xC20015 168*4882a593Smuzhiyun #define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 169*4882a593Smuzhiyun #define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 170*4882a593Smuzhiyun #define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 171*4882a593Smuzhiyun #define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 172*4882a593Smuzhiyun #define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 173*4882a593Smuzhiyun #define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A 174*4882a593Smuzhiyun #define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B 175*4882a593Smuzhiyun #define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 176*4882a593Smuzhiyun #define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 177*4882a593Smuzhiyun #define FE_AG_REG_EGC_SET_LVL__A 0xC20025 178*4882a593Smuzhiyun #define FE_AG_REG_EGC_SET_LVL__M 0x1FF 179*4882a593Smuzhiyun #define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 180*4882a593Smuzhiyun #define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 181*4882a593Smuzhiyun #define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 182*4882a593Smuzhiyun #define FE_AG_REG_EGC_FLA_INC__A 0xC20029 183*4882a593Smuzhiyun #define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A 184*4882a593Smuzhiyun #define FE_AG_REG_EGC_SLO_INC__A 0xC2002B 185*4882a593Smuzhiyun #define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C 186*4882a593Smuzhiyun #define FE_AG_REG_EGC_FAS_INC__A 0xC2002D 187*4882a593Smuzhiyun #define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E 188*4882a593Smuzhiyun #define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 189*4882a593Smuzhiyun #define FE_AG_REG_PM1_AGC_WRI__M 0x7FF 190*4882a593Smuzhiyun #define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 191*4882a593Smuzhiyun #define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 192*4882a593Smuzhiyun #define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 193*4882a593Smuzhiyun #define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 194*4882a593Smuzhiyun #define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 195*4882a593Smuzhiyun #define FE_AG_REG_GC1_AGC_DAT__M 0x3FF 196*4882a593Smuzhiyun #define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 197*4882a593Smuzhiyun #define FE_AG_REG_IND_WIN__A 0xC2003C 198*4882a593Smuzhiyun #define FE_AG_REG_IND_THD_LOL__A 0xC2003D 199*4882a593Smuzhiyun #define FE_AG_REG_IND_THD_HIL__A 0xC2003E 200*4882a593Smuzhiyun #define FE_AG_REG_IND_DEL__A 0xC2003F 201*4882a593Smuzhiyun #define FE_AG_REG_IND_PD1_WRI__A 0xC20040 202*4882a593Smuzhiyun #define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 203*4882a593Smuzhiyun #define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 204*4882a593Smuzhiyun #define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 205*4882a593Smuzhiyun #define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 206*4882a593Smuzhiyun #define FE_AG_REG_PDC_SET_LVL__A 0xC20045 207*4882a593Smuzhiyun #define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 208*4882a593Smuzhiyun #define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 209*4882a593Smuzhiyun #define FE_AG_REG_PDC_FLA_STP__A 0xC20048 210*4882a593Smuzhiyun #define FE_AG_REG_PDC_SLO_STP__A 0xC20049 211*4882a593Smuzhiyun #define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A 212*4882a593Smuzhiyun #define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B 213*4882a593Smuzhiyun #define FE_AG_REG_PDC_MAX__A 0xC2004C 214*4882a593Smuzhiyun #define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D 215*4882a593Smuzhiyun #define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E 216*4882a593Smuzhiyun #define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F 217*4882a593Smuzhiyun #define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 218*4882a593Smuzhiyun #define FE_AG_REG_TGC_SET_LVL__A 0xC20051 219*4882a593Smuzhiyun #define FE_AG_REG_TGC_SET_LVL__M 0x3F 220*4882a593Smuzhiyun #define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 221*4882a593Smuzhiyun #define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 222*4882a593Smuzhiyun #define FE_AG_REG_TGC_FLA_STP__A 0xC20054 223*4882a593Smuzhiyun #define FE_AG_REG_TGC_SLO_STP__A 0xC20055 224*4882a593Smuzhiyun #define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 225*4882a593Smuzhiyun #define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 226*4882a593Smuzhiyun #define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 227*4882a593Smuzhiyun #define FE_AG_REG_FGM_WRI__A 0xC20061 228*4882a593Smuzhiyun #define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 229*4882a593Smuzhiyun #define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 230*4882a593Smuzhiyun #define FE_FS_REG_COMM_EXEC__A 0xC30000 231*4882a593Smuzhiyun #define FE_FS_REG_ADD_INC_LOP__A 0xC30010 232*4882a593Smuzhiyun #define FE_FD_REG_COMM_EXEC__A 0xC40000 233*4882a593Smuzhiyun #define FE_FD_REG_SCL__A 0xC40010 234*4882a593Smuzhiyun #define FE_FD_REG_MAX_LEV__A 0xC40011 235*4882a593Smuzhiyun #define FE_FD_REG_NR__A 0xC40012 236*4882a593Smuzhiyun #define FE_FD_REG_MEAS_VAL__A 0xC40014 237*4882a593Smuzhiyun #define FE_IF_REG_COMM_EXEC__A 0xC50000 238*4882a593Smuzhiyun #define FE_IF_REG_INCR0__A 0xC50010 239*4882a593Smuzhiyun #define FE_IF_REG_INCR0__W 16 240*4882a593Smuzhiyun #define FE_IF_REG_INCR0__M 0xFFFF 241*4882a593Smuzhiyun #define FE_IF_REG_INCR1__A 0xC50011 242*4882a593Smuzhiyun #define FE_IF_REG_INCR1__M 0xFF 243*4882a593Smuzhiyun #define FE_CF_REG_COMM_EXEC__A 0xC60000 244*4882a593Smuzhiyun #define FE_CF_REG_SCL__A 0xC60010 245*4882a593Smuzhiyun #define FE_CF_REG_MAX_LEV__A 0xC60011 246*4882a593Smuzhiyun #define FE_CF_REG_NR__A 0xC60012 247*4882a593Smuzhiyun #define FE_CF_REG_IMP_VAL__A 0xC60013 248*4882a593Smuzhiyun #define FE_CF_REG_MEAS_VAL__A 0xC60014 249*4882a593Smuzhiyun #define FE_CU_REG_COMM_EXEC__A 0xC70000 250*4882a593Smuzhiyun #define FE_CU_REG_FRM_CNT_RST__A 0xC70011 251*4882a593Smuzhiyun #define FE_CU_REG_FRM_CNT_STR__A 0xC70012 252*4882a593Smuzhiyun #define FT_COMM_EXEC__A 0x1000000 253*4882a593Smuzhiyun #define FT_REG_COMM_EXEC__A 0x1010000 254*4882a593Smuzhiyun #define CP_COMM_EXEC__A 0x1400000 255*4882a593Smuzhiyun #define CP_REG_COMM_EXEC__A 0x1410000 256*4882a593Smuzhiyun #define CP_REG_INTERVAL__A 0x1410011 257*4882a593Smuzhiyun #define CP_REG_BR_SPL_OFFSET__A 0x1410023 258*4882a593Smuzhiyun #define CP_REG_BR_STR_DEL__A 0x1410024 259*4882a593Smuzhiyun #define CP_REG_RT_ANG_INC0__A 0x1410030 260*4882a593Smuzhiyun #define CP_REG_RT_ANG_INC1__A 0x1410031 261*4882a593Smuzhiyun #define CP_REG_RT_DETECT_ENA__A 0x1410032 262*4882a593Smuzhiyun #define CP_REG_RT_DETECT_TRH__A 0x1410033 263*4882a593Smuzhiyun #define CP_REG_RT_EXP_MARG__A 0x141003E 264*4882a593Smuzhiyun #define CP_REG_AC_NEXP_OFFS__A 0x1410040 265*4882a593Smuzhiyun #define CP_REG_AC_AVER_POW__A 0x1410041 266*4882a593Smuzhiyun #define CP_REG_AC_MAX_POW__A 0x1410042 267*4882a593Smuzhiyun #define CP_REG_AC_WEIGHT_MAN__A 0x1410043 268*4882a593Smuzhiyun #define CP_REG_AC_WEIGHT_EXP__A 0x1410044 269*4882a593Smuzhiyun #define CP_REG_AC_AMP_MODE__A 0x1410047 270*4882a593Smuzhiyun #define CP_REG_AC_AMP_FIX__A 0x1410048 271*4882a593Smuzhiyun #define CP_REG_AC_ANG_MODE__A 0x141004A 272*4882a593Smuzhiyun #define CE_COMM_EXEC__A 0x1800000 273*4882a593Smuzhiyun #define CE_REG_COMM_EXEC__A 0x1810000 274*4882a593Smuzhiyun #define CE_REG_TAPSET__A 0x1810011 275*4882a593Smuzhiyun #define CE_REG_AVG_POW__A 0x1810012 276*4882a593Smuzhiyun #define CE_REG_MAX_POW__A 0x1810013 277*4882a593Smuzhiyun #define CE_REG_ATT__A 0x1810014 278*4882a593Smuzhiyun #define CE_REG_NRED__A 0x1810015 279*4882a593Smuzhiyun #define CE_REG_NE_ERR_SELECT__A 0x1810043 280*4882a593Smuzhiyun #define CE_REG_NE_TD_CAL__A 0x1810044 281*4882a593Smuzhiyun #define CE_REG_NE_MIXAVG__A 0x1810046 282*4882a593Smuzhiyun #define CE_REG_NE_NUPD_OFS__A 0x1810047 283*4882a593Smuzhiyun #define CE_REG_PE_NEXP_OFFS__A 0x1810050 284*4882a593Smuzhiyun #define CE_REG_PE_TIMESHIFT__A 0x1810051 285*4882a593Smuzhiyun #define CE_REG_TP_A0_TAP_NEW__A 0x1810064 286*4882a593Smuzhiyun #define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 287*4882a593Smuzhiyun #define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 288*4882a593Smuzhiyun #define CE_REG_TP_A1_TAP_NEW__A 0x1810068 289*4882a593Smuzhiyun #define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 290*4882a593Smuzhiyun #define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A 291*4882a593Smuzhiyun #define CE_REG_TI_NEXP_OFFS__A 0x1810070 292*4882a593Smuzhiyun #define CE_REG_FI_SHT_INCR__A 0x1810090 293*4882a593Smuzhiyun #define CE_REG_FI_EXP_NORM__A 0x1810091 294*4882a593Smuzhiyun #define CE_REG_IR_INPUTSEL__A 0x18100A0 295*4882a593Smuzhiyun #define CE_REG_IR_STARTPOS__A 0x18100A1 296*4882a593Smuzhiyun #define CE_REG_IR_NEXP_THRES__A 0x18100A2 297*4882a593Smuzhiyun #define CE_REG_FR_TREAL00__A 0x1820010 298*4882a593Smuzhiyun #define CE_REG_FR_TIMAG00__A 0x1820011 299*4882a593Smuzhiyun #define CE_REG_FR_TREAL01__A 0x1820012 300*4882a593Smuzhiyun #define CE_REG_FR_TIMAG01__A 0x1820013 301*4882a593Smuzhiyun #define CE_REG_FR_TREAL02__A 0x1820014 302*4882a593Smuzhiyun #define CE_REG_FR_TIMAG02__A 0x1820015 303*4882a593Smuzhiyun #define CE_REG_FR_TREAL03__A 0x1820016 304*4882a593Smuzhiyun #define CE_REG_FR_TIMAG03__A 0x1820017 305*4882a593Smuzhiyun #define CE_REG_FR_TREAL04__A 0x1820018 306*4882a593Smuzhiyun #define CE_REG_FR_TIMAG04__A 0x1820019 307*4882a593Smuzhiyun #define CE_REG_FR_TREAL05__A 0x182001A 308*4882a593Smuzhiyun #define CE_REG_FR_TIMAG05__A 0x182001B 309*4882a593Smuzhiyun #define CE_REG_FR_TREAL06__A 0x182001C 310*4882a593Smuzhiyun #define CE_REG_FR_TIMAG06__A 0x182001D 311*4882a593Smuzhiyun #define CE_REG_FR_TREAL07__A 0x182001E 312*4882a593Smuzhiyun #define CE_REG_FR_TIMAG07__A 0x182001F 313*4882a593Smuzhiyun #define CE_REG_FR_TREAL08__A 0x1820020 314*4882a593Smuzhiyun #define CE_REG_FR_TIMAG08__A 0x1820021 315*4882a593Smuzhiyun #define CE_REG_FR_TREAL09__A 0x1820022 316*4882a593Smuzhiyun #define CE_REG_FR_TIMAG09__A 0x1820023 317*4882a593Smuzhiyun #define CE_REG_FR_TREAL10__A 0x1820024 318*4882a593Smuzhiyun #define CE_REG_FR_TIMAG10__A 0x1820025 319*4882a593Smuzhiyun #define CE_REG_FR_TREAL11__A 0x1820026 320*4882a593Smuzhiyun #define CE_REG_FR_TIMAG11__A 0x1820027 321*4882a593Smuzhiyun #define CE_REG_FR_MID_TAP__A 0x1820028 322*4882a593Smuzhiyun #define CE_REG_FR_SQS_G00__A 0x1820029 323*4882a593Smuzhiyun #define CE_REG_FR_SQS_G01__A 0x182002A 324*4882a593Smuzhiyun #define CE_REG_FR_SQS_G02__A 0x182002B 325*4882a593Smuzhiyun #define CE_REG_FR_SQS_G03__A 0x182002C 326*4882a593Smuzhiyun #define CE_REG_FR_SQS_G04__A 0x182002D 327*4882a593Smuzhiyun #define CE_REG_FR_SQS_G05__A 0x182002E 328*4882a593Smuzhiyun #define CE_REG_FR_SQS_G06__A 0x182002F 329*4882a593Smuzhiyun #define CE_REG_FR_SQS_G07__A 0x1820030 330*4882a593Smuzhiyun #define CE_REG_FR_SQS_G08__A 0x1820031 331*4882a593Smuzhiyun #define CE_REG_FR_SQS_G09__A 0x1820032 332*4882a593Smuzhiyun #define CE_REG_FR_SQS_G10__A 0x1820033 333*4882a593Smuzhiyun #define CE_REG_FR_SQS_G11__A 0x1820034 334*4882a593Smuzhiyun #define CE_REG_FR_SQS_G12__A 0x1820035 335*4882a593Smuzhiyun #define CE_REG_FR_RIO_G00__A 0x1820036 336*4882a593Smuzhiyun #define CE_REG_FR_RIO_G01__A 0x1820037 337*4882a593Smuzhiyun #define CE_REG_FR_RIO_G02__A 0x1820038 338*4882a593Smuzhiyun #define CE_REG_FR_RIO_G03__A 0x1820039 339*4882a593Smuzhiyun #define CE_REG_FR_RIO_G04__A 0x182003A 340*4882a593Smuzhiyun #define CE_REG_FR_RIO_G05__A 0x182003B 341*4882a593Smuzhiyun #define CE_REG_FR_RIO_G06__A 0x182003C 342*4882a593Smuzhiyun #define CE_REG_FR_RIO_G07__A 0x182003D 343*4882a593Smuzhiyun #define CE_REG_FR_RIO_G08__A 0x182003E 344*4882a593Smuzhiyun #define CE_REG_FR_RIO_G09__A 0x182003F 345*4882a593Smuzhiyun #define CE_REG_FR_RIO_G10__A 0x1820040 346*4882a593Smuzhiyun #define CE_REG_FR_MODE__A 0x1820041 347*4882a593Smuzhiyun #define CE_REG_FR_SQS_TRH__A 0x1820042 348*4882a593Smuzhiyun #define CE_REG_FR_RIO_GAIN__A 0x1820043 349*4882a593Smuzhiyun #define CE_REG_FR_BYPASS__A 0x1820044 350*4882a593Smuzhiyun #define CE_REG_FR_PM_SET__A 0x1820045 351*4882a593Smuzhiyun #define CE_REG_FR_ERR_SH__A 0x1820046 352*4882a593Smuzhiyun #define CE_REG_FR_MAN_SH__A 0x1820047 353*4882a593Smuzhiyun #define CE_REG_FR_TAP_SH__A 0x1820048 354*4882a593Smuzhiyun #define EQ_COMM_EXEC__A 0x1C00000 355*4882a593Smuzhiyun #define EQ_REG_COMM_EXEC__A 0x1C10000 356*4882a593Smuzhiyun #define EQ_REG_COMM_MB__A 0x1C10002 357*4882a593Smuzhiyun #define EQ_REG_IS_GAIN_MAN__A 0x1C10015 358*4882a593Smuzhiyun #define EQ_REG_IS_GAIN_EXP__A 0x1C10016 359*4882a593Smuzhiyun #define EQ_REG_IS_CLIP_EXP__A 0x1C10017 360*4882a593Smuzhiyun #define EQ_REG_SN_CEGAIN__A 0x1C1002A 361*4882a593Smuzhiyun #define EQ_REG_SN_OFFSET__A 0x1C1002B 362*4882a593Smuzhiyun #define EQ_REG_RC_SEL_CAR__A 0x1C10032 363*4882a593Smuzhiyun #define EQ_REG_RC_SEL_CAR_INIT 0x0 364*4882a593Smuzhiyun #define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 365*4882a593Smuzhiyun #define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 366*4882a593Smuzhiyun #define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 367*4882a593Smuzhiyun #define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 368*4882a593Smuzhiyun #define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 369*4882a593Smuzhiyun #define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 370*4882a593Smuzhiyun #define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 371*4882a593Smuzhiyun #define EQ_REG_OT_CONST__A 0x1C10046 372*4882a593Smuzhiyun #define EQ_REG_OT_ALPHA__A 0x1C10047 373*4882a593Smuzhiyun #define EQ_REG_OT_QNT_THRES0__A 0x1C10048 374*4882a593Smuzhiyun #define EQ_REG_OT_QNT_THRES1__A 0x1C10049 375*4882a593Smuzhiyun #define EQ_REG_OT_CSI_STEP__A 0x1C1004A 376*4882a593Smuzhiyun #define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B 377*4882a593Smuzhiyun #define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 378*4882a593Smuzhiyun #define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 379*4882a593Smuzhiyun #define EC_SB_REG_COMM_EXEC__A 0x2010000 380*4882a593Smuzhiyun #define EC_SB_REG_TR_MODE__A 0x2010010 381*4882a593Smuzhiyun #define EC_SB_REG_TR_MODE_8K 0x0 382*4882a593Smuzhiyun #define EC_SB_REG_TR_MODE_2K 0x1 383*4882a593Smuzhiyun #define EC_SB_REG_CONST__A 0x2010011 384*4882a593Smuzhiyun #define EC_SB_REG_CONST_QPSK 0x0 385*4882a593Smuzhiyun #define EC_SB_REG_CONST_16QAM 0x1 386*4882a593Smuzhiyun #define EC_SB_REG_CONST_64QAM 0x2 387*4882a593Smuzhiyun #define EC_SB_REG_ALPHA__A 0x2010012 388*4882a593Smuzhiyun #define EC_SB_REG_PRIOR__A 0x2010013 389*4882a593Smuzhiyun #define EC_SB_REG_PRIOR_HI 0x0 390*4882a593Smuzhiyun #define EC_SB_REG_PRIOR_LO 0x1 391*4882a593Smuzhiyun #define EC_SB_REG_CSI_HI__A 0x2010014 392*4882a593Smuzhiyun #define EC_SB_REG_CSI_LO__A 0x2010015 393*4882a593Smuzhiyun #define EC_SB_REG_SMB_TGL__A 0x2010016 394*4882a593Smuzhiyun #define EC_SB_REG_SNR_HI__A 0x2010017 395*4882a593Smuzhiyun #define EC_SB_REG_SNR_MID__A 0x2010018 396*4882a593Smuzhiyun #define EC_SB_REG_SNR_LO__A 0x2010019 397*4882a593Smuzhiyun #define EC_SB_REG_SCALE_MSB__A 0x201001A 398*4882a593Smuzhiyun #define EC_SB_REG_SCALE_BIT2__A 0x201001B 399*4882a593Smuzhiyun #define EC_SB_REG_SCALE_LSB__A 0x201001C 400*4882a593Smuzhiyun #define EC_SB_REG_CSI_OFS__A 0x201001D 401*4882a593Smuzhiyun #define EC_VD_REG_COMM_EXEC__A 0x2090000 402*4882a593Smuzhiyun #define EC_VD_REG_FORCE__A 0x2090010 403*4882a593Smuzhiyun #define EC_VD_REG_SET_CODERATE__A 0x2090011 404*4882a593Smuzhiyun #define EC_VD_REG_SET_CODERATE_C1_2 0x0 405*4882a593Smuzhiyun #define EC_VD_REG_SET_CODERATE_C2_3 0x1 406*4882a593Smuzhiyun #define EC_VD_REG_SET_CODERATE_C3_4 0x2 407*4882a593Smuzhiyun #define EC_VD_REG_SET_CODERATE_C5_6 0x3 408*4882a593Smuzhiyun #define EC_VD_REG_SET_CODERATE_C7_8 0x4 409*4882a593Smuzhiyun #define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 410*4882a593Smuzhiyun #define EC_VD_REG_RLK_ENA__A 0x2090014 411*4882a593Smuzhiyun #define EC_OD_REG_COMM_EXEC__A 0x2110000 412*4882a593Smuzhiyun #define EC_OD_REG_SYNC__A 0x2110010 413*4882a593Smuzhiyun #define EC_OD_DEINT_RAM__A 0x2120000 414*4882a593Smuzhiyun #define EC_RS_REG_COMM_EXEC__A 0x2130000 415*4882a593Smuzhiyun #define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 416*4882a593Smuzhiyun #define EC_RS_REG_VAL__A 0x2130011 417*4882a593Smuzhiyun #define EC_RS_REG_VAL_PCK 0x1 418*4882a593Smuzhiyun #define EC_RS_EC_RAM__A 0x2140000 419*4882a593Smuzhiyun #define EC_OC_REG_COMM_EXEC__A 0x2150000 420*4882a593Smuzhiyun #define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 421*4882a593Smuzhiyun #define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 422*4882a593Smuzhiyun #define EC_OC_REG_COMM_INT_STA__A 0x2150007 423*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_LOP__A 0x2150010 424*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 425*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 426*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 427*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 428*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 429*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 430*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 431*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_HIP__A 0x2150011 432*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 433*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 434*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 435*4882a593Smuzhiyun #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 436*4882a593Smuzhiyun #define EC_OC_REG_OC_MPG_SIO__A 0x2150012 437*4882a593Smuzhiyun #define EC_OC_REG_OC_MPG_SIO__M 0xFFF 438*4882a593Smuzhiyun #define EC_OC_REG_OC_MON_SIO__A 0x2150013 439*4882a593Smuzhiyun #define EC_OC_REG_DTO_INC_LOP__A 0x2150014 440*4882a593Smuzhiyun #define EC_OC_REG_DTO_INC_HIP__A 0x2150015 441*4882a593Smuzhiyun #define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 442*4882a593Smuzhiyun #define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 443*4882a593Smuzhiyun #define EC_OC_REG_TMD_TOP_MODE__A 0x215001D 444*4882a593Smuzhiyun #define EC_OC_REG_TMD_TOP_CNT__A 0x215001E 445*4882a593Smuzhiyun #define EC_OC_REG_TMD_HIL_MAR__A 0x215001F 446*4882a593Smuzhiyun #define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 447*4882a593Smuzhiyun #define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 448*4882a593Smuzhiyun #define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 449*4882a593Smuzhiyun #define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 450*4882a593Smuzhiyun #define EC_OC_REG_RCN_MODE__A 0x2150027 451*4882a593Smuzhiyun #define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 452*4882a593Smuzhiyun #define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 453*4882a593Smuzhiyun #define EC_OC_REG_RCN_CST_LOP__A 0x215002A 454*4882a593Smuzhiyun #define EC_OC_REG_RCN_CST_HIP__A 0x215002B 455*4882a593Smuzhiyun #define EC_OC_REG_RCN_SET_LVL__A 0x215002C 456*4882a593Smuzhiyun #define EC_OC_REG_RCN_GAI_LVL__A 0x215002D 457*4882a593Smuzhiyun #define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 458*4882a593Smuzhiyun #define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 459*4882a593Smuzhiyun #define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 460*4882a593Smuzhiyun #define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 461*4882a593Smuzhiyun #define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 462*4882a593Smuzhiyun #define EC_OC_REG_OCR_MPG_UOS__M 0xFFF 463*4882a593Smuzhiyun #define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 464*4882a593Smuzhiyun #define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 465*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS__A 0x2150039 466*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 467*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 468*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 469*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 470*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 471*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 472*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 473*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 474*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 475*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 476*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 477*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 478*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_WRI__A 0x215003A 479*4882a593Smuzhiyun #define EC_OC_REG_OCR_MON_WRI_INIT 0x0 480*4882a593Smuzhiyun #define EC_OC_REG_IPR_INV_MPG__A 0x2150045 481*4882a593Smuzhiyun #define CC_REG_OSC_MODE__A 0x2410010 482*4882a593Smuzhiyun #define CC_REG_OSC_MODE_M20 0x1 483*4882a593Smuzhiyun #define CC_REG_PLL_MODE__A 0x2410011 484*4882a593Smuzhiyun #define CC_REG_PLL_MODE_BYPASS_PLL 0x1 485*4882a593Smuzhiyun #define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 486*4882a593Smuzhiyun #define CC_REG_REF_DIVIDE__A 0x2410012 487*4882a593Smuzhiyun #define CC_REG_PWD_MODE__A 0x2410015 488*4882a593Smuzhiyun #define CC_REG_PWD_MODE_DOWN_PLL 0x2 489*4882a593Smuzhiyun #define CC_REG_UPDATE__A 0x2410017 490*4882a593Smuzhiyun #define CC_REG_UPDATE_KEY 0x3973 491*4882a593Smuzhiyun #define CC_REG_JTAGID_L__A 0x2410019 492*4882a593Smuzhiyun #define LC_COMM_EXEC__A 0x2800000 493*4882a593Smuzhiyun #define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C 494*4882a593Smuzhiyun #define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A 495*4882a593Smuzhiyun #define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 496*4882a593Smuzhiyun #define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 497*4882a593Smuzhiyun #define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 498*4882a593Smuzhiyun #define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 499*4882a593Smuzhiyun #define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 500*4882a593Smuzhiyun #define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 501*4882a593Smuzhiyun #define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 502*4882a593Smuzhiyun #define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 503*4882a593Smuzhiyun #define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 504*4882a593Smuzhiyun #define B_HI_COMM_EXEC__A 0x400000 505*4882a593Smuzhiyun #define B_HI_COMM_MB__A 0x400002 506*4882a593Smuzhiyun #define B_HI_CT_REG_COMM_STATE__A 0x410001 507*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_RES__A 0x420031 508*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CMD__A 0x420032 509*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CMD_RESET 0x2 510*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 511*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 512*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 513*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 514*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 515*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 516*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 517*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 518*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 519*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 520*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 521*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 522*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 523*4882a593Smuzhiyun #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 524*4882a593Smuzhiyun #define B_HI_RA_RAM_USR_BEGIN__A 0x420040 525*4882a593Smuzhiyun #define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 526*4882a593Smuzhiyun #define B_HI_IF_RAM_USR_BEGIN__A 0x430200 527*4882a593Smuzhiyun #define B_SC_COMM_EXEC__A 0x800000 528*4882a593Smuzhiyun #define B_SC_COMM_EXEC_CTL_STOP 0x0 529*4882a593Smuzhiyun #define B_SC_COMM_STATE__A 0x800001 530*4882a593Smuzhiyun #define B_SC_RA_RAM_PARAM0__A 0x820040 531*4882a593Smuzhiyun #define B_SC_RA_RAM_PARAM1__A 0x820041 532*4882a593Smuzhiyun #define B_SC_RA_RAM_CMD_ADDR__A 0x820042 533*4882a593Smuzhiyun #define B_SC_RA_RAM_CMD__A 0x820043 534*4882a593Smuzhiyun #define B_SC_RA_RAM_CMD_PROC_START 0x1 535*4882a593Smuzhiyun #define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 536*4882a593Smuzhiyun #define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 537*4882a593Smuzhiyun #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 538*4882a593Smuzhiyun #define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 539*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 540*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 541*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 542*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 543*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 544*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC 545*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 546*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 547*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 548*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 549*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 550*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 551*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 552*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 553*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 554*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 555*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 556*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 557*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 558*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 559*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 560*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 561*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 562*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 563*4882a593Smuzhiyun #define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 564*4882a593Smuzhiyun #define B_SC_RA_RAM_LOCK__A 0x82004B 565*4882a593Smuzhiyun #define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 566*4882a593Smuzhiyun #define B_SC_RA_RAM_LOCK_FEC__M 0x2 567*4882a593Smuzhiyun #define B_SC_RA_RAM_LOCK_MPEG__M 0x4 568*4882a593Smuzhiyun #define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C 569*4882a593Smuzhiyun #define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 570*4882a593Smuzhiyun #define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D 571*4882a593Smuzhiyun #define B_SC_RA_RAM_CONFIG__A 0x820050 572*4882a593Smuzhiyun #define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 573*4882a593Smuzhiyun #define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 574*4882a593Smuzhiyun #define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 575*4882a593Smuzhiyun #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 576*4882a593Smuzhiyun #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 577*4882a593Smuzhiyun #define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D 578*4882a593Smuzhiyun #define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E 579*4882a593Smuzhiyun #define B_SC_RA_RAM_IF_SAVE__AX 0x82008E 580*4882a593Smuzhiyun #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 581*4882a593Smuzhiyun #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 582*4882a593Smuzhiyun #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A 583*4882a593Smuzhiyun #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B 584*4882a593Smuzhiyun #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C 585*4882a593Smuzhiyun #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D 586*4882a593Smuzhiyun #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E 587*4882a593Smuzhiyun #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F 588*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 589*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 590*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 591*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 592*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 593*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 594*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 595*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 596*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 597*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 598*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 599*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 600*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 601*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 602*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 603*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 604*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 605*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 606*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA 607*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB 608*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB 609*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 610*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC 611*4882a593Smuzhiyun #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 612*4882a593Smuzhiyun #define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD 613*4882a593Smuzhiyun #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 614*4882a593Smuzhiyun #define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 615*4882a593Smuzhiyun #define B_SC_RA_RAM_BAND__A 0x8200EC 616*4882a593Smuzhiyun #define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 617*4882a593Smuzhiyun #define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F 618*4882a593Smuzhiyun #define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 619*4882a593Smuzhiyun #define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F 620*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 621*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 622*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 623*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 624*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D 625*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 626*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D 627*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 628*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 629*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 630*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 631*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 632*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A 633*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 634*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB 635*4882a593Smuzhiyun #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 636*4882a593Smuzhiyun #define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE 637*4882a593Smuzhiyun #define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 638*4882a593Smuzhiyun #define B_FE_COMM_EXEC__A 0xC00000 639*4882a593Smuzhiyun #define B_FE_AD_REG_COMM_EXEC__A 0xC10000 640*4882a593Smuzhiyun #define B_FE_AD_REG_FDB_IN__A 0xC10012 641*4882a593Smuzhiyun #define B_FE_AD_REG_PD__A 0xC10013 642*4882a593Smuzhiyun #define B_FE_AD_REG_INVEXT__A 0xC10014 643*4882a593Smuzhiyun #define B_FE_AD_REG_CLKNEG__A 0xC10015 644*4882a593Smuzhiyun #define B_FE_AG_REG_COMM_EXEC__A 0xC20000 645*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 646*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 647*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 648*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 649*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 650*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 651*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 652*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 653*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 654*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 655*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 656*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 657*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 658*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 659*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 660*4882a593Smuzhiyun #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 661*4882a593Smuzhiyun #define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 662*4882a593Smuzhiyun #define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 663*4882a593Smuzhiyun #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 664*4882a593Smuzhiyun #define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 665*4882a593Smuzhiyun #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 666*4882a593Smuzhiyun #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 667*4882a593Smuzhiyun #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 668*4882a593Smuzhiyun #define B_FE_AG_REG_AG_PWD__A 0xC20015 669*4882a593Smuzhiyun #define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 670*4882a593Smuzhiyun #define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 671*4882a593Smuzhiyun #define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 672*4882a593Smuzhiyun #define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 673*4882a593Smuzhiyun #define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 674*4882a593Smuzhiyun #define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A 675*4882a593Smuzhiyun #define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B 676*4882a593Smuzhiyun #define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 677*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 678*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 679*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF 680*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 681*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 682*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 683*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 684*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A 685*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B 686*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C 687*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D 688*4882a593Smuzhiyun #define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E 689*4882a593Smuzhiyun #define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 690*4882a593Smuzhiyun #define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF 691*4882a593Smuzhiyun #define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 692*4882a593Smuzhiyun #define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 693*4882a593Smuzhiyun #define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 694*4882a593Smuzhiyun #define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 695*4882a593Smuzhiyun #define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 696*4882a593Smuzhiyun #define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF 697*4882a593Smuzhiyun #define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 698*4882a593Smuzhiyun #define B_FE_AG_REG_IND_WIN__A 0xC2003C 699*4882a593Smuzhiyun #define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D 700*4882a593Smuzhiyun #define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E 701*4882a593Smuzhiyun #define B_FE_AG_REG_IND_DEL__A 0xC2003F 702*4882a593Smuzhiyun #define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 703*4882a593Smuzhiyun #define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 704*4882a593Smuzhiyun #define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 705*4882a593Smuzhiyun #define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 706*4882a593Smuzhiyun #define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 707*4882a593Smuzhiyun #define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 708*4882a593Smuzhiyun #define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 709*4882a593Smuzhiyun #define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 710*4882a593Smuzhiyun #define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 711*4882a593Smuzhiyun #define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 712*4882a593Smuzhiyun #define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A 713*4882a593Smuzhiyun #define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B 714*4882a593Smuzhiyun #define B_FE_AG_REG_PDC_MAX__A 0xC2004C 715*4882a593Smuzhiyun #define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D 716*4882a593Smuzhiyun #define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E 717*4882a593Smuzhiyun #define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F 718*4882a593Smuzhiyun #define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 719*4882a593Smuzhiyun #define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 720*4882a593Smuzhiyun #define B_FE_AG_REG_TGC_SET_LVL__M 0x3F 721*4882a593Smuzhiyun #define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 722*4882a593Smuzhiyun #define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 723*4882a593Smuzhiyun #define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 724*4882a593Smuzhiyun #define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 725*4882a593Smuzhiyun #define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 726*4882a593Smuzhiyun #define B_FE_AG_REG_FGM_WRI__A 0xC20061 727*4882a593Smuzhiyun #define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 728*4882a593Smuzhiyun #define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 729*4882a593Smuzhiyun #define B_FE_FS_REG_COMM_EXEC__A 0xC30000 730*4882a593Smuzhiyun #define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 731*4882a593Smuzhiyun #define B_FE_FD_REG_COMM_EXEC__A 0xC40000 732*4882a593Smuzhiyun #define B_FE_FD_REG_SCL__A 0xC40010 733*4882a593Smuzhiyun #define B_FE_FD_REG_MAX_LEV__A 0xC40011 734*4882a593Smuzhiyun #define B_FE_FD_REG_NR__A 0xC40012 735*4882a593Smuzhiyun #define B_FE_FD_REG_MEAS_VAL__A 0xC40014 736*4882a593Smuzhiyun #define B_FE_IF_REG_COMM_EXEC__A 0xC50000 737*4882a593Smuzhiyun #define B_FE_IF_REG_INCR0__A 0xC50010 738*4882a593Smuzhiyun #define B_FE_IF_REG_INCR0__W 16 739*4882a593Smuzhiyun #define B_FE_IF_REG_INCR0__M 0xFFFF 740*4882a593Smuzhiyun #define B_FE_IF_REG_INCR1__A 0xC50011 741*4882a593Smuzhiyun #define B_FE_IF_REG_INCR1__M 0xFF 742*4882a593Smuzhiyun #define B_FE_CF_REG_COMM_EXEC__A 0xC60000 743*4882a593Smuzhiyun #define B_FE_CF_REG_SCL__A 0xC60010 744*4882a593Smuzhiyun #define B_FE_CF_REG_MAX_LEV__A 0xC60011 745*4882a593Smuzhiyun #define B_FE_CF_REG_NR__A 0xC60012 746*4882a593Smuzhiyun #define B_FE_CF_REG_IMP_VAL__A 0xC60013 747*4882a593Smuzhiyun #define B_FE_CF_REG_MEAS_VAL__A 0xC60014 748*4882a593Smuzhiyun #define B_FE_CU_REG_COMM_EXEC__A 0xC70000 749*4882a593Smuzhiyun #define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 750*4882a593Smuzhiyun #define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 751*4882a593Smuzhiyun #define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 752*4882a593Smuzhiyun #define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 753*4882a593Smuzhiyun #define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 754*4882a593Smuzhiyun #define B_FT_COMM_EXEC__A 0x1000000 755*4882a593Smuzhiyun #define B_FT_REG_COMM_EXEC__A 0x1010000 756*4882a593Smuzhiyun #define B_CP_COMM_EXEC__A 0x1400000 757*4882a593Smuzhiyun #define B_CP_REG_COMM_EXEC__A 0x1410000 758*4882a593Smuzhiyun #define B_CP_REG_INTERVAL__A 0x1410011 759*4882a593Smuzhiyun #define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 760*4882a593Smuzhiyun #define B_CP_REG_BR_STR_DEL__A 0x1410024 761*4882a593Smuzhiyun #define B_CP_REG_RT_ANG_INC0__A 0x1410030 762*4882a593Smuzhiyun #define B_CP_REG_RT_ANG_INC1__A 0x1410031 763*4882a593Smuzhiyun #define B_CP_REG_RT_DETECT_TRH__A 0x1410033 764*4882a593Smuzhiyun #define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 765*4882a593Smuzhiyun #define B_CP_REG_AC_AVER_POW__A 0x1410041 766*4882a593Smuzhiyun #define B_CP_REG_AC_MAX_POW__A 0x1410042 767*4882a593Smuzhiyun #define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 768*4882a593Smuzhiyun #define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 769*4882a593Smuzhiyun #define B_CP_REG_AC_AMP_MODE__A 0x1410047 770*4882a593Smuzhiyun #define B_CP_REG_AC_AMP_FIX__A 0x1410048 771*4882a593Smuzhiyun #define B_CP_REG_AC_ANG_MODE__A 0x141004A 772*4882a593Smuzhiyun #define B_CE_COMM_EXEC__A 0x1800000 773*4882a593Smuzhiyun #define B_CE_REG_COMM_EXEC__A 0x1810000 774*4882a593Smuzhiyun #define B_CE_REG_TAPSET__A 0x1810011 775*4882a593Smuzhiyun #define B_CE_REG_AVG_POW__A 0x1810012 776*4882a593Smuzhiyun #define B_CE_REG_MAX_POW__A 0x1810013 777*4882a593Smuzhiyun #define B_CE_REG_ATT__A 0x1810014 778*4882a593Smuzhiyun #define B_CE_REG_NRED__A 0x1810015 779*4882a593Smuzhiyun #define B_CE_REG_NE_ERR_SELECT__A 0x1810043 780*4882a593Smuzhiyun #define B_CE_REG_NE_TD_CAL__A 0x1810044 781*4882a593Smuzhiyun #define B_CE_REG_NE_MIXAVG__A 0x1810046 782*4882a593Smuzhiyun #define B_CE_REG_NE_NUPD_OFS__A 0x1810047 783*4882a593Smuzhiyun #define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 784*4882a593Smuzhiyun #define B_CE_REG_PE_TIMESHIFT__A 0x1810051 785*4882a593Smuzhiyun #define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 786*4882a593Smuzhiyun #define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 787*4882a593Smuzhiyun #define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 788*4882a593Smuzhiyun #define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 789*4882a593Smuzhiyun #define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 790*4882a593Smuzhiyun #define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A 791*4882a593Smuzhiyun #define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 792*4882a593Smuzhiyun #define B_CE_REG_FI_SHT_INCR__A 0x1810090 793*4882a593Smuzhiyun #define B_CE_REG_FI_EXP_NORM__A 0x1810091 794*4882a593Smuzhiyun #define B_CE_REG_IR_INPUTSEL__A 0x18100A0 795*4882a593Smuzhiyun #define B_CE_REG_IR_STARTPOS__A 0x18100A1 796*4882a593Smuzhiyun #define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 797*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL00__A 0x1820010 798*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG00__A 0x1820011 799*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL01__A 0x1820012 800*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG01__A 0x1820013 801*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL02__A 0x1820014 802*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG02__A 0x1820015 803*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL03__A 0x1820016 804*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG03__A 0x1820017 805*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL04__A 0x1820018 806*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG04__A 0x1820019 807*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL05__A 0x182001A 808*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG05__A 0x182001B 809*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL06__A 0x182001C 810*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG06__A 0x182001D 811*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL07__A 0x182001E 812*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG07__A 0x182001F 813*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL08__A 0x1820020 814*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG08__A 0x1820021 815*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL09__A 0x1820022 816*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG09__A 0x1820023 817*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL10__A 0x1820024 818*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG10__A 0x1820025 819*4882a593Smuzhiyun #define B_CE_REG_FR_TREAL11__A 0x1820026 820*4882a593Smuzhiyun #define B_CE_REG_FR_TIMAG11__A 0x1820027 821*4882a593Smuzhiyun #define B_CE_REG_FR_MID_TAP__A 0x1820028 822*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G00__A 0x1820029 823*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G01__A 0x182002A 824*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G02__A 0x182002B 825*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G03__A 0x182002C 826*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G04__A 0x182002D 827*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G05__A 0x182002E 828*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G06__A 0x182002F 829*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G07__A 0x1820030 830*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G08__A 0x1820031 831*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G09__A 0x1820032 832*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G10__A 0x1820033 833*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G11__A 0x1820034 834*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_G12__A 0x1820035 835*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G00__A 0x1820036 836*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G01__A 0x1820037 837*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G02__A 0x1820038 838*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G03__A 0x1820039 839*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G04__A 0x182003A 840*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G05__A 0x182003B 841*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G06__A 0x182003C 842*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G07__A 0x182003D 843*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G08__A 0x182003E 844*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G09__A 0x182003F 845*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_G10__A 0x1820040 846*4882a593Smuzhiyun #define B_CE_REG_FR_MODE__A 0x1820041 847*4882a593Smuzhiyun #define B_CE_REG_FR_SQS_TRH__A 0x1820042 848*4882a593Smuzhiyun #define B_CE_REG_FR_RIO_GAIN__A 0x1820043 849*4882a593Smuzhiyun #define B_CE_REG_FR_BYPASS__A 0x1820044 850*4882a593Smuzhiyun #define B_CE_REG_FR_PM_SET__A 0x1820045 851*4882a593Smuzhiyun #define B_CE_REG_FR_ERR_SH__A 0x1820046 852*4882a593Smuzhiyun #define B_CE_REG_FR_MAN_SH__A 0x1820047 853*4882a593Smuzhiyun #define B_CE_REG_FR_TAP_SH__A 0x1820048 854*4882a593Smuzhiyun #define B_EQ_COMM_EXEC__A 0x1C00000 855*4882a593Smuzhiyun #define B_EQ_REG_COMM_EXEC__A 0x1C10000 856*4882a593Smuzhiyun #define B_EQ_REG_COMM_MB__A 0x1C10002 857*4882a593Smuzhiyun #define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 858*4882a593Smuzhiyun #define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 859*4882a593Smuzhiyun #define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 860*4882a593Smuzhiyun #define B_EQ_REG_SN_CEGAIN__A 0x1C1002A 861*4882a593Smuzhiyun #define B_EQ_REG_SN_OFFSET__A 0x1C1002B 862*4882a593Smuzhiyun #define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 863*4882a593Smuzhiyun #define B_EQ_REG_RC_SEL_CAR_INIT 0x2 864*4882a593Smuzhiyun #define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 865*4882a593Smuzhiyun #define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 866*4882a593Smuzhiyun #define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 867*4882a593Smuzhiyun #define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 868*4882a593Smuzhiyun #define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 869*4882a593Smuzhiyun #define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 870*4882a593Smuzhiyun #define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 871*4882a593Smuzhiyun #define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 872*4882a593Smuzhiyun #define B_EQ_REG_OT_CONST__A 0x1C10046 873*4882a593Smuzhiyun #define B_EQ_REG_OT_ALPHA__A 0x1C10047 874*4882a593Smuzhiyun #define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 875*4882a593Smuzhiyun #define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 876*4882a593Smuzhiyun #define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A 877*4882a593Smuzhiyun #define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B 878*4882a593Smuzhiyun #define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 879*4882a593Smuzhiyun #define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 880*4882a593Smuzhiyun #define B_EC_SB_REG_COMM_EXEC__A 0x2010000 881*4882a593Smuzhiyun #define B_EC_SB_REG_TR_MODE__A 0x2010010 882*4882a593Smuzhiyun #define B_EC_SB_REG_TR_MODE_8K 0x0 883*4882a593Smuzhiyun #define B_EC_SB_REG_TR_MODE_2K 0x1 884*4882a593Smuzhiyun #define B_EC_SB_REG_CONST__A 0x2010011 885*4882a593Smuzhiyun #define B_EC_SB_REG_CONST_QPSK 0x0 886*4882a593Smuzhiyun #define B_EC_SB_REG_CONST_16QAM 0x1 887*4882a593Smuzhiyun #define B_EC_SB_REG_CONST_64QAM 0x2 888*4882a593Smuzhiyun #define B_EC_SB_REG_ALPHA__A 0x2010012 889*4882a593Smuzhiyun #define B_EC_SB_REG_PRIOR__A 0x2010013 890*4882a593Smuzhiyun #define B_EC_SB_REG_PRIOR_HI 0x0 891*4882a593Smuzhiyun #define B_EC_SB_REG_PRIOR_LO 0x1 892*4882a593Smuzhiyun #define B_EC_SB_REG_CSI_HI__A 0x2010014 893*4882a593Smuzhiyun #define B_EC_SB_REG_CSI_LO__A 0x2010015 894*4882a593Smuzhiyun #define B_EC_SB_REG_SMB_TGL__A 0x2010016 895*4882a593Smuzhiyun #define B_EC_SB_REG_SNR_HI__A 0x2010017 896*4882a593Smuzhiyun #define B_EC_SB_REG_SNR_MID__A 0x2010018 897*4882a593Smuzhiyun #define B_EC_SB_REG_SNR_LO__A 0x2010019 898*4882a593Smuzhiyun #define B_EC_SB_REG_SCALE_MSB__A 0x201001A 899*4882a593Smuzhiyun #define B_EC_SB_REG_SCALE_BIT2__A 0x201001B 900*4882a593Smuzhiyun #define B_EC_SB_REG_SCALE_LSB__A 0x201001C 901*4882a593Smuzhiyun #define B_EC_SB_REG_CSI_OFS0__A 0x201001D 902*4882a593Smuzhiyun #define B_EC_SB_REG_CSI_OFS1__A 0x201001E 903*4882a593Smuzhiyun #define B_EC_SB_REG_CSI_OFS2__A 0x201001F 904*4882a593Smuzhiyun #define B_EC_VD_REG_COMM_EXEC__A 0x2090000 905*4882a593Smuzhiyun #define B_EC_VD_REG_FORCE__A 0x2090010 906*4882a593Smuzhiyun #define B_EC_VD_REG_SET_CODERATE__A 0x2090011 907*4882a593Smuzhiyun #define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 908*4882a593Smuzhiyun #define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 909*4882a593Smuzhiyun #define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 910*4882a593Smuzhiyun #define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 911*4882a593Smuzhiyun #define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 912*4882a593Smuzhiyun #define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 913*4882a593Smuzhiyun #define B_EC_VD_REG_RLK_ENA__A 0x2090014 914*4882a593Smuzhiyun #define B_EC_OD_REG_COMM_EXEC__A 0x2110000 915*4882a593Smuzhiyun #define B_EC_OD_REG_SYNC__A 0x2110664 916*4882a593Smuzhiyun #define B_EC_OD_DEINT_RAM__A 0x2120000 917*4882a593Smuzhiyun #define B_EC_RS_REG_COMM_EXEC__A 0x2130000 918*4882a593Smuzhiyun #define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 919*4882a593Smuzhiyun #define B_EC_RS_REG_VAL__A 0x2130011 920*4882a593Smuzhiyun #define B_EC_RS_REG_VAL_PCK 0x1 921*4882a593Smuzhiyun #define B_EC_RS_EC_RAM__A 0x2140000 922*4882a593Smuzhiyun #define B_EC_OC_REG_COMM_EXEC__A 0x2150000 923*4882a593Smuzhiyun #define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 924*4882a593Smuzhiyun #define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 925*4882a593Smuzhiyun #define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 926*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 927*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 928*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 929*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 930*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 931*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 932*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 933*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 934*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 935*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 936*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 937*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 938*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 939*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 940*4882a593Smuzhiyun #define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF 941*4882a593Smuzhiyun #define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 942*4882a593Smuzhiyun #define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 943*4882a593Smuzhiyun #define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 944*4882a593Smuzhiyun #define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 945*4882a593Smuzhiyun #define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D 946*4882a593Smuzhiyun #define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E 947*4882a593Smuzhiyun #define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F 948*4882a593Smuzhiyun #define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 949*4882a593Smuzhiyun #define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 950*4882a593Smuzhiyun #define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 951*4882a593Smuzhiyun #define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 952*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_MODE__A 0x2150027 953*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 954*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 955*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A 956*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B 957*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C 958*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D 959*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 960*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 961*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 962*4882a593Smuzhiyun #define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 963*4882a593Smuzhiyun #define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 964*4882a593Smuzhiyun #define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF 965*4882a593Smuzhiyun #define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 966*4882a593Smuzhiyun #define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 967*4882a593Smuzhiyun #define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 968*4882a593Smuzhiyun #define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 969*4882a593Smuzhiyun #define B_EC_OC_REG_DTO_PER__A 0x2150048 970*4882a593Smuzhiyun #define B_EC_OC_REG_DTO_BUR__A 0x2150049 971*4882a593Smuzhiyun #define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A 972*4882a593Smuzhiyun #define B_CC_REG_OSC_MODE__A 0x2410010 973*4882a593Smuzhiyun #define B_CC_REG_OSC_MODE_M20 0x1 974*4882a593Smuzhiyun #define B_CC_REG_PLL_MODE__A 0x2410011 975*4882a593Smuzhiyun #define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 976*4882a593Smuzhiyun #define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 977*4882a593Smuzhiyun #define B_CC_REG_REF_DIVIDE__A 0x2410012 978*4882a593Smuzhiyun #define B_CC_REG_PWD_MODE__A 0x2410015 979*4882a593Smuzhiyun #define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 980*4882a593Smuzhiyun #define B_CC_REG_UPDATE__A 0x2410017 981*4882a593Smuzhiyun #define B_CC_REG_UPDATE_KEY 0x3973 982*4882a593Smuzhiyun #define B_CC_REG_JTAGID_L__A 0x2410019 983*4882a593Smuzhiyun #define B_CC_REG_DIVERSITY__A 0x241001B 984*4882a593Smuzhiyun #define B_LC_COMM_EXEC__A 0x2800000 985*4882a593Smuzhiyun #define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C 986*4882a593Smuzhiyun #define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A 987*4882a593Smuzhiyun #define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 988*4882a593Smuzhiyun #define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 989*4882a593Smuzhiyun #define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 990*4882a593Smuzhiyun #define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 991*4882a593Smuzhiyun #define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 992*4882a593Smuzhiyun #define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 993*4882a593Smuzhiyun #define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 994*4882a593Smuzhiyun #define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 995*4882a593Smuzhiyun #define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 996*4882a593Smuzhiyun 997*4882a593Smuzhiyun #endif 998