1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * drxd_firm.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2006-2007 Micronas 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DRXD_FIRM_H_ 9*4882a593Smuzhiyun #define _DRXD_FIRM_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/types.h> 12*4882a593Smuzhiyun #include "drxd_map_firm.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define VERSION_MAJOR 1 15*4882a593Smuzhiyun #define VERSION_MINOR 4 16*4882a593Smuzhiyun #define VERSION_PATCH 23 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define DRXD_MAX_RETRIES (1000) 21*4882a593Smuzhiyun #define HI_I2C_DELAY 84 22*4882a593Smuzhiyun #define HI_I2C_BRIDGE_DELAY 750 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */ 25*4882a593Smuzhiyun #define EQ_TD_TPS_PWR_QPSK 0x016a 26*4882a593Smuzhiyun #define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195 27*4882a593Smuzhiyun #define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195 28*4882a593Smuzhiyun #define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E 29*4882a593Smuzhiyun #define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE 30*4882a593Smuzhiyun #define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F 31*4882a593Smuzhiyun #define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F 32*4882a593Smuzhiyun #define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8 33*4882a593Smuzhiyun #define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define DRXD_DEF_AG_PWD_CONSUMER 0x000E 36*4882a593Smuzhiyun #define DRXD_DEF_AG_PWD_PRO 0x0000 37*4882a593Smuzhiyun #define DRXD_DEF_AG_AGC_SIO 0x0000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define DRXD_FE_CTRL_MAX 1023 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define DRXD_OSCDEV_DO_SCAN (16) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define DRXD_OSCDEV_DONT_SCAN (0) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define DRXD_OSCDEV_STEP (275) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define DRXD_SCAN_TIMEOUT (650) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) 50*4882a593Smuzhiyun #define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) 51*4882a593Smuzhiyun #define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define IRLEN_COARSE_8K (10) 54*4882a593Smuzhiyun #define IRLEN_FINE_8K (10) 55*4882a593Smuzhiyun #define IRLEN_COARSE_2K (7) 56*4882a593Smuzhiyun #define IRLEN_FINE_2K (9) 57*4882a593Smuzhiyun #define DIFF_INVALID (511) 58*4882a593Smuzhiyun #define DIFF_TARGET (4) 59*4882a593Smuzhiyun #define DIFF_MARGIN (1) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun extern u8 DRXD_InitAtomicRead[]; 62*4882a593Smuzhiyun extern u8 DRXD_HiI2cPatch_1[]; 63*4882a593Smuzhiyun extern u8 DRXD_HiI2cPatch_3[]; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun extern u8 DRXD_InitSC[]; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun extern u8 DRXD_ResetCEFR[]; 68*4882a593Smuzhiyun extern u8 DRXD_InitFEA2_1[]; 69*4882a593Smuzhiyun extern u8 DRXD_InitFEA2_2[]; 70*4882a593Smuzhiyun extern u8 DRXD_InitCPA2[]; 71*4882a593Smuzhiyun extern u8 DRXD_InitCEA2[]; 72*4882a593Smuzhiyun extern u8 DRXD_InitEQA2[]; 73*4882a593Smuzhiyun extern u8 DRXD_InitECA2[]; 74*4882a593Smuzhiyun extern u8 DRXD_ResetECA2[]; 75*4882a593Smuzhiyun extern u8 DRXD_ResetECRAM[]; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun extern u8 DRXD_A2_microcode[]; 78*4882a593Smuzhiyun extern u32 DRXD_A2_microcode_length; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun extern u8 DRXD_InitFEB1_1[]; 81*4882a593Smuzhiyun extern u8 DRXD_InitFEB1_2[]; 82*4882a593Smuzhiyun extern u8 DRXD_InitCPB1[]; 83*4882a593Smuzhiyun extern u8 DRXD_InitCEB1[]; 84*4882a593Smuzhiyun extern u8 DRXD_InitEQB1[]; 85*4882a593Smuzhiyun extern u8 DRXD_InitECB1[]; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun extern u8 DRXD_InitDiversityFront[]; 88*4882a593Smuzhiyun extern u8 DRXD_InitDiversityEnd[]; 89*4882a593Smuzhiyun extern u8 DRXD_DisableDiversity[]; 90*4882a593Smuzhiyun extern u8 DRXD_StartDiversityFront[]; 91*4882a593Smuzhiyun extern u8 DRXD_StartDiversityEnd[]; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun extern u8 DRXD_DiversityDelay8MHZ[]; 94*4882a593Smuzhiyun extern u8 DRXD_DiversityDelay6MHZ[]; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun extern u8 DRXD_B1_microcode[]; 97*4882a593Smuzhiyun extern u32 DRXD_B1_microcode_length; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif 100