1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * drxd_firm.c : DRXD firmware tables 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2006-2007 Micronas 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* TODO: generate this file with a script from a settings file */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Contains A2 firmware version: 1.4.2 11*4882a593Smuzhiyun * Contains B1 firmware version: 3.3.33 12*4882a593Smuzhiyun * Contains settings from driver 1.4.23 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include "drxd_firm.h" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF) 18*4882a593Smuzhiyun #define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Is written via block write, must be little endian */ 21*4882a593Smuzhiyun #define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define WRBLOCK(a, l) ADDRESS(a), LENGTH(l) 24*4882a593Smuzhiyun #define WR16(a, d) ADDRESS(a), LENGTH(1), DATA16(d) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define END_OF_TABLE 0xFF, 0xFF, 0xFF, 0xFF 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* HI firmware patches */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A 31*4882a593Smuzhiyun #define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun u8 DRXD_InitAtomicRead[] = { 34*4882a593Smuzhiyun WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE), 35*4882a593Smuzhiyun 0x26, 0x00, /* 0 -> ring.rdy; */ 36*4882a593Smuzhiyun 0x60, 0x04, /* r0rami.dt -> ring.xba; */ 37*4882a593Smuzhiyun 0x61, 0x04, /* r0rami.dt -> ring.xad; */ 38*4882a593Smuzhiyun 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */ 39*4882a593Smuzhiyun 0x40, 0x00, /* (long immediate) */ 40*4882a593Smuzhiyun 0x64, 0x04, /* r0rami.dt -> ring.len; */ 41*4882a593Smuzhiyun 0x65, 0x04, /* r0rami.dt -> ring.ctl; */ 42*4882a593Smuzhiyun 0x26, 0x00, /* 0 -> ring.rdy; */ 43*4882a593Smuzhiyun 0x38, 0x00, /* 0 -> jumps.ad; */ 44*4882a593Smuzhiyun END_OF_TABLE 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Pins D0 and D1 of the parallel MPEG output can be used 48*4882a593Smuzhiyun to set the I2C address of a device. */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define HI_RST_FUNC_ADDR (HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE) 51*4882a593Smuzhiyun #define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* D0 Version */ 54*4882a593Smuzhiyun u8 DRXD_HiI2cPatch_1[] = { 55*4882a593Smuzhiyun WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE), 56*4882a593Smuzhiyun 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */ 57*4882a593Smuzhiyun 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ 58*4882a593Smuzhiyun 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ 59*4882a593Smuzhiyun 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ 60*4882a593Smuzhiyun 0x23, 0x00, /* &data -> ring.iad; */ 61*4882a593Smuzhiyun 0x24, 0x00, /* 0 -> ring.len; */ 62*4882a593Smuzhiyun 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ 63*4882a593Smuzhiyun 0x26, 0x00, /* 0 -> ring.rdy; */ 64*4882a593Smuzhiyun 0x42, 0x00, /* &data+1 -> w0ram.ad; */ 65*4882a593Smuzhiyun 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ 66*4882a593Smuzhiyun 0x63, 0x00, /* &data+1 -> ring.iad; */ 67*4882a593Smuzhiyun 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ 68*4882a593Smuzhiyun 0x26, 0x00, /* 0 -> ring.rdy; */ 69*4882a593Smuzhiyun 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ 70*4882a593Smuzhiyun 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ 71*4882a593Smuzhiyun 0x26, 0x00, /* 0 -> ring.rdy; */ 72*4882a593Smuzhiyun 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ 73*4882a593Smuzhiyun 0x23, 0x00, /* &data -> ring.iad; */ 74*4882a593Smuzhiyun 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ 75*4882a593Smuzhiyun 0x26, 0x00, /* 0 -> ring.rdy; */ 76*4882a593Smuzhiyun 0x42, 0x00, /* &data+1 -> w0ram.ad; */ 77*4882a593Smuzhiyun 0x0F, 0x04, /* r0ram.dt -> and.op; */ 78*4882a593Smuzhiyun 0x1C, 0x06, /* reg0.dt -> and.tr; */ 79*4882a593Smuzhiyun 0xCF, 0x04, /* and.rs -> add.op; */ 80*4882a593Smuzhiyun 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ 81*4882a593Smuzhiyun 0xD0, 0x04, /* add.rs -> add.tr; */ 82*4882a593Smuzhiyun 0xC8, 0x04, /* add.rs -> reg0.dt; */ 83*4882a593Smuzhiyun 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ 84*4882a593Smuzhiyun 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ 85*4882a593Smuzhiyun 0x01, 0x00, /* 0 -> w0rami.dt; */ 86*4882a593Smuzhiyun 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ 87*4882a593Smuzhiyun 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ 88*4882a593Smuzhiyun 0x01, 0x00, /* 0 -> w0rami.dt; */ 89*4882a593Smuzhiyun 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ 90*4882a593Smuzhiyun 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ 91*4882a593Smuzhiyun 0x01, 0x00, /* 0 -> w0rami.dt; */ 92*4882a593Smuzhiyun 0x01, 0x00, /* 0 -> w0rami.dt; */ 93*4882a593Smuzhiyun 0x01, 0x00, /* 0 -> w0rami.dt; */ 94*4882a593Smuzhiyun 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ 95*4882a593Smuzhiyun 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ 96*4882a593Smuzhiyun 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ 97*4882a593Smuzhiyun 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ 98*4882a593Smuzhiyun 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)), 101*4882a593Smuzhiyun (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 102*4882a593Smuzhiyun WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)), 103*4882a593Smuzhiyun (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 104*4882a593Smuzhiyun WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)), 105*4882a593Smuzhiyun (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 106*4882a593Smuzhiyun WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)), 107*4882a593Smuzhiyun (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* Force quick and dirty reset */ 110*4882a593Smuzhiyun WR16(B_HI_CT_REG_COMM_STATE__A, 0), 111*4882a593Smuzhiyun END_OF_TABLE 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* D0,D1 Version */ 115*4882a593Smuzhiyun u8 DRXD_HiI2cPatch_3[] = { 116*4882a593Smuzhiyun WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE), 117*4882a593Smuzhiyun 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */ 118*4882a593Smuzhiyun 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ 119*4882a593Smuzhiyun 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ 120*4882a593Smuzhiyun 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ 121*4882a593Smuzhiyun 0x23, 0x00, /* &data -> ring.iad; */ 122*4882a593Smuzhiyun 0x24, 0x00, /* 0 -> ring.len; */ 123*4882a593Smuzhiyun 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ 124*4882a593Smuzhiyun 0x26, 0x00, /* 0 -> ring.rdy; */ 125*4882a593Smuzhiyun 0x42, 0x00, /* &data+1 -> w0ram.ad; */ 126*4882a593Smuzhiyun 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ 127*4882a593Smuzhiyun 0x63, 0x00, /* &data+1 -> ring.iad; */ 128*4882a593Smuzhiyun 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ 129*4882a593Smuzhiyun 0x26, 0x00, /* 0 -> ring.rdy; */ 130*4882a593Smuzhiyun 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ 131*4882a593Smuzhiyun 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ 132*4882a593Smuzhiyun 0x26, 0x00, /* 0 -> ring.rdy; */ 133*4882a593Smuzhiyun 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ 134*4882a593Smuzhiyun 0x23, 0x00, /* &data -> ring.iad; */ 135*4882a593Smuzhiyun 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ 136*4882a593Smuzhiyun 0x26, 0x00, /* 0 -> ring.rdy; */ 137*4882a593Smuzhiyun 0x42, 0x00, /* &data+1 -> w0ram.ad; */ 138*4882a593Smuzhiyun 0x0F, 0x04, /* r0ram.dt -> and.op; */ 139*4882a593Smuzhiyun 0x1C, 0x06, /* reg0.dt -> and.tr; */ 140*4882a593Smuzhiyun 0xCF, 0x04, /* and.rs -> add.op; */ 141*4882a593Smuzhiyun 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ 142*4882a593Smuzhiyun 0xD0, 0x04, /* add.rs -> add.tr; */ 143*4882a593Smuzhiyun 0xC8, 0x04, /* add.rs -> reg0.dt; */ 144*4882a593Smuzhiyun 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ 145*4882a593Smuzhiyun 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ 146*4882a593Smuzhiyun 0x01, 0x00, /* 0 -> w0rami.dt; */ 147*4882a593Smuzhiyun 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ 148*4882a593Smuzhiyun 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ 149*4882a593Smuzhiyun 0x01, 0x00, /* 0 -> w0rami.dt; */ 150*4882a593Smuzhiyun 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ 151*4882a593Smuzhiyun 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ 152*4882a593Smuzhiyun 0x01, 0x00, /* 0 -> w0rami.dt; */ 153*4882a593Smuzhiyun 0x01, 0x00, /* 0 -> w0rami.dt; */ 154*4882a593Smuzhiyun 0x01, 0x00, /* 0 -> w0rami.dt; */ 155*4882a593Smuzhiyun 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ 156*4882a593Smuzhiyun 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ 157*4882a593Smuzhiyun 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ 158*4882a593Smuzhiyun 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ 159*4882a593Smuzhiyun 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)), 162*4882a593Smuzhiyun (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 163*4882a593Smuzhiyun WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)), 164*4882a593Smuzhiyun (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 165*4882a593Smuzhiyun WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)), 166*4882a593Smuzhiyun (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 167*4882a593Smuzhiyun WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)), 168*4882a593Smuzhiyun (u16) (HI_RST_FUNC_ADDR & 0x3FF)), 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* Force quick and dirty reset */ 171*4882a593Smuzhiyun WR16(B_HI_CT_REG_COMM_STATE__A, 0), 172*4882a593Smuzhiyun END_OF_TABLE 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun u8 DRXD_ResetCEFR[] = { 176*4882a593Smuzhiyun WRBLOCK(CE_REG_FR_TREAL00__A, 57), 177*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL00__A */ 178*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */ 179*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL01__A */ 180*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG01__A */ 181*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL02__A */ 182*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG02__A */ 183*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL03__A */ 184*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG03__A */ 185*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL04__A */ 186*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG04__A */ 187*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL05__A */ 188*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG05__A */ 189*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL06__A */ 190*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG06__A */ 191*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL07__A */ 192*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG07__A */ 193*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL08__A */ 194*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG08__A */ 195*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL09__A */ 196*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG09__A */ 197*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL10__A */ 198*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG10__A */ 199*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_TREAL11__A */ 200*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_TIMAG11__A */ 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun 0x52, 0x00, /* CE_REG_FR_MID_TAP__A */ 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G00__A */ 205*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G01__A */ 206*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G02__A */ 207*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G03__A */ 208*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G04__A */ 209*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G05__A */ 210*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G06__A */ 211*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G07__A */ 212*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G08__A */ 213*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G09__A */ 214*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G10__A */ 215*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G11__A */ 216*4882a593Smuzhiyun 0x0B, 0x00, /* CE_REG_FR_SQS_G12__A */ 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun 0xFF, 0x01, /* CE_REG_FR_RIO_G00__A */ 219*4882a593Smuzhiyun 0x90, 0x01, /* CE_REG_FR_RIO_G01__A */ 220*4882a593Smuzhiyun 0x0B, 0x01, /* CE_REG_FR_RIO_G02__A */ 221*4882a593Smuzhiyun 0xC8, 0x00, /* CE_REG_FR_RIO_G03__A */ 222*4882a593Smuzhiyun 0xA0, 0x00, /* CE_REG_FR_RIO_G04__A */ 223*4882a593Smuzhiyun 0x85, 0x00, /* CE_REG_FR_RIO_G05__A */ 224*4882a593Smuzhiyun 0x72, 0x00, /* CE_REG_FR_RIO_G06__A */ 225*4882a593Smuzhiyun 0x64, 0x00, /* CE_REG_FR_RIO_G07__A */ 226*4882a593Smuzhiyun 0x59, 0x00, /* CE_REG_FR_RIO_G08__A */ 227*4882a593Smuzhiyun 0x50, 0x00, /* CE_REG_FR_RIO_G09__A */ 228*4882a593Smuzhiyun 0x49, 0x00, /* CE_REG_FR_RIO_G10__A */ 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun 0x10, 0x00, /* CE_REG_FR_MODE__A */ 231*4882a593Smuzhiyun 0x78, 0x00, /* CE_REG_FR_SQS_TRH__A */ 232*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_FR_RIO_GAIN__A */ 233*4882a593Smuzhiyun 0x00, 0x02, /* CE_REG_FR_BYPASS__A */ 234*4882a593Smuzhiyun 0x0D, 0x00, /* CE_REG_FR_PM_SET__A */ 235*4882a593Smuzhiyun 0x07, 0x00, /* CE_REG_FR_ERR_SH__A */ 236*4882a593Smuzhiyun 0x04, 0x00, /* CE_REG_FR_MAN_SH__A */ 237*4882a593Smuzhiyun 0x06, 0x00, /* CE_REG_FR_TAP_SH__A */ 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun END_OF_TABLE 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun u8 DRXD_InitFEA2_1[] = { 243*4882a593Smuzhiyun WRBLOCK(FE_AD_REG_PD__A, 3), 244*4882a593Smuzhiyun 0x00, 0x00, /* FE_AD_REG_PD__A */ 245*4882a593Smuzhiyun 0x01, 0x00, /* FE_AD_REG_INVEXT__A */ 246*4882a593Smuzhiyun 0x00, 0x00, /* FE_AD_REG_CLKNEG__A */ 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2), 249*4882a593Smuzhiyun 0x10, 0x00, /* FE_AG_REG_DCE_AUR_CNT__A */ 250*4882a593Smuzhiyun 0x10, 0x00, /* FE_AG_REG_DCE_RUR_CNT__A */ 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2), 253*4882a593Smuzhiyun 0x0E, 0x00, /* FE_AG_REG_ACE_AUR_CNT__A */ 254*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_ACE_RUR_CNT__A */ 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5), 257*4882a593Smuzhiyun 0x04, 0x00, /* FE_AG_REG_EGC_FLA_RGN__A */ 258*4882a593Smuzhiyun 0x1F, 0x00, /* FE_AG_REG_EGC_SLO_RGN__A */ 259*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_EGC_JMP_PSN__A */ 260*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_EGC_FLA_INC__A */ 261*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_EGC_FLA_DEC__A */ 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2), 264*4882a593Smuzhiyun 0xFF, 0x01, /* FE_AG_REG_GC1_AGC_MAX__A */ 265*4882a593Smuzhiyun 0x00, 0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */ 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun WRBLOCK(FE_AG_REG_IND_WIN__A, 29), 268*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_IND_WIN__A */ 269*4882a593Smuzhiyun 0x05, 0x00, /* FE_AG_REG_IND_THD_LOL__A */ 270*4882a593Smuzhiyun 0x0F, 0x00, /* FE_AG_REG_IND_THD_HIL__A */ 271*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_IND_DEL__A don't care */ 272*4882a593Smuzhiyun 0x1E, 0x00, /* FE_AG_REG_IND_PD1_WRI__A */ 273*4882a593Smuzhiyun 0x0C, 0x00, /* FE_AG_REG_PDA_AUR_CNT__A */ 274*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_PDA_RUR_CNT__A */ 275*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */ 276*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_PDC_RUR_CNT__A */ 277*4882a593Smuzhiyun 0x01, 0x00, /* FE_AG_REG_PDC_SET_LVL__A */ 278*4882a593Smuzhiyun 0x02, 0x00, /* FE_AG_REG_PDC_FLA_RGN__A */ 279*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */ 280*4882a593Smuzhiyun 0xFF, 0xFF, /* FE_AG_REG_PDC_FLA_STP__A */ 281*4882a593Smuzhiyun 0xFF, 0xFF, /* FE_AG_REG_PDC_SLO_STP__A */ 282*4882a593Smuzhiyun 0x00, 0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */ 283*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */ 284*4882a593Smuzhiyun 0x02, 0x00, /* FE_AG_REG_PDC_MAX__A */ 285*4882a593Smuzhiyun 0x0C, 0x00, /* FE_AG_REG_TGA_AUR_CNT__A */ 286*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_TGA_RUR_CNT__A */ 287*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */ 288*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_TGC_RUR_CNT__A */ 289*4882a593Smuzhiyun 0x22, 0x00, /* FE_AG_REG_TGC_SET_LVL__A */ 290*4882a593Smuzhiyun 0x15, 0x00, /* FE_AG_REG_TGC_FLA_RGN__A */ 291*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */ 292*4882a593Smuzhiyun 0x01, 0x00, /* FE_AG_REG_TGC_FLA_STP__A */ 293*4882a593Smuzhiyun 0x0A, 0x00, /* FE_AG_REG_TGC_SLO_STP__A */ 294*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */ 295*4882a593Smuzhiyun 0x10, 0x00, /* FE_AG_REG_FGA_AUR_CNT__A */ 296*4882a593Smuzhiyun 0x10, 0x00, /* FE_AG_REG_FGA_RUR_CNT__A */ 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2), 299*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_BGC_FGC_WRI__A */ 300*4882a593Smuzhiyun 0x00, 0x00, /* FE_AG_REG_BGC_CGC_WRI__A */ 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun WRBLOCK(FE_FD_REG_SCL__A, 3), 303*4882a593Smuzhiyun 0x05, 0x00, /* FE_FD_REG_SCL__A */ 304*4882a593Smuzhiyun 0x03, 0x00, /* FE_FD_REG_MAX_LEV__A */ 305*4882a593Smuzhiyun 0x05, 0x00, /* FE_FD_REG_NR__A */ 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun WRBLOCK(FE_CF_REG_SCL__A, 5), 308*4882a593Smuzhiyun 0x16, 0x00, /* FE_CF_REG_SCL__A */ 309*4882a593Smuzhiyun 0x04, 0x00, /* FE_CF_REG_MAX_LEV__A */ 310*4882a593Smuzhiyun 0x06, 0x00, /* FE_CF_REG_NR__A */ 311*4882a593Smuzhiyun 0x00, 0x00, /* FE_CF_REG_IMP_VAL__A */ 312*4882a593Smuzhiyun 0x01, 0x00, /* FE_CF_REG_MEAS_VAL__A */ 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2), 315*4882a593Smuzhiyun 0x00, 0x08, /* FE_CU_REG_FRM_CNT_RST__A */ 316*4882a593Smuzhiyun 0x00, 0x00, /* FE_CU_REG_FRM_CNT_STR__A */ 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun END_OF_TABLE 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun /* with PGA */ 322*4882a593Smuzhiyun /* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */ 323*4882a593Smuzhiyun /* without PGA */ 324*4882a593Smuzhiyun /* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */ 325*4882a593Smuzhiyun /* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/ 326*4882a593Smuzhiyun /* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun u8 DRXD_InitFEA2_2[] = { 329*4882a593Smuzhiyun WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010), 330*4882a593Smuzhiyun WR16(FE_AG_REG_FGM_WRI__A, 48), 331*4882a593Smuzhiyun /* Activate measurement, activate scale */ 332*4882a593Smuzhiyun WR16(FE_FD_REG_MEAS_VAL__A, 0x0001), 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun WR16(FE_CU_REG_COMM_EXEC__A, 0x0001), 335*4882a593Smuzhiyun WR16(FE_CF_REG_COMM_EXEC__A, 0x0001), 336*4882a593Smuzhiyun WR16(FE_IF_REG_COMM_EXEC__A, 0x0001), 337*4882a593Smuzhiyun WR16(FE_FD_REG_COMM_EXEC__A, 0x0001), 338*4882a593Smuzhiyun WR16(FE_FS_REG_COMM_EXEC__A, 0x0001), 339*4882a593Smuzhiyun WR16(FE_AD_REG_COMM_EXEC__A, 0x0001), 340*4882a593Smuzhiyun WR16(FE_AG_REG_COMM_EXEC__A, 0x0001), 341*4882a593Smuzhiyun WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E), 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun END_OF_TABLE 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun u8 DRXD_InitFEB1_1[] = { 347*4882a593Smuzhiyun WR16(B_FE_AD_REG_PD__A, 0x0000), 348*4882a593Smuzhiyun WR16(B_FE_AD_REG_CLKNEG__A, 0x0000), 349*4882a593Smuzhiyun WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000), 350*4882a593Smuzhiyun WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000), 351*4882a593Smuzhiyun WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a), 352*4882a593Smuzhiyun WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35), 353*4882a593Smuzhiyun WR16(B_FE_AG_REG_IND_WIN__A, 0), 354*4882a593Smuzhiyun WR16(B_FE_AG_REG_IND_THD_LOL__A, 8), 355*4882a593Smuzhiyun WR16(B_FE_AG_REG_IND_THD_HIL__A, 8), 356*4882a593Smuzhiyun WR16(B_FE_CF_REG_IMP_VAL__A, 1), 357*4882a593Smuzhiyun WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7), 358*4882a593Smuzhiyun END_OF_TABLE 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun /* with PGA */ 362*4882a593Smuzhiyun /* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */ 363*4882a593Smuzhiyun /* without PGA */ 364*4882a593Smuzhiyun /* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 365*4882a593Smuzhiyun B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/ 366*4882a593Smuzhiyun /* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */ 367*4882a593Smuzhiyun /* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun u8 DRXD_InitFEB1_2[] = { 370*4882a593Smuzhiyun WR16(B_FE_COMM_EXEC__A, 0x0001), 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun /* RF-AGC setup */ 373*4882a593Smuzhiyun WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C), 374*4882a593Smuzhiyun WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01), 375*4882a593Smuzhiyun WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02), 376*4882a593Smuzhiyun WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF), 377*4882a593Smuzhiyun WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF), 378*4882a593Smuzhiyun WR16(B_FE_AG_REG_PDC_MAX__A, 0x02), 379*4882a593Smuzhiyun WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C), 380*4882a593Smuzhiyun WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22), 381*4882a593Smuzhiyun WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15), 382*4882a593Smuzhiyun WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01), 383*4882a593Smuzhiyun WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A), 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0), 386*4882a593Smuzhiyun WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000), 387*4882a593Smuzhiyun WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1), 388*4882a593Smuzhiyun END_OF_TABLE 389*4882a593Smuzhiyun }; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun u8 DRXD_InitCPA2[] = { 392*4882a593Smuzhiyun WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2), 393*4882a593Smuzhiyun 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */ 394*4882a593Smuzhiyun 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */ 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun WRBLOCK(CP_REG_RT_ANG_INC0__A, 4), 397*4882a593Smuzhiyun 0x00, 0x00, /* CP_REG_RT_ANG_INC0__A */ 398*4882a593Smuzhiyun 0x00, 0x00, /* CP_REG_RT_ANG_INC1__A */ 399*4882a593Smuzhiyun 0x03, 0x00, /* CP_REG_RT_DETECT_ENA__A */ 400*4882a593Smuzhiyun 0x03, 0x00, /* CP_REG_RT_DETECT_TRH__A */ 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5), 403*4882a593Smuzhiyun 0x32, 0x00, /* CP_REG_AC_NEXP_OFFS__A */ 404*4882a593Smuzhiyun 0x62, 0x00, /* CP_REG_AC_AVER_POW__A */ 405*4882a593Smuzhiyun 0x82, 0x00, /* CP_REG_AC_MAX_POW__A */ 406*4882a593Smuzhiyun 0x26, 0x00, /* CP_REG_AC_WEIGHT_MAN__A */ 407*4882a593Smuzhiyun 0x0F, 0x00, /* CP_REG_AC_WEIGHT_EXP__A */ 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun WRBLOCK(CP_REG_AC_AMP_MODE__A, 2), 410*4882a593Smuzhiyun 0x02, 0x00, /* CP_REG_AC_AMP_MODE__A */ 411*4882a593Smuzhiyun 0x01, 0x00, /* CP_REG_AC_AMP_FIX__A */ 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun WR16(CP_REG_INTERVAL__A, 0x0005), 414*4882a593Smuzhiyun WR16(CP_REG_RT_EXP_MARG__A, 0x0004), 415*4882a593Smuzhiyun WR16(CP_REG_AC_ANG_MODE__A, 0x0003), 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun WR16(CP_REG_COMM_EXEC__A, 0x0001), 418*4882a593Smuzhiyun END_OF_TABLE 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun u8 DRXD_InitCPB1[] = { 422*4882a593Smuzhiyun WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008), 423*4882a593Smuzhiyun WR16(B_CP_COMM_EXEC__A, 0x0001), 424*4882a593Smuzhiyun END_OF_TABLE 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun u8 DRXD_InitCEA2[] = { 428*4882a593Smuzhiyun WRBLOCK(CE_REG_AVG_POW__A, 4), 429*4882a593Smuzhiyun 0x62, 0x00, /* CE_REG_AVG_POW__A */ 430*4882a593Smuzhiyun 0x78, 0x00, /* CE_REG_MAX_POW__A */ 431*4882a593Smuzhiyun 0x62, 0x00, /* CE_REG_ATT__A */ 432*4882a593Smuzhiyun 0x17, 0x00, /* CE_REG_NRED__A */ 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2), 435*4882a593Smuzhiyun 0x07, 0x00, /* CE_REG_NE_ERR_SELECT__A */ 436*4882a593Smuzhiyun 0xEB, 0xFF, /* CE_REG_NE_TD_CAL__A */ 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun WRBLOCK(CE_REG_NE_MIXAVG__A, 2), 439*4882a593Smuzhiyun 0x06, 0x00, /* CE_REG_NE_MIXAVG__A */ 440*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_NE_NUPD_OFS__A */ 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2), 443*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_PE_NEXP_OFFS__A */ 444*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_PE_TIMESHIFT__A */ 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3), 447*4882a593Smuzhiyun 0x00, 0x01, /* CE_REG_TP_A0_TAP_NEW__A */ 448*4882a593Smuzhiyun 0x01, 0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */ 449*4882a593Smuzhiyun 0x0E, 0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */ 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun WRBLOCK(CE_REG_TP_A1_TAP_NEW__A, 3), 452*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_TP_A1_TAP_NEW__A */ 453*4882a593Smuzhiyun 0x01, 0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */ 454*4882a593Smuzhiyun 0x0A, 0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */ 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun WRBLOCK(CE_REG_FI_SHT_INCR__A, 2), 457*4882a593Smuzhiyun 0x12, 0x00, /* CE_REG_FI_SHT_INCR__A */ 458*4882a593Smuzhiyun 0x0C, 0x00, /* CE_REG_FI_EXP_NORM__A */ 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun WRBLOCK(CE_REG_IR_INPUTSEL__A, 3), 461*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_IR_INPUTSEL__A */ 462*4882a593Smuzhiyun 0x00, 0x00, /* CE_REG_IR_STARTPOS__A */ 463*4882a593Smuzhiyun 0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */ 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000), 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun END_OF_TABLE 468*4882a593Smuzhiyun }; 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun u8 DRXD_InitCEB1[] = { 471*4882a593Smuzhiyun WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001), 472*4882a593Smuzhiyun WR16(B_CE_REG_FR_PM_SET__A, 0x000D), 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun END_OF_TABLE 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun u8 DRXD_InitEQA2[] = { 478*4882a593Smuzhiyun WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4), 479*4882a593Smuzhiyun 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */ 480*4882a593Smuzhiyun 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */ 481*4882a593Smuzhiyun 0x06, 0x00, /* EQ_REG_OT_CSI_STEP__A */ 482*4882a593Smuzhiyun 0x02, 0x00, /* EQ_REG_OT_CSI_OFFSET__A */ 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200), 485*4882a593Smuzhiyun WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F), 486*4882a593Smuzhiyun WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)), 487*4882a593Smuzhiyun WR16(EQ_REG_RC_SEL_CAR__A, 0x0002), 488*4882a593Smuzhiyun WR16(EQ_REG_COMM_EXEC__A, 0x0001), 489*4882a593Smuzhiyun END_OF_TABLE 490*4882a593Smuzhiyun }; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun u8 DRXD_InitEQB1[] = { 493*4882a593Smuzhiyun WR16(B_EQ_REG_COMM_EXEC__A, 0x0001), 494*4882a593Smuzhiyun END_OF_TABLE 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun u8 DRXD_ResetECRAM[] = { 498*4882a593Smuzhiyun /* Reset packet sync bytes in EC_VD ram */ 499*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), 500*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), 501*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000), 502*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000), 503*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000), 504*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000), 505*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000), 506*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000), 507*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000), 508*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000), 509*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000), 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun /* Reset packet sync bytes in EC_RS ram */ 512*4882a593Smuzhiyun WR16(EC_RS_EC_RAM__A, 0x0000), 513*4882a593Smuzhiyun WR16(EC_RS_EC_RAM__A + 204, 0x0000), 514*4882a593Smuzhiyun END_OF_TABLE 515*4882a593Smuzhiyun }; 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun u8 DRXD_InitECA2[] = { 518*4882a593Smuzhiyun WRBLOCK(EC_SB_REG_CSI_HI__A, 6), 519*4882a593Smuzhiyun 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */ 520*4882a593Smuzhiyun 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */ 521*4882a593Smuzhiyun 0x01, 0x00, /* EC_SB_REG_SMB_TGL__A */ 522*4882a593Smuzhiyun 0x7F, 0x00, /* EC_SB_REG_SNR_HI__A */ 523*4882a593Smuzhiyun 0x7F, 0x00, /* EC_SB_REG_SNR_MID__A */ 524*4882a593Smuzhiyun 0x7F, 0x00, /* EC_SB_REG_SNR_LO__A */ 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun WRBLOCK(EC_RS_REG_REQ_PCK_CNT__A, 2), 527*4882a593Smuzhiyun 0x00, 0x10, /* EC_RS_REG_REQ_PCK_CNT__A */ 528*4882a593Smuzhiyun DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */ 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5), 531*4882a593Smuzhiyun 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ 532*4882a593Smuzhiyun 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ 533*4882a593Smuzhiyun 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ 534*4882a593Smuzhiyun 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ 535*4882a593Smuzhiyun 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2), 538*4882a593Smuzhiyun 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ 539*4882a593Smuzhiyun 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun WRBLOCK(EC_OC_REG_RCN_MODE__A, 7), 542*4882a593Smuzhiyun 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */ 543*4882a593Smuzhiyun 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ 544*4882a593Smuzhiyun 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ 545*4882a593Smuzhiyun 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */ 546*4882a593Smuzhiyun 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */ 547*4882a593Smuzhiyun 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */ 548*4882a593Smuzhiyun 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2), 551*4882a593Smuzhiyun 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ 552*4882a593Smuzhiyun 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun WR16(EC_SB_REG_CSI_OFS__A, 0x0001), 555*4882a593Smuzhiyun WR16(EC_VD_REG_FORCE__A, 0x0002), 556*4882a593Smuzhiyun WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001), 557*4882a593Smuzhiyun WR16(EC_VD_REG_RLK_ENA__A, 0x0001), 558*4882a593Smuzhiyun WR16(EC_OD_REG_SYNC__A, 0x0664), 559*4882a593Smuzhiyun WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000), 560*4882a593Smuzhiyun WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C), 561*4882a593Smuzhiyun /* Output zero on monitorbus pads, power saving */ 562*4882a593Smuzhiyun WR16(EC_OC_REG_OCR_MON_UOS__A, 563*4882a593Smuzhiyun (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | 564*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | 565*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | 566*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | 567*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | 568*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | 569*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | 570*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | 571*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | 572*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | 573*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | 574*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)), 575*4882a593Smuzhiyun WR16(EC_OC_REG_OCR_MON_WRI__A, 576*4882a593Smuzhiyun EC_OC_REG_OCR_MON_WRI_INIT), 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun /* CHK_ERROR(ResetECRAM(demod)); */ 579*4882a593Smuzhiyun /* Reset packet sync bytes in EC_VD ram */ 580*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), 581*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), 582*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000), 583*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000), 584*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000), 585*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000), 586*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000), 587*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000), 588*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000), 589*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000), 590*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000), 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun /* Reset packet sync bytes in EC_RS ram */ 593*4882a593Smuzhiyun WR16(EC_RS_EC_RAM__A, 0x0000), 594*4882a593Smuzhiyun WR16(EC_RS_EC_RAM__A + 204, 0x0000), 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun WR16(EC_SB_REG_COMM_EXEC__A, 0x0001), 597*4882a593Smuzhiyun WR16(EC_VD_REG_COMM_EXEC__A, 0x0001), 598*4882a593Smuzhiyun WR16(EC_OD_REG_COMM_EXEC__A, 0x0001), 599*4882a593Smuzhiyun WR16(EC_RS_REG_COMM_EXEC__A, 0x0001), 600*4882a593Smuzhiyun END_OF_TABLE 601*4882a593Smuzhiyun }; 602*4882a593Smuzhiyun 603*4882a593Smuzhiyun u8 DRXD_InitECB1[] = { 604*4882a593Smuzhiyun WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001), 605*4882a593Smuzhiyun WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001), 606*4882a593Smuzhiyun WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001), 607*4882a593Smuzhiyun WR16(B_EC_SB_REG_CSI_LO__A, 0x000c), 608*4882a593Smuzhiyun WR16(B_EC_SB_REG_CSI_HI__A, 0x0018), 609*4882a593Smuzhiyun WR16(B_EC_SB_REG_SNR_HI__A, 0x007f), 610*4882a593Smuzhiyun WR16(B_EC_SB_REG_SNR_MID__A, 0x007f), 611*4882a593Smuzhiyun WR16(B_EC_SB_REG_SNR_LO__A, 0x007f), 612*4882a593Smuzhiyun 613*4882a593Smuzhiyun WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002), 614*4882a593Smuzhiyun WR16(B_EC_OC_REG_DTO_PER__A, 0x0006), 615*4882a593Smuzhiyun WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001), 616*4882a593Smuzhiyun WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000), 617*4882a593Smuzhiyun WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D), 618*4882a593Smuzhiyun WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000), 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun /* Needed because shadow registers do not have correct default value */ 621*4882a593Smuzhiyun WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000), 622*4882a593Smuzhiyun WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000), 623*4882a593Smuzhiyun WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000), 624*4882a593Smuzhiyun WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0), 625*4882a593Smuzhiyun WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000), 626*4882a593Smuzhiyun WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0), 627*4882a593Smuzhiyun WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000), 628*4882a593Smuzhiyun WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0), 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun WR16(B_EC_OD_REG_SYNC__A, 0x0664), 631*4882a593Smuzhiyun WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000), 632*4882a593Smuzhiyun 633*4882a593Smuzhiyun /* CHK_ERROR(ResetECRAM(demod)); */ 634*4882a593Smuzhiyun /* Reset packet sync bytes in EC_VD ram */ 635*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), 636*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), 637*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000), 638*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000), 639*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000), 640*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000), 641*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000), 642*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000), 643*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000), 644*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000), 645*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000), 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun /* Reset packet sync bytes in EC_RS ram */ 648*4882a593Smuzhiyun WR16(EC_RS_EC_RAM__A, 0x0000), 649*4882a593Smuzhiyun WR16(EC_RS_EC_RAM__A + 204, 0x0000), 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001), 652*4882a593Smuzhiyun WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001), 653*4882a593Smuzhiyun WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001), 654*4882a593Smuzhiyun WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001), 655*4882a593Smuzhiyun END_OF_TABLE 656*4882a593Smuzhiyun }; 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun u8 DRXD_ResetECA2[] = { 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun WR16(EC_OC_REG_COMM_EXEC__A, 0x0000), 661*4882a593Smuzhiyun WR16(EC_OD_REG_COMM_EXEC__A, 0x0000), 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5), 664*4882a593Smuzhiyun 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ 665*4882a593Smuzhiyun 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ 666*4882a593Smuzhiyun 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ 667*4882a593Smuzhiyun 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ 668*4882a593Smuzhiyun 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2), 671*4882a593Smuzhiyun 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ 672*4882a593Smuzhiyun 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun WRBLOCK(EC_OC_REG_RCN_MODE__A, 7), 675*4882a593Smuzhiyun 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */ 676*4882a593Smuzhiyun 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ 677*4882a593Smuzhiyun 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ 678*4882a593Smuzhiyun 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */ 679*4882a593Smuzhiyun 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */ 680*4882a593Smuzhiyun 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */ 681*4882a593Smuzhiyun 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2), 684*4882a593Smuzhiyun 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ 685*4882a593Smuzhiyun 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ 686*4882a593Smuzhiyun 687*4882a593Smuzhiyun WR16(EC_OD_REG_SYNC__A, 0x0664), 688*4882a593Smuzhiyun WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000), 689*4882a593Smuzhiyun WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C), 690*4882a593Smuzhiyun /* Output zero on monitorbus pads, power saving */ 691*4882a593Smuzhiyun WR16(EC_OC_REG_OCR_MON_UOS__A, 692*4882a593Smuzhiyun (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | 693*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | 694*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | 695*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | 696*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | 697*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | 698*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | 699*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | 700*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | 701*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | 702*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | 703*4882a593Smuzhiyun EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)), 704*4882a593Smuzhiyun WR16(EC_OC_REG_OCR_MON_WRI__A, 705*4882a593Smuzhiyun EC_OC_REG_OCR_MON_WRI_INIT), 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun /* CHK_ERROR(ResetECRAM(demod)); */ 708*4882a593Smuzhiyun /* Reset packet sync bytes in EC_VD ram */ 709*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), 710*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), 711*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000), 712*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000), 713*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000), 714*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000), 715*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000), 716*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000), 717*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000), 718*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000), 719*4882a593Smuzhiyun WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000), 720*4882a593Smuzhiyun 721*4882a593Smuzhiyun /* Reset packet sync bytes in EC_RS ram */ 722*4882a593Smuzhiyun WR16(EC_RS_EC_RAM__A, 0x0000), 723*4882a593Smuzhiyun WR16(EC_RS_EC_RAM__A + 204, 0x0000), 724*4882a593Smuzhiyun 725*4882a593Smuzhiyun WR16(EC_OD_REG_COMM_EXEC__A, 0x0001), 726*4882a593Smuzhiyun END_OF_TABLE 727*4882a593Smuzhiyun }; 728*4882a593Smuzhiyun 729*4882a593Smuzhiyun u8 DRXD_InitSC[] = { 730*4882a593Smuzhiyun WR16(SC_COMM_EXEC__A, 0), 731*4882a593Smuzhiyun WR16(SC_COMM_STATE__A, 0), 732*4882a593Smuzhiyun 733*4882a593Smuzhiyun #ifdef COMPILE_FOR_QT 734*4882a593Smuzhiyun WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100), 735*4882a593Smuzhiyun #endif 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun /* SC is not started, this is done in SetChannels() */ 738*4882a593Smuzhiyun END_OF_TABLE 739*4882a593Smuzhiyun }; 740*4882a593Smuzhiyun 741*4882a593Smuzhiyun /* Diversity settings */ 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun u8 DRXD_InitDiversityFront[] = { 744*4882a593Smuzhiyun /* Start demod ********* RF in , diversity out **************************** */ 745*4882a593Smuzhiyun WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | 746*4882a593Smuzhiyun B_SC_RA_RAM_CONFIG_FREQSCAN__M), 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7), 749*4882a593Smuzhiyun WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7), 750*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K), 751*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)), 752*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)), 753*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K), 754*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)), 755*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)), 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K), 758*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)), 759*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)), 760*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K), 761*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)), 762*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)), 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7), 765*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4), 766*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7), 767*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4), 768*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500), 769*4882a593Smuzhiyun 770*4882a593Smuzhiyun WR16(B_CC_REG_DIVERSITY__A, 0x0001), 771*4882a593Smuzhiyun WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010), 772*4882a593Smuzhiyun WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | 773*4882a593Smuzhiyun B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE), 774*4882a593Smuzhiyun 775*4882a593Smuzhiyun /* 0x2a ), *//* CE to PASS mux */ 776*4882a593Smuzhiyun 777*4882a593Smuzhiyun END_OF_TABLE 778*4882a593Smuzhiyun }; 779*4882a593Smuzhiyun 780*4882a593Smuzhiyun u8 DRXD_InitDiversityEnd[] = { 781*4882a593Smuzhiyun /* End demod *********** combining RF in and diversity in, MPEG TS out **** */ 782*4882a593Smuzhiyun /* disable near/far; switch on timing slave mode */ 783*4882a593Smuzhiyun WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | 784*4882a593Smuzhiyun B_SC_RA_RAM_CONFIG_FREQSCAN__M | 785*4882a593Smuzhiyun B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M | 786*4882a593Smuzhiyun B_SC_RA_RAM_CONFIG_SLAVE__M | 787*4882a593Smuzhiyun B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 788*4882a593Smuzhiyun /* MV from CtrlDiversity */ 789*4882a593Smuzhiyun ), 790*4882a593Smuzhiyun #ifdef DRXDDIV_SRMM_SLAVING 791*4882a593Smuzhiyun WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7), 792*4882a593Smuzhiyun WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7), 793*4882a593Smuzhiyun #else 794*4882a593Smuzhiyun WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7), 795*4882a593Smuzhiyun WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7), 796*4882a593Smuzhiyun #endif 797*4882a593Smuzhiyun 798*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K), 799*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)), 800*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)), 801*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K), 802*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)), 803*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)), 804*4882a593Smuzhiyun 805*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K), 806*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)), 807*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)), 808*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K), 809*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)), 810*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)), 811*4882a593Smuzhiyun 812*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7), 813*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4), 814*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7), 815*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4), 816*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500), 817*4882a593Smuzhiyun 818*4882a593Smuzhiyun WR16(B_CC_REG_DIVERSITY__A, 0x0001), 819*4882a593Smuzhiyun END_OF_TABLE 820*4882a593Smuzhiyun }; 821*4882a593Smuzhiyun 822*4882a593Smuzhiyun u8 DRXD_DisableDiversity[] = { 823*4882a593Smuzhiyun WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE), 824*4882a593Smuzhiyun WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE), 825*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, 826*4882a593Smuzhiyun B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE), 827*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 828*4882a593Smuzhiyun B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE), 829*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 830*4882a593Smuzhiyun B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE), 831*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, 832*4882a593Smuzhiyun B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE), 833*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 834*4882a593Smuzhiyun B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE), 835*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 836*4882a593Smuzhiyun B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE), 837*4882a593Smuzhiyun 838*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, 839*4882a593Smuzhiyun B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE), 840*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 841*4882a593Smuzhiyun B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE), 842*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 843*4882a593Smuzhiyun B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE), 844*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, 845*4882a593Smuzhiyun B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE), 846*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 847*4882a593Smuzhiyun B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE), 848*4882a593Smuzhiyun WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 849*4882a593Smuzhiyun B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE), 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE), 852*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE), 853*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE), 854*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE), 855*4882a593Smuzhiyun WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE), 856*4882a593Smuzhiyun 857*4882a593Smuzhiyun WR16(B_CC_REG_DIVERSITY__A, 0x0000), 858*4882a593Smuzhiyun WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */ 859*4882a593Smuzhiyun 860*4882a593Smuzhiyun END_OF_TABLE 861*4882a593Smuzhiyun }; 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun u8 DRXD_StartDiversityFront[] = { 864*4882a593Smuzhiyun /* Start demod, RF in and diversity out, no combining */ 865*4882a593Smuzhiyun WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), 866*4882a593Smuzhiyun WR16(B_FE_AD_REG_FDB_IN__A, 0x0), 867*4882a593Smuzhiyun WR16(B_FE_AD_REG_INVEXT__A, 0x0), 868*4882a593Smuzhiyun WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */ 869*4882a593Smuzhiyun WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */ 870*4882a593Smuzhiyun B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE), 871*4882a593Smuzhiyun 872*4882a593Smuzhiyun WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2), 873*4882a593Smuzhiyun 874*4882a593Smuzhiyun END_OF_TABLE 875*4882a593Smuzhiyun }; 876*4882a593Smuzhiyun 877*4882a593Smuzhiyun u8 DRXD_StartDiversityEnd[] = { 878*4882a593Smuzhiyun /* End demod, combining RF in and diversity in, MPEG TS out */ 879*4882a593Smuzhiyun WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */ 880*4882a593Smuzhiyun WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */ 881*4882a593Smuzhiyun WR16(B_CP_REG_BR_STR_DEL__A, 10), /* apparently no mb delay matching is best */ 882*4882a593Smuzhiyun 883*4882a593Smuzhiyun WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */ 884*4882a593Smuzhiyun B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | 885*4882a593Smuzhiyun B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC), 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun END_OF_TABLE 888*4882a593Smuzhiyun }; 889*4882a593Smuzhiyun 890*4882a593Smuzhiyun u8 DRXD_DiversityDelay8MHZ[] = { 891*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50), 892*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50), 893*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50), 894*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50), 895*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50), 896*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50), 897*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50), 898*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50), 899*4882a593Smuzhiyun END_OF_TABLE 900*4882a593Smuzhiyun }; 901*4882a593Smuzhiyun 902*4882a593Smuzhiyun u8 DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ 903*4882a593Smuzhiyun { 904*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50), 905*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50), 906*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50), 907*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50), 908*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50), 909*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50), 910*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50), 911*4882a593Smuzhiyun WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50), 912*4882a593Smuzhiyun END_OF_TABLE 913*4882a593Smuzhiyun }; 914