1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef DIB8000_H
3*4882a593Smuzhiyun #define DIB8000_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include "dibx000_common.h"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun struct dib8000_config {
8*4882a593Smuzhiyun u8 output_mpeg2_in_188_bytes;
9*4882a593Smuzhiyun u8 hostbus_diversity;
10*4882a593Smuzhiyun u8 tuner_is_baseband;
11*4882a593Smuzhiyun int (*update_lna) (struct dvb_frontend *, u16 agc_global);
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun u8 agc_config_count;
14*4882a593Smuzhiyun struct dibx000_agc_config *agc;
15*4882a593Smuzhiyun struct dibx000_bandwidth_config *pll;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define DIB8000_GPIO_DEFAULT_DIRECTIONS 0xffff
18*4882a593Smuzhiyun u16 gpio_dir;
19*4882a593Smuzhiyun #define DIB8000_GPIO_DEFAULT_VALUES 0x0000
20*4882a593Smuzhiyun u16 gpio_val;
21*4882a593Smuzhiyun #define DIB8000_GPIO_PWM_POS0(v) ((v & 0xf) << 12)
22*4882a593Smuzhiyun #define DIB8000_GPIO_PWM_POS1(v) ((v & 0xf) << 8 )
23*4882a593Smuzhiyun #define DIB8000_GPIO_PWM_POS2(v) ((v & 0xf) << 4 )
24*4882a593Smuzhiyun #define DIB8000_GPIO_PWM_POS3(v) (v & 0xf)
25*4882a593Smuzhiyun #define DIB8000_GPIO_DEFAULT_PWM_POS 0xffff
26*4882a593Smuzhiyun u16 gpio_pwm_pos;
27*4882a593Smuzhiyun u16 pwm_freq_div;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun void (*agc_control) (struct dvb_frontend *, u8 before);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun u16 drives;
32*4882a593Smuzhiyun u16 diversity_delay;
33*4882a593Smuzhiyun u8 div_cfg;
34*4882a593Smuzhiyun u8 output_mode;
35*4882a593Smuzhiyun u8 refclksel;
36*4882a593Smuzhiyun u8 enMpegOutput:1;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun struct dibx000_bandwidth_config *plltable;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define DEFAULT_DIB8000_I2C_ADDRESS 18
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct dib8000_ops {
44*4882a593Smuzhiyun int (*set_wbd_ref)(struct dvb_frontend *fe, u16 value);
45*4882a593Smuzhiyun int (*update_pll)(struct dvb_frontend *fe,
46*4882a593Smuzhiyun struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio);
47*4882a593Smuzhiyun int (*set_gpio)(struct dvb_frontend *fe, u8 num, u8 dir, u8 val);
48*4882a593Smuzhiyun void (*pwm_agc_reset)(struct dvb_frontend *fe);
49*4882a593Smuzhiyun struct i2c_adapter *(*get_i2c_tuner)(struct dvb_frontend *fe);
50*4882a593Smuzhiyun int (*tuner_sleep)(struct dvb_frontend *fe, int onoff);
51*4882a593Smuzhiyun s32 (*get_adc_power)(struct dvb_frontend *fe, u8 mode);
52*4882a593Smuzhiyun int (*get_dc_power)(struct dvb_frontend *fe, u8 IQ);
53*4882a593Smuzhiyun u32 (*ctrl_timf)(struct dvb_frontend *fe, uint8_t op, uint32_t timf);
54*4882a593Smuzhiyun enum frontend_tune_state (*get_tune_state)(struct dvb_frontend *fe);
55*4882a593Smuzhiyun int (*set_tune_state)(struct dvb_frontend *fe, enum frontend_tune_state tune_state);
56*4882a593Smuzhiyun int (*set_slave_frontend)(struct dvb_frontend *fe, struct dvb_frontend *fe_slave);
57*4882a593Smuzhiyun struct dvb_frontend *(*get_slave_frontend)(struct dvb_frontend *fe, int slave_index);
58*4882a593Smuzhiyun int (*i2c_enumeration)(struct i2c_adapter *host, int no_of_demods,
59*4882a593Smuzhiyun u8 default_addr, u8 first_addr, u8 is_dib8096p);
60*4882a593Smuzhiyun struct i2c_adapter *(*get_i2c_master)(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating);
61*4882a593Smuzhiyun int (*pid_filter_ctrl)(struct dvb_frontend *fe, u8 onoff);
62*4882a593Smuzhiyun int (*pid_filter)(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff);
63*4882a593Smuzhiyun struct dvb_frontend *(*init)(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg);
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #if IS_REACHABLE(CONFIG_DVB_DIB8000)
67*4882a593Smuzhiyun void *dib8000_attach(struct dib8000_ops *ops);
68*4882a593Smuzhiyun #else
dib8000_attach(struct dib8000_ops * ops)69*4882a593Smuzhiyun static inline void *dib8000_attach(struct dib8000_ops *ops)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
72*4882a593Smuzhiyun return NULL;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #endif
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